1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = CountTrailingZeros_32(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 180 unsigned RegNo, uint64_t Address, 181 const void *Decoder); 182 183 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 196 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 201 unsigned Insn, 202 uint64_t Address, 203 const void *Decoder); 204 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 213 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 214 unsigned Insn, 215 uint64_t Adddress, 216 const void *Decoder); 217 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 312 const void *Decoder); 313 314 315 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 376 uint64_t Address, const void *Decoder); 377 378 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 #include "ARMGenDisassemblerTables.inc" 383 384 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 385 return new ARMDisassembler(STI); 386 } 387 388 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 389 return new ThumbDisassembler(STI); 390 } 391 392 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 393 const MemoryObject &Region, 394 uint64_t Address, 395 raw_ostream &os, 396 raw_ostream &cs) const { 397 CommentStream = &cs; 398 399 uint8_t bytes[4]; 400 401 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 402 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 403 404 // We want to read exactly 4 bytes of data. 405 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 406 Size = 0; 407 return MCDisassembler::Fail; 408 } 409 410 // Encoded as a small-endian 32-bit word in the stream. 411 uint32_t insn = (bytes[3] << 24) | 412 (bytes[2] << 16) | 413 (bytes[1] << 8) | 414 (bytes[0] << 0); 415 416 // Calling the auto-generated decoder function. 417 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 418 Address, this, STI); 419 if (result != MCDisassembler::Fail) { 420 Size = 4; 421 return result; 422 } 423 424 // VFP and NEON instructions, similarly, are shared between ARM 425 // and Thumb modes. 426 MI.clear(); 427 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 428 if (result != MCDisassembler::Fail) { 429 Size = 4; 430 return result; 431 } 432 433 MI.clear(); 434 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 435 this, STI); 436 if (result != MCDisassembler::Fail) { 437 Size = 4; 438 // Add a fake predicate operand, because we share these instruction 439 // definitions with Thumb2 where these instructions are predicable. 440 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 441 return MCDisassembler::Fail; 442 return result; 443 } 444 445 MI.clear(); 446 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 447 this, STI); 448 if (result != MCDisassembler::Fail) { 449 Size = 4; 450 // Add a fake predicate operand, because we share these instruction 451 // definitions with Thumb2 where these instructions are predicable. 452 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 453 return MCDisassembler::Fail; 454 return result; 455 } 456 457 MI.clear(); 458 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 459 this, STI); 460 if (result != MCDisassembler::Fail) { 461 Size = 4; 462 // Add a fake predicate operand, because we share these instruction 463 // definitions with Thumb2 where these instructions are predicable. 464 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 465 return MCDisassembler::Fail; 466 return result; 467 } 468 469 MI.clear(); 470 471 Size = 0; 472 return MCDisassembler::Fail; 473 } 474 475 namespace llvm { 476 extern const MCInstrDesc ARMInsts[]; 477 } 478 479 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 480 /// immediate Value in the MCInst. The immediate Value has had any PC 481 /// adjustment made by the caller. If the instruction is a branch instruction 482 /// then isBranch is true, else false. If the getOpInfo() function was set as 483 /// part of the setupForSymbolicDisassembly() call then that function is called 484 /// to get any symbolic information at the Address for this instruction. If 485 /// that returns non-zero then the symbolic information it returns is used to 486 /// create an MCExpr and that is added as an operand to the MCInst. If 487 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 488 /// Value is done and if a symbol is found an MCExpr is created with that, else 489 /// an MCExpr with Value is created. This function returns true if it adds an 490 /// operand to the MCInst and false otherwise. 491 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 492 bool isBranch, uint64_t InstSize, 493 MCInst &MI, const void *Decoder) { 494 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 495 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 496 struct LLVMOpInfo1 SymbolicOp; 497 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 498 SymbolicOp.Value = Value; 499 void *DisInfo = Dis->getDisInfoBlock(); 500 501 if (!getOpInfo || 502 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 503 // Clear SymbolicOp.Value from above and also all other fields. 504 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 505 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 506 if (!SymbolLookUp) 507 return false; 508 uint64_t ReferenceType; 509 if (isBranch) 510 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 511 else 512 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 513 const char *ReferenceName; 514 uint64_t SymbolValue = 0x00000000ffffffffULL & Value; 515 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType, 516 Address, &ReferenceName); 517 if (Name) { 518 SymbolicOp.AddSymbol.Name = Name; 519 SymbolicOp.AddSymbol.Present = true; 520 } 521 // For branches always create an MCExpr so it gets printed as hex address. 522 else if (isBranch) { 523 SymbolicOp.Value = Value; 524 } 525 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 526 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 527 if (!Name && !isBranch) 528 return false; 529 } 530 531 MCContext *Ctx = Dis->getMCContext(); 532 const MCExpr *Add = NULL; 533 if (SymbolicOp.AddSymbol.Present) { 534 if (SymbolicOp.AddSymbol.Name) { 535 StringRef Name(SymbolicOp.AddSymbol.Name); 536 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 537 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 538 } else { 539 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 540 } 541 } 542 543 const MCExpr *Sub = NULL; 544 if (SymbolicOp.SubtractSymbol.Present) { 545 if (SymbolicOp.SubtractSymbol.Name) { 546 StringRef Name(SymbolicOp.SubtractSymbol.Name); 547 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 548 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 549 } else { 550 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 551 } 552 } 553 554 const MCExpr *Off = NULL; 555 if (SymbolicOp.Value != 0) 556 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 557 558 const MCExpr *Expr; 559 if (Sub) { 560 const MCExpr *LHS; 561 if (Add) 562 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 563 else 564 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 565 if (Off != 0) 566 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 567 else 568 Expr = LHS; 569 } else if (Add) { 570 if (Off != 0) 571 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 572 else 573 Expr = Add; 574 } else { 575 if (Off != 0) 576 Expr = Off; 577 else 578 Expr = MCConstantExpr::Create(0, *Ctx); 579 } 580 581 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 582 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 583 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 584 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 585 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 586 MI.addOperand(MCOperand::CreateExpr(Expr)); 587 else 588 llvm_unreachable("bad SymbolicOp.VariantKind"); 589 590 return true; 591 } 592 593 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 594 /// referenced by a load instruction with the base register that is the Pc. 595 /// These can often be values in a literal pool near the Address of the 596 /// instruction. The Address of the instruction and its immediate Value are 597 /// used as a possible literal pool entry. The SymbolLookUp call back will 598 /// return the name of a symbol referenced by the literal pool's entry if 599 /// the referenced address is that of a symbol. Or it will return a pointer to 600 /// a literal 'C' string if the referenced address of the literal pool's entry 601 /// is an address into a section with 'C' string literals. 602 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 603 const void *Decoder) { 604 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 605 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 606 if (SymbolLookUp) { 607 void *DisInfo = Dis->getDisInfoBlock(); 608 uint64_t ReferenceType; 609 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 610 const char *ReferenceName; 611 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 612 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 613 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 614 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 615 } 616 } 617 618 // Thumb1 instructions don't have explicit S bits. Rather, they 619 // implicitly set CPSR. Since it's not represented in the encoding, the 620 // auto-generated decoder won't inject the CPSR operand. We need to fix 621 // that as a post-pass. 622 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 623 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 624 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 625 MCInst::iterator I = MI.begin(); 626 for (unsigned i = 0; i < NumOps; ++i, ++I) { 627 if (I == MI.end()) break; 628 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 629 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 630 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 631 return; 632 } 633 } 634 635 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 636 } 637 638 // Most Thumb instructions don't have explicit predicates in the 639 // encoding, but rather get their predicates from IT context. We need 640 // to fix up the predicate operands using this context information as a 641 // post-pass. 642 MCDisassembler::DecodeStatus 643 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 644 MCDisassembler::DecodeStatus S = Success; 645 646 // A few instructions actually have predicates encoded in them. Don't 647 // try to overwrite it if we're seeing one of those. 648 switch (MI.getOpcode()) { 649 case ARM::tBcc: 650 case ARM::t2Bcc: 651 case ARM::tCBZ: 652 case ARM::tCBNZ: 653 case ARM::tCPS: 654 case ARM::t2CPS3p: 655 case ARM::t2CPS2p: 656 case ARM::t2CPS1p: 657 case ARM::tMOVSr: 658 case ARM::tSETEND: 659 // Some instructions (mostly conditional branches) are not 660 // allowed in IT blocks. 661 if (ITBlock.instrInITBlock()) 662 S = SoftFail; 663 else 664 return Success; 665 break; 666 case ARM::tB: 667 case ARM::t2B: 668 case ARM::t2TBB: 669 case ARM::t2TBH: 670 // Some instructions (mostly unconditional branches) can 671 // only appears at the end of, or outside of, an IT. 672 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 673 S = SoftFail; 674 break; 675 default: 676 break; 677 } 678 679 // If we're in an IT block, base the predicate on that. Otherwise, 680 // assume a predicate of AL. 681 unsigned CC; 682 CC = ITBlock.getITCC(); 683 if (CC == 0xF) 684 CC = ARMCC::AL; 685 if (ITBlock.instrInITBlock()) 686 ITBlock.advanceITState(); 687 688 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 689 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 690 MCInst::iterator I = MI.begin(); 691 for (unsigned i = 0; i < NumOps; ++i, ++I) { 692 if (I == MI.end()) break; 693 if (OpInfo[i].isPredicate()) { 694 I = MI.insert(I, MCOperand::CreateImm(CC)); 695 ++I; 696 if (CC == ARMCC::AL) 697 MI.insert(I, MCOperand::CreateReg(0)); 698 else 699 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 700 return S; 701 } 702 } 703 704 I = MI.insert(I, MCOperand::CreateImm(CC)); 705 ++I; 706 if (CC == ARMCC::AL) 707 MI.insert(I, MCOperand::CreateReg(0)); 708 else 709 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 710 711 return S; 712 } 713 714 // Thumb VFP instructions are a special case. Because we share their 715 // encodings between ARM and Thumb modes, and they are predicable in ARM 716 // mode, the auto-generated decoder will give them an (incorrect) 717 // predicate operand. We need to rewrite these operands based on the IT 718 // context as a post-pass. 719 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 720 unsigned CC; 721 CC = ITBlock.getITCC(); 722 if (ITBlock.instrInITBlock()) 723 ITBlock.advanceITState(); 724 725 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 726 MCInst::iterator I = MI.begin(); 727 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 728 for (unsigned i = 0; i < NumOps; ++i, ++I) { 729 if (OpInfo[i].isPredicate() ) { 730 I->setImm(CC); 731 ++I; 732 if (CC == ARMCC::AL) 733 I->setReg(0); 734 else 735 I->setReg(ARM::CPSR); 736 return; 737 } 738 } 739 } 740 741 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 742 const MemoryObject &Region, 743 uint64_t Address, 744 raw_ostream &os, 745 raw_ostream &cs) const { 746 CommentStream = &cs; 747 748 uint8_t bytes[4]; 749 750 assert((STI.getFeatureBits() & ARM::ModeThumb) && 751 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 752 753 // We want to read exactly 2 bytes of data. 754 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 755 Size = 0; 756 return MCDisassembler::Fail; 757 } 758 759 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 760 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 761 Address, this, STI); 762 if (result != MCDisassembler::Fail) { 763 Size = 2; 764 Check(result, AddThumbPredicate(MI)); 765 return result; 766 } 767 768 MI.clear(); 769 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 770 Address, this, STI); 771 if (result) { 772 Size = 2; 773 bool InITBlock = ITBlock.instrInITBlock(); 774 Check(result, AddThumbPredicate(MI)); 775 AddThumb1SBit(MI, InITBlock); 776 return result; 777 } 778 779 MI.clear(); 780 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 781 Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 2; 784 785 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 786 // the Thumb predicate. 787 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 788 result = MCDisassembler::SoftFail; 789 790 Check(result, AddThumbPredicate(MI)); 791 792 // If we find an IT instruction, we need to parse its condition 793 // code and mask operands so that we can apply them correctly 794 // to the subsequent instructions. 795 if (MI.getOpcode() == ARM::t2IT) { 796 797 unsigned Firstcond = MI.getOperand(0).getImm(); 798 unsigned Mask = MI.getOperand(1).getImm(); 799 ITBlock.setITState(Firstcond, Mask); 800 } 801 802 return result; 803 } 804 805 // We want to read exactly 4 bytes of data. 806 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 807 Size = 0; 808 return MCDisassembler::Fail; 809 } 810 811 uint32_t insn32 = (bytes[3] << 8) | 812 (bytes[2] << 0) | 813 (bytes[1] << 24) | 814 (bytes[0] << 16); 815 MI.clear(); 816 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 817 this, STI); 818 if (result != MCDisassembler::Fail) { 819 Size = 4; 820 bool InITBlock = ITBlock.instrInITBlock(); 821 Check(result, AddThumbPredicate(MI)); 822 AddThumb1SBit(MI, InITBlock); 823 return result; 824 } 825 826 MI.clear(); 827 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 828 this, STI); 829 if (result != MCDisassembler::Fail) { 830 Size = 4; 831 Check(result, AddThumbPredicate(MI)); 832 return result; 833 } 834 835 MI.clear(); 836 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 837 if (result != MCDisassembler::Fail) { 838 Size = 4; 839 UpdateThumbVFPPredicate(MI); 840 return result; 841 } 842 843 MI.clear(); 844 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 845 this, STI); 846 if (result != MCDisassembler::Fail) { 847 Size = 4; 848 Check(result, AddThumbPredicate(MI)); 849 return result; 850 } 851 852 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 853 MI.clear(); 854 uint32_t NEONLdStInsn = insn32; 855 NEONLdStInsn &= 0xF0FFFFFF; 856 NEONLdStInsn |= 0x04000000; 857 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 858 Address, this, STI); 859 if (result != MCDisassembler::Fail) { 860 Size = 4; 861 Check(result, AddThumbPredicate(MI)); 862 return result; 863 } 864 } 865 866 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 867 MI.clear(); 868 uint32_t NEONDataInsn = insn32; 869 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 870 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 871 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 872 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 873 Address, this, STI); 874 if (result != MCDisassembler::Fail) { 875 Size = 4; 876 Check(result, AddThumbPredicate(MI)); 877 return result; 878 } 879 } 880 881 Size = 0; 882 return MCDisassembler::Fail; 883 } 884 885 886 extern "C" void LLVMInitializeARMDisassembler() { 887 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 888 createARMDisassembler); 889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 890 createThumbDisassembler); 891 } 892 893 static const uint16_t GPRDecoderTable[] = { 894 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 895 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 896 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 897 ARM::R12, ARM::SP, ARM::LR, ARM::PC 898 }; 899 900 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 if (RegNo > 15) 903 return MCDisassembler::Fail; 904 905 unsigned Register = GPRDecoderTable[RegNo]; 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static DecodeStatus 911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo == 15) 916 S = MCDisassembler::SoftFail; 917 918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 919 920 return S; 921 } 922 923 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 7) 926 return MCDisassembler::Fail; 927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 928 } 929 930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 unsigned Register = 0; 933 switch (RegNo) { 934 case 0: 935 Register = ARM::R0; 936 break; 937 case 1: 938 Register = ARM::R1; 939 break; 940 case 2: 941 Register = ARM::R2; 942 break; 943 case 3: 944 Register = ARM::R3; 945 break; 946 case 9: 947 Register = ARM::R9; 948 break; 949 case 12: 950 Register = ARM::R12; 951 break; 952 default: 953 return MCDisassembler::Fail; 954 } 955 956 Inst.addOperand(MCOperand::CreateReg(Register)); 957 return MCDisassembler::Success; 958 } 959 960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 964 } 965 966 static const uint16_t SPRDecoderTable[] = { 967 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 968 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 969 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 970 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 971 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 972 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 973 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 974 ARM::S28, ARM::S29, ARM::S30, ARM::S31 975 }; 976 977 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 if (RegNo > 31) 980 return MCDisassembler::Fail; 981 982 unsigned Register = SPRDecoderTable[RegNo]; 983 Inst.addOperand(MCOperand::CreateReg(Register)); 984 return MCDisassembler::Success; 985 } 986 987 static const uint16_t DPRDecoderTable[] = { 988 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 989 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 990 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 991 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 992 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 993 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 994 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 995 ARM::D28, ARM::D29, ARM::D30, ARM::D31 996 }; 997 998 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 999 uint64_t Address, const void *Decoder) { 1000 if (RegNo > 31) 1001 return MCDisassembler::Fail; 1002 1003 unsigned Register = DPRDecoderTable[RegNo]; 1004 Inst.addOperand(MCOperand::CreateReg(Register)); 1005 return MCDisassembler::Success; 1006 } 1007 1008 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 7) 1011 return MCDisassembler::Fail; 1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1013 } 1014 1015 static DecodeStatus 1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1017 uint64_t Address, const void *Decoder) { 1018 if (RegNo > 15) 1019 return MCDisassembler::Fail; 1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1021 } 1022 1023 static const uint16_t QPRDecoderTable[] = { 1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1028 }; 1029 1030 1031 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1032 uint64_t Address, const void *Decoder) { 1033 if (RegNo > 31) 1034 return MCDisassembler::Fail; 1035 RegNo >>= 1; 1036 1037 unsigned Register = QPRDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040 } 1041 1042 static const uint16_t DPairDecoderTable[] = { 1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1048 ARM::Q15 1049 }; 1050 1051 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1052 uint64_t Address, const void *Decoder) { 1053 if (RegNo > 30) 1054 return MCDisassembler::Fail; 1055 1056 unsigned Register = DPairDecoderTable[RegNo]; 1057 Inst.addOperand(MCOperand::CreateReg(Register)); 1058 return MCDisassembler::Success; 1059 } 1060 1061 static const uint16_t DPairSpacedDecoderTable[] = { 1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1069 ARM::D28_D30, ARM::D29_D31 1070 }; 1071 1072 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1073 unsigned RegNo, 1074 uint64_t Address, 1075 const void *Decoder) { 1076 if (RegNo > 29) 1077 return MCDisassembler::Fail; 1078 1079 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1080 Inst.addOperand(MCOperand::CreateReg(Register)); 1081 return MCDisassembler::Success; 1082 } 1083 1084 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1085 uint64_t Address, const void *Decoder) { 1086 if (Val == 0xF) return MCDisassembler::Fail; 1087 // AL predicate is not allowed on Thumb1 branches. 1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1089 return MCDisassembler::Fail; 1090 Inst.addOperand(MCOperand::CreateImm(Val)); 1091 if (Val == ARMCC::AL) { 1092 Inst.addOperand(MCOperand::CreateReg(0)); 1093 } else 1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val) 1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1102 else 1103 Inst.addOperand(MCOperand::CreateReg(0)); 1104 return MCDisassembler::Success; 1105 } 1106 1107 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1108 uint64_t Address, const void *Decoder) { 1109 uint32_t imm = Val & 0xFF; 1110 uint32_t rot = (Val & 0xF00) >> 7; 1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1112 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 1120 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1121 unsigned type = fieldFromInstruction(Val, 5, 2); 1122 unsigned imm = fieldFromInstruction(Val, 7, 5); 1123 1124 // Register-immediate 1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1126 return MCDisassembler::Fail; 1127 1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1129 switch (type) { 1130 case 0: 1131 Shift = ARM_AM::lsl; 1132 break; 1133 case 1: 1134 Shift = ARM_AM::lsr; 1135 break; 1136 case 2: 1137 Shift = ARM_AM::asr; 1138 break; 1139 case 3: 1140 Shift = ARM_AM::ror; 1141 break; 1142 } 1143 1144 if (Shift == ARM_AM::ror && imm == 0) 1145 Shift = ARM_AM::rrx; 1146 1147 unsigned Op = Shift | (imm << 3); 1148 Inst.addOperand(MCOperand::CreateImm(Op)); 1149 1150 return S; 1151 } 1152 1153 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1154 uint64_t Address, const void *Decoder) { 1155 DecodeStatus S = MCDisassembler::Success; 1156 1157 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1158 unsigned type = fieldFromInstruction(Val, 5, 2); 1159 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1160 1161 // Register-register 1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1165 return MCDisassembler::Fail; 1166 1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1168 switch (type) { 1169 case 0: 1170 Shift = ARM_AM::lsl; 1171 break; 1172 case 1: 1173 Shift = ARM_AM::lsr; 1174 break; 1175 case 2: 1176 Shift = ARM_AM::asr; 1177 break; 1178 case 3: 1179 Shift = ARM_AM::ror; 1180 break; 1181 } 1182 1183 Inst.addOperand(MCOperand::CreateImm(Shift)); 1184 1185 return S; 1186 } 1187 1188 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 bool writebackLoad = false; 1193 unsigned writebackReg = 0; 1194 switch (Inst.getOpcode()) { 1195 default: 1196 break; 1197 case ARM::LDMIA_UPD: 1198 case ARM::LDMDB_UPD: 1199 case ARM::LDMIB_UPD: 1200 case ARM::LDMDA_UPD: 1201 case ARM::t2LDMIA_UPD: 1202 case ARM::t2LDMDB_UPD: 1203 writebackLoad = true; 1204 writebackReg = Inst.getOperand(0).getReg(); 1205 break; 1206 } 1207 1208 // Empty register lists are not allowed. 1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1210 for (unsigned i = 0; i < 16; ++i) { 1211 if (Val & (1 << i)) { 1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1213 return MCDisassembler::Fail; 1214 // Writeback not allowed if Rn is in the target list. 1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1216 Check(S, MCDisassembler::SoftFail); 1217 } 1218 } 1219 1220 return S; 1221 } 1222 1223 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1228 unsigned regs = fieldFromInstruction(Val, 0, 8); 1229 1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < (regs - 1); ++i) { 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 } 1236 1237 return S; 1238 } 1239 1240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1241 uint64_t Address, const void *Decoder) { 1242 DecodeStatus S = MCDisassembler::Success; 1243 1244 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1245 unsigned regs = fieldFromInstruction(Val, 0, 8); 1246 1247 regs = regs >> 1; 1248 1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 for (unsigned i = 0; i < (regs - 1); ++i) { 1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1253 return MCDisassembler::Fail; 1254 } 1255 1256 return S; 1257 } 1258 1259 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1260 uint64_t Address, const void *Decoder) { 1261 // This operand encodes a mask of contiguous zeros between a specified MSB 1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1263 // the mask of all bits LSB-and-lower, and then xor them to create 1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1265 // create the final mask. 1266 unsigned msb = fieldFromInstruction(Val, 5, 5); 1267 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1268 1269 DecodeStatus S = MCDisassembler::Success; 1270 if (lsb > msb) { 1271 Check(S, MCDisassembler::SoftFail); 1272 // The check above will cause the warning for the "potentially undefined 1273 // instruction encoding" but we can't build a bad MCOperand value here 1274 // with a lsb > msb or else printing the MCInst will cause a crash. 1275 lsb = msb; 1276 } 1277 1278 uint32_t msb_mask = 0xFFFFFFFF; 1279 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1280 uint32_t lsb_mask = (1U << lsb) - 1; 1281 1282 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1283 return S; 1284 } 1285 1286 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1287 uint64_t Address, const void *Decoder) { 1288 DecodeStatus S = MCDisassembler::Success; 1289 1290 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1291 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1292 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1293 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1294 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1295 unsigned U = fieldFromInstruction(Insn, 23, 1); 1296 1297 switch (Inst.getOpcode()) { 1298 case ARM::LDC_OFFSET: 1299 case ARM::LDC_PRE: 1300 case ARM::LDC_POST: 1301 case ARM::LDC_OPTION: 1302 case ARM::LDCL_OFFSET: 1303 case ARM::LDCL_PRE: 1304 case ARM::LDCL_POST: 1305 case ARM::LDCL_OPTION: 1306 case ARM::STC_OFFSET: 1307 case ARM::STC_PRE: 1308 case ARM::STC_POST: 1309 case ARM::STC_OPTION: 1310 case ARM::STCL_OFFSET: 1311 case ARM::STCL_PRE: 1312 case ARM::STCL_POST: 1313 case ARM::STCL_OPTION: 1314 case ARM::t2LDC_OFFSET: 1315 case ARM::t2LDC_PRE: 1316 case ARM::t2LDC_POST: 1317 case ARM::t2LDC_OPTION: 1318 case ARM::t2LDCL_OFFSET: 1319 case ARM::t2LDCL_PRE: 1320 case ARM::t2LDCL_POST: 1321 case ARM::t2LDCL_OPTION: 1322 case ARM::t2STC_OFFSET: 1323 case ARM::t2STC_PRE: 1324 case ARM::t2STC_POST: 1325 case ARM::t2STC_OPTION: 1326 case ARM::t2STCL_OFFSET: 1327 case ARM::t2STCL_PRE: 1328 case ARM::t2STCL_POST: 1329 case ARM::t2STCL_OPTION: 1330 if (coproc == 0xA || coproc == 0xB) 1331 return MCDisassembler::Fail; 1332 break; 1333 default: 1334 break; 1335 } 1336 1337 Inst.addOperand(MCOperand::CreateImm(coproc)); 1338 Inst.addOperand(MCOperand::CreateImm(CRd)); 1339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1340 return MCDisassembler::Fail; 1341 1342 switch (Inst.getOpcode()) { 1343 case ARM::t2LDC2_OFFSET: 1344 case ARM::t2LDC2L_OFFSET: 1345 case ARM::t2LDC2_PRE: 1346 case ARM::t2LDC2L_PRE: 1347 case ARM::t2STC2_OFFSET: 1348 case ARM::t2STC2L_OFFSET: 1349 case ARM::t2STC2_PRE: 1350 case ARM::t2STC2L_PRE: 1351 case ARM::LDC2_OFFSET: 1352 case ARM::LDC2L_OFFSET: 1353 case ARM::LDC2_PRE: 1354 case ARM::LDC2L_PRE: 1355 case ARM::STC2_OFFSET: 1356 case ARM::STC2L_OFFSET: 1357 case ARM::STC2_PRE: 1358 case ARM::STC2L_PRE: 1359 case ARM::t2LDC_OFFSET: 1360 case ARM::t2LDCL_OFFSET: 1361 case ARM::t2LDC_PRE: 1362 case ARM::t2LDCL_PRE: 1363 case ARM::t2STC_OFFSET: 1364 case ARM::t2STCL_OFFSET: 1365 case ARM::t2STC_PRE: 1366 case ARM::t2STCL_PRE: 1367 case ARM::LDC_OFFSET: 1368 case ARM::LDCL_OFFSET: 1369 case ARM::LDC_PRE: 1370 case ARM::LDCL_PRE: 1371 case ARM::STC_OFFSET: 1372 case ARM::STCL_OFFSET: 1373 case ARM::STC_PRE: 1374 case ARM::STCL_PRE: 1375 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1376 Inst.addOperand(MCOperand::CreateImm(imm)); 1377 break; 1378 case ARM::t2LDC2_POST: 1379 case ARM::t2LDC2L_POST: 1380 case ARM::t2STC2_POST: 1381 case ARM::t2STC2L_POST: 1382 case ARM::LDC2_POST: 1383 case ARM::LDC2L_POST: 1384 case ARM::STC2_POST: 1385 case ARM::STC2L_POST: 1386 case ARM::t2LDC_POST: 1387 case ARM::t2LDCL_POST: 1388 case ARM::t2STC_POST: 1389 case ARM::t2STCL_POST: 1390 case ARM::LDC_POST: 1391 case ARM::LDCL_POST: 1392 case ARM::STC_POST: 1393 case ARM::STCL_POST: 1394 imm |= U << 8; 1395 // fall through. 1396 default: 1397 // The 'option' variant doesn't encode 'U' in the immediate since 1398 // the immediate is unsigned [0,255]. 1399 Inst.addOperand(MCOperand::CreateImm(imm)); 1400 break; 1401 } 1402 1403 switch (Inst.getOpcode()) { 1404 case ARM::LDC_OFFSET: 1405 case ARM::LDC_PRE: 1406 case ARM::LDC_POST: 1407 case ARM::LDC_OPTION: 1408 case ARM::LDCL_OFFSET: 1409 case ARM::LDCL_PRE: 1410 case ARM::LDCL_POST: 1411 case ARM::LDCL_OPTION: 1412 case ARM::STC_OFFSET: 1413 case ARM::STC_PRE: 1414 case ARM::STC_POST: 1415 case ARM::STC_OPTION: 1416 case ARM::STCL_OFFSET: 1417 case ARM::STCL_PRE: 1418 case ARM::STCL_POST: 1419 case ARM::STCL_OPTION: 1420 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1421 return MCDisassembler::Fail; 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return S; 1428 } 1429 1430 static DecodeStatus 1431 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1432 uint64_t Address, const void *Decoder) { 1433 DecodeStatus S = MCDisassembler::Success; 1434 1435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1436 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1437 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1438 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1439 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1440 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1441 unsigned P = fieldFromInstruction(Insn, 24, 1); 1442 unsigned W = fieldFromInstruction(Insn, 21, 1); 1443 1444 // On stores, the writeback operand precedes Rt. 1445 switch (Inst.getOpcode()) { 1446 case ARM::STR_POST_IMM: 1447 case ARM::STR_POST_REG: 1448 case ARM::STRB_POST_IMM: 1449 case ARM::STRB_POST_REG: 1450 case ARM::STRT_POST_REG: 1451 case ARM::STRT_POST_IMM: 1452 case ARM::STRBT_POST_REG: 1453 case ARM::STRBT_POST_IMM: 1454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1455 return MCDisassembler::Fail; 1456 break; 1457 default: 1458 break; 1459 } 1460 1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1462 return MCDisassembler::Fail; 1463 1464 // On loads, the writeback operand comes after Rt. 1465 switch (Inst.getOpcode()) { 1466 case ARM::LDR_POST_IMM: 1467 case ARM::LDR_POST_REG: 1468 case ARM::LDRB_POST_IMM: 1469 case ARM::LDRB_POST_REG: 1470 case ARM::LDRBT_POST_REG: 1471 case ARM::LDRBT_POST_IMM: 1472 case ARM::LDRT_POST_REG: 1473 case ARM::LDRT_POST_IMM: 1474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1475 return MCDisassembler::Fail; 1476 break; 1477 default: 1478 break; 1479 } 1480 1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 1484 ARM_AM::AddrOpc Op = ARM_AM::add; 1485 if (!fieldFromInstruction(Insn, 23, 1)) 1486 Op = ARM_AM::sub; 1487 1488 bool writeback = (P == 0) || (W == 1); 1489 unsigned idx_mode = 0; 1490 if (P && writeback) 1491 idx_mode = ARMII::IndexModePre; 1492 else if (!P && writeback) 1493 idx_mode = ARMII::IndexModePost; 1494 1495 if (writeback && (Rn == 15 || Rn == Rt)) 1496 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1497 1498 if (reg) { 1499 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1500 return MCDisassembler::Fail; 1501 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1502 switch( fieldFromInstruction(Insn, 5, 2)) { 1503 case 0: 1504 Opc = ARM_AM::lsl; 1505 break; 1506 case 1: 1507 Opc = ARM_AM::lsr; 1508 break; 1509 case 2: 1510 Opc = ARM_AM::asr; 1511 break; 1512 case 3: 1513 Opc = ARM_AM::ror; 1514 break; 1515 default: 1516 return MCDisassembler::Fail; 1517 } 1518 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1519 if (Opc == ARM_AM::ror && amt == 0) 1520 Opc = ARM_AM::rrx; 1521 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1522 1523 Inst.addOperand(MCOperand::CreateImm(imm)); 1524 } else { 1525 Inst.addOperand(MCOperand::CreateReg(0)); 1526 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1527 Inst.addOperand(MCOperand::CreateImm(tmp)); 1528 } 1529 1530 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1531 return MCDisassembler::Fail; 1532 1533 return S; 1534 } 1535 1536 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1537 uint64_t Address, const void *Decoder) { 1538 DecodeStatus S = MCDisassembler::Success; 1539 1540 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1541 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1542 unsigned type = fieldFromInstruction(Val, 5, 2); 1543 unsigned imm = fieldFromInstruction(Val, 7, 5); 1544 unsigned U = fieldFromInstruction(Val, 12, 1); 1545 1546 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1547 switch (type) { 1548 case 0: 1549 ShOp = ARM_AM::lsl; 1550 break; 1551 case 1: 1552 ShOp = ARM_AM::lsr; 1553 break; 1554 case 2: 1555 ShOp = ARM_AM::asr; 1556 break; 1557 case 3: 1558 ShOp = ARM_AM::ror; 1559 break; 1560 } 1561 1562 if (ShOp == ARM_AM::ror && imm == 0) 1563 ShOp = ARM_AM::rrx; 1564 1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1566 return MCDisassembler::Fail; 1567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1568 return MCDisassembler::Fail; 1569 unsigned shift; 1570 if (U) 1571 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1572 else 1573 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1574 Inst.addOperand(MCOperand::CreateImm(shift)); 1575 1576 return S; 1577 } 1578 1579 static DecodeStatus 1580 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1581 uint64_t Address, const void *Decoder) { 1582 DecodeStatus S = MCDisassembler::Success; 1583 1584 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1586 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1587 unsigned type = fieldFromInstruction(Insn, 22, 1); 1588 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1589 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1590 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1591 unsigned W = fieldFromInstruction(Insn, 21, 1); 1592 unsigned P = fieldFromInstruction(Insn, 24, 1); 1593 unsigned Rt2 = Rt + 1; 1594 1595 bool writeback = (W == 1) | (P == 0); 1596 1597 // For {LD,ST}RD, Rt must be even, else undefined. 1598 switch (Inst.getOpcode()) { 1599 case ARM::STRD: 1600 case ARM::STRD_PRE: 1601 case ARM::STRD_POST: 1602 case ARM::LDRD: 1603 case ARM::LDRD_PRE: 1604 case ARM::LDRD_POST: 1605 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1606 break; 1607 default: 1608 break; 1609 } 1610 switch (Inst.getOpcode()) { 1611 case ARM::STRD: 1612 case ARM::STRD_PRE: 1613 case ARM::STRD_POST: 1614 if (P == 0 && W == 1) 1615 S = MCDisassembler::SoftFail; 1616 1617 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1618 S = MCDisassembler::SoftFail; 1619 if (type && Rm == 15) 1620 S = MCDisassembler::SoftFail; 1621 if (Rt2 == 15) 1622 S = MCDisassembler::SoftFail; 1623 if (!type && fieldFromInstruction(Insn, 8, 4)) 1624 S = MCDisassembler::SoftFail; 1625 break; 1626 case ARM::STRH: 1627 case ARM::STRH_PRE: 1628 case ARM::STRH_POST: 1629 if (Rt == 15) 1630 S = MCDisassembler::SoftFail; 1631 if (writeback && (Rn == 15 || Rn == Rt)) 1632 S = MCDisassembler::SoftFail; 1633 if (!type && Rm == 15) 1634 S = MCDisassembler::SoftFail; 1635 break; 1636 case ARM::LDRD: 1637 case ARM::LDRD_PRE: 1638 case ARM::LDRD_POST: 1639 if (type && Rn == 15){ 1640 if (Rt2 == 15) 1641 S = MCDisassembler::SoftFail; 1642 break; 1643 } 1644 if (P == 0 && W == 1) 1645 S = MCDisassembler::SoftFail; 1646 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1647 S = MCDisassembler::SoftFail; 1648 if (!type && writeback && Rn == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (writeback && (Rn == Rt || Rn == Rt2)) 1651 S = MCDisassembler::SoftFail; 1652 break; 1653 case ARM::LDRH: 1654 case ARM::LDRH_PRE: 1655 case ARM::LDRH_POST: 1656 if (type && Rn == 15){ 1657 if (Rt == 15) 1658 S = MCDisassembler::SoftFail; 1659 break; 1660 } 1661 if (Rt == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && Rm == 15) 1664 S = MCDisassembler::SoftFail; 1665 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1666 S = MCDisassembler::SoftFail; 1667 break; 1668 case ARM::LDRSH: 1669 case ARM::LDRSH_PRE: 1670 case ARM::LDRSH_POST: 1671 case ARM::LDRSB: 1672 case ARM::LDRSB_PRE: 1673 case ARM::LDRSB_POST: 1674 if (type && Rn == 15){ 1675 if (Rt == 15) 1676 S = MCDisassembler::SoftFail; 1677 break; 1678 } 1679 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1680 S = MCDisassembler::SoftFail; 1681 if (!type && (Rt == 15 || Rm == 15)) 1682 S = MCDisassembler::SoftFail; 1683 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1684 S = MCDisassembler::SoftFail; 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 if (writeback) { // Writeback 1691 if (P) 1692 U |= ARMII::IndexModePre << 9; 1693 else 1694 U |= ARMII::IndexModePost << 9; 1695 1696 // On stores, the writeback operand precedes Rt. 1697 switch (Inst.getOpcode()) { 1698 case ARM::STRD: 1699 case ARM::STRD_PRE: 1700 case ARM::STRD_POST: 1701 case ARM::STRH: 1702 case ARM::STRH_PRE: 1703 case ARM::STRH_POST: 1704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1705 return MCDisassembler::Fail; 1706 break; 1707 default: 1708 break; 1709 } 1710 } 1711 1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 switch (Inst.getOpcode()) { 1715 case ARM::STRD: 1716 case ARM::STRD_PRE: 1717 case ARM::STRD_POST: 1718 case ARM::LDRD: 1719 case ARM::LDRD_PRE: 1720 case ARM::LDRD_POST: 1721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1722 return MCDisassembler::Fail; 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 if (writeback) { 1729 // On loads, the writeback operand comes after Rt. 1730 switch (Inst.getOpcode()) { 1731 case ARM::LDRD: 1732 case ARM::LDRD_PRE: 1733 case ARM::LDRD_POST: 1734 case ARM::LDRH: 1735 case ARM::LDRH_PRE: 1736 case ARM::LDRH_POST: 1737 case ARM::LDRSH: 1738 case ARM::LDRSH_PRE: 1739 case ARM::LDRSH_POST: 1740 case ARM::LDRSB: 1741 case ARM::LDRSB_PRE: 1742 case ARM::LDRSB_POST: 1743 case ARM::LDRHTr: 1744 case ARM::LDRSBTr: 1745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1746 return MCDisassembler::Fail; 1747 break; 1748 default: 1749 break; 1750 } 1751 } 1752 1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1754 return MCDisassembler::Fail; 1755 1756 if (type) { 1757 Inst.addOperand(MCOperand::CreateReg(0)); 1758 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1759 } else { 1760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 Inst.addOperand(MCOperand::CreateImm(U)); 1763 } 1764 1765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1766 return MCDisassembler::Fail; 1767 1768 return S; 1769 } 1770 1771 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1772 uint64_t Address, const void *Decoder) { 1773 DecodeStatus S = MCDisassembler::Success; 1774 1775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1776 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1777 1778 switch (mode) { 1779 case 0: 1780 mode = ARM_AM::da; 1781 break; 1782 case 1: 1783 mode = ARM_AM::ia; 1784 break; 1785 case 2: 1786 mode = ARM_AM::db; 1787 break; 1788 case 3: 1789 mode = ARM_AM::ib; 1790 break; 1791 } 1792 1793 Inst.addOperand(MCOperand::CreateImm(mode)); 1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 1797 return S; 1798 } 1799 1800 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1801 unsigned Insn, 1802 uint64_t Address, const void *Decoder) { 1803 DecodeStatus S = MCDisassembler::Success; 1804 1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1806 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1807 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1808 1809 if (pred == 0xF) { 1810 switch (Inst.getOpcode()) { 1811 case ARM::LDMDA: 1812 Inst.setOpcode(ARM::RFEDA); 1813 break; 1814 case ARM::LDMDA_UPD: 1815 Inst.setOpcode(ARM::RFEDA_UPD); 1816 break; 1817 case ARM::LDMDB: 1818 Inst.setOpcode(ARM::RFEDB); 1819 break; 1820 case ARM::LDMDB_UPD: 1821 Inst.setOpcode(ARM::RFEDB_UPD); 1822 break; 1823 case ARM::LDMIA: 1824 Inst.setOpcode(ARM::RFEIA); 1825 break; 1826 case ARM::LDMIA_UPD: 1827 Inst.setOpcode(ARM::RFEIA_UPD); 1828 break; 1829 case ARM::LDMIB: 1830 Inst.setOpcode(ARM::RFEIB); 1831 break; 1832 case ARM::LDMIB_UPD: 1833 Inst.setOpcode(ARM::RFEIB_UPD); 1834 break; 1835 case ARM::STMDA: 1836 Inst.setOpcode(ARM::SRSDA); 1837 break; 1838 case ARM::STMDA_UPD: 1839 Inst.setOpcode(ARM::SRSDA_UPD); 1840 break; 1841 case ARM::STMDB: 1842 Inst.setOpcode(ARM::SRSDB); 1843 break; 1844 case ARM::STMDB_UPD: 1845 Inst.setOpcode(ARM::SRSDB_UPD); 1846 break; 1847 case ARM::STMIA: 1848 Inst.setOpcode(ARM::SRSIA); 1849 break; 1850 case ARM::STMIA_UPD: 1851 Inst.setOpcode(ARM::SRSIA_UPD); 1852 break; 1853 case ARM::STMIB: 1854 Inst.setOpcode(ARM::SRSIB); 1855 break; 1856 case ARM::STMIB_UPD: 1857 Inst.setOpcode(ARM::SRSIB_UPD); 1858 break; 1859 default: 1860 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1861 } 1862 1863 // For stores (which become SRS's, the only operand is the mode. 1864 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1865 Inst.addOperand( 1866 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1867 return S; 1868 } 1869 1870 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1871 } 1872 1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1874 return MCDisassembler::Fail; 1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1876 return MCDisassembler::Fail; // Tied 1877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1878 return MCDisassembler::Fail; 1879 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 1882 return S; 1883 } 1884 1885 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1886 uint64_t Address, const void *Decoder) { 1887 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1888 unsigned M = fieldFromInstruction(Insn, 17, 1); 1889 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1890 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1891 1892 DecodeStatus S = MCDisassembler::Success; 1893 1894 // imod == '01' --> UNPREDICTABLE 1895 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1896 // return failure here. The '01' imod value is unprintable, so there's 1897 // nothing useful we could do even if we returned UNPREDICTABLE. 1898 1899 if (imod == 1) return MCDisassembler::Fail; 1900 1901 if (imod && M) { 1902 Inst.setOpcode(ARM::CPS3p); 1903 Inst.addOperand(MCOperand::CreateImm(imod)); 1904 Inst.addOperand(MCOperand::CreateImm(iflags)); 1905 Inst.addOperand(MCOperand::CreateImm(mode)); 1906 } else if (imod && !M) { 1907 Inst.setOpcode(ARM::CPS2p); 1908 Inst.addOperand(MCOperand::CreateImm(imod)); 1909 Inst.addOperand(MCOperand::CreateImm(iflags)); 1910 if (mode) S = MCDisassembler::SoftFail; 1911 } else if (!imod && M) { 1912 Inst.setOpcode(ARM::CPS1p); 1913 Inst.addOperand(MCOperand::CreateImm(mode)); 1914 if (iflags) S = MCDisassembler::SoftFail; 1915 } else { 1916 // imod == '00' && M == '0' --> UNPREDICTABLE 1917 Inst.setOpcode(ARM::CPS1p); 1918 Inst.addOperand(MCOperand::CreateImm(mode)); 1919 S = MCDisassembler::SoftFail; 1920 } 1921 1922 return S; 1923 } 1924 1925 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1926 uint64_t Address, const void *Decoder) { 1927 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1928 unsigned M = fieldFromInstruction(Insn, 8, 1); 1929 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1930 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1931 1932 DecodeStatus S = MCDisassembler::Success; 1933 1934 // imod == '01' --> UNPREDICTABLE 1935 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1936 // return failure here. The '01' imod value is unprintable, so there's 1937 // nothing useful we could do even if we returned UNPREDICTABLE. 1938 1939 if (imod == 1) return MCDisassembler::Fail; 1940 1941 if (imod && M) { 1942 Inst.setOpcode(ARM::t2CPS3p); 1943 Inst.addOperand(MCOperand::CreateImm(imod)); 1944 Inst.addOperand(MCOperand::CreateImm(iflags)); 1945 Inst.addOperand(MCOperand::CreateImm(mode)); 1946 } else if (imod && !M) { 1947 Inst.setOpcode(ARM::t2CPS2p); 1948 Inst.addOperand(MCOperand::CreateImm(imod)); 1949 Inst.addOperand(MCOperand::CreateImm(iflags)); 1950 if (mode) S = MCDisassembler::SoftFail; 1951 } else if (!imod && M) { 1952 Inst.setOpcode(ARM::t2CPS1p); 1953 Inst.addOperand(MCOperand::CreateImm(mode)); 1954 if (iflags) S = MCDisassembler::SoftFail; 1955 } else { 1956 // imod == '00' && M == '0' --> UNPREDICTABLE 1957 Inst.setOpcode(ARM::t2CPS1p); 1958 Inst.addOperand(MCOperand::CreateImm(mode)); 1959 S = MCDisassembler::SoftFail; 1960 } 1961 1962 return S; 1963 } 1964 1965 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 DecodeStatus S = MCDisassembler::Success; 1968 1969 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1970 unsigned imm = 0; 1971 1972 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1973 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1974 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1975 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1976 1977 if (Inst.getOpcode() == ARM::t2MOVTi16) 1978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 1983 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1984 Inst.addOperand(MCOperand::CreateImm(imm)); 1985 1986 return S; 1987 } 1988 1989 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1990 uint64_t Address, const void *Decoder) { 1991 DecodeStatus S = MCDisassembler::Success; 1992 1993 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1994 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1995 unsigned imm = 0; 1996 1997 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 1998 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1999 2000 if (Inst.getOpcode() == ARM::MOVTi16) 2001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2002 return MCDisassembler::Fail; 2003 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2004 return MCDisassembler::Fail; 2005 2006 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2007 Inst.addOperand(MCOperand::CreateImm(imm)); 2008 2009 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 2012 return S; 2013 } 2014 2015 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2016 uint64_t Address, const void *Decoder) { 2017 DecodeStatus S = MCDisassembler::Success; 2018 2019 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2020 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2021 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2022 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2023 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2024 2025 if (pred == 0xF) 2026 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2027 2028 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2029 return MCDisassembler::Fail; 2030 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2031 return MCDisassembler::Fail; 2032 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2033 return MCDisassembler::Fail; 2034 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2035 return MCDisassembler::Fail; 2036 2037 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2038 return MCDisassembler::Fail; 2039 2040 return S; 2041 } 2042 2043 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2044 uint64_t Address, const void *Decoder) { 2045 DecodeStatus S = MCDisassembler::Success; 2046 2047 unsigned add = fieldFromInstruction(Val, 12, 1); 2048 unsigned imm = fieldFromInstruction(Val, 0, 12); 2049 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2050 2051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2052 return MCDisassembler::Fail; 2053 2054 if (!add) imm *= -1; 2055 if (imm == 0 && !add) imm = INT32_MIN; 2056 Inst.addOperand(MCOperand::CreateImm(imm)); 2057 if (Rn == 15) 2058 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2059 2060 return S; 2061 } 2062 2063 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2064 uint64_t Address, const void *Decoder) { 2065 DecodeStatus S = MCDisassembler::Success; 2066 2067 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2068 unsigned U = fieldFromInstruction(Val, 8, 1); 2069 unsigned imm = fieldFromInstruction(Val, 0, 8); 2070 2071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 2074 if (U) 2075 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2076 else 2077 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2078 2079 return S; 2080 } 2081 2082 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2083 uint64_t Address, const void *Decoder) { 2084 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2085 } 2086 2087 static DecodeStatus 2088 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2089 uint64_t Address, const void *Decoder) { 2090 DecodeStatus Status = MCDisassembler::Success; 2091 2092 // Note the J1 and J2 values are from the encoded instruction. So here 2093 // change them to I1 and I2 values via as documented: 2094 // I1 = NOT(J1 EOR S); 2095 // I2 = NOT(J2 EOR S); 2096 // and build the imm32 with one trailing zero as documented: 2097 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2098 unsigned S = fieldFromInstruction(Insn, 26, 1); 2099 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2100 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2101 unsigned I1 = !(J1 ^ S); 2102 unsigned I2 = !(J2 ^ S); 2103 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2104 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2105 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2106 int imm32 = SignExtend32<24>(tmp << 1); 2107 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2108 true, 4, Inst, Decoder)) 2109 Inst.addOperand(MCOperand::CreateImm(imm32)); 2110 2111 return Status; 2112 } 2113 2114 static DecodeStatus 2115 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2116 uint64_t Address, const void *Decoder) { 2117 DecodeStatus S = MCDisassembler::Success; 2118 2119 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2120 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2121 2122 if (pred == 0xF) { 2123 Inst.setOpcode(ARM::BLXi); 2124 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2125 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2126 true, 4, Inst, Decoder)) 2127 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2128 return S; 2129 } 2130 2131 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2132 true, 4, Inst, Decoder)) 2133 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2134 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 2137 return S; 2138 } 2139 2140 2141 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2142 uint64_t Address, const void *Decoder) { 2143 DecodeStatus S = MCDisassembler::Success; 2144 2145 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2146 unsigned align = fieldFromInstruction(Val, 4, 2); 2147 2148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2149 return MCDisassembler::Fail; 2150 if (!align) 2151 Inst.addOperand(MCOperand::CreateImm(0)); 2152 else 2153 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2154 2155 return S; 2156 } 2157 2158 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2159 uint64_t Address, const void *Decoder) { 2160 DecodeStatus S = MCDisassembler::Success; 2161 2162 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2163 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2164 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2165 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2166 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2167 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2168 2169 // First output register 2170 switch (Inst.getOpcode()) { 2171 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2172 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2173 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2174 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2175 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2176 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2177 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2178 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2179 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2180 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2181 return MCDisassembler::Fail; 2182 break; 2183 case ARM::VLD2b16: 2184 case ARM::VLD2b32: 2185 case ARM::VLD2b8: 2186 case ARM::VLD2b16wb_fixed: 2187 case ARM::VLD2b16wb_register: 2188 case ARM::VLD2b32wb_fixed: 2189 case ARM::VLD2b32wb_register: 2190 case ARM::VLD2b8wb_fixed: 2191 case ARM::VLD2b8wb_register: 2192 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2193 return MCDisassembler::Fail; 2194 break; 2195 default: 2196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2197 return MCDisassembler::Fail; 2198 } 2199 2200 // Second output register 2201 switch (Inst.getOpcode()) { 2202 case ARM::VLD3d8: 2203 case ARM::VLD3d16: 2204 case ARM::VLD3d32: 2205 case ARM::VLD3d8_UPD: 2206 case ARM::VLD3d16_UPD: 2207 case ARM::VLD3d32_UPD: 2208 case ARM::VLD4d8: 2209 case ARM::VLD4d16: 2210 case ARM::VLD4d32: 2211 case ARM::VLD4d8_UPD: 2212 case ARM::VLD4d16_UPD: 2213 case ARM::VLD4d32_UPD: 2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 break; 2217 case ARM::VLD3q8: 2218 case ARM::VLD3q16: 2219 case ARM::VLD3q32: 2220 case ARM::VLD3q8_UPD: 2221 case ARM::VLD3q16_UPD: 2222 case ARM::VLD3q32_UPD: 2223 case ARM::VLD4q8: 2224 case ARM::VLD4q16: 2225 case ARM::VLD4q32: 2226 case ARM::VLD4q8_UPD: 2227 case ARM::VLD4q16_UPD: 2228 case ARM::VLD4q32_UPD: 2229 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2230 return MCDisassembler::Fail; 2231 default: 2232 break; 2233 } 2234 2235 // Third output register 2236 switch(Inst.getOpcode()) { 2237 case ARM::VLD3d8: 2238 case ARM::VLD3d16: 2239 case ARM::VLD3d32: 2240 case ARM::VLD3d8_UPD: 2241 case ARM::VLD3d16_UPD: 2242 case ARM::VLD3d32_UPD: 2243 case ARM::VLD4d8: 2244 case ARM::VLD4d16: 2245 case ARM::VLD4d32: 2246 case ARM::VLD4d8_UPD: 2247 case ARM::VLD4d16_UPD: 2248 case ARM::VLD4d32_UPD: 2249 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2250 return MCDisassembler::Fail; 2251 break; 2252 case ARM::VLD3q8: 2253 case ARM::VLD3q16: 2254 case ARM::VLD3q32: 2255 case ARM::VLD3q8_UPD: 2256 case ARM::VLD3q16_UPD: 2257 case ARM::VLD3q32_UPD: 2258 case ARM::VLD4q8: 2259 case ARM::VLD4q16: 2260 case ARM::VLD4q32: 2261 case ARM::VLD4q8_UPD: 2262 case ARM::VLD4q16_UPD: 2263 case ARM::VLD4q32_UPD: 2264 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2265 return MCDisassembler::Fail; 2266 break; 2267 default: 2268 break; 2269 } 2270 2271 // Fourth output register 2272 switch (Inst.getOpcode()) { 2273 case ARM::VLD4d8: 2274 case ARM::VLD4d16: 2275 case ARM::VLD4d32: 2276 case ARM::VLD4d8_UPD: 2277 case ARM::VLD4d16_UPD: 2278 case ARM::VLD4d32_UPD: 2279 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2280 return MCDisassembler::Fail; 2281 break; 2282 case ARM::VLD4q8: 2283 case ARM::VLD4q16: 2284 case ARM::VLD4q32: 2285 case ARM::VLD4q8_UPD: 2286 case ARM::VLD4q16_UPD: 2287 case ARM::VLD4q32_UPD: 2288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2289 return MCDisassembler::Fail; 2290 break; 2291 default: 2292 break; 2293 } 2294 2295 // Writeback operand 2296 switch (Inst.getOpcode()) { 2297 case ARM::VLD1d8wb_fixed: 2298 case ARM::VLD1d16wb_fixed: 2299 case ARM::VLD1d32wb_fixed: 2300 case ARM::VLD1d64wb_fixed: 2301 case ARM::VLD1d8wb_register: 2302 case ARM::VLD1d16wb_register: 2303 case ARM::VLD1d32wb_register: 2304 case ARM::VLD1d64wb_register: 2305 case ARM::VLD1q8wb_fixed: 2306 case ARM::VLD1q16wb_fixed: 2307 case ARM::VLD1q32wb_fixed: 2308 case ARM::VLD1q64wb_fixed: 2309 case ARM::VLD1q8wb_register: 2310 case ARM::VLD1q16wb_register: 2311 case ARM::VLD1q32wb_register: 2312 case ARM::VLD1q64wb_register: 2313 case ARM::VLD1d8Twb_fixed: 2314 case ARM::VLD1d8Twb_register: 2315 case ARM::VLD1d16Twb_fixed: 2316 case ARM::VLD1d16Twb_register: 2317 case ARM::VLD1d32Twb_fixed: 2318 case ARM::VLD1d32Twb_register: 2319 case ARM::VLD1d64Twb_fixed: 2320 case ARM::VLD1d64Twb_register: 2321 case ARM::VLD1d8Qwb_fixed: 2322 case ARM::VLD1d8Qwb_register: 2323 case ARM::VLD1d16Qwb_fixed: 2324 case ARM::VLD1d16Qwb_register: 2325 case ARM::VLD1d32Qwb_fixed: 2326 case ARM::VLD1d32Qwb_register: 2327 case ARM::VLD1d64Qwb_fixed: 2328 case ARM::VLD1d64Qwb_register: 2329 case ARM::VLD2d8wb_fixed: 2330 case ARM::VLD2d16wb_fixed: 2331 case ARM::VLD2d32wb_fixed: 2332 case ARM::VLD2q8wb_fixed: 2333 case ARM::VLD2q16wb_fixed: 2334 case ARM::VLD2q32wb_fixed: 2335 case ARM::VLD2d8wb_register: 2336 case ARM::VLD2d16wb_register: 2337 case ARM::VLD2d32wb_register: 2338 case ARM::VLD2q8wb_register: 2339 case ARM::VLD2q16wb_register: 2340 case ARM::VLD2q32wb_register: 2341 case ARM::VLD2b8wb_fixed: 2342 case ARM::VLD2b16wb_fixed: 2343 case ARM::VLD2b32wb_fixed: 2344 case ARM::VLD2b8wb_register: 2345 case ARM::VLD2b16wb_register: 2346 case ARM::VLD2b32wb_register: 2347 Inst.addOperand(MCOperand::CreateImm(0)); 2348 break; 2349 case ARM::VLD3d8_UPD: 2350 case ARM::VLD3d16_UPD: 2351 case ARM::VLD3d32_UPD: 2352 case ARM::VLD3q8_UPD: 2353 case ARM::VLD3q16_UPD: 2354 case ARM::VLD3q32_UPD: 2355 case ARM::VLD4d8_UPD: 2356 case ARM::VLD4d16_UPD: 2357 case ARM::VLD4d32_UPD: 2358 case ARM::VLD4q8_UPD: 2359 case ARM::VLD4q16_UPD: 2360 case ARM::VLD4q32_UPD: 2361 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2362 return MCDisassembler::Fail; 2363 break; 2364 default: 2365 break; 2366 } 2367 2368 // AddrMode6 Base (register+alignment) 2369 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 2372 // AddrMode6 Offset (register) 2373 switch (Inst.getOpcode()) { 2374 default: 2375 // The below have been updated to have explicit am6offset split 2376 // between fixed and register offset. For those instructions not 2377 // yet updated, we need to add an additional reg0 operand for the 2378 // fixed variant. 2379 // 2380 // The fixed offset encodes as Rm == 0xd, so we check for that. 2381 if (Rm == 0xd) { 2382 Inst.addOperand(MCOperand::CreateReg(0)); 2383 break; 2384 } 2385 // Fall through to handle the register offset variant. 2386 case ARM::VLD1d8wb_fixed: 2387 case ARM::VLD1d16wb_fixed: 2388 case ARM::VLD1d32wb_fixed: 2389 case ARM::VLD1d64wb_fixed: 2390 case ARM::VLD1d8Twb_fixed: 2391 case ARM::VLD1d16Twb_fixed: 2392 case ARM::VLD1d32Twb_fixed: 2393 case ARM::VLD1d64Twb_fixed: 2394 case ARM::VLD1d8Qwb_fixed: 2395 case ARM::VLD1d16Qwb_fixed: 2396 case ARM::VLD1d32Qwb_fixed: 2397 case ARM::VLD1d64Qwb_fixed: 2398 case ARM::VLD1d8wb_register: 2399 case ARM::VLD1d16wb_register: 2400 case ARM::VLD1d32wb_register: 2401 case ARM::VLD1d64wb_register: 2402 case ARM::VLD1q8wb_fixed: 2403 case ARM::VLD1q16wb_fixed: 2404 case ARM::VLD1q32wb_fixed: 2405 case ARM::VLD1q64wb_fixed: 2406 case ARM::VLD1q8wb_register: 2407 case ARM::VLD1q16wb_register: 2408 case ARM::VLD1q32wb_register: 2409 case ARM::VLD1q64wb_register: 2410 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2411 // variant encodes Rm == 0xf. Anything else is a register offset post- 2412 // increment and we need to add the register operand to the instruction. 2413 if (Rm != 0xD && Rm != 0xF && 2414 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2415 return MCDisassembler::Fail; 2416 break; 2417 case ARM::VLD2d8wb_fixed: 2418 case ARM::VLD2d16wb_fixed: 2419 case ARM::VLD2d32wb_fixed: 2420 case ARM::VLD2b8wb_fixed: 2421 case ARM::VLD2b16wb_fixed: 2422 case ARM::VLD2b32wb_fixed: 2423 case ARM::VLD2q8wb_fixed: 2424 case ARM::VLD2q16wb_fixed: 2425 case ARM::VLD2q32wb_fixed: 2426 break; 2427 } 2428 2429 return S; 2430 } 2431 2432 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2433 uint64_t Address, const void *Decoder) { 2434 DecodeStatus S = MCDisassembler::Success; 2435 2436 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2437 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2438 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2439 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2440 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2441 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2442 2443 // Writeback Operand 2444 switch (Inst.getOpcode()) { 2445 case ARM::VST1d8wb_fixed: 2446 case ARM::VST1d16wb_fixed: 2447 case ARM::VST1d32wb_fixed: 2448 case ARM::VST1d64wb_fixed: 2449 case ARM::VST1d8wb_register: 2450 case ARM::VST1d16wb_register: 2451 case ARM::VST1d32wb_register: 2452 case ARM::VST1d64wb_register: 2453 case ARM::VST1q8wb_fixed: 2454 case ARM::VST1q16wb_fixed: 2455 case ARM::VST1q32wb_fixed: 2456 case ARM::VST1q64wb_fixed: 2457 case ARM::VST1q8wb_register: 2458 case ARM::VST1q16wb_register: 2459 case ARM::VST1q32wb_register: 2460 case ARM::VST1q64wb_register: 2461 case ARM::VST1d8Twb_fixed: 2462 case ARM::VST1d16Twb_fixed: 2463 case ARM::VST1d32Twb_fixed: 2464 case ARM::VST1d64Twb_fixed: 2465 case ARM::VST1d8Twb_register: 2466 case ARM::VST1d16Twb_register: 2467 case ARM::VST1d32Twb_register: 2468 case ARM::VST1d64Twb_register: 2469 case ARM::VST1d8Qwb_fixed: 2470 case ARM::VST1d16Qwb_fixed: 2471 case ARM::VST1d32Qwb_fixed: 2472 case ARM::VST1d64Qwb_fixed: 2473 case ARM::VST1d8Qwb_register: 2474 case ARM::VST1d16Qwb_register: 2475 case ARM::VST1d32Qwb_register: 2476 case ARM::VST1d64Qwb_register: 2477 case ARM::VST2d8wb_fixed: 2478 case ARM::VST2d16wb_fixed: 2479 case ARM::VST2d32wb_fixed: 2480 case ARM::VST2d8wb_register: 2481 case ARM::VST2d16wb_register: 2482 case ARM::VST2d32wb_register: 2483 case ARM::VST2q8wb_fixed: 2484 case ARM::VST2q16wb_fixed: 2485 case ARM::VST2q32wb_fixed: 2486 case ARM::VST2q8wb_register: 2487 case ARM::VST2q16wb_register: 2488 case ARM::VST2q32wb_register: 2489 case ARM::VST2b8wb_fixed: 2490 case ARM::VST2b16wb_fixed: 2491 case ARM::VST2b32wb_fixed: 2492 case ARM::VST2b8wb_register: 2493 case ARM::VST2b16wb_register: 2494 case ARM::VST2b32wb_register: 2495 if (Rm == 0xF) 2496 return MCDisassembler::Fail; 2497 Inst.addOperand(MCOperand::CreateImm(0)); 2498 break; 2499 case ARM::VST3d8_UPD: 2500 case ARM::VST3d16_UPD: 2501 case ARM::VST3d32_UPD: 2502 case ARM::VST3q8_UPD: 2503 case ARM::VST3q16_UPD: 2504 case ARM::VST3q32_UPD: 2505 case ARM::VST4d8_UPD: 2506 case ARM::VST4d16_UPD: 2507 case ARM::VST4d32_UPD: 2508 case ARM::VST4q8_UPD: 2509 case ARM::VST4q16_UPD: 2510 case ARM::VST4q32_UPD: 2511 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2512 return MCDisassembler::Fail; 2513 break; 2514 default: 2515 break; 2516 } 2517 2518 // AddrMode6 Base (register+alignment) 2519 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2520 return MCDisassembler::Fail; 2521 2522 // AddrMode6 Offset (register) 2523 switch (Inst.getOpcode()) { 2524 default: 2525 if (Rm == 0xD) 2526 Inst.addOperand(MCOperand::CreateReg(0)); 2527 else if (Rm != 0xF) { 2528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2529 return MCDisassembler::Fail; 2530 } 2531 break; 2532 case ARM::VST1d8wb_fixed: 2533 case ARM::VST1d16wb_fixed: 2534 case ARM::VST1d32wb_fixed: 2535 case ARM::VST1d64wb_fixed: 2536 case ARM::VST1q8wb_fixed: 2537 case ARM::VST1q16wb_fixed: 2538 case ARM::VST1q32wb_fixed: 2539 case ARM::VST1q64wb_fixed: 2540 case ARM::VST1d8Twb_fixed: 2541 case ARM::VST1d16Twb_fixed: 2542 case ARM::VST1d32Twb_fixed: 2543 case ARM::VST1d64Twb_fixed: 2544 case ARM::VST1d8Qwb_fixed: 2545 case ARM::VST1d16Qwb_fixed: 2546 case ARM::VST1d32Qwb_fixed: 2547 case ARM::VST1d64Qwb_fixed: 2548 case ARM::VST2d8wb_fixed: 2549 case ARM::VST2d16wb_fixed: 2550 case ARM::VST2d32wb_fixed: 2551 case ARM::VST2q8wb_fixed: 2552 case ARM::VST2q16wb_fixed: 2553 case ARM::VST2q32wb_fixed: 2554 case ARM::VST2b8wb_fixed: 2555 case ARM::VST2b16wb_fixed: 2556 case ARM::VST2b32wb_fixed: 2557 break; 2558 } 2559 2560 2561 // First input register 2562 switch (Inst.getOpcode()) { 2563 case ARM::VST1q16: 2564 case ARM::VST1q32: 2565 case ARM::VST1q64: 2566 case ARM::VST1q8: 2567 case ARM::VST1q16wb_fixed: 2568 case ARM::VST1q16wb_register: 2569 case ARM::VST1q32wb_fixed: 2570 case ARM::VST1q32wb_register: 2571 case ARM::VST1q64wb_fixed: 2572 case ARM::VST1q64wb_register: 2573 case ARM::VST1q8wb_fixed: 2574 case ARM::VST1q8wb_register: 2575 case ARM::VST2d16: 2576 case ARM::VST2d32: 2577 case ARM::VST2d8: 2578 case ARM::VST2d16wb_fixed: 2579 case ARM::VST2d16wb_register: 2580 case ARM::VST2d32wb_fixed: 2581 case ARM::VST2d32wb_register: 2582 case ARM::VST2d8wb_fixed: 2583 case ARM::VST2d8wb_register: 2584 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2585 return MCDisassembler::Fail; 2586 break; 2587 case ARM::VST2b16: 2588 case ARM::VST2b32: 2589 case ARM::VST2b8: 2590 case ARM::VST2b16wb_fixed: 2591 case ARM::VST2b16wb_register: 2592 case ARM::VST2b32wb_fixed: 2593 case ARM::VST2b32wb_register: 2594 case ARM::VST2b8wb_fixed: 2595 case ARM::VST2b8wb_register: 2596 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2597 return MCDisassembler::Fail; 2598 break; 2599 default: 2600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2601 return MCDisassembler::Fail; 2602 } 2603 2604 // Second input register 2605 switch (Inst.getOpcode()) { 2606 case ARM::VST3d8: 2607 case ARM::VST3d16: 2608 case ARM::VST3d32: 2609 case ARM::VST3d8_UPD: 2610 case ARM::VST3d16_UPD: 2611 case ARM::VST3d32_UPD: 2612 case ARM::VST4d8: 2613 case ARM::VST4d16: 2614 case ARM::VST4d32: 2615 case ARM::VST4d8_UPD: 2616 case ARM::VST4d16_UPD: 2617 case ARM::VST4d32_UPD: 2618 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 break; 2621 case ARM::VST3q8: 2622 case ARM::VST3q16: 2623 case ARM::VST3q32: 2624 case ARM::VST3q8_UPD: 2625 case ARM::VST3q16_UPD: 2626 case ARM::VST3q32_UPD: 2627 case ARM::VST4q8: 2628 case ARM::VST4q16: 2629 case ARM::VST4q32: 2630 case ARM::VST4q8_UPD: 2631 case ARM::VST4q16_UPD: 2632 case ARM::VST4q32_UPD: 2633 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2634 return MCDisassembler::Fail; 2635 break; 2636 default: 2637 break; 2638 } 2639 2640 // Third input register 2641 switch (Inst.getOpcode()) { 2642 case ARM::VST3d8: 2643 case ARM::VST3d16: 2644 case ARM::VST3d32: 2645 case ARM::VST3d8_UPD: 2646 case ARM::VST3d16_UPD: 2647 case ARM::VST3d32_UPD: 2648 case ARM::VST4d8: 2649 case ARM::VST4d16: 2650 case ARM::VST4d32: 2651 case ARM::VST4d8_UPD: 2652 case ARM::VST4d16_UPD: 2653 case ARM::VST4d32_UPD: 2654 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 break; 2657 case ARM::VST3q8: 2658 case ARM::VST3q16: 2659 case ARM::VST3q32: 2660 case ARM::VST3q8_UPD: 2661 case ARM::VST3q16_UPD: 2662 case ARM::VST3q32_UPD: 2663 case ARM::VST4q8: 2664 case ARM::VST4q16: 2665 case ARM::VST4q32: 2666 case ARM::VST4q8_UPD: 2667 case ARM::VST4q16_UPD: 2668 case ARM::VST4q32_UPD: 2669 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2670 return MCDisassembler::Fail; 2671 break; 2672 default: 2673 break; 2674 } 2675 2676 // Fourth input register 2677 switch (Inst.getOpcode()) { 2678 case ARM::VST4d8: 2679 case ARM::VST4d16: 2680 case ARM::VST4d32: 2681 case ARM::VST4d8_UPD: 2682 case ARM::VST4d16_UPD: 2683 case ARM::VST4d32_UPD: 2684 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2685 return MCDisassembler::Fail; 2686 break; 2687 case ARM::VST4q8: 2688 case ARM::VST4q16: 2689 case ARM::VST4q32: 2690 case ARM::VST4q8_UPD: 2691 case ARM::VST4q16_UPD: 2692 case ARM::VST4q32_UPD: 2693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2694 return MCDisassembler::Fail; 2695 break; 2696 default: 2697 break; 2698 } 2699 2700 return S; 2701 } 2702 2703 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2704 uint64_t Address, const void *Decoder) { 2705 DecodeStatus S = MCDisassembler::Success; 2706 2707 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2708 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2709 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2710 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2711 unsigned align = fieldFromInstruction(Insn, 4, 1); 2712 unsigned size = fieldFromInstruction(Insn, 6, 2); 2713 2714 if (size == 0 && align == 1) 2715 return MCDisassembler::Fail; 2716 align *= (1 << size); 2717 2718 switch (Inst.getOpcode()) { 2719 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2720 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2721 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2722 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2723 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 break; 2726 default: 2727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2728 return MCDisassembler::Fail; 2729 break; 2730 } 2731 if (Rm != 0xF) { 2732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 } 2735 2736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2737 return MCDisassembler::Fail; 2738 Inst.addOperand(MCOperand::CreateImm(align)); 2739 2740 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2741 // variant encodes Rm == 0xf. Anything else is a register offset post- 2742 // increment and we need to add the register operand to the instruction. 2743 if (Rm != 0xD && Rm != 0xF && 2744 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 2747 return S; 2748 } 2749 2750 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2751 uint64_t Address, const void *Decoder) { 2752 DecodeStatus S = MCDisassembler::Success; 2753 2754 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2755 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2756 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2757 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2758 unsigned align = fieldFromInstruction(Insn, 4, 1); 2759 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2760 align *= 2*size; 2761 2762 switch (Inst.getOpcode()) { 2763 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2764 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2765 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2766 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2767 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2768 return MCDisassembler::Fail; 2769 break; 2770 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2771 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2772 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2773 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2774 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2775 return MCDisassembler::Fail; 2776 break; 2777 default: 2778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2779 return MCDisassembler::Fail; 2780 break; 2781 } 2782 2783 if (Rm != 0xF) 2784 Inst.addOperand(MCOperand::CreateImm(0)); 2785 2786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 Inst.addOperand(MCOperand::CreateImm(align)); 2789 2790 if (Rm != 0xD && Rm != 0xF) { 2791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2792 return MCDisassembler::Fail; 2793 } 2794 2795 return S; 2796 } 2797 2798 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2799 uint64_t Address, const void *Decoder) { 2800 DecodeStatus S = MCDisassembler::Success; 2801 2802 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2803 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2804 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2805 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2806 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2807 2808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2811 return MCDisassembler::Fail; 2812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2813 return MCDisassembler::Fail; 2814 if (Rm != 0xF) { 2815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2816 return MCDisassembler::Fail; 2817 } 2818 2819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2820 return MCDisassembler::Fail; 2821 Inst.addOperand(MCOperand::CreateImm(0)); 2822 2823 if (Rm == 0xD) 2824 Inst.addOperand(MCOperand::CreateReg(0)); 2825 else if (Rm != 0xF) { 2826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 } 2829 2830 return S; 2831 } 2832 2833 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2834 uint64_t Address, const void *Decoder) { 2835 DecodeStatus S = MCDisassembler::Success; 2836 2837 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2840 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2841 unsigned size = fieldFromInstruction(Insn, 6, 2); 2842 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2843 unsigned align = fieldFromInstruction(Insn, 4, 1); 2844 2845 if (size == 0x3) { 2846 if (align == 0) 2847 return MCDisassembler::Fail; 2848 size = 4; 2849 align = 16; 2850 } else { 2851 if (size == 2) { 2852 size = 1 << size; 2853 align *= 8; 2854 } else { 2855 size = 1 << size; 2856 align *= 4*size; 2857 } 2858 } 2859 2860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2861 return MCDisassembler::Fail; 2862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2865 return MCDisassembler::Fail; 2866 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2867 return MCDisassembler::Fail; 2868 if (Rm != 0xF) { 2869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2870 return MCDisassembler::Fail; 2871 } 2872 2873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2874 return MCDisassembler::Fail; 2875 Inst.addOperand(MCOperand::CreateImm(align)); 2876 2877 if (Rm == 0xD) 2878 Inst.addOperand(MCOperand::CreateReg(0)); 2879 else if (Rm != 0xF) { 2880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 } 2883 2884 return S; 2885 } 2886 2887 static DecodeStatus 2888 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2889 uint64_t Address, const void *Decoder) { 2890 DecodeStatus S = MCDisassembler::Success; 2891 2892 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2893 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2894 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2895 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2896 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2897 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2898 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2899 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2900 2901 if (Q) { 2902 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2903 return MCDisassembler::Fail; 2904 } else { 2905 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 } 2908 2909 Inst.addOperand(MCOperand::CreateImm(imm)); 2910 2911 switch (Inst.getOpcode()) { 2912 case ARM::VORRiv4i16: 2913 case ARM::VORRiv2i32: 2914 case ARM::VBICiv4i16: 2915 case ARM::VBICiv2i32: 2916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 break; 2919 case ARM::VORRiv8i16: 2920 case ARM::VORRiv4i32: 2921 case ARM::VBICiv8i16: 2922 case ARM::VBICiv4i32: 2923 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 break; 2926 default: 2927 break; 2928 } 2929 2930 return S; 2931 } 2932 2933 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2934 uint64_t Address, const void *Decoder) { 2935 DecodeStatus S = MCDisassembler::Success; 2936 2937 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2938 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2940 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2941 unsigned size = fieldFromInstruction(Insn, 18, 2); 2942 2943 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2948 2949 return S; 2950 } 2951 2952 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2953 uint64_t Address, const void *Decoder) { 2954 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2955 return MCDisassembler::Success; 2956 } 2957 2958 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2959 uint64_t Address, const void *Decoder) { 2960 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2961 return MCDisassembler::Success; 2962 } 2963 2964 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2965 uint64_t Address, const void *Decoder) { 2966 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2967 return MCDisassembler::Success; 2968 } 2969 2970 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2971 uint64_t Address, const void *Decoder) { 2972 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2973 return MCDisassembler::Success; 2974 } 2975 2976 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2977 uint64_t Address, const void *Decoder) { 2978 DecodeStatus S = MCDisassembler::Success; 2979 2980 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2981 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2982 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2983 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2984 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2985 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2986 unsigned op = fieldFromInstruction(Insn, 6, 1); 2987 2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2989 return MCDisassembler::Fail; 2990 if (op) { 2991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2992 return MCDisassembler::Fail; // Writeback 2993 } 2994 2995 switch (Inst.getOpcode()) { 2996 case ARM::VTBL2: 2997 case ARM::VTBX2: 2998 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 break; 3001 default: 3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 } 3005 3006 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 3009 return S; 3010 } 3011 3012 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3013 uint64_t Address, const void *Decoder) { 3014 DecodeStatus S = MCDisassembler::Success; 3015 3016 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3017 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3018 3019 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3020 return MCDisassembler::Fail; 3021 3022 switch(Inst.getOpcode()) { 3023 default: 3024 return MCDisassembler::Fail; 3025 case ARM::tADR: 3026 break; // tADR does not explicitly represent the PC as an operand. 3027 case ARM::tADDrSPi: 3028 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3029 break; 3030 } 3031 3032 Inst.addOperand(MCOperand::CreateImm(imm)); 3033 return S; 3034 } 3035 3036 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3037 uint64_t Address, const void *Decoder) { 3038 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3039 true, 2, Inst, Decoder)) 3040 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3041 return MCDisassembler::Success; 3042 } 3043 3044 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3045 uint64_t Address, const void *Decoder) { 3046 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3047 true, 4, Inst, Decoder)) 3048 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3049 return MCDisassembler::Success; 3050 } 3051 3052 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3053 uint64_t Address, const void *Decoder) { 3054 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3055 true, 2, Inst, Decoder)) 3056 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3057 return MCDisassembler::Success; 3058 } 3059 3060 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3061 uint64_t Address, const void *Decoder) { 3062 DecodeStatus S = MCDisassembler::Success; 3063 3064 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3065 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3066 3067 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3068 return MCDisassembler::Fail; 3069 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 3072 return S; 3073 } 3074 3075 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3076 uint64_t Address, const void *Decoder) { 3077 DecodeStatus S = MCDisassembler::Success; 3078 3079 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3080 unsigned imm = fieldFromInstruction(Val, 3, 5); 3081 3082 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 Inst.addOperand(MCOperand::CreateImm(imm)); 3085 3086 return S; 3087 } 3088 3089 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3090 uint64_t Address, const void *Decoder) { 3091 unsigned imm = Val << 2; 3092 3093 Inst.addOperand(MCOperand::CreateImm(imm)); 3094 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3095 3096 return MCDisassembler::Success; 3097 } 3098 3099 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3100 uint64_t Address, const void *Decoder) { 3101 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3102 Inst.addOperand(MCOperand::CreateImm(Val)); 3103 3104 return MCDisassembler::Success; 3105 } 3106 3107 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3108 uint64_t Address, const void *Decoder) { 3109 DecodeStatus S = MCDisassembler::Success; 3110 3111 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3112 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3113 unsigned imm = fieldFromInstruction(Val, 0, 2); 3114 3115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3116 return MCDisassembler::Fail; 3117 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 Inst.addOperand(MCOperand::CreateImm(imm)); 3120 3121 return S; 3122 } 3123 3124 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3125 uint64_t Address, const void *Decoder) { 3126 DecodeStatus S = MCDisassembler::Success; 3127 3128 switch (Inst.getOpcode()) { 3129 case ARM::t2PLDs: 3130 case ARM::t2PLDWs: 3131 case ARM::t2PLIs: 3132 break; 3133 default: { 3134 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3135 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3136 return MCDisassembler::Fail; 3137 } 3138 } 3139 3140 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3141 if (Rn == 0xF) { 3142 switch (Inst.getOpcode()) { 3143 case ARM::t2LDRBs: 3144 Inst.setOpcode(ARM::t2LDRBpci); 3145 break; 3146 case ARM::t2LDRHs: 3147 Inst.setOpcode(ARM::t2LDRHpci); 3148 break; 3149 case ARM::t2LDRSHs: 3150 Inst.setOpcode(ARM::t2LDRSHpci); 3151 break; 3152 case ARM::t2LDRSBs: 3153 Inst.setOpcode(ARM::t2LDRSBpci); 3154 break; 3155 case ARM::t2PLDs: 3156 Inst.setOpcode(ARM::t2PLDi12); 3157 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3158 break; 3159 default: 3160 return MCDisassembler::Fail; 3161 } 3162 3163 int imm = fieldFromInstruction(Insn, 0, 12); 3164 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3165 Inst.addOperand(MCOperand::CreateImm(imm)); 3166 3167 return S; 3168 } 3169 3170 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3171 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3172 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3173 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3174 return MCDisassembler::Fail; 3175 3176 return S; 3177 } 3178 3179 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3180 uint64_t Address, const void *Decoder) { 3181 if (Val == 0) 3182 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3183 else { 3184 int imm = Val & 0xFF; 3185 3186 if (!(Val & 0x100)) imm *= -1; 3187 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3188 } 3189 3190 return MCDisassembler::Success; 3191 } 3192 3193 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3194 uint64_t Address, const void *Decoder) { 3195 DecodeStatus S = MCDisassembler::Success; 3196 3197 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3198 unsigned imm = fieldFromInstruction(Val, 0, 9); 3199 3200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3201 return MCDisassembler::Fail; 3202 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3203 return MCDisassembler::Fail; 3204 3205 return S; 3206 } 3207 3208 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3209 uint64_t Address, const void *Decoder) { 3210 DecodeStatus S = MCDisassembler::Success; 3211 3212 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3213 unsigned imm = fieldFromInstruction(Val, 0, 8); 3214 3215 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3216 return MCDisassembler::Fail; 3217 3218 Inst.addOperand(MCOperand::CreateImm(imm)); 3219 3220 return S; 3221 } 3222 3223 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3224 uint64_t Address, const void *Decoder) { 3225 int imm = Val & 0xFF; 3226 if (Val == 0) 3227 imm = INT32_MIN; 3228 else if (!(Val & 0x100)) 3229 imm *= -1; 3230 Inst.addOperand(MCOperand::CreateImm(imm)); 3231 3232 return MCDisassembler::Success; 3233 } 3234 3235 3236 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3237 uint64_t Address, const void *Decoder) { 3238 DecodeStatus S = MCDisassembler::Success; 3239 3240 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3241 unsigned imm = fieldFromInstruction(Val, 0, 9); 3242 3243 // Some instructions always use an additive offset. 3244 switch (Inst.getOpcode()) { 3245 case ARM::t2LDRT: 3246 case ARM::t2LDRBT: 3247 case ARM::t2LDRHT: 3248 case ARM::t2LDRSBT: 3249 case ARM::t2LDRSHT: 3250 case ARM::t2STRT: 3251 case ARM::t2STRBT: 3252 case ARM::t2STRHT: 3253 imm |= 0x100; 3254 break; 3255 default: 3256 break; 3257 } 3258 3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3262 return MCDisassembler::Fail; 3263 3264 return S; 3265 } 3266 3267 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3268 uint64_t Address, const void *Decoder) { 3269 DecodeStatus S = MCDisassembler::Success; 3270 3271 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3272 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3273 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3274 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3275 addr |= Rn << 9; 3276 unsigned load = fieldFromInstruction(Insn, 20, 1); 3277 3278 if (!load) { 3279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 } 3282 3283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3284 return MCDisassembler::Fail; 3285 3286 if (load) { 3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3288 return MCDisassembler::Fail; 3289 } 3290 3291 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 3294 return S; 3295 } 3296 3297 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3298 uint64_t Address, const void *Decoder) { 3299 DecodeStatus S = MCDisassembler::Success; 3300 3301 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3302 unsigned imm = fieldFromInstruction(Val, 0, 12); 3303 3304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 Inst.addOperand(MCOperand::CreateImm(imm)); 3307 3308 return S; 3309 } 3310 3311 3312 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3313 uint64_t Address, const void *Decoder) { 3314 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3315 3316 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3317 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3318 Inst.addOperand(MCOperand::CreateImm(imm)); 3319 3320 return MCDisassembler::Success; 3321 } 3322 3323 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3324 uint64_t Address, const void *Decoder) { 3325 DecodeStatus S = MCDisassembler::Success; 3326 3327 if (Inst.getOpcode() == ARM::tADDrSP) { 3328 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3329 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3330 3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3335 return MCDisassembler::Fail; 3336 } else if (Inst.getOpcode() == ARM::tADDspr) { 3337 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3338 3339 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3340 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3342 return MCDisassembler::Fail; 3343 } 3344 3345 return S; 3346 } 3347 3348 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3349 uint64_t Address, const void *Decoder) { 3350 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3351 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3352 3353 Inst.addOperand(MCOperand::CreateImm(imod)); 3354 Inst.addOperand(MCOperand::CreateImm(flags)); 3355 3356 return MCDisassembler::Success; 3357 } 3358 3359 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3360 uint64_t Address, const void *Decoder) { 3361 DecodeStatus S = MCDisassembler::Success; 3362 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3363 unsigned add = fieldFromInstruction(Insn, 4, 1); 3364 3365 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 Inst.addOperand(MCOperand::CreateImm(add)); 3368 3369 return S; 3370 } 3371 3372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3373 uint64_t Address, const void *Decoder) { 3374 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3375 // Note only one trailing zero not two. Also the J1 and J2 values are from 3376 // the encoded instruction. So here change to I1 and I2 values via: 3377 // I1 = NOT(J1 EOR S); 3378 // I2 = NOT(J2 EOR S); 3379 // and build the imm32 with two trailing zeros as documented: 3380 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3381 unsigned S = (Val >> 23) & 1; 3382 unsigned J1 = (Val >> 22) & 1; 3383 unsigned J2 = (Val >> 21) & 1; 3384 unsigned I1 = !(J1 ^ S); 3385 unsigned I2 = !(J2 ^ S); 3386 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3387 int imm32 = SignExtend32<25>(tmp << 1); 3388 3389 if (!tryAddingSymbolicOperand(Address, 3390 (Address & ~2u) + imm32 + 4, 3391 true, 4, Inst, Decoder)) 3392 Inst.addOperand(MCOperand::CreateImm(imm32)); 3393 return MCDisassembler::Success; 3394 } 3395 3396 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3397 uint64_t Address, const void *Decoder) { 3398 if (Val == 0xA || Val == 0xB) 3399 return MCDisassembler::Fail; 3400 3401 Inst.addOperand(MCOperand::CreateImm(Val)); 3402 return MCDisassembler::Success; 3403 } 3404 3405 static DecodeStatus 3406 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3407 uint64_t Address, const void *Decoder) { 3408 DecodeStatus S = MCDisassembler::Success; 3409 3410 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3411 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3412 3413 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3417 return MCDisassembler::Fail; 3418 return S; 3419 } 3420 3421 static DecodeStatus 3422 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3423 uint64_t Address, const void *Decoder) { 3424 DecodeStatus S = MCDisassembler::Success; 3425 3426 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3427 if (pred == 0xE || pred == 0xF) { 3428 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3429 switch (opc) { 3430 default: 3431 return MCDisassembler::Fail; 3432 case 0xf3bf8f4: 3433 Inst.setOpcode(ARM::t2DSB); 3434 break; 3435 case 0xf3bf8f5: 3436 Inst.setOpcode(ARM::t2DMB); 3437 break; 3438 case 0xf3bf8f6: 3439 Inst.setOpcode(ARM::t2ISB); 3440 break; 3441 } 3442 3443 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3444 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3445 } 3446 3447 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3448 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3449 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3450 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3451 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3452 3453 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 3458 return S; 3459 } 3460 3461 // Decode a shifted immediate operand. These basically consist 3462 // of an 8-bit value, and a 4-bit directive that specifies either 3463 // a splat operation or a rotation. 3464 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3465 uint64_t Address, const void *Decoder) { 3466 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3467 if (ctrl == 0) { 3468 unsigned byte = fieldFromInstruction(Val, 8, 2); 3469 unsigned imm = fieldFromInstruction(Val, 0, 8); 3470 switch (byte) { 3471 case 0: 3472 Inst.addOperand(MCOperand::CreateImm(imm)); 3473 break; 3474 case 1: 3475 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3476 break; 3477 case 2: 3478 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3479 break; 3480 case 3: 3481 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3482 (imm << 8) | imm)); 3483 break; 3484 } 3485 } else { 3486 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3487 unsigned rot = fieldFromInstruction(Val, 7, 5); 3488 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3489 Inst.addOperand(MCOperand::CreateImm(imm)); 3490 } 3491 3492 return MCDisassembler::Success; 3493 } 3494 3495 static DecodeStatus 3496 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3497 uint64_t Address, const void *Decoder){ 3498 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3499 true, 2, Inst, Decoder)) 3500 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3501 return MCDisassembler::Success; 3502 } 3503 3504 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3505 uint64_t Address, const void *Decoder){ 3506 // Val is passed in as S:J1:J2:imm10:imm11 3507 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3508 // the encoded instruction. So here change to I1 and I2 values via: 3509 // I1 = NOT(J1 EOR S); 3510 // I2 = NOT(J2 EOR S); 3511 // and build the imm32 with one trailing zero as documented: 3512 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3513 unsigned S = (Val >> 23) & 1; 3514 unsigned J1 = (Val >> 22) & 1; 3515 unsigned J2 = (Val >> 21) & 1; 3516 unsigned I1 = !(J1 ^ S); 3517 unsigned I2 = !(J2 ^ S); 3518 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3519 int imm32 = SignExtend32<25>(tmp << 1); 3520 3521 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3522 true, 4, Inst, Decoder)) 3523 Inst.addOperand(MCOperand::CreateImm(imm32)); 3524 return MCDisassembler::Success; 3525 } 3526 3527 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3528 uint64_t Address, const void *Decoder) { 3529 if (Val & ~0xf) 3530 return MCDisassembler::Fail; 3531 3532 Inst.addOperand(MCOperand::CreateImm(Val)); 3533 return MCDisassembler::Success; 3534 } 3535 3536 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3537 uint64_t Address, const void *Decoder) { 3538 if (!Val) return MCDisassembler::Fail; 3539 Inst.addOperand(MCOperand::CreateImm(Val)); 3540 return MCDisassembler::Success; 3541 } 3542 3543 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3544 uint64_t Address, const void *Decoder) { 3545 DecodeStatus S = MCDisassembler::Success; 3546 3547 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3548 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3549 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3550 3551 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3552 3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3554 return MCDisassembler::Fail; 3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 3562 return S; 3563 } 3564 3565 3566 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3567 uint64_t Address, const void *Decoder){ 3568 DecodeStatus S = MCDisassembler::Success; 3569 3570 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3571 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3572 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3573 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3574 3575 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 3578 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3579 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3580 3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3584 return MCDisassembler::Fail; 3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3588 return MCDisassembler::Fail; 3589 3590 return S; 3591 } 3592 3593 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3594 uint64_t Address, const void *Decoder) { 3595 DecodeStatus S = MCDisassembler::Success; 3596 3597 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3598 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3599 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3600 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3601 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3602 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3603 3604 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3605 3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3611 return MCDisassembler::Fail; 3612 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 3615 return S; 3616 } 3617 3618 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3619 uint64_t Address, const void *Decoder) { 3620 DecodeStatus S = MCDisassembler::Success; 3621 3622 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3623 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3624 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3625 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3626 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3627 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3628 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3629 3630 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3631 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3632 3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3640 return MCDisassembler::Fail; 3641 3642 return S; 3643 } 3644 3645 3646 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3647 uint64_t Address, const void *Decoder) { 3648 DecodeStatus S = MCDisassembler::Success; 3649 3650 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3651 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3652 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3653 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3654 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3655 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3656 3657 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3658 3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3662 return MCDisassembler::Fail; 3663 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3664 return MCDisassembler::Fail; 3665 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3666 return MCDisassembler::Fail; 3667 3668 return S; 3669 } 3670 3671 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3672 uint64_t Address, const void *Decoder) { 3673 DecodeStatus S = MCDisassembler::Success; 3674 3675 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3676 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3677 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3678 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3679 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3680 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3681 3682 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3683 3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 3693 return S; 3694 } 3695 3696 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3697 uint64_t Address, const void *Decoder) { 3698 DecodeStatus S = MCDisassembler::Success; 3699 3700 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3701 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3702 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3703 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3704 unsigned size = fieldFromInstruction(Insn, 10, 2); 3705 3706 unsigned align = 0; 3707 unsigned index = 0; 3708 switch (size) { 3709 default: 3710 return MCDisassembler::Fail; 3711 case 0: 3712 if (fieldFromInstruction(Insn, 4, 1)) 3713 return MCDisassembler::Fail; // UNDEFINED 3714 index = fieldFromInstruction(Insn, 5, 3); 3715 break; 3716 case 1: 3717 if (fieldFromInstruction(Insn, 5, 1)) 3718 return MCDisassembler::Fail; // UNDEFINED 3719 index = fieldFromInstruction(Insn, 6, 2); 3720 if (fieldFromInstruction(Insn, 4, 1)) 3721 align = 2; 3722 break; 3723 case 2: 3724 if (fieldFromInstruction(Insn, 6, 1)) 3725 return MCDisassembler::Fail; // UNDEFINED 3726 index = fieldFromInstruction(Insn, 7, 1); 3727 3728 switch (fieldFromInstruction(Insn, 4, 2)) { 3729 case 0 : 3730 align = 0; break; 3731 case 3: 3732 align = 4; break; 3733 default: 3734 return MCDisassembler::Fail; 3735 } 3736 break; 3737 } 3738 3739 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 if (Rm != 0xF) { // Writeback 3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3743 return MCDisassembler::Fail; 3744 } 3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 Inst.addOperand(MCOperand::CreateImm(align)); 3748 if (Rm != 0xF) { 3749 if (Rm != 0xD) { 3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 } else 3753 Inst.addOperand(MCOperand::CreateReg(0)); 3754 } 3755 3756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3757 return MCDisassembler::Fail; 3758 Inst.addOperand(MCOperand::CreateImm(index)); 3759 3760 return S; 3761 } 3762 3763 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3764 uint64_t Address, const void *Decoder) { 3765 DecodeStatus S = MCDisassembler::Success; 3766 3767 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3768 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3769 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3770 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3771 unsigned size = fieldFromInstruction(Insn, 10, 2); 3772 3773 unsigned align = 0; 3774 unsigned index = 0; 3775 switch (size) { 3776 default: 3777 return MCDisassembler::Fail; 3778 case 0: 3779 if (fieldFromInstruction(Insn, 4, 1)) 3780 return MCDisassembler::Fail; // UNDEFINED 3781 index = fieldFromInstruction(Insn, 5, 3); 3782 break; 3783 case 1: 3784 if (fieldFromInstruction(Insn, 5, 1)) 3785 return MCDisassembler::Fail; // UNDEFINED 3786 index = fieldFromInstruction(Insn, 6, 2); 3787 if (fieldFromInstruction(Insn, 4, 1)) 3788 align = 2; 3789 break; 3790 case 2: 3791 if (fieldFromInstruction(Insn, 6, 1)) 3792 return MCDisassembler::Fail; // UNDEFINED 3793 index = fieldFromInstruction(Insn, 7, 1); 3794 3795 switch (fieldFromInstruction(Insn, 4, 2)) { 3796 case 0: 3797 align = 0; break; 3798 case 3: 3799 align = 4; break; 3800 default: 3801 return MCDisassembler::Fail; 3802 } 3803 break; 3804 } 3805 3806 if (Rm != 0xF) { // Writeback 3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3808 return MCDisassembler::Fail; 3809 } 3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 Inst.addOperand(MCOperand::CreateImm(align)); 3813 if (Rm != 0xF) { 3814 if (Rm != 0xD) { 3815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3816 return MCDisassembler::Fail; 3817 } else 3818 Inst.addOperand(MCOperand::CreateReg(0)); 3819 } 3820 3821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 Inst.addOperand(MCOperand::CreateImm(index)); 3824 3825 return S; 3826 } 3827 3828 3829 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3830 uint64_t Address, const void *Decoder) { 3831 DecodeStatus S = MCDisassembler::Success; 3832 3833 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3834 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3835 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3836 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3837 unsigned size = fieldFromInstruction(Insn, 10, 2); 3838 3839 unsigned align = 0; 3840 unsigned index = 0; 3841 unsigned inc = 1; 3842 switch (size) { 3843 default: 3844 return MCDisassembler::Fail; 3845 case 0: 3846 index = fieldFromInstruction(Insn, 5, 3); 3847 if (fieldFromInstruction(Insn, 4, 1)) 3848 align = 2; 3849 break; 3850 case 1: 3851 index = fieldFromInstruction(Insn, 6, 2); 3852 if (fieldFromInstruction(Insn, 4, 1)) 3853 align = 4; 3854 if (fieldFromInstruction(Insn, 5, 1)) 3855 inc = 2; 3856 break; 3857 case 2: 3858 if (fieldFromInstruction(Insn, 5, 1)) 3859 return MCDisassembler::Fail; // UNDEFINED 3860 index = fieldFromInstruction(Insn, 7, 1); 3861 if (fieldFromInstruction(Insn, 4, 1) != 0) 3862 align = 8; 3863 if (fieldFromInstruction(Insn, 6, 1)) 3864 inc = 2; 3865 break; 3866 } 3867 3868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3869 return MCDisassembler::Fail; 3870 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 if (Rm != 0xF) { // Writeback 3873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3874 return MCDisassembler::Fail; 3875 } 3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3877 return MCDisassembler::Fail; 3878 Inst.addOperand(MCOperand::CreateImm(align)); 3879 if (Rm != 0xF) { 3880 if (Rm != 0xD) { 3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 } else 3884 Inst.addOperand(MCOperand::CreateReg(0)); 3885 } 3886 3887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3888 return MCDisassembler::Fail; 3889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3890 return MCDisassembler::Fail; 3891 Inst.addOperand(MCOperand::CreateImm(index)); 3892 3893 return S; 3894 } 3895 3896 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3897 uint64_t Address, const void *Decoder) { 3898 DecodeStatus S = MCDisassembler::Success; 3899 3900 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3901 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3902 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3903 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3904 unsigned size = fieldFromInstruction(Insn, 10, 2); 3905 3906 unsigned align = 0; 3907 unsigned index = 0; 3908 unsigned inc = 1; 3909 switch (size) { 3910 default: 3911 return MCDisassembler::Fail; 3912 case 0: 3913 index = fieldFromInstruction(Insn, 5, 3); 3914 if (fieldFromInstruction(Insn, 4, 1)) 3915 align = 2; 3916 break; 3917 case 1: 3918 index = fieldFromInstruction(Insn, 6, 2); 3919 if (fieldFromInstruction(Insn, 4, 1)) 3920 align = 4; 3921 if (fieldFromInstruction(Insn, 5, 1)) 3922 inc = 2; 3923 break; 3924 case 2: 3925 if (fieldFromInstruction(Insn, 5, 1)) 3926 return MCDisassembler::Fail; // UNDEFINED 3927 index = fieldFromInstruction(Insn, 7, 1); 3928 if (fieldFromInstruction(Insn, 4, 1) != 0) 3929 align = 8; 3930 if (fieldFromInstruction(Insn, 6, 1)) 3931 inc = 2; 3932 break; 3933 } 3934 3935 if (Rm != 0xF) { // Writeback 3936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3937 return MCDisassembler::Fail; 3938 } 3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3940 return MCDisassembler::Fail; 3941 Inst.addOperand(MCOperand::CreateImm(align)); 3942 if (Rm != 0xF) { 3943 if (Rm != 0xD) { 3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 } else 3947 Inst.addOperand(MCOperand::CreateReg(0)); 3948 } 3949 3950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 Inst.addOperand(MCOperand::CreateImm(index)); 3955 3956 return S; 3957 } 3958 3959 3960 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3961 uint64_t Address, const void *Decoder) { 3962 DecodeStatus S = MCDisassembler::Success; 3963 3964 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3965 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3966 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3967 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3968 unsigned size = fieldFromInstruction(Insn, 10, 2); 3969 3970 unsigned align = 0; 3971 unsigned index = 0; 3972 unsigned inc = 1; 3973 switch (size) { 3974 default: 3975 return MCDisassembler::Fail; 3976 case 0: 3977 if (fieldFromInstruction(Insn, 4, 1)) 3978 return MCDisassembler::Fail; // UNDEFINED 3979 index = fieldFromInstruction(Insn, 5, 3); 3980 break; 3981 case 1: 3982 if (fieldFromInstruction(Insn, 4, 1)) 3983 return MCDisassembler::Fail; // UNDEFINED 3984 index = fieldFromInstruction(Insn, 6, 2); 3985 if (fieldFromInstruction(Insn, 5, 1)) 3986 inc = 2; 3987 break; 3988 case 2: 3989 if (fieldFromInstruction(Insn, 4, 2)) 3990 return MCDisassembler::Fail; // UNDEFINED 3991 index = fieldFromInstruction(Insn, 7, 1); 3992 if (fieldFromInstruction(Insn, 6, 1)) 3993 inc = 2; 3994 break; 3995 } 3996 3997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3998 return MCDisassembler::Fail; 3999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 4004 if (Rm != 0xF) { // Writeback 4005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 } 4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 Inst.addOperand(MCOperand::CreateImm(align)); 4011 if (Rm != 0xF) { 4012 if (Rm != 0xD) { 4013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 } else 4016 Inst.addOperand(MCOperand::CreateReg(0)); 4017 } 4018 4019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4024 return MCDisassembler::Fail; 4025 Inst.addOperand(MCOperand::CreateImm(index)); 4026 4027 return S; 4028 } 4029 4030 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4031 uint64_t Address, const void *Decoder) { 4032 DecodeStatus S = MCDisassembler::Success; 4033 4034 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4035 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4036 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4037 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4038 unsigned size = fieldFromInstruction(Insn, 10, 2); 4039 4040 unsigned align = 0; 4041 unsigned index = 0; 4042 unsigned inc = 1; 4043 switch (size) { 4044 default: 4045 return MCDisassembler::Fail; 4046 case 0: 4047 if (fieldFromInstruction(Insn, 4, 1)) 4048 return MCDisassembler::Fail; // UNDEFINED 4049 index = fieldFromInstruction(Insn, 5, 3); 4050 break; 4051 case 1: 4052 if (fieldFromInstruction(Insn, 4, 1)) 4053 return MCDisassembler::Fail; // UNDEFINED 4054 index = fieldFromInstruction(Insn, 6, 2); 4055 if (fieldFromInstruction(Insn, 5, 1)) 4056 inc = 2; 4057 break; 4058 case 2: 4059 if (fieldFromInstruction(Insn, 4, 2)) 4060 return MCDisassembler::Fail; // UNDEFINED 4061 index = fieldFromInstruction(Insn, 7, 1); 4062 if (fieldFromInstruction(Insn, 6, 1)) 4063 inc = 2; 4064 break; 4065 } 4066 4067 if (Rm != 0xF) { // Writeback 4068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4069 return MCDisassembler::Fail; 4070 } 4071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4072 return MCDisassembler::Fail; 4073 Inst.addOperand(MCOperand::CreateImm(align)); 4074 if (Rm != 0xF) { 4075 if (Rm != 0xD) { 4076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4077 return MCDisassembler::Fail; 4078 } else 4079 Inst.addOperand(MCOperand::CreateReg(0)); 4080 } 4081 4082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4085 return MCDisassembler::Fail; 4086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 Inst.addOperand(MCOperand::CreateImm(index)); 4089 4090 return S; 4091 } 4092 4093 4094 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4095 uint64_t Address, const void *Decoder) { 4096 DecodeStatus S = MCDisassembler::Success; 4097 4098 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4099 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4100 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4101 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4102 unsigned size = fieldFromInstruction(Insn, 10, 2); 4103 4104 unsigned align = 0; 4105 unsigned index = 0; 4106 unsigned inc = 1; 4107 switch (size) { 4108 default: 4109 return MCDisassembler::Fail; 4110 case 0: 4111 if (fieldFromInstruction(Insn, 4, 1)) 4112 align = 4; 4113 index = fieldFromInstruction(Insn, 5, 3); 4114 break; 4115 case 1: 4116 if (fieldFromInstruction(Insn, 4, 1)) 4117 align = 8; 4118 index = fieldFromInstruction(Insn, 6, 2); 4119 if (fieldFromInstruction(Insn, 5, 1)) 4120 inc = 2; 4121 break; 4122 case 2: 4123 switch (fieldFromInstruction(Insn, 4, 2)) { 4124 case 0: 4125 align = 0; break; 4126 case 3: 4127 return MCDisassembler::Fail; 4128 default: 4129 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4130 } 4131 4132 index = fieldFromInstruction(Insn, 7, 1); 4133 if (fieldFromInstruction(Insn, 6, 1)) 4134 inc = 2; 4135 break; 4136 } 4137 4138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4139 return MCDisassembler::Fail; 4140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4143 return MCDisassembler::Fail; 4144 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 4147 if (Rm != 0xF) { // Writeback 4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 } 4151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 Inst.addOperand(MCOperand::CreateImm(align)); 4154 if (Rm != 0xF) { 4155 if (Rm != 0xD) { 4156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 } else 4159 Inst.addOperand(MCOperand::CreateReg(0)); 4160 } 4161 4162 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4163 return MCDisassembler::Fail; 4164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4165 return MCDisassembler::Fail; 4166 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4167 return MCDisassembler::Fail; 4168 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4169 return MCDisassembler::Fail; 4170 Inst.addOperand(MCOperand::CreateImm(index)); 4171 4172 return S; 4173 } 4174 4175 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4176 uint64_t Address, const void *Decoder) { 4177 DecodeStatus S = MCDisassembler::Success; 4178 4179 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4180 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4181 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4182 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4183 unsigned size = fieldFromInstruction(Insn, 10, 2); 4184 4185 unsigned align = 0; 4186 unsigned index = 0; 4187 unsigned inc = 1; 4188 switch (size) { 4189 default: 4190 return MCDisassembler::Fail; 4191 case 0: 4192 if (fieldFromInstruction(Insn, 4, 1)) 4193 align = 4; 4194 index = fieldFromInstruction(Insn, 5, 3); 4195 break; 4196 case 1: 4197 if (fieldFromInstruction(Insn, 4, 1)) 4198 align = 8; 4199 index = fieldFromInstruction(Insn, 6, 2); 4200 if (fieldFromInstruction(Insn, 5, 1)) 4201 inc = 2; 4202 break; 4203 case 2: 4204 switch (fieldFromInstruction(Insn, 4, 2)) { 4205 case 0: 4206 align = 0; break; 4207 case 3: 4208 return MCDisassembler::Fail; 4209 default: 4210 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4211 } 4212 4213 index = fieldFromInstruction(Insn, 7, 1); 4214 if (fieldFromInstruction(Insn, 6, 1)) 4215 inc = 2; 4216 break; 4217 } 4218 4219 if (Rm != 0xF) { // Writeback 4220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4221 return MCDisassembler::Fail; 4222 } 4223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4224 return MCDisassembler::Fail; 4225 Inst.addOperand(MCOperand::CreateImm(align)); 4226 if (Rm != 0xF) { 4227 if (Rm != 0xD) { 4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 } else 4231 Inst.addOperand(MCOperand::CreateReg(0)); 4232 } 4233 4234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 Inst.addOperand(MCOperand::CreateImm(index)); 4243 4244 return S; 4245 } 4246 4247 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4248 uint64_t Address, const void *Decoder) { 4249 DecodeStatus S = MCDisassembler::Success; 4250 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4251 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4252 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4253 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4254 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4255 4256 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4257 S = MCDisassembler::SoftFail; 4258 4259 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4264 return MCDisassembler::Fail; 4265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 4270 return S; 4271 } 4272 4273 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4274 uint64_t Address, const void *Decoder) { 4275 DecodeStatus S = MCDisassembler::Success; 4276 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4277 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4278 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4279 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4280 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4281 4282 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4283 S = MCDisassembler::SoftFail; 4284 4285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4286 return MCDisassembler::Fail; 4287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4288 return MCDisassembler::Fail; 4289 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4292 return MCDisassembler::Fail; 4293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4294 return MCDisassembler::Fail; 4295 4296 return S; 4297 } 4298 4299 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4300 uint64_t Address, const void *Decoder) { 4301 DecodeStatus S = MCDisassembler::Success; 4302 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4303 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4304 4305 if (pred == 0xF) { 4306 pred = 0xE; 4307 S = MCDisassembler::SoftFail; 4308 } 4309 4310 if (mask == 0x0) { 4311 mask |= 0x8; 4312 S = MCDisassembler::SoftFail; 4313 } 4314 4315 Inst.addOperand(MCOperand::CreateImm(pred)); 4316 Inst.addOperand(MCOperand::CreateImm(mask)); 4317 return S; 4318 } 4319 4320 static DecodeStatus 4321 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4322 uint64_t Address, const void *Decoder) { 4323 DecodeStatus S = MCDisassembler::Success; 4324 4325 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4326 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4328 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4329 unsigned W = fieldFromInstruction(Insn, 21, 1); 4330 unsigned U = fieldFromInstruction(Insn, 23, 1); 4331 unsigned P = fieldFromInstruction(Insn, 24, 1); 4332 bool writeback = (W == 1) | (P == 0); 4333 4334 addr |= (U << 8) | (Rn << 9); 4335 4336 if (writeback && (Rn == Rt || Rn == Rt2)) 4337 Check(S, MCDisassembler::SoftFail); 4338 if (Rt == Rt2) 4339 Check(S, MCDisassembler::SoftFail); 4340 4341 // Rt 4342 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 // Rt2 4345 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4346 return MCDisassembler::Fail; 4347 // Writeback operand 4348 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 // addr 4351 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 4354 return S; 4355 } 4356 4357 static DecodeStatus 4358 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4359 uint64_t Address, const void *Decoder) { 4360 DecodeStatus S = MCDisassembler::Success; 4361 4362 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4363 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4364 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4365 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4366 unsigned W = fieldFromInstruction(Insn, 21, 1); 4367 unsigned U = fieldFromInstruction(Insn, 23, 1); 4368 unsigned P = fieldFromInstruction(Insn, 24, 1); 4369 bool writeback = (W == 1) | (P == 0); 4370 4371 addr |= (U << 8) | (Rn << 9); 4372 4373 if (writeback && (Rn == Rt || Rn == Rt2)) 4374 Check(S, MCDisassembler::SoftFail); 4375 4376 // Writeback operand 4377 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4378 return MCDisassembler::Fail; 4379 // Rt 4380 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4381 return MCDisassembler::Fail; 4382 // Rt2 4383 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4384 return MCDisassembler::Fail; 4385 // addr 4386 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 4389 return S; 4390 } 4391 4392 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4393 uint64_t Address, const void *Decoder) { 4394 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4395 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4396 if (sign1 != sign2) return MCDisassembler::Fail; 4397 4398 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4399 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4400 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4401 Val |= sign1 << 12; 4402 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4403 4404 return MCDisassembler::Success; 4405 } 4406 4407 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4408 uint64_t Address, 4409 const void *Decoder) { 4410 DecodeStatus S = MCDisassembler::Success; 4411 4412 // Shift of "asr #32" is not allowed in Thumb2 mode. 4413 if (Val == 0x20) S = MCDisassembler::SoftFail; 4414 Inst.addOperand(MCOperand::CreateImm(Val)); 4415 return S; 4416 } 4417 4418 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4419 uint64_t Address, const void *Decoder) { 4420 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4421 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4422 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4423 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4424 4425 if (pred == 0xF) 4426 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4427 4428 DecodeStatus S = MCDisassembler::Success; 4429 4430 if (Rt == Rn || Rn == Rt2) 4431 S = MCDisassembler::SoftFail; 4432 4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4440 return MCDisassembler::Fail; 4441 4442 return S; 4443 } 4444 4445 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4446 uint64_t Address, const void *Decoder) { 4447 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4448 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4449 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4450 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4451 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4452 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4453 4454 DecodeStatus S = MCDisassembler::Success; 4455 4456 // VMOVv2f32 is ambiguous with these decodings. 4457 if (!(imm & 0x38) && cmode == 0xF) { 4458 Inst.setOpcode(ARM::VMOVv2f32); 4459 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4460 } 4461 4462 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4463 4464 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4465 return MCDisassembler::Fail; 4466 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4469 4470 return S; 4471 } 4472 4473 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4474 uint64_t Address, const void *Decoder) { 4475 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4476 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4477 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4478 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4479 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4480 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4481 4482 DecodeStatus S = MCDisassembler::Success; 4483 4484 // VMOVv4f32 is ambiguous with these decodings. 4485 if (!(imm & 0x38) && cmode == 0xF) { 4486 Inst.setOpcode(ARM::VMOVv4f32); 4487 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4488 } 4489 4490 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4491 4492 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4493 return MCDisassembler::Fail; 4494 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4495 return MCDisassembler::Fail; 4496 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4497 4498 return S; 4499 } 4500 4501 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4502 const void *Decoder) 4503 { 4504 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4505 if (Imm > 4) return MCDisassembler::Fail; 4506 Inst.addOperand(MCOperand::CreateImm(Imm)); 4507 return MCDisassembler::Success; 4508 } 4509 4510 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4511 uint64_t Address, const void *Decoder) { 4512 DecodeStatus S = MCDisassembler::Success; 4513 4514 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4515 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4516 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4517 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4518 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4519 4520 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4521 S = MCDisassembler::SoftFail; 4522 4523 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4524 return MCDisassembler::Fail; 4525 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4528 return MCDisassembler::Fail; 4529 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4530 return MCDisassembler::Fail; 4531 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4532 return MCDisassembler::Fail; 4533 4534 return S; 4535 } 4536 4537 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4538 uint64_t Address, const void *Decoder) { 4539 4540 DecodeStatus S = MCDisassembler::Success; 4541 4542 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4543 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4544 unsigned cop = fieldFromInstruction(Val, 8, 4); 4545 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4546 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4547 4548 if ((cop & ~0x1) == 0xa) 4549 return MCDisassembler::Fail; 4550 4551 if (Rt == Rt2) 4552 S = MCDisassembler::SoftFail; 4553 4554 Inst.addOperand(MCOperand::CreateImm(cop)); 4555 Inst.addOperand(MCOperand::CreateImm(opc1)); 4556 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4557 return MCDisassembler::Fail; 4558 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4559 return MCDisassembler::Fail; 4560 Inst.addOperand(MCOperand::CreateImm(CRm)); 4561 4562 return S; 4563 } 4564 4565