1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = CountTrailingZeros_32(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder); 178 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 183 unsigned RegNo, uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 217 unsigned Insn, 218 uint64_t Adddress, 219 const void *Decoder); 220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 315 const void *Decoder); 316 317 318 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 381 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 #include "ARMGenDisassemblerTables.inc" 386 387 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 388 return new ARMDisassembler(STI); 389 } 390 391 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 392 return new ThumbDisassembler(STI); 393 } 394 395 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 396 const MemoryObject &Region, 397 uint64_t Address, 398 raw_ostream &os, 399 raw_ostream &cs) const { 400 CommentStream = &cs; 401 402 uint8_t bytes[4]; 403 404 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 405 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 406 407 // We want to read exactly 4 bytes of data. 408 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 409 Size = 0; 410 return MCDisassembler::Fail; 411 } 412 413 // Encoded as a small-endian 32-bit word in the stream. 414 uint32_t insn = (bytes[3] << 24) | 415 (bytes[2] << 16) | 416 (bytes[1] << 8) | 417 (bytes[0] << 0); 418 419 // Calling the auto-generated decoder function. 420 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 421 Address, this, STI); 422 if (result != MCDisassembler::Fail) { 423 Size = 4; 424 return result; 425 } 426 427 // VFP and NEON instructions, similarly, are shared between ARM 428 // and Thumb modes. 429 MI.clear(); 430 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 431 if (result != MCDisassembler::Fail) { 432 Size = 4; 433 return result; 434 } 435 436 MI.clear(); 437 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 438 this, STI); 439 if (result != MCDisassembler::Fail) { 440 Size = 4; 441 // Add a fake predicate operand, because we share these instruction 442 // definitions with Thumb2 where these instructions are predicable. 443 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 444 return MCDisassembler::Fail; 445 return result; 446 } 447 448 MI.clear(); 449 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 450 this, STI); 451 if (result != MCDisassembler::Fail) { 452 Size = 4; 453 // Add a fake predicate operand, because we share these instruction 454 // definitions with Thumb2 where these instructions are predicable. 455 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 456 return MCDisassembler::Fail; 457 return result; 458 } 459 460 MI.clear(); 461 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 462 this, STI); 463 if (result != MCDisassembler::Fail) { 464 Size = 4; 465 // Add a fake predicate operand, because we share these instruction 466 // definitions with Thumb2 where these instructions are predicable. 467 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 468 return MCDisassembler::Fail; 469 return result; 470 } 471 472 MI.clear(); 473 474 Size = 0; 475 return MCDisassembler::Fail; 476 } 477 478 namespace llvm { 479 extern const MCInstrDesc ARMInsts[]; 480 } 481 482 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 483 /// immediate Value in the MCInst. The immediate Value has had any PC 484 /// adjustment made by the caller. If the instruction is a branch instruction 485 /// then isBranch is true, else false. If the getOpInfo() function was set as 486 /// part of the setupForSymbolicDisassembly() call then that function is called 487 /// to get any symbolic information at the Address for this instruction. If 488 /// that returns non-zero then the symbolic information it returns is used to 489 /// create an MCExpr and that is added as an operand to the MCInst. If 490 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 491 /// Value is done and if a symbol is found an MCExpr is created with that, else 492 /// an MCExpr with Value is created. This function returns true if it adds an 493 /// operand to the MCInst and false otherwise. 494 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 495 bool isBranch, uint64_t InstSize, 496 MCInst &MI, const void *Decoder) { 497 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 498 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 499 struct LLVMOpInfo1 SymbolicOp; 500 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 501 SymbolicOp.Value = Value; 502 void *DisInfo = Dis->getDisInfoBlock(); 503 504 if (!getOpInfo || 505 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 506 // Clear SymbolicOp.Value from above and also all other fields. 507 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 508 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 509 if (!SymbolLookUp) 510 return false; 511 uint64_t ReferenceType; 512 if (isBranch) 513 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 514 else 515 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 516 const char *ReferenceName; 517 uint64_t SymbolValue = 0x00000000ffffffffULL & Value; 518 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType, 519 Address, &ReferenceName); 520 if (Name) { 521 SymbolicOp.AddSymbol.Name = Name; 522 SymbolicOp.AddSymbol.Present = true; 523 } 524 // For branches always create an MCExpr so it gets printed as hex address. 525 else if (isBranch) { 526 SymbolicOp.Value = Value; 527 } 528 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 529 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 530 if (!Name && !isBranch) 531 return false; 532 } 533 534 MCContext *Ctx = Dis->getMCContext(); 535 const MCExpr *Add = NULL; 536 if (SymbolicOp.AddSymbol.Present) { 537 if (SymbolicOp.AddSymbol.Name) { 538 StringRef Name(SymbolicOp.AddSymbol.Name); 539 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 540 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 541 } else { 542 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 543 } 544 } 545 546 const MCExpr *Sub = NULL; 547 if (SymbolicOp.SubtractSymbol.Present) { 548 if (SymbolicOp.SubtractSymbol.Name) { 549 StringRef Name(SymbolicOp.SubtractSymbol.Name); 550 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 551 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 552 } else { 553 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 554 } 555 } 556 557 const MCExpr *Off = NULL; 558 if (SymbolicOp.Value != 0) 559 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 560 561 const MCExpr *Expr; 562 if (Sub) { 563 const MCExpr *LHS; 564 if (Add) 565 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 566 else 567 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 568 if (Off != 0) 569 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 570 else 571 Expr = LHS; 572 } else if (Add) { 573 if (Off != 0) 574 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 575 else 576 Expr = Add; 577 } else { 578 if (Off != 0) 579 Expr = Off; 580 else 581 Expr = MCConstantExpr::Create(0, *Ctx); 582 } 583 584 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 585 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 586 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 587 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 588 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 589 MI.addOperand(MCOperand::CreateExpr(Expr)); 590 else 591 llvm_unreachable("bad SymbolicOp.VariantKind"); 592 593 return true; 594 } 595 596 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 597 /// referenced by a load instruction with the base register that is the Pc. 598 /// These can often be values in a literal pool near the Address of the 599 /// instruction. The Address of the instruction and its immediate Value are 600 /// used as a possible literal pool entry. The SymbolLookUp call back will 601 /// return the name of a symbol referenced by the literal pool's entry if 602 /// the referenced address is that of a symbol. Or it will return a pointer to 603 /// a literal 'C' string if the referenced address of the literal pool's entry 604 /// is an address into a section with 'C' string literals. 605 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 606 const void *Decoder) { 607 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 608 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 609 if (SymbolLookUp) { 610 void *DisInfo = Dis->getDisInfoBlock(); 611 uint64_t ReferenceType; 612 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 613 const char *ReferenceName; 614 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 615 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 616 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 617 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 618 } 619 } 620 621 // Thumb1 instructions don't have explicit S bits. Rather, they 622 // implicitly set CPSR. Since it's not represented in the encoding, the 623 // auto-generated decoder won't inject the CPSR operand. We need to fix 624 // that as a post-pass. 625 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 626 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 627 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 628 MCInst::iterator I = MI.begin(); 629 for (unsigned i = 0; i < NumOps; ++i, ++I) { 630 if (I == MI.end()) break; 631 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 632 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 633 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 634 return; 635 } 636 } 637 638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 639 } 640 641 // Most Thumb instructions don't have explicit predicates in the 642 // encoding, but rather get their predicates from IT context. We need 643 // to fix up the predicate operands using this context information as a 644 // post-pass. 645 MCDisassembler::DecodeStatus 646 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 647 MCDisassembler::DecodeStatus S = Success; 648 649 // A few instructions actually have predicates encoded in them. Don't 650 // try to overwrite it if we're seeing one of those. 651 switch (MI.getOpcode()) { 652 case ARM::tBcc: 653 case ARM::t2Bcc: 654 case ARM::tCBZ: 655 case ARM::tCBNZ: 656 case ARM::tCPS: 657 case ARM::t2CPS3p: 658 case ARM::t2CPS2p: 659 case ARM::t2CPS1p: 660 case ARM::tMOVSr: 661 case ARM::tSETEND: 662 // Some instructions (mostly conditional branches) are not 663 // allowed in IT blocks. 664 if (ITBlock.instrInITBlock()) 665 S = SoftFail; 666 else 667 return Success; 668 break; 669 case ARM::tB: 670 case ARM::t2B: 671 case ARM::t2TBB: 672 case ARM::t2TBH: 673 // Some instructions (mostly unconditional branches) can 674 // only appears at the end of, or outside of, an IT. 675 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 676 S = SoftFail; 677 break; 678 default: 679 break; 680 } 681 682 // If we're in an IT block, base the predicate on that. Otherwise, 683 // assume a predicate of AL. 684 unsigned CC; 685 CC = ITBlock.getITCC(); 686 if (CC == 0xF) 687 CC = ARMCC::AL; 688 if (ITBlock.instrInITBlock()) 689 ITBlock.advanceITState(); 690 691 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 692 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 693 MCInst::iterator I = MI.begin(); 694 for (unsigned i = 0; i < NumOps; ++i, ++I) { 695 if (I == MI.end()) break; 696 if (OpInfo[i].isPredicate()) { 697 I = MI.insert(I, MCOperand::CreateImm(CC)); 698 ++I; 699 if (CC == ARMCC::AL) 700 MI.insert(I, MCOperand::CreateReg(0)); 701 else 702 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 703 return S; 704 } 705 } 706 707 I = MI.insert(I, MCOperand::CreateImm(CC)); 708 ++I; 709 if (CC == ARMCC::AL) 710 MI.insert(I, MCOperand::CreateReg(0)); 711 else 712 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 713 714 return S; 715 } 716 717 // Thumb VFP instructions are a special case. Because we share their 718 // encodings between ARM and Thumb modes, and they are predicable in ARM 719 // mode, the auto-generated decoder will give them an (incorrect) 720 // predicate operand. We need to rewrite these operands based on the IT 721 // context as a post-pass. 722 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 723 unsigned CC; 724 CC = ITBlock.getITCC(); 725 if (ITBlock.instrInITBlock()) 726 ITBlock.advanceITState(); 727 728 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 729 MCInst::iterator I = MI.begin(); 730 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 731 for (unsigned i = 0; i < NumOps; ++i, ++I) { 732 if (OpInfo[i].isPredicate() ) { 733 I->setImm(CC); 734 ++I; 735 if (CC == ARMCC::AL) 736 I->setReg(0); 737 else 738 I->setReg(ARM::CPSR); 739 return; 740 } 741 } 742 } 743 744 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 745 const MemoryObject &Region, 746 uint64_t Address, 747 raw_ostream &os, 748 raw_ostream &cs) const { 749 CommentStream = &cs; 750 751 uint8_t bytes[4]; 752 753 assert((STI.getFeatureBits() & ARM::ModeThumb) && 754 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 755 756 // We want to read exactly 2 bytes of data. 757 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 758 Size = 0; 759 return MCDisassembler::Fail; 760 } 761 762 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 763 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 764 Address, this, STI); 765 if (result != MCDisassembler::Fail) { 766 Size = 2; 767 Check(result, AddThumbPredicate(MI)); 768 return result; 769 } 770 771 MI.clear(); 772 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 773 Address, this, STI); 774 if (result) { 775 Size = 2; 776 bool InITBlock = ITBlock.instrInITBlock(); 777 Check(result, AddThumbPredicate(MI)); 778 AddThumb1SBit(MI, InITBlock); 779 return result; 780 } 781 782 MI.clear(); 783 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 784 Address, this, STI); 785 if (result != MCDisassembler::Fail) { 786 Size = 2; 787 788 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 789 // the Thumb predicate. 790 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 791 result = MCDisassembler::SoftFail; 792 793 Check(result, AddThumbPredicate(MI)); 794 795 // If we find an IT instruction, we need to parse its condition 796 // code and mask operands so that we can apply them correctly 797 // to the subsequent instructions. 798 if (MI.getOpcode() == ARM::t2IT) { 799 800 unsigned Firstcond = MI.getOperand(0).getImm(); 801 unsigned Mask = MI.getOperand(1).getImm(); 802 ITBlock.setITState(Firstcond, Mask); 803 } 804 805 return result; 806 } 807 808 // We want to read exactly 4 bytes of data. 809 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 810 Size = 0; 811 return MCDisassembler::Fail; 812 } 813 814 uint32_t insn32 = (bytes[3] << 8) | 815 (bytes[2] << 0) | 816 (bytes[1] << 24) | 817 (bytes[0] << 16); 818 MI.clear(); 819 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 820 this, STI); 821 if (result != MCDisassembler::Fail) { 822 Size = 4; 823 bool InITBlock = ITBlock.instrInITBlock(); 824 Check(result, AddThumbPredicate(MI)); 825 AddThumb1SBit(MI, InITBlock); 826 return result; 827 } 828 829 MI.clear(); 830 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 831 this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 Check(result, AddThumbPredicate(MI)); 835 return result; 836 } 837 838 MI.clear(); 839 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 840 if (result != MCDisassembler::Fail) { 841 Size = 4; 842 UpdateThumbVFPPredicate(MI); 843 return result; 844 } 845 846 MI.clear(); 847 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 848 this, STI); 849 if (result != MCDisassembler::Fail) { 850 Size = 4; 851 Check(result, AddThumbPredicate(MI)); 852 return result; 853 } 854 855 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 856 MI.clear(); 857 uint32_t NEONLdStInsn = insn32; 858 NEONLdStInsn &= 0xF0FFFFFF; 859 NEONLdStInsn |= 0x04000000; 860 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 861 Address, this, STI); 862 if (result != MCDisassembler::Fail) { 863 Size = 4; 864 Check(result, AddThumbPredicate(MI)); 865 return result; 866 } 867 } 868 869 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 870 MI.clear(); 871 uint32_t NEONDataInsn = insn32; 872 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 873 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 874 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 875 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 876 Address, this, STI); 877 if (result != MCDisassembler::Fail) { 878 Size = 4; 879 Check(result, AddThumbPredicate(MI)); 880 return result; 881 } 882 } 883 884 Size = 0; 885 return MCDisassembler::Fail; 886 } 887 888 889 extern "C" void LLVMInitializeARMDisassembler() { 890 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 891 createARMDisassembler); 892 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 893 createThumbDisassembler); 894 } 895 896 static const uint16_t GPRDecoderTable[] = { 897 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 898 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 899 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 900 ARM::R12, ARM::SP, ARM::LR, ARM::PC 901 }; 902 903 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 904 uint64_t Address, const void *Decoder) { 905 if (RegNo > 15) 906 return MCDisassembler::Fail; 907 908 unsigned Register = GPRDecoderTable[RegNo]; 909 Inst.addOperand(MCOperand::CreateReg(Register)); 910 return MCDisassembler::Success; 911 } 912 913 static DecodeStatus 914 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 915 uint64_t Address, const void *Decoder) { 916 DecodeStatus S = MCDisassembler::Success; 917 918 if (RegNo == 15) 919 S = MCDisassembler::SoftFail; 920 921 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 922 923 return S; 924 } 925 926 static DecodeStatus 927 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 928 uint64_t Address, const void *Decoder) { 929 DecodeStatus S = MCDisassembler::Success; 930 931 if (RegNo == 15) 932 { 933 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 934 return MCDisassembler::Success; 935 } 936 937 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 938 return S; 939 } 940 941 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) { 943 if (RegNo > 7) 944 return MCDisassembler::Fail; 945 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 946 } 947 948 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 949 uint64_t Address, const void *Decoder) { 950 unsigned Register = 0; 951 switch (RegNo) { 952 case 0: 953 Register = ARM::R0; 954 break; 955 case 1: 956 Register = ARM::R1; 957 break; 958 case 2: 959 Register = ARM::R2; 960 break; 961 case 3: 962 Register = ARM::R3; 963 break; 964 case 9: 965 Register = ARM::R9; 966 break; 967 case 12: 968 Register = ARM::R12; 969 break; 970 default: 971 return MCDisassembler::Fail; 972 } 973 974 Inst.addOperand(MCOperand::CreateReg(Register)); 975 return MCDisassembler::Success; 976 } 977 978 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 979 uint64_t Address, const void *Decoder) { 980 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 981 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 982 } 983 984 static const uint16_t SPRDecoderTable[] = { 985 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 986 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 987 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 988 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 989 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 990 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 991 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 992 ARM::S28, ARM::S29, ARM::S30, ARM::S31 993 }; 994 995 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 996 uint64_t Address, const void *Decoder) { 997 if (RegNo > 31) 998 return MCDisassembler::Fail; 999 1000 unsigned Register = SPRDecoderTable[RegNo]; 1001 Inst.addOperand(MCOperand::CreateReg(Register)); 1002 return MCDisassembler::Success; 1003 } 1004 1005 static const uint16_t DPRDecoderTable[] = { 1006 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1007 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1008 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1009 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1010 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1011 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1012 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1013 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1014 }; 1015 1016 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1017 uint64_t Address, const void *Decoder) { 1018 if (RegNo > 31) 1019 return MCDisassembler::Fail; 1020 1021 unsigned Register = DPRDecoderTable[RegNo]; 1022 Inst.addOperand(MCOperand::CreateReg(Register)); 1023 return MCDisassembler::Success; 1024 } 1025 1026 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1027 uint64_t Address, const void *Decoder) { 1028 if (RegNo > 7) 1029 return MCDisassembler::Fail; 1030 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1031 } 1032 1033 static DecodeStatus 1034 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1035 uint64_t Address, const void *Decoder) { 1036 if (RegNo > 15) 1037 return MCDisassembler::Fail; 1038 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1039 } 1040 1041 static const uint16_t QPRDecoderTable[] = { 1042 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1043 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1044 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1045 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1046 }; 1047 1048 1049 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1050 uint64_t Address, const void *Decoder) { 1051 if (RegNo > 31) 1052 return MCDisassembler::Fail; 1053 RegNo >>= 1; 1054 1055 unsigned Register = QPRDecoderTable[RegNo]; 1056 Inst.addOperand(MCOperand::CreateReg(Register)); 1057 return MCDisassembler::Success; 1058 } 1059 1060 static const uint16_t DPairDecoderTable[] = { 1061 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1062 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1063 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1064 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1065 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1066 ARM::Q15 1067 }; 1068 1069 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1070 uint64_t Address, const void *Decoder) { 1071 if (RegNo > 30) 1072 return MCDisassembler::Fail; 1073 1074 unsigned Register = DPairDecoderTable[RegNo]; 1075 Inst.addOperand(MCOperand::CreateReg(Register)); 1076 return MCDisassembler::Success; 1077 } 1078 1079 static const uint16_t DPairSpacedDecoderTable[] = { 1080 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1081 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1082 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1083 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1084 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1085 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1086 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1087 ARM::D28_D30, ARM::D29_D31 1088 }; 1089 1090 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1091 unsigned RegNo, 1092 uint64_t Address, 1093 const void *Decoder) { 1094 if (RegNo > 29) 1095 return MCDisassembler::Fail; 1096 1097 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1098 Inst.addOperand(MCOperand::CreateReg(Register)); 1099 return MCDisassembler::Success; 1100 } 1101 1102 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1103 uint64_t Address, const void *Decoder) { 1104 if (Val == 0xF) return MCDisassembler::Fail; 1105 // AL predicate is not allowed on Thumb1 branches. 1106 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1107 return MCDisassembler::Fail; 1108 Inst.addOperand(MCOperand::CreateImm(Val)); 1109 if (Val == ARMCC::AL) { 1110 Inst.addOperand(MCOperand::CreateReg(0)); 1111 } else 1112 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 if (Val) 1119 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1120 else 1121 Inst.addOperand(MCOperand::CreateReg(0)); 1122 return MCDisassembler::Success; 1123 } 1124 1125 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1126 uint64_t Address, const void *Decoder) { 1127 uint32_t imm = Val & 0xFF; 1128 uint32_t rot = (Val & 0xF00) >> 7; 1129 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1130 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1131 return MCDisassembler::Success; 1132 } 1133 1134 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1135 uint64_t Address, const void *Decoder) { 1136 DecodeStatus S = MCDisassembler::Success; 1137 1138 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1139 unsigned type = fieldFromInstruction(Val, 5, 2); 1140 unsigned imm = fieldFromInstruction(Val, 7, 5); 1141 1142 // Register-immediate 1143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1144 return MCDisassembler::Fail; 1145 1146 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1147 switch (type) { 1148 case 0: 1149 Shift = ARM_AM::lsl; 1150 break; 1151 case 1: 1152 Shift = ARM_AM::lsr; 1153 break; 1154 case 2: 1155 Shift = ARM_AM::asr; 1156 break; 1157 case 3: 1158 Shift = ARM_AM::ror; 1159 break; 1160 } 1161 1162 if (Shift == ARM_AM::ror && imm == 0) 1163 Shift = ARM_AM::rrx; 1164 1165 unsigned Op = Shift | (imm << 3); 1166 Inst.addOperand(MCOperand::CreateImm(Op)); 1167 1168 return S; 1169 } 1170 1171 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1172 uint64_t Address, const void *Decoder) { 1173 DecodeStatus S = MCDisassembler::Success; 1174 1175 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1176 unsigned type = fieldFromInstruction(Val, 5, 2); 1177 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1178 1179 // Register-register 1180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1181 return MCDisassembler::Fail; 1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1183 return MCDisassembler::Fail; 1184 1185 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1186 switch (type) { 1187 case 0: 1188 Shift = ARM_AM::lsl; 1189 break; 1190 case 1: 1191 Shift = ARM_AM::lsr; 1192 break; 1193 case 2: 1194 Shift = ARM_AM::asr; 1195 break; 1196 case 3: 1197 Shift = ARM_AM::ror; 1198 break; 1199 } 1200 1201 Inst.addOperand(MCOperand::CreateImm(Shift)); 1202 1203 return S; 1204 } 1205 1206 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1207 uint64_t Address, const void *Decoder) { 1208 DecodeStatus S = MCDisassembler::Success; 1209 1210 bool writebackLoad = false; 1211 unsigned writebackReg = 0; 1212 switch (Inst.getOpcode()) { 1213 default: 1214 break; 1215 case ARM::LDMIA_UPD: 1216 case ARM::LDMDB_UPD: 1217 case ARM::LDMIB_UPD: 1218 case ARM::LDMDA_UPD: 1219 case ARM::t2LDMIA_UPD: 1220 case ARM::t2LDMDB_UPD: 1221 writebackLoad = true; 1222 writebackReg = Inst.getOperand(0).getReg(); 1223 break; 1224 } 1225 1226 // Empty register lists are not allowed. 1227 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1228 for (unsigned i = 0; i < 16; ++i) { 1229 if (Val & (1 << i)) { 1230 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 // Writeback not allowed if Rn is in the target list. 1233 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1234 Check(S, MCDisassembler::SoftFail); 1235 } 1236 } 1237 1238 return S; 1239 } 1240 1241 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1242 uint64_t Address, const void *Decoder) { 1243 DecodeStatus S = MCDisassembler::Success; 1244 1245 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1246 unsigned regs = fieldFromInstruction(Val, 0, 8); 1247 1248 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1249 return MCDisassembler::Fail; 1250 for (unsigned i = 0; i < (regs - 1); ++i) { 1251 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1252 return MCDisassembler::Fail; 1253 } 1254 1255 return S; 1256 } 1257 1258 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1259 uint64_t Address, const void *Decoder) { 1260 DecodeStatus S = MCDisassembler::Success; 1261 1262 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1263 unsigned regs = fieldFromInstruction(Val, 0, 8); 1264 1265 regs = regs >> 1; 1266 1267 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1268 return MCDisassembler::Fail; 1269 for (unsigned i = 0; i < (regs - 1); ++i) { 1270 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1271 return MCDisassembler::Fail; 1272 } 1273 1274 return S; 1275 } 1276 1277 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1278 uint64_t Address, const void *Decoder) { 1279 // This operand encodes a mask of contiguous zeros between a specified MSB 1280 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1281 // the mask of all bits LSB-and-lower, and then xor them to create 1282 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1283 // create the final mask. 1284 unsigned msb = fieldFromInstruction(Val, 5, 5); 1285 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1286 1287 DecodeStatus S = MCDisassembler::Success; 1288 if (lsb > msb) { 1289 Check(S, MCDisassembler::SoftFail); 1290 // The check above will cause the warning for the "potentially undefined 1291 // instruction encoding" but we can't build a bad MCOperand value here 1292 // with a lsb > msb or else printing the MCInst will cause a crash. 1293 lsb = msb; 1294 } 1295 1296 uint32_t msb_mask = 0xFFFFFFFF; 1297 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1298 uint32_t lsb_mask = (1U << lsb) - 1; 1299 1300 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1301 return S; 1302 } 1303 1304 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1305 uint64_t Address, const void *Decoder) { 1306 DecodeStatus S = MCDisassembler::Success; 1307 1308 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1309 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1310 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1311 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1312 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1313 unsigned U = fieldFromInstruction(Insn, 23, 1); 1314 1315 switch (Inst.getOpcode()) { 1316 case ARM::LDC_OFFSET: 1317 case ARM::LDC_PRE: 1318 case ARM::LDC_POST: 1319 case ARM::LDC_OPTION: 1320 case ARM::LDCL_OFFSET: 1321 case ARM::LDCL_PRE: 1322 case ARM::LDCL_POST: 1323 case ARM::LDCL_OPTION: 1324 case ARM::STC_OFFSET: 1325 case ARM::STC_PRE: 1326 case ARM::STC_POST: 1327 case ARM::STC_OPTION: 1328 case ARM::STCL_OFFSET: 1329 case ARM::STCL_PRE: 1330 case ARM::STCL_POST: 1331 case ARM::STCL_OPTION: 1332 case ARM::t2LDC_OFFSET: 1333 case ARM::t2LDC_PRE: 1334 case ARM::t2LDC_POST: 1335 case ARM::t2LDC_OPTION: 1336 case ARM::t2LDCL_OFFSET: 1337 case ARM::t2LDCL_PRE: 1338 case ARM::t2LDCL_POST: 1339 case ARM::t2LDCL_OPTION: 1340 case ARM::t2STC_OFFSET: 1341 case ARM::t2STC_PRE: 1342 case ARM::t2STC_POST: 1343 case ARM::t2STC_OPTION: 1344 case ARM::t2STCL_OFFSET: 1345 case ARM::t2STCL_PRE: 1346 case ARM::t2STCL_POST: 1347 case ARM::t2STCL_OPTION: 1348 if (coproc == 0xA || coproc == 0xB) 1349 return MCDisassembler::Fail; 1350 break; 1351 default: 1352 break; 1353 } 1354 1355 Inst.addOperand(MCOperand::CreateImm(coproc)); 1356 Inst.addOperand(MCOperand::CreateImm(CRd)); 1357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1358 return MCDisassembler::Fail; 1359 1360 switch (Inst.getOpcode()) { 1361 case ARM::t2LDC2_OFFSET: 1362 case ARM::t2LDC2L_OFFSET: 1363 case ARM::t2LDC2_PRE: 1364 case ARM::t2LDC2L_PRE: 1365 case ARM::t2STC2_OFFSET: 1366 case ARM::t2STC2L_OFFSET: 1367 case ARM::t2STC2_PRE: 1368 case ARM::t2STC2L_PRE: 1369 case ARM::LDC2_OFFSET: 1370 case ARM::LDC2L_OFFSET: 1371 case ARM::LDC2_PRE: 1372 case ARM::LDC2L_PRE: 1373 case ARM::STC2_OFFSET: 1374 case ARM::STC2L_OFFSET: 1375 case ARM::STC2_PRE: 1376 case ARM::STC2L_PRE: 1377 case ARM::t2LDC_OFFSET: 1378 case ARM::t2LDCL_OFFSET: 1379 case ARM::t2LDC_PRE: 1380 case ARM::t2LDCL_PRE: 1381 case ARM::t2STC_OFFSET: 1382 case ARM::t2STCL_OFFSET: 1383 case ARM::t2STC_PRE: 1384 case ARM::t2STCL_PRE: 1385 case ARM::LDC_OFFSET: 1386 case ARM::LDCL_OFFSET: 1387 case ARM::LDC_PRE: 1388 case ARM::LDCL_PRE: 1389 case ARM::STC_OFFSET: 1390 case ARM::STCL_OFFSET: 1391 case ARM::STC_PRE: 1392 case ARM::STCL_PRE: 1393 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1394 Inst.addOperand(MCOperand::CreateImm(imm)); 1395 break; 1396 case ARM::t2LDC2_POST: 1397 case ARM::t2LDC2L_POST: 1398 case ARM::t2STC2_POST: 1399 case ARM::t2STC2L_POST: 1400 case ARM::LDC2_POST: 1401 case ARM::LDC2L_POST: 1402 case ARM::STC2_POST: 1403 case ARM::STC2L_POST: 1404 case ARM::t2LDC_POST: 1405 case ARM::t2LDCL_POST: 1406 case ARM::t2STC_POST: 1407 case ARM::t2STCL_POST: 1408 case ARM::LDC_POST: 1409 case ARM::LDCL_POST: 1410 case ARM::STC_POST: 1411 case ARM::STCL_POST: 1412 imm |= U << 8; 1413 // fall through. 1414 default: 1415 // The 'option' variant doesn't encode 'U' in the immediate since 1416 // the immediate is unsigned [0,255]. 1417 Inst.addOperand(MCOperand::CreateImm(imm)); 1418 break; 1419 } 1420 1421 switch (Inst.getOpcode()) { 1422 case ARM::LDC_OFFSET: 1423 case ARM::LDC_PRE: 1424 case ARM::LDC_POST: 1425 case ARM::LDC_OPTION: 1426 case ARM::LDCL_OFFSET: 1427 case ARM::LDCL_PRE: 1428 case ARM::LDCL_POST: 1429 case ARM::LDCL_OPTION: 1430 case ARM::STC_OFFSET: 1431 case ARM::STC_PRE: 1432 case ARM::STC_POST: 1433 case ARM::STC_OPTION: 1434 case ARM::STCL_OFFSET: 1435 case ARM::STCL_PRE: 1436 case ARM::STCL_POST: 1437 case ARM::STCL_OPTION: 1438 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1439 return MCDisassembler::Fail; 1440 break; 1441 default: 1442 break; 1443 } 1444 1445 return S; 1446 } 1447 1448 static DecodeStatus 1449 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1450 uint64_t Address, const void *Decoder) { 1451 DecodeStatus S = MCDisassembler::Success; 1452 1453 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1454 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1455 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1456 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1457 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1458 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1459 unsigned P = fieldFromInstruction(Insn, 24, 1); 1460 unsigned W = fieldFromInstruction(Insn, 21, 1); 1461 1462 // On stores, the writeback operand precedes Rt. 1463 switch (Inst.getOpcode()) { 1464 case ARM::STR_POST_IMM: 1465 case ARM::STR_POST_REG: 1466 case ARM::STRB_POST_IMM: 1467 case ARM::STRB_POST_REG: 1468 case ARM::STRT_POST_REG: 1469 case ARM::STRT_POST_IMM: 1470 case ARM::STRBT_POST_REG: 1471 case ARM::STRBT_POST_IMM: 1472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1473 return MCDisassembler::Fail; 1474 break; 1475 default: 1476 break; 1477 } 1478 1479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1480 return MCDisassembler::Fail; 1481 1482 // On loads, the writeback operand comes after Rt. 1483 switch (Inst.getOpcode()) { 1484 case ARM::LDR_POST_IMM: 1485 case ARM::LDR_POST_REG: 1486 case ARM::LDRB_POST_IMM: 1487 case ARM::LDRB_POST_REG: 1488 case ARM::LDRBT_POST_REG: 1489 case ARM::LDRBT_POST_IMM: 1490 case ARM::LDRT_POST_REG: 1491 case ARM::LDRT_POST_IMM: 1492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1493 return MCDisassembler::Fail; 1494 break; 1495 default: 1496 break; 1497 } 1498 1499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1500 return MCDisassembler::Fail; 1501 1502 ARM_AM::AddrOpc Op = ARM_AM::add; 1503 if (!fieldFromInstruction(Insn, 23, 1)) 1504 Op = ARM_AM::sub; 1505 1506 bool writeback = (P == 0) || (W == 1); 1507 unsigned idx_mode = 0; 1508 if (P && writeback) 1509 idx_mode = ARMII::IndexModePre; 1510 else if (!P && writeback) 1511 idx_mode = ARMII::IndexModePost; 1512 1513 if (writeback && (Rn == 15 || Rn == Rt)) 1514 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1515 1516 if (reg) { 1517 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1518 return MCDisassembler::Fail; 1519 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1520 switch( fieldFromInstruction(Insn, 5, 2)) { 1521 case 0: 1522 Opc = ARM_AM::lsl; 1523 break; 1524 case 1: 1525 Opc = ARM_AM::lsr; 1526 break; 1527 case 2: 1528 Opc = ARM_AM::asr; 1529 break; 1530 case 3: 1531 Opc = ARM_AM::ror; 1532 break; 1533 default: 1534 return MCDisassembler::Fail; 1535 } 1536 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1537 if (Opc == ARM_AM::ror && amt == 0) 1538 Opc = ARM_AM::rrx; 1539 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1540 1541 Inst.addOperand(MCOperand::CreateImm(imm)); 1542 } else { 1543 Inst.addOperand(MCOperand::CreateReg(0)); 1544 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1545 Inst.addOperand(MCOperand::CreateImm(tmp)); 1546 } 1547 1548 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1549 return MCDisassembler::Fail; 1550 1551 return S; 1552 } 1553 1554 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1555 uint64_t Address, const void *Decoder) { 1556 DecodeStatus S = MCDisassembler::Success; 1557 1558 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1559 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1560 unsigned type = fieldFromInstruction(Val, 5, 2); 1561 unsigned imm = fieldFromInstruction(Val, 7, 5); 1562 unsigned U = fieldFromInstruction(Val, 12, 1); 1563 1564 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1565 switch (type) { 1566 case 0: 1567 ShOp = ARM_AM::lsl; 1568 break; 1569 case 1: 1570 ShOp = ARM_AM::lsr; 1571 break; 1572 case 2: 1573 ShOp = ARM_AM::asr; 1574 break; 1575 case 3: 1576 ShOp = ARM_AM::ror; 1577 break; 1578 } 1579 1580 if (ShOp == ARM_AM::ror && imm == 0) 1581 ShOp = ARM_AM::rrx; 1582 1583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1584 return MCDisassembler::Fail; 1585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1586 return MCDisassembler::Fail; 1587 unsigned shift; 1588 if (U) 1589 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1590 else 1591 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1592 Inst.addOperand(MCOperand::CreateImm(shift)); 1593 1594 return S; 1595 } 1596 1597 static DecodeStatus 1598 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1599 uint64_t Address, const void *Decoder) { 1600 DecodeStatus S = MCDisassembler::Success; 1601 1602 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1603 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1604 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1605 unsigned type = fieldFromInstruction(Insn, 22, 1); 1606 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1607 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1608 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1609 unsigned W = fieldFromInstruction(Insn, 21, 1); 1610 unsigned P = fieldFromInstruction(Insn, 24, 1); 1611 unsigned Rt2 = Rt + 1; 1612 1613 bool writeback = (W == 1) | (P == 0); 1614 1615 // For {LD,ST}RD, Rt must be even, else undefined. 1616 switch (Inst.getOpcode()) { 1617 case ARM::STRD: 1618 case ARM::STRD_PRE: 1619 case ARM::STRD_POST: 1620 case ARM::LDRD: 1621 case ARM::LDRD_PRE: 1622 case ARM::LDRD_POST: 1623 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1624 break; 1625 default: 1626 break; 1627 } 1628 switch (Inst.getOpcode()) { 1629 case ARM::STRD: 1630 case ARM::STRD_PRE: 1631 case ARM::STRD_POST: 1632 if (P == 0 && W == 1) 1633 S = MCDisassembler::SoftFail; 1634 1635 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1636 S = MCDisassembler::SoftFail; 1637 if (type && Rm == 15) 1638 S = MCDisassembler::SoftFail; 1639 if (Rt2 == 15) 1640 S = MCDisassembler::SoftFail; 1641 if (!type && fieldFromInstruction(Insn, 8, 4)) 1642 S = MCDisassembler::SoftFail; 1643 break; 1644 case ARM::STRH: 1645 case ARM::STRH_PRE: 1646 case ARM::STRH_POST: 1647 if (Rt == 15) 1648 S = MCDisassembler::SoftFail; 1649 if (writeback && (Rn == 15 || Rn == Rt)) 1650 S = MCDisassembler::SoftFail; 1651 if (!type && Rm == 15) 1652 S = MCDisassembler::SoftFail; 1653 break; 1654 case ARM::LDRD: 1655 case ARM::LDRD_PRE: 1656 case ARM::LDRD_POST: 1657 if (type && Rn == 15){ 1658 if (Rt2 == 15) 1659 S = MCDisassembler::SoftFail; 1660 break; 1661 } 1662 if (P == 0 && W == 1) 1663 S = MCDisassembler::SoftFail; 1664 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1665 S = MCDisassembler::SoftFail; 1666 if (!type && writeback && Rn == 15) 1667 S = MCDisassembler::SoftFail; 1668 if (writeback && (Rn == Rt || Rn == Rt2)) 1669 S = MCDisassembler::SoftFail; 1670 break; 1671 case ARM::LDRH: 1672 case ARM::LDRH_PRE: 1673 case ARM::LDRH_POST: 1674 if (type && Rn == 15){ 1675 if (Rt == 15) 1676 S = MCDisassembler::SoftFail; 1677 break; 1678 } 1679 if (Rt == 15) 1680 S = MCDisassembler::SoftFail; 1681 if (!type && Rm == 15) 1682 S = MCDisassembler::SoftFail; 1683 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1684 S = MCDisassembler::SoftFail; 1685 break; 1686 case ARM::LDRSH: 1687 case ARM::LDRSH_PRE: 1688 case ARM::LDRSH_POST: 1689 case ARM::LDRSB: 1690 case ARM::LDRSB_PRE: 1691 case ARM::LDRSB_POST: 1692 if (type && Rn == 15){ 1693 if (Rt == 15) 1694 S = MCDisassembler::SoftFail; 1695 break; 1696 } 1697 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1698 S = MCDisassembler::SoftFail; 1699 if (!type && (Rt == 15 || Rm == 15)) 1700 S = MCDisassembler::SoftFail; 1701 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1702 S = MCDisassembler::SoftFail; 1703 break; 1704 default: 1705 break; 1706 } 1707 1708 if (writeback) { // Writeback 1709 if (P) 1710 U |= ARMII::IndexModePre << 9; 1711 else 1712 U |= ARMII::IndexModePost << 9; 1713 1714 // On stores, the writeback operand precedes Rt. 1715 switch (Inst.getOpcode()) { 1716 case ARM::STRD: 1717 case ARM::STRD_PRE: 1718 case ARM::STRD_POST: 1719 case ARM::STRH: 1720 case ARM::STRH_PRE: 1721 case ARM::STRH_POST: 1722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1723 return MCDisassembler::Fail; 1724 break; 1725 default: 1726 break; 1727 } 1728 } 1729 1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1731 return MCDisassembler::Fail; 1732 switch (Inst.getOpcode()) { 1733 case ARM::STRD: 1734 case ARM::STRD_PRE: 1735 case ARM::STRD_POST: 1736 case ARM::LDRD: 1737 case ARM::LDRD_PRE: 1738 case ARM::LDRD_POST: 1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 break; 1742 default: 1743 break; 1744 } 1745 1746 if (writeback) { 1747 // On loads, the writeback operand comes after Rt. 1748 switch (Inst.getOpcode()) { 1749 case ARM::LDRD: 1750 case ARM::LDRD_PRE: 1751 case ARM::LDRD_POST: 1752 case ARM::LDRH: 1753 case ARM::LDRH_PRE: 1754 case ARM::LDRH_POST: 1755 case ARM::LDRSH: 1756 case ARM::LDRSH_PRE: 1757 case ARM::LDRSH_POST: 1758 case ARM::LDRSB: 1759 case ARM::LDRSB_PRE: 1760 case ARM::LDRSB_POST: 1761 case ARM::LDRHTr: 1762 case ARM::LDRSBTr: 1763 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1764 return MCDisassembler::Fail; 1765 break; 1766 default: 1767 break; 1768 } 1769 } 1770 1771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1772 return MCDisassembler::Fail; 1773 1774 if (type) { 1775 Inst.addOperand(MCOperand::CreateReg(0)); 1776 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1777 } else { 1778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1779 return MCDisassembler::Fail; 1780 Inst.addOperand(MCOperand::CreateImm(U)); 1781 } 1782 1783 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1784 return MCDisassembler::Fail; 1785 1786 return S; 1787 } 1788 1789 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1790 uint64_t Address, const void *Decoder) { 1791 DecodeStatus S = MCDisassembler::Success; 1792 1793 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1794 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1795 1796 switch (mode) { 1797 case 0: 1798 mode = ARM_AM::da; 1799 break; 1800 case 1: 1801 mode = ARM_AM::ia; 1802 break; 1803 case 2: 1804 mode = ARM_AM::db; 1805 break; 1806 case 3: 1807 mode = ARM_AM::ib; 1808 break; 1809 } 1810 1811 Inst.addOperand(MCOperand::CreateImm(mode)); 1812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1813 return MCDisassembler::Fail; 1814 1815 return S; 1816 } 1817 1818 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1819 unsigned Insn, 1820 uint64_t Address, const void *Decoder) { 1821 DecodeStatus S = MCDisassembler::Success; 1822 1823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1824 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1825 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1826 1827 if (pred == 0xF) { 1828 switch (Inst.getOpcode()) { 1829 case ARM::LDMDA: 1830 Inst.setOpcode(ARM::RFEDA); 1831 break; 1832 case ARM::LDMDA_UPD: 1833 Inst.setOpcode(ARM::RFEDA_UPD); 1834 break; 1835 case ARM::LDMDB: 1836 Inst.setOpcode(ARM::RFEDB); 1837 break; 1838 case ARM::LDMDB_UPD: 1839 Inst.setOpcode(ARM::RFEDB_UPD); 1840 break; 1841 case ARM::LDMIA: 1842 Inst.setOpcode(ARM::RFEIA); 1843 break; 1844 case ARM::LDMIA_UPD: 1845 Inst.setOpcode(ARM::RFEIA_UPD); 1846 break; 1847 case ARM::LDMIB: 1848 Inst.setOpcode(ARM::RFEIB); 1849 break; 1850 case ARM::LDMIB_UPD: 1851 Inst.setOpcode(ARM::RFEIB_UPD); 1852 break; 1853 case ARM::STMDA: 1854 Inst.setOpcode(ARM::SRSDA); 1855 break; 1856 case ARM::STMDA_UPD: 1857 Inst.setOpcode(ARM::SRSDA_UPD); 1858 break; 1859 case ARM::STMDB: 1860 Inst.setOpcode(ARM::SRSDB); 1861 break; 1862 case ARM::STMDB_UPD: 1863 Inst.setOpcode(ARM::SRSDB_UPD); 1864 break; 1865 case ARM::STMIA: 1866 Inst.setOpcode(ARM::SRSIA); 1867 break; 1868 case ARM::STMIA_UPD: 1869 Inst.setOpcode(ARM::SRSIA_UPD); 1870 break; 1871 case ARM::STMIB: 1872 Inst.setOpcode(ARM::SRSIB); 1873 break; 1874 case ARM::STMIB_UPD: 1875 Inst.setOpcode(ARM::SRSIB_UPD); 1876 break; 1877 default: 1878 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1879 } 1880 1881 // For stores (which become SRS's, the only operand is the mode. 1882 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1883 Inst.addOperand( 1884 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1885 return S; 1886 } 1887 1888 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1889 } 1890 1891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1892 return MCDisassembler::Fail; 1893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1894 return MCDisassembler::Fail; // Tied 1895 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1896 return MCDisassembler::Fail; 1897 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 1900 return S; 1901 } 1902 1903 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1906 unsigned M = fieldFromInstruction(Insn, 17, 1); 1907 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1908 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1909 1910 DecodeStatus S = MCDisassembler::Success; 1911 1912 // imod == '01' --> UNPREDICTABLE 1913 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1914 // return failure here. The '01' imod value is unprintable, so there's 1915 // nothing useful we could do even if we returned UNPREDICTABLE. 1916 1917 if (imod == 1) return MCDisassembler::Fail; 1918 1919 if (imod && M) { 1920 Inst.setOpcode(ARM::CPS3p); 1921 Inst.addOperand(MCOperand::CreateImm(imod)); 1922 Inst.addOperand(MCOperand::CreateImm(iflags)); 1923 Inst.addOperand(MCOperand::CreateImm(mode)); 1924 } else if (imod && !M) { 1925 Inst.setOpcode(ARM::CPS2p); 1926 Inst.addOperand(MCOperand::CreateImm(imod)); 1927 Inst.addOperand(MCOperand::CreateImm(iflags)); 1928 if (mode) S = MCDisassembler::SoftFail; 1929 } else if (!imod && M) { 1930 Inst.setOpcode(ARM::CPS1p); 1931 Inst.addOperand(MCOperand::CreateImm(mode)); 1932 if (iflags) S = MCDisassembler::SoftFail; 1933 } else { 1934 // imod == '00' && M == '0' --> UNPREDICTABLE 1935 Inst.setOpcode(ARM::CPS1p); 1936 Inst.addOperand(MCOperand::CreateImm(mode)); 1937 S = MCDisassembler::SoftFail; 1938 } 1939 1940 return S; 1941 } 1942 1943 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1944 uint64_t Address, const void *Decoder) { 1945 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1946 unsigned M = fieldFromInstruction(Insn, 8, 1); 1947 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1948 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1949 1950 DecodeStatus S = MCDisassembler::Success; 1951 1952 // imod == '01' --> UNPREDICTABLE 1953 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1954 // return failure here. The '01' imod value is unprintable, so there's 1955 // nothing useful we could do even if we returned UNPREDICTABLE. 1956 1957 if (imod == 1) return MCDisassembler::Fail; 1958 1959 if (imod && M) { 1960 Inst.setOpcode(ARM::t2CPS3p); 1961 Inst.addOperand(MCOperand::CreateImm(imod)); 1962 Inst.addOperand(MCOperand::CreateImm(iflags)); 1963 Inst.addOperand(MCOperand::CreateImm(mode)); 1964 } else if (imod && !M) { 1965 Inst.setOpcode(ARM::t2CPS2p); 1966 Inst.addOperand(MCOperand::CreateImm(imod)); 1967 Inst.addOperand(MCOperand::CreateImm(iflags)); 1968 if (mode) S = MCDisassembler::SoftFail; 1969 } else if (!imod && M) { 1970 Inst.setOpcode(ARM::t2CPS1p); 1971 Inst.addOperand(MCOperand::CreateImm(mode)); 1972 if (iflags) S = MCDisassembler::SoftFail; 1973 } else { 1974 // imod == '00' && M == '0' --> this is a HINT instruction 1975 int imm = fieldFromInstruction(Insn, 0, 8); 1976 // HINT are defined only for immediate in [0..4] 1977 if(imm > 4) return MCDisassembler::Fail; 1978 Inst.setOpcode(ARM::t2HINT); 1979 Inst.addOperand(MCOperand::CreateImm(imm)); 1980 } 1981 1982 return S; 1983 } 1984 1985 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1986 uint64_t Address, const void *Decoder) { 1987 DecodeStatus S = MCDisassembler::Success; 1988 1989 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1990 unsigned imm = 0; 1991 1992 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1993 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1994 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1995 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1996 1997 if (Inst.getOpcode() == ARM::t2MOVTi16) 1998 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1999 return MCDisassembler::Fail; 2000 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2001 return MCDisassembler::Fail; 2002 2003 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2004 Inst.addOperand(MCOperand::CreateImm(imm)); 2005 2006 return S; 2007 } 2008 2009 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2010 uint64_t Address, const void *Decoder) { 2011 DecodeStatus S = MCDisassembler::Success; 2012 2013 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2014 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2015 unsigned imm = 0; 2016 2017 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2018 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2019 2020 if (Inst.getOpcode() == ARM::MOVTi16) 2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2022 return MCDisassembler::Fail; 2023 2024 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2025 return MCDisassembler::Fail; 2026 2027 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2028 Inst.addOperand(MCOperand::CreateImm(imm)); 2029 2030 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2031 return MCDisassembler::Fail; 2032 2033 return S; 2034 } 2035 2036 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2037 uint64_t Address, const void *Decoder) { 2038 DecodeStatus S = MCDisassembler::Success; 2039 2040 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2041 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2042 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2043 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2044 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2045 2046 if (pred == 0xF) 2047 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2048 2049 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2050 return MCDisassembler::Fail; 2051 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2052 return MCDisassembler::Fail; 2053 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2056 return MCDisassembler::Fail; 2057 2058 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 2061 return S; 2062 } 2063 2064 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2065 uint64_t Address, const void *Decoder) { 2066 DecodeStatus S = MCDisassembler::Success; 2067 2068 unsigned add = fieldFromInstruction(Val, 12, 1); 2069 unsigned imm = fieldFromInstruction(Val, 0, 12); 2070 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2071 2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2073 return MCDisassembler::Fail; 2074 2075 if (!add) imm *= -1; 2076 if (imm == 0 && !add) imm = INT32_MIN; 2077 Inst.addOperand(MCOperand::CreateImm(imm)); 2078 if (Rn == 15) 2079 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2080 2081 return S; 2082 } 2083 2084 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2085 uint64_t Address, const void *Decoder) { 2086 DecodeStatus S = MCDisassembler::Success; 2087 2088 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2089 unsigned U = fieldFromInstruction(Val, 8, 1); 2090 unsigned imm = fieldFromInstruction(Val, 0, 8); 2091 2092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2093 return MCDisassembler::Fail; 2094 2095 if (U) 2096 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2097 else 2098 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2099 2100 return S; 2101 } 2102 2103 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2104 uint64_t Address, const void *Decoder) { 2105 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2106 } 2107 2108 static DecodeStatus 2109 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2110 uint64_t Address, const void *Decoder) { 2111 DecodeStatus Status = MCDisassembler::Success; 2112 2113 // Note the J1 and J2 values are from the encoded instruction. So here 2114 // change them to I1 and I2 values via as documented: 2115 // I1 = NOT(J1 EOR S); 2116 // I2 = NOT(J2 EOR S); 2117 // and build the imm32 with one trailing zero as documented: 2118 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2119 unsigned S = fieldFromInstruction(Insn, 26, 1); 2120 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2121 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2122 unsigned I1 = !(J1 ^ S); 2123 unsigned I2 = !(J2 ^ S); 2124 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2125 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2126 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2127 int imm32 = SignExtend32<24>(tmp << 1); 2128 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2129 true, 4, Inst, Decoder)) 2130 Inst.addOperand(MCOperand::CreateImm(imm32)); 2131 2132 return Status; 2133 } 2134 2135 static DecodeStatus 2136 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2137 uint64_t Address, const void *Decoder) { 2138 DecodeStatus S = MCDisassembler::Success; 2139 2140 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2141 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2142 2143 if (pred == 0xF) { 2144 Inst.setOpcode(ARM::BLXi); 2145 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2146 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2147 true, 4, Inst, Decoder)) 2148 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2149 return S; 2150 } 2151 2152 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2153 true, 4, Inst, Decoder)) 2154 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2155 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2156 return MCDisassembler::Fail; 2157 2158 return S; 2159 } 2160 2161 2162 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2163 uint64_t Address, const void *Decoder) { 2164 DecodeStatus S = MCDisassembler::Success; 2165 2166 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2167 unsigned align = fieldFromInstruction(Val, 4, 2); 2168 2169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2170 return MCDisassembler::Fail; 2171 if (!align) 2172 Inst.addOperand(MCOperand::CreateImm(0)); 2173 else 2174 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2175 2176 return S; 2177 } 2178 2179 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2180 uint64_t Address, const void *Decoder) { 2181 DecodeStatus S = MCDisassembler::Success; 2182 2183 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2184 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2185 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2186 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2187 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2188 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2189 2190 // First output register 2191 switch (Inst.getOpcode()) { 2192 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2193 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2194 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2195 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2196 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2197 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2198 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2199 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2200 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2201 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2202 return MCDisassembler::Fail; 2203 break; 2204 case ARM::VLD2b16: 2205 case ARM::VLD2b32: 2206 case ARM::VLD2b8: 2207 case ARM::VLD2b16wb_fixed: 2208 case ARM::VLD2b16wb_register: 2209 case ARM::VLD2b32wb_fixed: 2210 case ARM::VLD2b32wb_register: 2211 case ARM::VLD2b8wb_fixed: 2212 case ARM::VLD2b8wb_register: 2213 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2214 return MCDisassembler::Fail; 2215 break; 2216 default: 2217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 } 2220 2221 // Second output register 2222 switch (Inst.getOpcode()) { 2223 case ARM::VLD3d8: 2224 case ARM::VLD3d16: 2225 case ARM::VLD3d32: 2226 case ARM::VLD3d8_UPD: 2227 case ARM::VLD3d16_UPD: 2228 case ARM::VLD3d32_UPD: 2229 case ARM::VLD4d8: 2230 case ARM::VLD4d16: 2231 case ARM::VLD4d32: 2232 case ARM::VLD4d8_UPD: 2233 case ARM::VLD4d16_UPD: 2234 case ARM::VLD4d32_UPD: 2235 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2236 return MCDisassembler::Fail; 2237 break; 2238 case ARM::VLD3q8: 2239 case ARM::VLD3q16: 2240 case ARM::VLD3q32: 2241 case ARM::VLD3q8_UPD: 2242 case ARM::VLD3q16_UPD: 2243 case ARM::VLD3q32_UPD: 2244 case ARM::VLD4q8: 2245 case ARM::VLD4q16: 2246 case ARM::VLD4q32: 2247 case ARM::VLD4q8_UPD: 2248 case ARM::VLD4q16_UPD: 2249 case ARM::VLD4q32_UPD: 2250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 default: 2253 break; 2254 } 2255 2256 // Third output register 2257 switch(Inst.getOpcode()) { 2258 case ARM::VLD3d8: 2259 case ARM::VLD3d16: 2260 case ARM::VLD3d32: 2261 case ARM::VLD3d8_UPD: 2262 case ARM::VLD3d16_UPD: 2263 case ARM::VLD3d32_UPD: 2264 case ARM::VLD4d8: 2265 case ARM::VLD4d16: 2266 case ARM::VLD4d32: 2267 case ARM::VLD4d8_UPD: 2268 case ARM::VLD4d16_UPD: 2269 case ARM::VLD4d32_UPD: 2270 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 break; 2273 case ARM::VLD3q8: 2274 case ARM::VLD3q16: 2275 case ARM::VLD3q32: 2276 case ARM::VLD3q8_UPD: 2277 case ARM::VLD3q16_UPD: 2278 case ARM::VLD3q32_UPD: 2279 case ARM::VLD4q8: 2280 case ARM::VLD4q16: 2281 case ARM::VLD4q32: 2282 case ARM::VLD4q8_UPD: 2283 case ARM::VLD4q16_UPD: 2284 case ARM::VLD4q32_UPD: 2285 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2286 return MCDisassembler::Fail; 2287 break; 2288 default: 2289 break; 2290 } 2291 2292 // Fourth output register 2293 switch (Inst.getOpcode()) { 2294 case ARM::VLD4d8: 2295 case ARM::VLD4d16: 2296 case ARM::VLD4d32: 2297 case ARM::VLD4d8_UPD: 2298 case ARM::VLD4d16_UPD: 2299 case ARM::VLD4d32_UPD: 2300 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 break; 2303 case ARM::VLD4q8: 2304 case ARM::VLD4q16: 2305 case ARM::VLD4q32: 2306 case ARM::VLD4q8_UPD: 2307 case ARM::VLD4q16_UPD: 2308 case ARM::VLD4q32_UPD: 2309 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2310 return MCDisassembler::Fail; 2311 break; 2312 default: 2313 break; 2314 } 2315 2316 // Writeback operand 2317 switch (Inst.getOpcode()) { 2318 case ARM::VLD1d8wb_fixed: 2319 case ARM::VLD1d16wb_fixed: 2320 case ARM::VLD1d32wb_fixed: 2321 case ARM::VLD1d64wb_fixed: 2322 case ARM::VLD1d8wb_register: 2323 case ARM::VLD1d16wb_register: 2324 case ARM::VLD1d32wb_register: 2325 case ARM::VLD1d64wb_register: 2326 case ARM::VLD1q8wb_fixed: 2327 case ARM::VLD1q16wb_fixed: 2328 case ARM::VLD1q32wb_fixed: 2329 case ARM::VLD1q64wb_fixed: 2330 case ARM::VLD1q8wb_register: 2331 case ARM::VLD1q16wb_register: 2332 case ARM::VLD1q32wb_register: 2333 case ARM::VLD1q64wb_register: 2334 case ARM::VLD1d8Twb_fixed: 2335 case ARM::VLD1d8Twb_register: 2336 case ARM::VLD1d16Twb_fixed: 2337 case ARM::VLD1d16Twb_register: 2338 case ARM::VLD1d32Twb_fixed: 2339 case ARM::VLD1d32Twb_register: 2340 case ARM::VLD1d64Twb_fixed: 2341 case ARM::VLD1d64Twb_register: 2342 case ARM::VLD1d8Qwb_fixed: 2343 case ARM::VLD1d8Qwb_register: 2344 case ARM::VLD1d16Qwb_fixed: 2345 case ARM::VLD1d16Qwb_register: 2346 case ARM::VLD1d32Qwb_fixed: 2347 case ARM::VLD1d32Qwb_register: 2348 case ARM::VLD1d64Qwb_fixed: 2349 case ARM::VLD1d64Qwb_register: 2350 case ARM::VLD2d8wb_fixed: 2351 case ARM::VLD2d16wb_fixed: 2352 case ARM::VLD2d32wb_fixed: 2353 case ARM::VLD2q8wb_fixed: 2354 case ARM::VLD2q16wb_fixed: 2355 case ARM::VLD2q32wb_fixed: 2356 case ARM::VLD2d8wb_register: 2357 case ARM::VLD2d16wb_register: 2358 case ARM::VLD2d32wb_register: 2359 case ARM::VLD2q8wb_register: 2360 case ARM::VLD2q16wb_register: 2361 case ARM::VLD2q32wb_register: 2362 case ARM::VLD2b8wb_fixed: 2363 case ARM::VLD2b16wb_fixed: 2364 case ARM::VLD2b32wb_fixed: 2365 case ARM::VLD2b8wb_register: 2366 case ARM::VLD2b16wb_register: 2367 case ARM::VLD2b32wb_register: 2368 Inst.addOperand(MCOperand::CreateImm(0)); 2369 break; 2370 case ARM::VLD3d8_UPD: 2371 case ARM::VLD3d16_UPD: 2372 case ARM::VLD3d32_UPD: 2373 case ARM::VLD3q8_UPD: 2374 case ARM::VLD3q16_UPD: 2375 case ARM::VLD3q32_UPD: 2376 case ARM::VLD4d8_UPD: 2377 case ARM::VLD4d16_UPD: 2378 case ARM::VLD4d32_UPD: 2379 case ARM::VLD4q8_UPD: 2380 case ARM::VLD4q16_UPD: 2381 case ARM::VLD4q32_UPD: 2382 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2383 return MCDisassembler::Fail; 2384 break; 2385 default: 2386 break; 2387 } 2388 2389 // AddrMode6 Base (register+alignment) 2390 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2391 return MCDisassembler::Fail; 2392 2393 // AddrMode6 Offset (register) 2394 switch (Inst.getOpcode()) { 2395 default: 2396 // The below have been updated to have explicit am6offset split 2397 // between fixed and register offset. For those instructions not 2398 // yet updated, we need to add an additional reg0 operand for the 2399 // fixed variant. 2400 // 2401 // The fixed offset encodes as Rm == 0xd, so we check for that. 2402 if (Rm == 0xd) { 2403 Inst.addOperand(MCOperand::CreateReg(0)); 2404 break; 2405 } 2406 // Fall through to handle the register offset variant. 2407 case ARM::VLD1d8wb_fixed: 2408 case ARM::VLD1d16wb_fixed: 2409 case ARM::VLD1d32wb_fixed: 2410 case ARM::VLD1d64wb_fixed: 2411 case ARM::VLD1d8Twb_fixed: 2412 case ARM::VLD1d16Twb_fixed: 2413 case ARM::VLD1d32Twb_fixed: 2414 case ARM::VLD1d64Twb_fixed: 2415 case ARM::VLD1d8Qwb_fixed: 2416 case ARM::VLD1d16Qwb_fixed: 2417 case ARM::VLD1d32Qwb_fixed: 2418 case ARM::VLD1d64Qwb_fixed: 2419 case ARM::VLD1d8wb_register: 2420 case ARM::VLD1d16wb_register: 2421 case ARM::VLD1d32wb_register: 2422 case ARM::VLD1d64wb_register: 2423 case ARM::VLD1q8wb_fixed: 2424 case ARM::VLD1q16wb_fixed: 2425 case ARM::VLD1q32wb_fixed: 2426 case ARM::VLD1q64wb_fixed: 2427 case ARM::VLD1q8wb_register: 2428 case ARM::VLD1q16wb_register: 2429 case ARM::VLD1q32wb_register: 2430 case ARM::VLD1q64wb_register: 2431 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2432 // variant encodes Rm == 0xf. Anything else is a register offset post- 2433 // increment and we need to add the register operand to the instruction. 2434 if (Rm != 0xD && Rm != 0xF && 2435 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2436 return MCDisassembler::Fail; 2437 break; 2438 case ARM::VLD2d8wb_fixed: 2439 case ARM::VLD2d16wb_fixed: 2440 case ARM::VLD2d32wb_fixed: 2441 case ARM::VLD2b8wb_fixed: 2442 case ARM::VLD2b16wb_fixed: 2443 case ARM::VLD2b32wb_fixed: 2444 case ARM::VLD2q8wb_fixed: 2445 case ARM::VLD2q16wb_fixed: 2446 case ARM::VLD2q32wb_fixed: 2447 break; 2448 } 2449 2450 return S; 2451 } 2452 2453 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2454 uint64_t Address, const void *Decoder) { 2455 DecodeStatus S = MCDisassembler::Success; 2456 2457 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2458 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2459 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2460 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2461 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2462 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2463 2464 // Writeback Operand 2465 switch (Inst.getOpcode()) { 2466 case ARM::VST1d8wb_fixed: 2467 case ARM::VST1d16wb_fixed: 2468 case ARM::VST1d32wb_fixed: 2469 case ARM::VST1d64wb_fixed: 2470 case ARM::VST1d8wb_register: 2471 case ARM::VST1d16wb_register: 2472 case ARM::VST1d32wb_register: 2473 case ARM::VST1d64wb_register: 2474 case ARM::VST1q8wb_fixed: 2475 case ARM::VST1q16wb_fixed: 2476 case ARM::VST1q32wb_fixed: 2477 case ARM::VST1q64wb_fixed: 2478 case ARM::VST1q8wb_register: 2479 case ARM::VST1q16wb_register: 2480 case ARM::VST1q32wb_register: 2481 case ARM::VST1q64wb_register: 2482 case ARM::VST1d8Twb_fixed: 2483 case ARM::VST1d16Twb_fixed: 2484 case ARM::VST1d32Twb_fixed: 2485 case ARM::VST1d64Twb_fixed: 2486 case ARM::VST1d8Twb_register: 2487 case ARM::VST1d16Twb_register: 2488 case ARM::VST1d32Twb_register: 2489 case ARM::VST1d64Twb_register: 2490 case ARM::VST1d8Qwb_fixed: 2491 case ARM::VST1d16Qwb_fixed: 2492 case ARM::VST1d32Qwb_fixed: 2493 case ARM::VST1d64Qwb_fixed: 2494 case ARM::VST1d8Qwb_register: 2495 case ARM::VST1d16Qwb_register: 2496 case ARM::VST1d32Qwb_register: 2497 case ARM::VST1d64Qwb_register: 2498 case ARM::VST2d8wb_fixed: 2499 case ARM::VST2d16wb_fixed: 2500 case ARM::VST2d32wb_fixed: 2501 case ARM::VST2d8wb_register: 2502 case ARM::VST2d16wb_register: 2503 case ARM::VST2d32wb_register: 2504 case ARM::VST2q8wb_fixed: 2505 case ARM::VST2q16wb_fixed: 2506 case ARM::VST2q32wb_fixed: 2507 case ARM::VST2q8wb_register: 2508 case ARM::VST2q16wb_register: 2509 case ARM::VST2q32wb_register: 2510 case ARM::VST2b8wb_fixed: 2511 case ARM::VST2b16wb_fixed: 2512 case ARM::VST2b32wb_fixed: 2513 case ARM::VST2b8wb_register: 2514 case ARM::VST2b16wb_register: 2515 case ARM::VST2b32wb_register: 2516 if (Rm == 0xF) 2517 return MCDisassembler::Fail; 2518 Inst.addOperand(MCOperand::CreateImm(0)); 2519 break; 2520 case ARM::VST3d8_UPD: 2521 case ARM::VST3d16_UPD: 2522 case ARM::VST3d32_UPD: 2523 case ARM::VST3q8_UPD: 2524 case ARM::VST3q16_UPD: 2525 case ARM::VST3q32_UPD: 2526 case ARM::VST4d8_UPD: 2527 case ARM::VST4d16_UPD: 2528 case ARM::VST4d32_UPD: 2529 case ARM::VST4q8_UPD: 2530 case ARM::VST4q16_UPD: 2531 case ARM::VST4q32_UPD: 2532 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2533 return MCDisassembler::Fail; 2534 break; 2535 default: 2536 break; 2537 } 2538 2539 // AddrMode6 Base (register+alignment) 2540 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2541 return MCDisassembler::Fail; 2542 2543 // AddrMode6 Offset (register) 2544 switch (Inst.getOpcode()) { 2545 default: 2546 if (Rm == 0xD) 2547 Inst.addOperand(MCOperand::CreateReg(0)); 2548 else if (Rm != 0xF) { 2549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2550 return MCDisassembler::Fail; 2551 } 2552 break; 2553 case ARM::VST1d8wb_fixed: 2554 case ARM::VST1d16wb_fixed: 2555 case ARM::VST1d32wb_fixed: 2556 case ARM::VST1d64wb_fixed: 2557 case ARM::VST1q8wb_fixed: 2558 case ARM::VST1q16wb_fixed: 2559 case ARM::VST1q32wb_fixed: 2560 case ARM::VST1q64wb_fixed: 2561 case ARM::VST1d8Twb_fixed: 2562 case ARM::VST1d16Twb_fixed: 2563 case ARM::VST1d32Twb_fixed: 2564 case ARM::VST1d64Twb_fixed: 2565 case ARM::VST1d8Qwb_fixed: 2566 case ARM::VST1d16Qwb_fixed: 2567 case ARM::VST1d32Qwb_fixed: 2568 case ARM::VST1d64Qwb_fixed: 2569 case ARM::VST2d8wb_fixed: 2570 case ARM::VST2d16wb_fixed: 2571 case ARM::VST2d32wb_fixed: 2572 case ARM::VST2q8wb_fixed: 2573 case ARM::VST2q16wb_fixed: 2574 case ARM::VST2q32wb_fixed: 2575 case ARM::VST2b8wb_fixed: 2576 case ARM::VST2b16wb_fixed: 2577 case ARM::VST2b32wb_fixed: 2578 break; 2579 } 2580 2581 2582 // First input register 2583 switch (Inst.getOpcode()) { 2584 case ARM::VST1q16: 2585 case ARM::VST1q32: 2586 case ARM::VST1q64: 2587 case ARM::VST1q8: 2588 case ARM::VST1q16wb_fixed: 2589 case ARM::VST1q16wb_register: 2590 case ARM::VST1q32wb_fixed: 2591 case ARM::VST1q32wb_register: 2592 case ARM::VST1q64wb_fixed: 2593 case ARM::VST1q64wb_register: 2594 case ARM::VST1q8wb_fixed: 2595 case ARM::VST1q8wb_register: 2596 case ARM::VST2d16: 2597 case ARM::VST2d32: 2598 case ARM::VST2d8: 2599 case ARM::VST2d16wb_fixed: 2600 case ARM::VST2d16wb_register: 2601 case ARM::VST2d32wb_fixed: 2602 case ARM::VST2d32wb_register: 2603 case ARM::VST2d8wb_fixed: 2604 case ARM::VST2d8wb_register: 2605 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2606 return MCDisassembler::Fail; 2607 break; 2608 case ARM::VST2b16: 2609 case ARM::VST2b32: 2610 case ARM::VST2b8: 2611 case ARM::VST2b16wb_fixed: 2612 case ARM::VST2b16wb_register: 2613 case ARM::VST2b32wb_fixed: 2614 case ARM::VST2b32wb_register: 2615 case ARM::VST2b8wb_fixed: 2616 case ARM::VST2b8wb_register: 2617 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2618 return MCDisassembler::Fail; 2619 break; 2620 default: 2621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2622 return MCDisassembler::Fail; 2623 } 2624 2625 // Second input register 2626 switch (Inst.getOpcode()) { 2627 case ARM::VST3d8: 2628 case ARM::VST3d16: 2629 case ARM::VST3d32: 2630 case ARM::VST3d8_UPD: 2631 case ARM::VST3d16_UPD: 2632 case ARM::VST3d32_UPD: 2633 case ARM::VST4d8: 2634 case ARM::VST4d16: 2635 case ARM::VST4d32: 2636 case ARM::VST4d8_UPD: 2637 case ARM::VST4d16_UPD: 2638 case ARM::VST4d32_UPD: 2639 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2640 return MCDisassembler::Fail; 2641 break; 2642 case ARM::VST3q8: 2643 case ARM::VST3q16: 2644 case ARM::VST3q32: 2645 case ARM::VST3q8_UPD: 2646 case ARM::VST3q16_UPD: 2647 case ARM::VST3q32_UPD: 2648 case ARM::VST4q8: 2649 case ARM::VST4q16: 2650 case ARM::VST4q32: 2651 case ARM::VST4q8_UPD: 2652 case ARM::VST4q16_UPD: 2653 case ARM::VST4q32_UPD: 2654 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 break; 2657 default: 2658 break; 2659 } 2660 2661 // Third input register 2662 switch (Inst.getOpcode()) { 2663 case ARM::VST3d8: 2664 case ARM::VST3d16: 2665 case ARM::VST3d32: 2666 case ARM::VST3d8_UPD: 2667 case ARM::VST3d16_UPD: 2668 case ARM::VST3d32_UPD: 2669 case ARM::VST4d8: 2670 case ARM::VST4d16: 2671 case ARM::VST4d32: 2672 case ARM::VST4d8_UPD: 2673 case ARM::VST4d16_UPD: 2674 case ARM::VST4d32_UPD: 2675 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2676 return MCDisassembler::Fail; 2677 break; 2678 case ARM::VST3q8: 2679 case ARM::VST3q16: 2680 case ARM::VST3q32: 2681 case ARM::VST3q8_UPD: 2682 case ARM::VST3q16_UPD: 2683 case ARM::VST3q32_UPD: 2684 case ARM::VST4q8: 2685 case ARM::VST4q16: 2686 case ARM::VST4q32: 2687 case ARM::VST4q8_UPD: 2688 case ARM::VST4q16_UPD: 2689 case ARM::VST4q32_UPD: 2690 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2691 return MCDisassembler::Fail; 2692 break; 2693 default: 2694 break; 2695 } 2696 2697 // Fourth input register 2698 switch (Inst.getOpcode()) { 2699 case ARM::VST4d8: 2700 case ARM::VST4d16: 2701 case ARM::VST4d32: 2702 case ARM::VST4d8_UPD: 2703 case ARM::VST4d16_UPD: 2704 case ARM::VST4d32_UPD: 2705 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2706 return MCDisassembler::Fail; 2707 break; 2708 case ARM::VST4q8: 2709 case ARM::VST4q16: 2710 case ARM::VST4q32: 2711 case ARM::VST4q8_UPD: 2712 case ARM::VST4q16_UPD: 2713 case ARM::VST4q32_UPD: 2714 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2715 return MCDisassembler::Fail; 2716 break; 2717 default: 2718 break; 2719 } 2720 2721 return S; 2722 } 2723 2724 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2725 uint64_t Address, const void *Decoder) { 2726 DecodeStatus S = MCDisassembler::Success; 2727 2728 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2729 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2730 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2731 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2732 unsigned align = fieldFromInstruction(Insn, 4, 1); 2733 unsigned size = fieldFromInstruction(Insn, 6, 2); 2734 2735 if (size == 0 && align == 1) 2736 return MCDisassembler::Fail; 2737 align *= (1 << size); 2738 2739 switch (Inst.getOpcode()) { 2740 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2741 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2742 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2743 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2744 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 break; 2747 default: 2748 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 break; 2751 } 2752 if (Rm != 0xF) { 2753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 } 2756 2757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2758 return MCDisassembler::Fail; 2759 Inst.addOperand(MCOperand::CreateImm(align)); 2760 2761 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2762 // variant encodes Rm == 0xf. Anything else is a register offset post- 2763 // increment and we need to add the register operand to the instruction. 2764 if (Rm != 0xD && Rm != 0xF && 2765 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2766 return MCDisassembler::Fail; 2767 2768 return S; 2769 } 2770 2771 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2772 uint64_t Address, const void *Decoder) { 2773 DecodeStatus S = MCDisassembler::Success; 2774 2775 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2776 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2777 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2778 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2779 unsigned align = fieldFromInstruction(Insn, 4, 1); 2780 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2781 align *= 2*size; 2782 2783 switch (Inst.getOpcode()) { 2784 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2785 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2786 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2787 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2788 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 break; 2791 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2792 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2793 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2794 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2795 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2796 return MCDisassembler::Fail; 2797 break; 2798 default: 2799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 break; 2802 } 2803 2804 if (Rm != 0xF) 2805 Inst.addOperand(MCOperand::CreateImm(0)); 2806 2807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2808 return MCDisassembler::Fail; 2809 Inst.addOperand(MCOperand::CreateImm(align)); 2810 2811 if (Rm != 0xD && Rm != 0xF) { 2812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2813 return MCDisassembler::Fail; 2814 } 2815 2816 return S; 2817 } 2818 2819 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2820 uint64_t Address, const void *Decoder) { 2821 DecodeStatus S = MCDisassembler::Success; 2822 2823 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2824 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2825 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2826 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2827 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2828 2829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2830 return MCDisassembler::Fail; 2831 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2832 return MCDisassembler::Fail; 2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 if (Rm != 0xF) { 2836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2837 return MCDisassembler::Fail; 2838 } 2839 2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2841 return MCDisassembler::Fail; 2842 Inst.addOperand(MCOperand::CreateImm(0)); 2843 2844 if (Rm == 0xD) 2845 Inst.addOperand(MCOperand::CreateReg(0)); 2846 else if (Rm != 0xF) { 2847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2848 return MCDisassembler::Fail; 2849 } 2850 2851 return S; 2852 } 2853 2854 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2855 uint64_t Address, const void *Decoder) { 2856 DecodeStatus S = MCDisassembler::Success; 2857 2858 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2859 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2860 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2861 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2862 unsigned size = fieldFromInstruction(Insn, 6, 2); 2863 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2864 unsigned align = fieldFromInstruction(Insn, 4, 1); 2865 2866 if (size == 0x3) { 2867 if (align == 0) 2868 return MCDisassembler::Fail; 2869 size = 4; 2870 align = 16; 2871 } else { 2872 if (size == 2) { 2873 size = 1 << size; 2874 align *= 8; 2875 } else { 2876 size = 1 << size; 2877 align *= 4*size; 2878 } 2879 } 2880 2881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2882 return MCDisassembler::Fail; 2883 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2886 return MCDisassembler::Fail; 2887 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 if (Rm != 0xF) { 2890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2891 return MCDisassembler::Fail; 2892 } 2893 2894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 Inst.addOperand(MCOperand::CreateImm(align)); 2897 2898 if (Rm == 0xD) 2899 Inst.addOperand(MCOperand::CreateReg(0)); 2900 else if (Rm != 0xF) { 2901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2902 return MCDisassembler::Fail; 2903 } 2904 2905 return S; 2906 } 2907 2908 static DecodeStatus 2909 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2910 uint64_t Address, const void *Decoder) { 2911 DecodeStatus S = MCDisassembler::Success; 2912 2913 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2914 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2915 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2916 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2917 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2918 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2919 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2920 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2921 2922 if (Q) { 2923 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 } else { 2926 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 } 2929 2930 Inst.addOperand(MCOperand::CreateImm(imm)); 2931 2932 switch (Inst.getOpcode()) { 2933 case ARM::VORRiv4i16: 2934 case ARM::VORRiv2i32: 2935 case ARM::VBICiv4i16: 2936 case ARM::VBICiv2i32: 2937 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 break; 2940 case ARM::VORRiv8i16: 2941 case ARM::VORRiv4i32: 2942 case ARM::VBICiv8i16: 2943 case ARM::VBICiv4i32: 2944 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 break; 2947 default: 2948 break; 2949 } 2950 2951 return S; 2952 } 2953 2954 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2955 uint64_t Address, const void *Decoder) { 2956 DecodeStatus S = MCDisassembler::Success; 2957 2958 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2959 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2960 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2961 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2962 unsigned size = fieldFromInstruction(Insn, 18, 2); 2963 2964 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2965 return MCDisassembler::Fail; 2966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2967 return MCDisassembler::Fail; 2968 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2969 2970 return S; 2971 } 2972 2973 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2974 uint64_t Address, const void *Decoder) { 2975 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2976 return MCDisassembler::Success; 2977 } 2978 2979 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2980 uint64_t Address, const void *Decoder) { 2981 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2982 return MCDisassembler::Success; 2983 } 2984 2985 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2986 uint64_t Address, const void *Decoder) { 2987 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2988 return MCDisassembler::Success; 2989 } 2990 2991 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2992 uint64_t Address, const void *Decoder) { 2993 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2994 return MCDisassembler::Success; 2995 } 2996 2997 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2998 uint64_t Address, const void *Decoder) { 2999 DecodeStatus S = MCDisassembler::Success; 3000 3001 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3002 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3004 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3005 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3006 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3007 unsigned op = fieldFromInstruction(Insn, 6, 1); 3008 3009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 if (op) { 3012 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3013 return MCDisassembler::Fail; // Writeback 3014 } 3015 3016 switch (Inst.getOpcode()) { 3017 case ARM::VTBL2: 3018 case ARM::VTBX2: 3019 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3020 return MCDisassembler::Fail; 3021 break; 3022 default: 3023 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3024 return MCDisassembler::Fail; 3025 } 3026 3027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3028 return MCDisassembler::Fail; 3029 3030 return S; 3031 } 3032 3033 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3034 uint64_t Address, const void *Decoder) { 3035 DecodeStatus S = MCDisassembler::Success; 3036 3037 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3038 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3039 3040 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3041 return MCDisassembler::Fail; 3042 3043 switch(Inst.getOpcode()) { 3044 default: 3045 return MCDisassembler::Fail; 3046 case ARM::tADR: 3047 break; // tADR does not explicitly represent the PC as an operand. 3048 case ARM::tADDrSPi: 3049 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3050 break; 3051 } 3052 3053 Inst.addOperand(MCOperand::CreateImm(imm)); 3054 return S; 3055 } 3056 3057 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3058 uint64_t Address, const void *Decoder) { 3059 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3060 true, 2, Inst, Decoder)) 3061 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3062 return MCDisassembler::Success; 3063 } 3064 3065 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3066 uint64_t Address, const void *Decoder) { 3067 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3068 true, 4, Inst, Decoder)) 3069 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3070 return MCDisassembler::Success; 3071 } 3072 3073 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3074 uint64_t Address, const void *Decoder) { 3075 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3076 true, 2, Inst, Decoder)) 3077 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3078 return MCDisassembler::Success; 3079 } 3080 3081 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3082 uint64_t Address, const void *Decoder) { 3083 DecodeStatus S = MCDisassembler::Success; 3084 3085 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3086 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3087 3088 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3091 return MCDisassembler::Fail; 3092 3093 return S; 3094 } 3095 3096 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3097 uint64_t Address, const void *Decoder) { 3098 DecodeStatus S = MCDisassembler::Success; 3099 3100 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3101 unsigned imm = fieldFromInstruction(Val, 3, 5); 3102 3103 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3104 return MCDisassembler::Fail; 3105 Inst.addOperand(MCOperand::CreateImm(imm)); 3106 3107 return S; 3108 } 3109 3110 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3111 uint64_t Address, const void *Decoder) { 3112 unsigned imm = Val << 2; 3113 3114 Inst.addOperand(MCOperand::CreateImm(imm)); 3115 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3116 3117 return MCDisassembler::Success; 3118 } 3119 3120 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3121 uint64_t Address, const void *Decoder) { 3122 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3123 Inst.addOperand(MCOperand::CreateImm(Val)); 3124 3125 return MCDisassembler::Success; 3126 } 3127 3128 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3129 uint64_t Address, const void *Decoder) { 3130 DecodeStatus S = MCDisassembler::Success; 3131 3132 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3133 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3134 unsigned imm = fieldFromInstruction(Val, 0, 2); 3135 3136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 Inst.addOperand(MCOperand::CreateImm(imm)); 3141 3142 return S; 3143 } 3144 3145 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3146 uint64_t Address, const void *Decoder) { 3147 DecodeStatus S = MCDisassembler::Success; 3148 3149 switch (Inst.getOpcode()) { 3150 case ARM::t2PLDs: 3151 case ARM::t2PLDWs: 3152 case ARM::t2PLIs: 3153 break; 3154 default: { 3155 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3156 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3157 return MCDisassembler::Fail; 3158 } 3159 } 3160 3161 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3162 if (Rn == 0xF) { 3163 switch (Inst.getOpcode()) { 3164 case ARM::t2LDRBs: 3165 Inst.setOpcode(ARM::t2LDRBpci); 3166 break; 3167 case ARM::t2LDRHs: 3168 Inst.setOpcode(ARM::t2LDRHpci); 3169 break; 3170 case ARM::t2LDRSHs: 3171 Inst.setOpcode(ARM::t2LDRSHpci); 3172 break; 3173 case ARM::t2LDRSBs: 3174 Inst.setOpcode(ARM::t2LDRSBpci); 3175 break; 3176 case ARM::t2PLDs: 3177 Inst.setOpcode(ARM::t2PLDi12); 3178 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3179 break; 3180 default: 3181 return MCDisassembler::Fail; 3182 } 3183 3184 int imm = fieldFromInstruction(Insn, 0, 12); 3185 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3186 Inst.addOperand(MCOperand::CreateImm(imm)); 3187 3188 return S; 3189 } 3190 3191 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3192 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3193 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3194 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3195 return MCDisassembler::Fail; 3196 3197 return S; 3198 } 3199 3200 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3201 uint64_t Address, const void *Decoder) { 3202 if (Val == 0) 3203 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3204 else { 3205 int imm = Val & 0xFF; 3206 3207 if (!(Val & 0x100)) imm *= -1; 3208 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3209 } 3210 3211 return MCDisassembler::Success; 3212 } 3213 3214 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3215 uint64_t Address, const void *Decoder) { 3216 DecodeStatus S = MCDisassembler::Success; 3217 3218 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3219 unsigned imm = fieldFromInstruction(Val, 0, 9); 3220 3221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3222 return MCDisassembler::Fail; 3223 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 3226 return S; 3227 } 3228 3229 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3230 uint64_t Address, const void *Decoder) { 3231 DecodeStatus S = MCDisassembler::Success; 3232 3233 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3234 unsigned imm = fieldFromInstruction(Val, 0, 8); 3235 3236 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3237 return MCDisassembler::Fail; 3238 3239 Inst.addOperand(MCOperand::CreateImm(imm)); 3240 3241 return S; 3242 } 3243 3244 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3245 uint64_t Address, const void *Decoder) { 3246 int imm = Val & 0xFF; 3247 if (Val == 0) 3248 imm = INT32_MIN; 3249 else if (!(Val & 0x100)) 3250 imm *= -1; 3251 Inst.addOperand(MCOperand::CreateImm(imm)); 3252 3253 return MCDisassembler::Success; 3254 } 3255 3256 3257 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3258 uint64_t Address, const void *Decoder) { 3259 DecodeStatus S = MCDisassembler::Success; 3260 3261 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3262 unsigned imm = fieldFromInstruction(Val, 0, 9); 3263 3264 // Some instructions always use an additive offset. 3265 switch (Inst.getOpcode()) { 3266 case ARM::t2LDRT: 3267 case ARM::t2LDRBT: 3268 case ARM::t2LDRHT: 3269 case ARM::t2LDRSBT: 3270 case ARM::t2LDRSHT: 3271 case ARM::t2STRT: 3272 case ARM::t2STRBT: 3273 case ARM::t2STRHT: 3274 imm |= 0x100; 3275 break; 3276 default: 3277 break; 3278 } 3279 3280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3281 return MCDisassembler::Fail; 3282 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 3285 return S; 3286 } 3287 3288 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3289 uint64_t Address, const void *Decoder) { 3290 DecodeStatus S = MCDisassembler::Success; 3291 3292 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3293 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3294 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3295 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3296 addr |= Rn << 9; 3297 unsigned load = fieldFromInstruction(Insn, 20, 1); 3298 3299 if (!load) { 3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3301 return MCDisassembler::Fail; 3302 } 3303 3304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 3307 if (load) { 3308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 } 3311 3312 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 3315 return S; 3316 } 3317 3318 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3319 uint64_t Address, const void *Decoder) { 3320 DecodeStatus S = MCDisassembler::Success; 3321 3322 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3323 unsigned imm = fieldFromInstruction(Val, 0, 12); 3324 3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 Inst.addOperand(MCOperand::CreateImm(imm)); 3328 3329 return S; 3330 } 3331 3332 3333 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3334 uint64_t Address, const void *Decoder) { 3335 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3336 3337 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3338 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3339 Inst.addOperand(MCOperand::CreateImm(imm)); 3340 3341 return MCDisassembler::Success; 3342 } 3343 3344 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3345 uint64_t Address, const void *Decoder) { 3346 DecodeStatus S = MCDisassembler::Success; 3347 3348 if (Inst.getOpcode() == ARM::tADDrSP) { 3349 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3350 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3351 3352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3353 return MCDisassembler::Fail; 3354 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 } else if (Inst.getOpcode() == ARM::tADDspr) { 3358 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3359 3360 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3361 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 } 3365 3366 return S; 3367 } 3368 3369 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3370 uint64_t Address, const void *Decoder) { 3371 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3372 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3373 3374 Inst.addOperand(MCOperand::CreateImm(imod)); 3375 Inst.addOperand(MCOperand::CreateImm(flags)); 3376 3377 return MCDisassembler::Success; 3378 } 3379 3380 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3381 uint64_t Address, const void *Decoder) { 3382 DecodeStatus S = MCDisassembler::Success; 3383 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3384 unsigned add = fieldFromInstruction(Insn, 4, 1); 3385 3386 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 Inst.addOperand(MCOperand::CreateImm(add)); 3389 3390 return S; 3391 } 3392 3393 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3394 uint64_t Address, const void *Decoder) { 3395 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3396 // Note only one trailing zero not two. Also the J1 and J2 values are from 3397 // the encoded instruction. So here change to I1 and I2 values via: 3398 // I1 = NOT(J1 EOR S); 3399 // I2 = NOT(J2 EOR S); 3400 // and build the imm32 with two trailing zeros as documented: 3401 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3402 unsigned S = (Val >> 23) & 1; 3403 unsigned J1 = (Val >> 22) & 1; 3404 unsigned J2 = (Val >> 21) & 1; 3405 unsigned I1 = !(J1 ^ S); 3406 unsigned I2 = !(J2 ^ S); 3407 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3408 int imm32 = SignExtend32<25>(tmp << 1); 3409 3410 if (!tryAddingSymbolicOperand(Address, 3411 (Address & ~2u) + imm32 + 4, 3412 true, 4, Inst, Decoder)) 3413 Inst.addOperand(MCOperand::CreateImm(imm32)); 3414 return MCDisassembler::Success; 3415 } 3416 3417 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3418 uint64_t Address, const void *Decoder) { 3419 if (Val == 0xA || Val == 0xB) 3420 return MCDisassembler::Fail; 3421 3422 Inst.addOperand(MCOperand::CreateImm(Val)); 3423 return MCDisassembler::Success; 3424 } 3425 3426 static DecodeStatus 3427 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3428 uint64_t Address, const void *Decoder) { 3429 DecodeStatus S = MCDisassembler::Success; 3430 3431 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3432 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3433 3434 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 return S; 3440 } 3441 3442 static DecodeStatus 3443 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3444 uint64_t Address, const void *Decoder) { 3445 DecodeStatus S = MCDisassembler::Success; 3446 3447 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3448 if (pred == 0xE || pred == 0xF) { 3449 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3450 switch (opc) { 3451 default: 3452 return MCDisassembler::Fail; 3453 case 0xf3bf8f4: 3454 Inst.setOpcode(ARM::t2DSB); 3455 break; 3456 case 0xf3bf8f5: 3457 Inst.setOpcode(ARM::t2DMB); 3458 break; 3459 case 0xf3bf8f6: 3460 Inst.setOpcode(ARM::t2ISB); 3461 break; 3462 } 3463 3464 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3465 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3466 } 3467 3468 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3469 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3470 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3471 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3472 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3473 3474 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3475 return MCDisassembler::Fail; 3476 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3477 return MCDisassembler::Fail; 3478 3479 return S; 3480 } 3481 3482 // Decode a shifted immediate operand. These basically consist 3483 // of an 8-bit value, and a 4-bit directive that specifies either 3484 // a splat operation or a rotation. 3485 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3486 uint64_t Address, const void *Decoder) { 3487 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3488 if (ctrl == 0) { 3489 unsigned byte = fieldFromInstruction(Val, 8, 2); 3490 unsigned imm = fieldFromInstruction(Val, 0, 8); 3491 switch (byte) { 3492 case 0: 3493 Inst.addOperand(MCOperand::CreateImm(imm)); 3494 break; 3495 case 1: 3496 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3497 break; 3498 case 2: 3499 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3500 break; 3501 case 3: 3502 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3503 (imm << 8) | imm)); 3504 break; 3505 } 3506 } else { 3507 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3508 unsigned rot = fieldFromInstruction(Val, 7, 5); 3509 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3510 Inst.addOperand(MCOperand::CreateImm(imm)); 3511 } 3512 3513 return MCDisassembler::Success; 3514 } 3515 3516 static DecodeStatus 3517 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3518 uint64_t Address, const void *Decoder){ 3519 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3520 true, 2, Inst, Decoder)) 3521 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3522 return MCDisassembler::Success; 3523 } 3524 3525 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3526 uint64_t Address, const void *Decoder){ 3527 // Val is passed in as S:J1:J2:imm10:imm11 3528 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3529 // the encoded instruction. So here change to I1 and I2 values via: 3530 // I1 = NOT(J1 EOR S); 3531 // I2 = NOT(J2 EOR S); 3532 // and build the imm32 with one trailing zero as documented: 3533 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3534 unsigned S = (Val >> 23) & 1; 3535 unsigned J1 = (Val >> 22) & 1; 3536 unsigned J2 = (Val >> 21) & 1; 3537 unsigned I1 = !(J1 ^ S); 3538 unsigned I2 = !(J2 ^ S); 3539 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3540 int imm32 = SignExtend32<25>(tmp << 1); 3541 3542 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3543 true, 4, Inst, Decoder)) 3544 Inst.addOperand(MCOperand::CreateImm(imm32)); 3545 return MCDisassembler::Success; 3546 } 3547 3548 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3549 uint64_t Address, const void *Decoder) { 3550 if (Val & ~0xf) 3551 return MCDisassembler::Fail; 3552 3553 Inst.addOperand(MCOperand::CreateImm(Val)); 3554 return MCDisassembler::Success; 3555 } 3556 3557 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3558 uint64_t Address, const void *Decoder) { 3559 if (!Val) return MCDisassembler::Fail; 3560 Inst.addOperand(MCOperand::CreateImm(Val)); 3561 return MCDisassembler::Success; 3562 } 3563 3564 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3565 uint64_t Address, const void *Decoder) { 3566 DecodeStatus S = MCDisassembler::Success; 3567 3568 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3570 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3571 3572 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3573 3574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3581 return MCDisassembler::Fail; 3582 3583 return S; 3584 } 3585 3586 3587 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3588 uint64_t Address, const void *Decoder){ 3589 DecodeStatus S = MCDisassembler::Success; 3590 3591 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3592 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3593 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3594 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3595 3596 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3597 return MCDisassembler::Fail; 3598 3599 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3600 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3601 3602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3603 return MCDisassembler::Fail; 3604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3605 return MCDisassembler::Fail; 3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 3611 return S; 3612 } 3613 3614 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3615 uint64_t Address, const void *Decoder) { 3616 DecodeStatus S = MCDisassembler::Success; 3617 3618 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3619 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3620 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3621 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3622 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3623 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3624 3625 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3626 3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3628 return MCDisassembler::Fail; 3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 3636 return S; 3637 } 3638 3639 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3640 uint64_t Address, const void *Decoder) { 3641 DecodeStatus S = MCDisassembler::Success; 3642 3643 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3644 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3645 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3646 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3647 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3648 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3649 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3650 3651 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3652 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3653 3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3655 return MCDisassembler::Fail; 3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3661 return MCDisassembler::Fail; 3662 3663 return S; 3664 } 3665 3666 3667 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3668 uint64_t Address, const void *Decoder) { 3669 DecodeStatus S = MCDisassembler::Success; 3670 3671 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3672 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3673 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3674 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3675 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3676 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3677 3678 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3679 3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3683 return MCDisassembler::Fail; 3684 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 3689 return S; 3690 } 3691 3692 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3693 uint64_t Address, const void *Decoder) { 3694 DecodeStatus S = MCDisassembler::Success; 3695 3696 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3697 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3698 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3699 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3700 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3701 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3702 3703 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3704 3705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3708 return MCDisassembler::Fail; 3709 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3710 return MCDisassembler::Fail; 3711 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3712 return MCDisassembler::Fail; 3713 3714 return S; 3715 } 3716 3717 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3718 uint64_t Address, const void *Decoder) { 3719 DecodeStatus S = MCDisassembler::Success; 3720 3721 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3722 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3723 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3724 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3725 unsigned size = fieldFromInstruction(Insn, 10, 2); 3726 3727 unsigned align = 0; 3728 unsigned index = 0; 3729 switch (size) { 3730 default: 3731 return MCDisassembler::Fail; 3732 case 0: 3733 if (fieldFromInstruction(Insn, 4, 1)) 3734 return MCDisassembler::Fail; // UNDEFINED 3735 index = fieldFromInstruction(Insn, 5, 3); 3736 break; 3737 case 1: 3738 if (fieldFromInstruction(Insn, 5, 1)) 3739 return MCDisassembler::Fail; // UNDEFINED 3740 index = fieldFromInstruction(Insn, 6, 2); 3741 if (fieldFromInstruction(Insn, 4, 1)) 3742 align = 2; 3743 break; 3744 case 2: 3745 if (fieldFromInstruction(Insn, 6, 1)) 3746 return MCDisassembler::Fail; // UNDEFINED 3747 index = fieldFromInstruction(Insn, 7, 1); 3748 3749 switch (fieldFromInstruction(Insn, 4, 2)) { 3750 case 0 : 3751 align = 0; break; 3752 case 3: 3753 align = 4; break; 3754 default: 3755 return MCDisassembler::Fail; 3756 } 3757 break; 3758 } 3759 3760 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3761 return MCDisassembler::Fail; 3762 if (Rm != 0xF) { // Writeback 3763 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3764 return MCDisassembler::Fail; 3765 } 3766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3767 return MCDisassembler::Fail; 3768 Inst.addOperand(MCOperand::CreateImm(align)); 3769 if (Rm != 0xF) { 3770 if (Rm != 0xD) { 3771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3772 return MCDisassembler::Fail; 3773 } else 3774 Inst.addOperand(MCOperand::CreateReg(0)); 3775 } 3776 3777 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3778 return MCDisassembler::Fail; 3779 Inst.addOperand(MCOperand::CreateImm(index)); 3780 3781 return S; 3782 } 3783 3784 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3785 uint64_t Address, const void *Decoder) { 3786 DecodeStatus S = MCDisassembler::Success; 3787 3788 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3789 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3790 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3791 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3792 unsigned size = fieldFromInstruction(Insn, 10, 2); 3793 3794 unsigned align = 0; 3795 unsigned index = 0; 3796 switch (size) { 3797 default: 3798 return MCDisassembler::Fail; 3799 case 0: 3800 if (fieldFromInstruction(Insn, 4, 1)) 3801 return MCDisassembler::Fail; // UNDEFINED 3802 index = fieldFromInstruction(Insn, 5, 3); 3803 break; 3804 case 1: 3805 if (fieldFromInstruction(Insn, 5, 1)) 3806 return MCDisassembler::Fail; // UNDEFINED 3807 index = fieldFromInstruction(Insn, 6, 2); 3808 if (fieldFromInstruction(Insn, 4, 1)) 3809 align = 2; 3810 break; 3811 case 2: 3812 if (fieldFromInstruction(Insn, 6, 1)) 3813 return MCDisassembler::Fail; // UNDEFINED 3814 index = fieldFromInstruction(Insn, 7, 1); 3815 3816 switch (fieldFromInstruction(Insn, 4, 2)) { 3817 case 0: 3818 align = 0; break; 3819 case 3: 3820 align = 4; break; 3821 default: 3822 return MCDisassembler::Fail; 3823 } 3824 break; 3825 } 3826 3827 if (Rm != 0xF) { // Writeback 3828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 } 3831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3832 return MCDisassembler::Fail; 3833 Inst.addOperand(MCOperand::CreateImm(align)); 3834 if (Rm != 0xF) { 3835 if (Rm != 0xD) { 3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3837 return MCDisassembler::Fail; 3838 } else 3839 Inst.addOperand(MCOperand::CreateReg(0)); 3840 } 3841 3842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3843 return MCDisassembler::Fail; 3844 Inst.addOperand(MCOperand::CreateImm(index)); 3845 3846 return S; 3847 } 3848 3849 3850 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3851 uint64_t Address, const void *Decoder) { 3852 DecodeStatus S = MCDisassembler::Success; 3853 3854 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3855 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3856 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3857 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3858 unsigned size = fieldFromInstruction(Insn, 10, 2); 3859 3860 unsigned align = 0; 3861 unsigned index = 0; 3862 unsigned inc = 1; 3863 switch (size) { 3864 default: 3865 return MCDisassembler::Fail; 3866 case 0: 3867 index = fieldFromInstruction(Insn, 5, 3); 3868 if (fieldFromInstruction(Insn, 4, 1)) 3869 align = 2; 3870 break; 3871 case 1: 3872 index = fieldFromInstruction(Insn, 6, 2); 3873 if (fieldFromInstruction(Insn, 4, 1)) 3874 align = 4; 3875 if (fieldFromInstruction(Insn, 5, 1)) 3876 inc = 2; 3877 break; 3878 case 2: 3879 if (fieldFromInstruction(Insn, 5, 1)) 3880 return MCDisassembler::Fail; // UNDEFINED 3881 index = fieldFromInstruction(Insn, 7, 1); 3882 if (fieldFromInstruction(Insn, 4, 1) != 0) 3883 align = 8; 3884 if (fieldFromInstruction(Insn, 6, 1)) 3885 inc = 2; 3886 break; 3887 } 3888 3889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3890 return MCDisassembler::Fail; 3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 if (Rm != 0xF) { // Writeback 3894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3895 return MCDisassembler::Fail; 3896 } 3897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 Inst.addOperand(MCOperand::CreateImm(align)); 3900 if (Rm != 0xF) { 3901 if (Rm != 0xD) { 3902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3903 return MCDisassembler::Fail; 3904 } else 3905 Inst.addOperand(MCOperand::CreateReg(0)); 3906 } 3907 3908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 Inst.addOperand(MCOperand::CreateImm(index)); 3913 3914 return S; 3915 } 3916 3917 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3918 uint64_t Address, const void *Decoder) { 3919 DecodeStatus S = MCDisassembler::Success; 3920 3921 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3922 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3923 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3924 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3925 unsigned size = fieldFromInstruction(Insn, 10, 2); 3926 3927 unsigned align = 0; 3928 unsigned index = 0; 3929 unsigned inc = 1; 3930 switch (size) { 3931 default: 3932 return MCDisassembler::Fail; 3933 case 0: 3934 index = fieldFromInstruction(Insn, 5, 3); 3935 if (fieldFromInstruction(Insn, 4, 1)) 3936 align = 2; 3937 break; 3938 case 1: 3939 index = fieldFromInstruction(Insn, 6, 2); 3940 if (fieldFromInstruction(Insn, 4, 1)) 3941 align = 4; 3942 if (fieldFromInstruction(Insn, 5, 1)) 3943 inc = 2; 3944 break; 3945 case 2: 3946 if (fieldFromInstruction(Insn, 5, 1)) 3947 return MCDisassembler::Fail; // UNDEFINED 3948 index = fieldFromInstruction(Insn, 7, 1); 3949 if (fieldFromInstruction(Insn, 4, 1) != 0) 3950 align = 8; 3951 if (fieldFromInstruction(Insn, 6, 1)) 3952 inc = 2; 3953 break; 3954 } 3955 3956 if (Rm != 0xF) { // Writeback 3957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3958 return MCDisassembler::Fail; 3959 } 3960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3961 return MCDisassembler::Fail; 3962 Inst.addOperand(MCOperand::CreateImm(align)); 3963 if (Rm != 0xF) { 3964 if (Rm != 0xD) { 3965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3966 return MCDisassembler::Fail; 3967 } else 3968 Inst.addOperand(MCOperand::CreateReg(0)); 3969 } 3970 3971 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3972 return MCDisassembler::Fail; 3973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3974 return MCDisassembler::Fail; 3975 Inst.addOperand(MCOperand::CreateImm(index)); 3976 3977 return S; 3978 } 3979 3980 3981 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3982 uint64_t Address, const void *Decoder) { 3983 DecodeStatus S = MCDisassembler::Success; 3984 3985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3986 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3987 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3988 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3989 unsigned size = fieldFromInstruction(Insn, 10, 2); 3990 3991 unsigned align = 0; 3992 unsigned index = 0; 3993 unsigned inc = 1; 3994 switch (size) { 3995 default: 3996 return MCDisassembler::Fail; 3997 case 0: 3998 if (fieldFromInstruction(Insn, 4, 1)) 3999 return MCDisassembler::Fail; // UNDEFINED 4000 index = fieldFromInstruction(Insn, 5, 3); 4001 break; 4002 case 1: 4003 if (fieldFromInstruction(Insn, 4, 1)) 4004 return MCDisassembler::Fail; // UNDEFINED 4005 index = fieldFromInstruction(Insn, 6, 2); 4006 if (fieldFromInstruction(Insn, 5, 1)) 4007 inc = 2; 4008 break; 4009 case 2: 4010 if (fieldFromInstruction(Insn, 4, 2)) 4011 return MCDisassembler::Fail; // UNDEFINED 4012 index = fieldFromInstruction(Insn, 7, 1); 4013 if (fieldFromInstruction(Insn, 6, 1)) 4014 inc = 2; 4015 break; 4016 } 4017 4018 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4019 return MCDisassembler::Fail; 4020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 4025 if (Rm != 0xF) { // Writeback 4026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 } 4029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 Inst.addOperand(MCOperand::CreateImm(align)); 4032 if (Rm != 0xF) { 4033 if (Rm != 0xD) { 4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 } else 4037 Inst.addOperand(MCOperand::CreateReg(0)); 4038 } 4039 4040 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4043 return MCDisassembler::Fail; 4044 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4045 return MCDisassembler::Fail; 4046 Inst.addOperand(MCOperand::CreateImm(index)); 4047 4048 return S; 4049 } 4050 4051 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4052 uint64_t Address, const void *Decoder) { 4053 DecodeStatus S = MCDisassembler::Success; 4054 4055 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4056 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4057 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4058 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4059 unsigned size = fieldFromInstruction(Insn, 10, 2); 4060 4061 unsigned align = 0; 4062 unsigned index = 0; 4063 unsigned inc = 1; 4064 switch (size) { 4065 default: 4066 return MCDisassembler::Fail; 4067 case 0: 4068 if (fieldFromInstruction(Insn, 4, 1)) 4069 return MCDisassembler::Fail; // UNDEFINED 4070 index = fieldFromInstruction(Insn, 5, 3); 4071 break; 4072 case 1: 4073 if (fieldFromInstruction(Insn, 4, 1)) 4074 return MCDisassembler::Fail; // UNDEFINED 4075 index = fieldFromInstruction(Insn, 6, 2); 4076 if (fieldFromInstruction(Insn, 5, 1)) 4077 inc = 2; 4078 break; 4079 case 2: 4080 if (fieldFromInstruction(Insn, 4, 2)) 4081 return MCDisassembler::Fail; // UNDEFINED 4082 index = fieldFromInstruction(Insn, 7, 1); 4083 if (fieldFromInstruction(Insn, 6, 1)) 4084 inc = 2; 4085 break; 4086 } 4087 4088 if (Rm != 0xF) { // Writeback 4089 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4090 return MCDisassembler::Fail; 4091 } 4092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 Inst.addOperand(MCOperand::CreateImm(align)); 4095 if (Rm != 0xF) { 4096 if (Rm != 0xD) { 4097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4098 return MCDisassembler::Fail; 4099 } else 4100 Inst.addOperand(MCOperand::CreateReg(0)); 4101 } 4102 4103 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4104 return MCDisassembler::Fail; 4105 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 Inst.addOperand(MCOperand::CreateImm(index)); 4110 4111 return S; 4112 } 4113 4114 4115 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4116 uint64_t Address, const void *Decoder) { 4117 DecodeStatus S = MCDisassembler::Success; 4118 4119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4120 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4121 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4122 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4123 unsigned size = fieldFromInstruction(Insn, 10, 2); 4124 4125 unsigned align = 0; 4126 unsigned index = 0; 4127 unsigned inc = 1; 4128 switch (size) { 4129 default: 4130 return MCDisassembler::Fail; 4131 case 0: 4132 if (fieldFromInstruction(Insn, 4, 1)) 4133 align = 4; 4134 index = fieldFromInstruction(Insn, 5, 3); 4135 break; 4136 case 1: 4137 if (fieldFromInstruction(Insn, 4, 1)) 4138 align = 8; 4139 index = fieldFromInstruction(Insn, 6, 2); 4140 if (fieldFromInstruction(Insn, 5, 1)) 4141 inc = 2; 4142 break; 4143 case 2: 4144 switch (fieldFromInstruction(Insn, 4, 2)) { 4145 case 0: 4146 align = 0; break; 4147 case 3: 4148 return MCDisassembler::Fail; 4149 default: 4150 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4151 } 4152 4153 index = fieldFromInstruction(Insn, 7, 1); 4154 if (fieldFromInstruction(Insn, 6, 1)) 4155 inc = 2; 4156 break; 4157 } 4158 4159 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4162 return MCDisassembler::Fail; 4163 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 4168 if (Rm != 0xF) { // Writeback 4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 } 4172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4173 return MCDisassembler::Fail; 4174 Inst.addOperand(MCOperand::CreateImm(align)); 4175 if (Rm != 0xF) { 4176 if (Rm != 0xD) { 4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 } else 4180 Inst.addOperand(MCOperand::CreateReg(0)); 4181 } 4182 4183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4184 return MCDisassembler::Fail; 4185 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4186 return MCDisassembler::Fail; 4187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4188 return MCDisassembler::Fail; 4189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4190 return MCDisassembler::Fail; 4191 Inst.addOperand(MCOperand::CreateImm(index)); 4192 4193 return S; 4194 } 4195 4196 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4197 uint64_t Address, const void *Decoder) { 4198 DecodeStatus S = MCDisassembler::Success; 4199 4200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4201 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4204 unsigned size = fieldFromInstruction(Insn, 10, 2); 4205 4206 unsigned align = 0; 4207 unsigned index = 0; 4208 unsigned inc = 1; 4209 switch (size) { 4210 default: 4211 return MCDisassembler::Fail; 4212 case 0: 4213 if (fieldFromInstruction(Insn, 4, 1)) 4214 align = 4; 4215 index = fieldFromInstruction(Insn, 5, 3); 4216 break; 4217 case 1: 4218 if (fieldFromInstruction(Insn, 4, 1)) 4219 align = 8; 4220 index = fieldFromInstruction(Insn, 6, 2); 4221 if (fieldFromInstruction(Insn, 5, 1)) 4222 inc = 2; 4223 break; 4224 case 2: 4225 switch (fieldFromInstruction(Insn, 4, 2)) { 4226 case 0: 4227 align = 0; break; 4228 case 3: 4229 return MCDisassembler::Fail; 4230 default: 4231 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4232 } 4233 4234 index = fieldFromInstruction(Insn, 7, 1); 4235 if (fieldFromInstruction(Insn, 6, 1)) 4236 inc = 2; 4237 break; 4238 } 4239 4240 if (Rm != 0xF) { // Writeback 4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 } 4244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 Inst.addOperand(MCOperand::CreateImm(align)); 4247 if (Rm != 0xF) { 4248 if (Rm != 0xD) { 4249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 } else 4252 Inst.addOperand(MCOperand::CreateReg(0)); 4253 } 4254 4255 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4256 return MCDisassembler::Fail; 4257 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4258 return MCDisassembler::Fail; 4259 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 Inst.addOperand(MCOperand::CreateImm(index)); 4264 4265 return S; 4266 } 4267 4268 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4269 uint64_t Address, const void *Decoder) { 4270 DecodeStatus S = MCDisassembler::Success; 4271 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4272 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4273 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4274 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4275 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4276 4277 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4278 S = MCDisassembler::SoftFail; 4279 4280 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4283 return MCDisassembler::Fail; 4284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4285 return MCDisassembler::Fail; 4286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 4291 return S; 4292 } 4293 4294 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4295 uint64_t Address, const void *Decoder) { 4296 DecodeStatus S = MCDisassembler::Success; 4297 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4298 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4299 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4300 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4301 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4302 4303 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4304 S = MCDisassembler::SoftFail; 4305 4306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4307 return MCDisassembler::Fail; 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4315 return MCDisassembler::Fail; 4316 4317 return S; 4318 } 4319 4320 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4321 uint64_t Address, const void *Decoder) { 4322 DecodeStatus S = MCDisassembler::Success; 4323 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4324 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4325 4326 if (pred == 0xF) { 4327 pred = 0xE; 4328 S = MCDisassembler::SoftFail; 4329 } 4330 4331 if (mask == 0x0) { 4332 mask |= 0x8; 4333 S = MCDisassembler::SoftFail; 4334 } 4335 4336 Inst.addOperand(MCOperand::CreateImm(pred)); 4337 Inst.addOperand(MCOperand::CreateImm(mask)); 4338 return S; 4339 } 4340 4341 static DecodeStatus 4342 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4343 uint64_t Address, const void *Decoder) { 4344 DecodeStatus S = MCDisassembler::Success; 4345 4346 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4347 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4348 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4349 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4350 unsigned W = fieldFromInstruction(Insn, 21, 1); 4351 unsigned U = fieldFromInstruction(Insn, 23, 1); 4352 unsigned P = fieldFromInstruction(Insn, 24, 1); 4353 bool writeback = (W == 1) | (P == 0); 4354 4355 addr |= (U << 8) | (Rn << 9); 4356 4357 if (writeback && (Rn == Rt || Rn == Rt2)) 4358 Check(S, MCDisassembler::SoftFail); 4359 if (Rt == Rt2) 4360 Check(S, MCDisassembler::SoftFail); 4361 4362 // Rt 4363 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4364 return MCDisassembler::Fail; 4365 // Rt2 4366 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4367 return MCDisassembler::Fail; 4368 // Writeback operand 4369 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4370 return MCDisassembler::Fail; 4371 // addr 4372 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4373 return MCDisassembler::Fail; 4374 4375 return S; 4376 } 4377 4378 static DecodeStatus 4379 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4380 uint64_t Address, const void *Decoder) { 4381 DecodeStatus S = MCDisassembler::Success; 4382 4383 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4384 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4385 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4386 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4387 unsigned W = fieldFromInstruction(Insn, 21, 1); 4388 unsigned U = fieldFromInstruction(Insn, 23, 1); 4389 unsigned P = fieldFromInstruction(Insn, 24, 1); 4390 bool writeback = (W == 1) | (P == 0); 4391 4392 addr |= (U << 8) | (Rn << 9); 4393 4394 if (writeback && (Rn == Rt || Rn == Rt2)) 4395 Check(S, MCDisassembler::SoftFail); 4396 4397 // Writeback operand 4398 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 // Rt 4401 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4402 return MCDisassembler::Fail; 4403 // Rt2 4404 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4405 return MCDisassembler::Fail; 4406 // addr 4407 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4408 return MCDisassembler::Fail; 4409 4410 return S; 4411 } 4412 4413 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4414 uint64_t Address, const void *Decoder) { 4415 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4416 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4417 if (sign1 != sign2) return MCDisassembler::Fail; 4418 4419 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4420 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4421 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4422 Val |= sign1 << 12; 4423 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4424 4425 return MCDisassembler::Success; 4426 } 4427 4428 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4429 uint64_t Address, 4430 const void *Decoder) { 4431 DecodeStatus S = MCDisassembler::Success; 4432 4433 // Shift of "asr #32" is not allowed in Thumb2 mode. 4434 if (Val == 0x20) S = MCDisassembler::SoftFail; 4435 Inst.addOperand(MCOperand::CreateImm(Val)); 4436 return S; 4437 } 4438 4439 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4440 uint64_t Address, const void *Decoder) { 4441 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4442 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4443 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4444 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4445 4446 if (pred == 0xF) 4447 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4448 4449 DecodeStatus S = MCDisassembler::Success; 4450 4451 if (Rt == Rn || Rn == Rt2) 4452 S = MCDisassembler::SoftFail; 4453 4454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4455 return MCDisassembler::Fail; 4456 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4457 return MCDisassembler::Fail; 4458 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4459 return MCDisassembler::Fail; 4460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4461 return MCDisassembler::Fail; 4462 4463 return S; 4464 } 4465 4466 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4467 uint64_t Address, const void *Decoder) { 4468 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4469 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4470 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4471 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4472 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4473 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4474 4475 DecodeStatus S = MCDisassembler::Success; 4476 4477 // VMOVv2f32 is ambiguous with these decodings. 4478 if (!(imm & 0x38) && cmode == 0xF) { 4479 Inst.setOpcode(ARM::VMOVv2f32); 4480 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4481 } 4482 4483 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4484 4485 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4486 return MCDisassembler::Fail; 4487 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4488 return MCDisassembler::Fail; 4489 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4490 4491 return S; 4492 } 4493 4494 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4495 uint64_t Address, const void *Decoder) { 4496 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4497 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4498 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4499 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4500 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4501 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4502 4503 DecodeStatus S = MCDisassembler::Success; 4504 4505 // VMOVv4f32 is ambiguous with these decodings. 4506 if (!(imm & 0x38) && cmode == 0xF) { 4507 Inst.setOpcode(ARM::VMOVv4f32); 4508 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4509 } 4510 4511 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4512 4513 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4514 return MCDisassembler::Fail; 4515 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4518 4519 return S; 4520 } 4521 4522 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4523 const void *Decoder) 4524 { 4525 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4526 if (Imm > 4) return MCDisassembler::Fail; 4527 Inst.addOperand(MCOperand::CreateImm(Imm)); 4528 return MCDisassembler::Success; 4529 } 4530 4531 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4532 uint64_t Address, const void *Decoder) { 4533 DecodeStatus S = MCDisassembler::Success; 4534 4535 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4536 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4537 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4538 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4539 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4540 4541 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4542 S = MCDisassembler::SoftFail; 4543 4544 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4545 return MCDisassembler::Fail; 4546 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4547 return MCDisassembler::Fail; 4548 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4549 return MCDisassembler::Fail; 4550 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4551 return MCDisassembler::Fail; 4552 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4553 return MCDisassembler::Fail; 4554 4555 return S; 4556 } 4557 4558 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4559 uint64_t Address, const void *Decoder) { 4560 4561 DecodeStatus S = MCDisassembler::Success; 4562 4563 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4564 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4565 unsigned cop = fieldFromInstruction(Val, 8, 4); 4566 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4567 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4568 4569 if ((cop & ~0x1) == 0xa) 4570 return MCDisassembler::Fail; 4571 4572 if (Rt == Rt2) 4573 S = MCDisassembler::SoftFail; 4574 4575 Inst.addOperand(MCOperand::CreateImm(cop)); 4576 Inst.addOperand(MCOperand::CreateImm(opc1)); 4577 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4578 return MCDisassembler::Fail; 4579 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4580 return MCDisassembler::Fail; 4581 Inst.addOperand(MCOperand::CreateImm(CRm)); 4582 4583 return S; 4584 } 4585 4586