1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = CountTrailingZeros_32(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 180 unsigned RegNo, uint64_t Address, 181 const void *Decoder); 182 183 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 196 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 201 unsigned Insn, 202 uint64_t Address, 203 const void *Decoder); 204 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 213 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 214 unsigned Insn, 215 uint64_t Adddress, 216 const void *Decoder); 217 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 312 const void *Decoder); 313 314 315 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 376 uint64_t Address, const void *Decoder); 377 378 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 #include "ARMGenDisassemblerTables.inc" 383 384 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 385 return new ARMDisassembler(STI); 386 } 387 388 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 389 return new ThumbDisassembler(STI); 390 } 391 392 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 393 const MemoryObject &Region, 394 uint64_t Address, 395 raw_ostream &os, 396 raw_ostream &cs) const { 397 CommentStream = &cs; 398 399 uint8_t bytes[4]; 400 401 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 402 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 403 404 // We want to read exactly 4 bytes of data. 405 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 406 Size = 0; 407 return MCDisassembler::Fail; 408 } 409 410 // Encoded as a small-endian 32-bit word in the stream. 411 uint32_t insn = (bytes[3] << 24) | 412 (bytes[2] << 16) | 413 (bytes[1] << 8) | 414 (bytes[0] << 0); 415 416 // Calling the auto-generated decoder function. 417 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 418 Address, this, STI); 419 if (result != MCDisassembler::Fail) { 420 Size = 4; 421 return result; 422 } 423 424 // VFP and NEON instructions, similarly, are shared between ARM 425 // and Thumb modes. 426 MI.clear(); 427 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 428 if (result != MCDisassembler::Fail) { 429 Size = 4; 430 return result; 431 } 432 433 MI.clear(); 434 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 435 this, STI); 436 if (result != MCDisassembler::Fail) { 437 Size = 4; 438 // Add a fake predicate operand, because we share these instruction 439 // definitions with Thumb2 where these instructions are predicable. 440 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 441 return MCDisassembler::Fail; 442 return result; 443 } 444 445 MI.clear(); 446 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 447 this, STI); 448 if (result != MCDisassembler::Fail) { 449 Size = 4; 450 // Add a fake predicate operand, because we share these instruction 451 // definitions with Thumb2 where these instructions are predicable. 452 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 453 return MCDisassembler::Fail; 454 return result; 455 } 456 457 MI.clear(); 458 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 459 this, STI); 460 if (result != MCDisassembler::Fail) { 461 Size = 4; 462 // Add a fake predicate operand, because we share these instruction 463 // definitions with Thumb2 where these instructions are predicable. 464 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 465 return MCDisassembler::Fail; 466 return result; 467 } 468 469 MI.clear(); 470 471 Size = 0; 472 return MCDisassembler::Fail; 473 } 474 475 namespace llvm { 476 extern const MCInstrDesc ARMInsts[]; 477 } 478 479 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 480 /// immediate Value in the MCInst. The immediate Value has had any PC 481 /// adjustment made by the caller. If the instruction is a branch instruction 482 /// then isBranch is true, else false. If the getOpInfo() function was set as 483 /// part of the setupForSymbolicDisassembly() call then that function is called 484 /// to get any symbolic information at the Address for this instruction. If 485 /// that returns non-zero then the symbolic information it returns is used to 486 /// create an MCExpr and that is added as an operand to the MCInst. If 487 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 488 /// Value is done and if a symbol is found an MCExpr is created with that, else 489 /// an MCExpr with Value is created. This function returns true if it adds an 490 /// operand to the MCInst and false otherwise. 491 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 492 bool isBranch, uint64_t InstSize, 493 MCInst &MI, const void *Decoder) { 494 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 495 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 496 struct LLVMOpInfo1 SymbolicOp; 497 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 498 SymbolicOp.Value = Value; 499 void *DisInfo = Dis->getDisInfoBlock(); 500 501 if (!getOpInfo || 502 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 503 // Clear SymbolicOp.Value from above and also all other fields. 504 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 505 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 506 if (!SymbolLookUp) 507 return false; 508 uint64_t ReferenceType; 509 if (isBranch) 510 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 511 else 512 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 513 const char *ReferenceName; 514 uint64_t SymbolValue = 0x00000000ffffffffULL & Value; 515 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType, 516 Address, &ReferenceName); 517 if (Name) { 518 SymbolicOp.AddSymbol.Name = Name; 519 SymbolicOp.AddSymbol.Present = true; 520 } 521 // For branches always create an MCExpr so it gets printed as hex address. 522 else if (isBranch) { 523 SymbolicOp.Value = Value; 524 } 525 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 526 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 527 if (!Name && !isBranch) 528 return false; 529 } 530 531 MCContext *Ctx = Dis->getMCContext(); 532 const MCExpr *Add = NULL; 533 if (SymbolicOp.AddSymbol.Present) { 534 if (SymbolicOp.AddSymbol.Name) { 535 StringRef Name(SymbolicOp.AddSymbol.Name); 536 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 537 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 538 } else { 539 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 540 } 541 } 542 543 const MCExpr *Sub = NULL; 544 if (SymbolicOp.SubtractSymbol.Present) { 545 if (SymbolicOp.SubtractSymbol.Name) { 546 StringRef Name(SymbolicOp.SubtractSymbol.Name); 547 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 548 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 549 } else { 550 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 551 } 552 } 553 554 const MCExpr *Off = NULL; 555 if (SymbolicOp.Value != 0) 556 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 557 558 const MCExpr *Expr; 559 if (Sub) { 560 const MCExpr *LHS; 561 if (Add) 562 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 563 else 564 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 565 if (Off != 0) 566 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 567 else 568 Expr = LHS; 569 } else if (Add) { 570 if (Off != 0) 571 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 572 else 573 Expr = Add; 574 } else { 575 if (Off != 0) 576 Expr = Off; 577 else 578 Expr = MCConstantExpr::Create(0, *Ctx); 579 } 580 581 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 582 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 583 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 584 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 585 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 586 MI.addOperand(MCOperand::CreateExpr(Expr)); 587 else 588 llvm_unreachable("bad SymbolicOp.VariantKind"); 589 590 return true; 591 } 592 593 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 594 /// referenced by a load instruction with the base register that is the Pc. 595 /// These can often be values in a literal pool near the Address of the 596 /// instruction. The Address of the instruction and its immediate Value are 597 /// used as a possible literal pool entry. The SymbolLookUp call back will 598 /// return the name of a symbol referenced by the literal pool's entry if 599 /// the referenced address is that of a symbol. Or it will return a pointer to 600 /// a literal 'C' string if the referenced address of the literal pool's entry 601 /// is an address into a section with 'C' string literals. 602 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 603 const void *Decoder) { 604 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 605 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 606 if (SymbolLookUp) { 607 void *DisInfo = Dis->getDisInfoBlock(); 608 uint64_t ReferenceType; 609 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 610 const char *ReferenceName; 611 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 612 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 613 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 614 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 615 } 616 } 617 618 // Thumb1 instructions don't have explicit S bits. Rather, they 619 // implicitly set CPSR. Since it's not represented in the encoding, the 620 // auto-generated decoder won't inject the CPSR operand. We need to fix 621 // that as a post-pass. 622 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 623 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 624 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 625 MCInst::iterator I = MI.begin(); 626 for (unsigned i = 0; i < NumOps; ++i, ++I) { 627 if (I == MI.end()) break; 628 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 629 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 630 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 631 return; 632 } 633 } 634 635 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 636 } 637 638 // Most Thumb instructions don't have explicit predicates in the 639 // encoding, but rather get their predicates from IT context. We need 640 // to fix up the predicate operands using this context information as a 641 // post-pass. 642 MCDisassembler::DecodeStatus 643 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 644 MCDisassembler::DecodeStatus S = Success; 645 646 // A few instructions actually have predicates encoded in them. Don't 647 // try to overwrite it if we're seeing one of those. 648 switch (MI.getOpcode()) { 649 case ARM::tBcc: 650 case ARM::t2Bcc: 651 case ARM::tCBZ: 652 case ARM::tCBNZ: 653 case ARM::tCPS: 654 case ARM::t2CPS3p: 655 case ARM::t2CPS2p: 656 case ARM::t2CPS1p: 657 case ARM::tMOVSr: 658 case ARM::tSETEND: 659 // Some instructions (mostly conditional branches) are not 660 // allowed in IT blocks. 661 if (ITBlock.instrInITBlock()) 662 S = SoftFail; 663 else 664 return Success; 665 break; 666 case ARM::tB: 667 case ARM::t2B: 668 case ARM::t2TBB: 669 case ARM::t2TBH: 670 // Some instructions (mostly unconditional branches) can 671 // only appears at the end of, or outside of, an IT. 672 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 673 S = SoftFail; 674 break; 675 default: 676 break; 677 } 678 679 // If we're in an IT block, base the predicate on that. Otherwise, 680 // assume a predicate of AL. 681 unsigned CC; 682 CC = ITBlock.getITCC(); 683 if (CC == 0xF) 684 CC = ARMCC::AL; 685 if (ITBlock.instrInITBlock()) 686 ITBlock.advanceITState(); 687 688 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 689 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 690 MCInst::iterator I = MI.begin(); 691 for (unsigned i = 0; i < NumOps; ++i, ++I) { 692 if (I == MI.end()) break; 693 if (OpInfo[i].isPredicate()) { 694 I = MI.insert(I, MCOperand::CreateImm(CC)); 695 ++I; 696 if (CC == ARMCC::AL) 697 MI.insert(I, MCOperand::CreateReg(0)); 698 else 699 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 700 return S; 701 } 702 } 703 704 I = MI.insert(I, MCOperand::CreateImm(CC)); 705 ++I; 706 if (CC == ARMCC::AL) 707 MI.insert(I, MCOperand::CreateReg(0)); 708 else 709 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 710 711 return S; 712 } 713 714 // Thumb VFP instructions are a special case. Because we share their 715 // encodings between ARM and Thumb modes, and they are predicable in ARM 716 // mode, the auto-generated decoder will give them an (incorrect) 717 // predicate operand. We need to rewrite these operands based on the IT 718 // context as a post-pass. 719 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 720 unsigned CC; 721 CC = ITBlock.getITCC(); 722 if (ITBlock.instrInITBlock()) 723 ITBlock.advanceITState(); 724 725 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 726 MCInst::iterator I = MI.begin(); 727 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 728 for (unsigned i = 0; i < NumOps; ++i, ++I) { 729 if (OpInfo[i].isPredicate() ) { 730 I->setImm(CC); 731 ++I; 732 if (CC == ARMCC::AL) 733 I->setReg(0); 734 else 735 I->setReg(ARM::CPSR); 736 return; 737 } 738 } 739 } 740 741 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 742 const MemoryObject &Region, 743 uint64_t Address, 744 raw_ostream &os, 745 raw_ostream &cs) const { 746 CommentStream = &cs; 747 748 uint8_t bytes[4]; 749 750 assert((STI.getFeatureBits() & ARM::ModeThumb) && 751 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 752 753 // We want to read exactly 2 bytes of data. 754 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 755 Size = 0; 756 return MCDisassembler::Fail; 757 } 758 759 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 760 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 761 Address, this, STI); 762 if (result != MCDisassembler::Fail) { 763 Size = 2; 764 Check(result, AddThumbPredicate(MI)); 765 return result; 766 } 767 768 MI.clear(); 769 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 770 Address, this, STI); 771 if (result) { 772 Size = 2; 773 bool InITBlock = ITBlock.instrInITBlock(); 774 Check(result, AddThumbPredicate(MI)); 775 AddThumb1SBit(MI, InITBlock); 776 return result; 777 } 778 779 MI.clear(); 780 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 781 Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 2; 784 785 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 786 // the Thumb predicate. 787 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 788 result = MCDisassembler::SoftFail; 789 790 Check(result, AddThumbPredicate(MI)); 791 792 // If we find an IT instruction, we need to parse its condition 793 // code and mask operands so that we can apply them correctly 794 // to the subsequent instructions. 795 if (MI.getOpcode() == ARM::t2IT) { 796 797 unsigned Firstcond = MI.getOperand(0).getImm(); 798 unsigned Mask = MI.getOperand(1).getImm(); 799 ITBlock.setITState(Firstcond, Mask); 800 } 801 802 return result; 803 } 804 805 // We want to read exactly 4 bytes of data. 806 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 807 Size = 0; 808 return MCDisassembler::Fail; 809 } 810 811 uint32_t insn32 = (bytes[3] << 8) | 812 (bytes[2] << 0) | 813 (bytes[1] << 24) | 814 (bytes[0] << 16); 815 MI.clear(); 816 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 817 this, STI); 818 if (result != MCDisassembler::Fail) { 819 Size = 4; 820 bool InITBlock = ITBlock.instrInITBlock(); 821 Check(result, AddThumbPredicate(MI)); 822 AddThumb1SBit(MI, InITBlock); 823 return result; 824 } 825 826 MI.clear(); 827 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 828 this, STI); 829 if (result != MCDisassembler::Fail) { 830 Size = 4; 831 Check(result, AddThumbPredicate(MI)); 832 return result; 833 } 834 835 MI.clear(); 836 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 837 if (result != MCDisassembler::Fail) { 838 Size = 4; 839 UpdateThumbVFPPredicate(MI); 840 return result; 841 } 842 843 MI.clear(); 844 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 845 this, STI); 846 if (result != MCDisassembler::Fail) { 847 Size = 4; 848 Check(result, AddThumbPredicate(MI)); 849 return result; 850 } 851 852 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 853 MI.clear(); 854 uint32_t NEONLdStInsn = insn32; 855 NEONLdStInsn &= 0xF0FFFFFF; 856 NEONLdStInsn |= 0x04000000; 857 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 858 Address, this, STI); 859 if (result != MCDisassembler::Fail) { 860 Size = 4; 861 Check(result, AddThumbPredicate(MI)); 862 return result; 863 } 864 } 865 866 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 867 MI.clear(); 868 uint32_t NEONDataInsn = insn32; 869 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 870 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 871 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 872 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 873 Address, this, STI); 874 if (result != MCDisassembler::Fail) { 875 Size = 4; 876 Check(result, AddThumbPredicate(MI)); 877 return result; 878 } 879 } 880 881 Size = 0; 882 return MCDisassembler::Fail; 883 } 884 885 886 extern "C" void LLVMInitializeARMDisassembler() { 887 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 888 createARMDisassembler); 889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 890 createThumbDisassembler); 891 } 892 893 static const uint16_t GPRDecoderTable[] = { 894 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 895 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 896 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 897 ARM::R12, ARM::SP, ARM::LR, ARM::PC 898 }; 899 900 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 if (RegNo > 15) 903 return MCDisassembler::Fail; 904 905 unsigned Register = GPRDecoderTable[RegNo]; 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static DecodeStatus 911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo == 15) 916 S = MCDisassembler::SoftFail; 917 918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 919 920 return S; 921 } 922 923 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 if (RegNo > 7) 926 return MCDisassembler::Fail; 927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 928 } 929 930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 unsigned Register = 0; 933 switch (RegNo) { 934 case 0: 935 Register = ARM::R0; 936 break; 937 case 1: 938 Register = ARM::R1; 939 break; 940 case 2: 941 Register = ARM::R2; 942 break; 943 case 3: 944 Register = ARM::R3; 945 break; 946 case 9: 947 Register = ARM::R9; 948 break; 949 case 12: 950 Register = ARM::R12; 951 break; 952 default: 953 return MCDisassembler::Fail; 954 } 955 956 Inst.addOperand(MCOperand::CreateReg(Register)); 957 return MCDisassembler::Success; 958 } 959 960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 961 uint64_t Address, const void *Decoder) { 962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 964 } 965 966 static const uint16_t SPRDecoderTable[] = { 967 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 968 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 969 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 970 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 971 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 972 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 973 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 974 ARM::S28, ARM::S29, ARM::S30, ARM::S31 975 }; 976 977 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 if (RegNo > 31) 980 return MCDisassembler::Fail; 981 982 unsigned Register = SPRDecoderTable[RegNo]; 983 Inst.addOperand(MCOperand::CreateReg(Register)); 984 return MCDisassembler::Success; 985 } 986 987 static const uint16_t DPRDecoderTable[] = { 988 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 989 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 990 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 991 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 992 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 993 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 994 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 995 ARM::D28, ARM::D29, ARM::D30, ARM::D31 996 }; 997 998 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 999 uint64_t Address, const void *Decoder) { 1000 if (RegNo > 31) 1001 return MCDisassembler::Fail; 1002 1003 unsigned Register = DPRDecoderTable[RegNo]; 1004 Inst.addOperand(MCOperand::CreateReg(Register)); 1005 return MCDisassembler::Success; 1006 } 1007 1008 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 7) 1011 return MCDisassembler::Fail; 1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1013 } 1014 1015 static DecodeStatus 1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1017 uint64_t Address, const void *Decoder) { 1018 if (RegNo > 15) 1019 return MCDisassembler::Fail; 1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1021 } 1022 1023 static const uint16_t QPRDecoderTable[] = { 1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1028 }; 1029 1030 1031 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1032 uint64_t Address, const void *Decoder) { 1033 if (RegNo > 31) 1034 return MCDisassembler::Fail; 1035 RegNo >>= 1; 1036 1037 unsigned Register = QPRDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040 } 1041 1042 static const uint16_t DPairDecoderTable[] = { 1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1048 ARM::Q15 1049 }; 1050 1051 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1052 uint64_t Address, const void *Decoder) { 1053 if (RegNo > 30) 1054 return MCDisassembler::Fail; 1055 1056 unsigned Register = DPairDecoderTable[RegNo]; 1057 Inst.addOperand(MCOperand::CreateReg(Register)); 1058 return MCDisassembler::Success; 1059 } 1060 1061 static const uint16_t DPairSpacedDecoderTable[] = { 1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1069 ARM::D28_D30, ARM::D29_D31 1070 }; 1071 1072 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1073 unsigned RegNo, 1074 uint64_t Address, 1075 const void *Decoder) { 1076 if (RegNo > 29) 1077 return MCDisassembler::Fail; 1078 1079 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1080 Inst.addOperand(MCOperand::CreateReg(Register)); 1081 return MCDisassembler::Success; 1082 } 1083 1084 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1085 uint64_t Address, const void *Decoder) { 1086 if (Val == 0xF) return MCDisassembler::Fail; 1087 // AL predicate is not allowed on Thumb1 branches. 1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1089 return MCDisassembler::Fail; 1090 Inst.addOperand(MCOperand::CreateImm(Val)); 1091 if (Val == ARMCC::AL) { 1092 Inst.addOperand(MCOperand::CreateReg(0)); 1093 } else 1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val) 1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1102 else 1103 Inst.addOperand(MCOperand::CreateReg(0)); 1104 return MCDisassembler::Success; 1105 } 1106 1107 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1108 uint64_t Address, const void *Decoder) { 1109 uint32_t imm = Val & 0xFF; 1110 uint32_t rot = (Val & 0xF00) >> 7; 1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1112 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 1120 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1121 unsigned type = fieldFromInstruction(Val, 5, 2); 1122 unsigned imm = fieldFromInstruction(Val, 7, 5); 1123 1124 // Register-immediate 1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1126 return MCDisassembler::Fail; 1127 1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1129 switch (type) { 1130 case 0: 1131 Shift = ARM_AM::lsl; 1132 break; 1133 case 1: 1134 Shift = ARM_AM::lsr; 1135 break; 1136 case 2: 1137 Shift = ARM_AM::asr; 1138 break; 1139 case 3: 1140 Shift = ARM_AM::ror; 1141 break; 1142 } 1143 1144 if (Shift == ARM_AM::ror && imm == 0) 1145 Shift = ARM_AM::rrx; 1146 1147 unsigned Op = Shift | (imm << 3); 1148 Inst.addOperand(MCOperand::CreateImm(Op)); 1149 1150 return S; 1151 } 1152 1153 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1154 uint64_t Address, const void *Decoder) { 1155 DecodeStatus S = MCDisassembler::Success; 1156 1157 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1158 unsigned type = fieldFromInstruction(Val, 5, 2); 1159 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1160 1161 // Register-register 1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1163 return MCDisassembler::Fail; 1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1165 return MCDisassembler::Fail; 1166 1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1168 switch (type) { 1169 case 0: 1170 Shift = ARM_AM::lsl; 1171 break; 1172 case 1: 1173 Shift = ARM_AM::lsr; 1174 break; 1175 case 2: 1176 Shift = ARM_AM::asr; 1177 break; 1178 case 3: 1179 Shift = ARM_AM::ror; 1180 break; 1181 } 1182 1183 Inst.addOperand(MCOperand::CreateImm(Shift)); 1184 1185 return S; 1186 } 1187 1188 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 bool writebackLoad = false; 1193 unsigned writebackReg = 0; 1194 switch (Inst.getOpcode()) { 1195 default: 1196 break; 1197 case ARM::LDMIA_UPD: 1198 case ARM::LDMDB_UPD: 1199 case ARM::LDMIB_UPD: 1200 case ARM::LDMDA_UPD: 1201 case ARM::t2LDMIA_UPD: 1202 case ARM::t2LDMDB_UPD: 1203 writebackLoad = true; 1204 writebackReg = Inst.getOperand(0).getReg(); 1205 break; 1206 } 1207 1208 // Empty register lists are not allowed. 1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1210 for (unsigned i = 0; i < 16; ++i) { 1211 if (Val & (1 << i)) { 1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1213 return MCDisassembler::Fail; 1214 // Writeback not allowed if Rn is in the target list. 1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1216 Check(S, MCDisassembler::SoftFail); 1217 } 1218 } 1219 1220 return S; 1221 } 1222 1223 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1228 unsigned regs = fieldFromInstruction(Val, 0, 8); 1229 1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1231 return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < (regs - 1); ++i) { 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 } 1236 1237 return S; 1238 } 1239 1240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1241 uint64_t Address, const void *Decoder) { 1242 DecodeStatus S = MCDisassembler::Success; 1243 1244 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1245 unsigned regs = fieldFromInstruction(Val, 0, 8); 1246 1247 regs = regs >> 1; 1248 1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 for (unsigned i = 0; i < (regs - 1); ++i) { 1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1253 return MCDisassembler::Fail; 1254 } 1255 1256 return S; 1257 } 1258 1259 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1260 uint64_t Address, const void *Decoder) { 1261 // This operand encodes a mask of contiguous zeros between a specified MSB 1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1263 // the mask of all bits LSB-and-lower, and then xor them to create 1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1265 // create the final mask. 1266 unsigned msb = fieldFromInstruction(Val, 5, 5); 1267 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1268 1269 DecodeStatus S = MCDisassembler::Success; 1270 if (lsb > msb) { 1271 Check(S, MCDisassembler::SoftFail); 1272 // The check above will cause the warning for the "potentially undefined 1273 // instruction encoding" but we can't build a bad MCOperand value here 1274 // with a lsb > msb or else printing the MCInst will cause a crash. 1275 lsb = msb; 1276 } 1277 1278 uint32_t msb_mask = 0xFFFFFFFF; 1279 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1280 uint32_t lsb_mask = (1U << lsb) - 1; 1281 1282 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1283 return S; 1284 } 1285 1286 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1287 uint64_t Address, const void *Decoder) { 1288 DecodeStatus S = MCDisassembler::Success; 1289 1290 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1291 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1292 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1293 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1294 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1295 unsigned U = fieldFromInstruction(Insn, 23, 1); 1296 1297 switch (Inst.getOpcode()) { 1298 case ARM::LDC_OFFSET: 1299 case ARM::LDC_PRE: 1300 case ARM::LDC_POST: 1301 case ARM::LDC_OPTION: 1302 case ARM::LDCL_OFFSET: 1303 case ARM::LDCL_PRE: 1304 case ARM::LDCL_POST: 1305 case ARM::LDCL_OPTION: 1306 case ARM::STC_OFFSET: 1307 case ARM::STC_PRE: 1308 case ARM::STC_POST: 1309 case ARM::STC_OPTION: 1310 case ARM::STCL_OFFSET: 1311 case ARM::STCL_PRE: 1312 case ARM::STCL_POST: 1313 case ARM::STCL_OPTION: 1314 case ARM::t2LDC_OFFSET: 1315 case ARM::t2LDC_PRE: 1316 case ARM::t2LDC_POST: 1317 case ARM::t2LDC_OPTION: 1318 case ARM::t2LDCL_OFFSET: 1319 case ARM::t2LDCL_PRE: 1320 case ARM::t2LDCL_POST: 1321 case ARM::t2LDCL_OPTION: 1322 case ARM::t2STC_OFFSET: 1323 case ARM::t2STC_PRE: 1324 case ARM::t2STC_POST: 1325 case ARM::t2STC_OPTION: 1326 case ARM::t2STCL_OFFSET: 1327 case ARM::t2STCL_PRE: 1328 case ARM::t2STCL_POST: 1329 case ARM::t2STCL_OPTION: 1330 if (coproc == 0xA || coproc == 0xB) 1331 return MCDisassembler::Fail; 1332 break; 1333 default: 1334 break; 1335 } 1336 1337 Inst.addOperand(MCOperand::CreateImm(coproc)); 1338 Inst.addOperand(MCOperand::CreateImm(CRd)); 1339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1340 return MCDisassembler::Fail; 1341 1342 switch (Inst.getOpcode()) { 1343 case ARM::t2LDC2_OFFSET: 1344 case ARM::t2LDC2L_OFFSET: 1345 case ARM::t2LDC2_PRE: 1346 case ARM::t2LDC2L_PRE: 1347 case ARM::t2STC2_OFFSET: 1348 case ARM::t2STC2L_OFFSET: 1349 case ARM::t2STC2_PRE: 1350 case ARM::t2STC2L_PRE: 1351 case ARM::LDC2_OFFSET: 1352 case ARM::LDC2L_OFFSET: 1353 case ARM::LDC2_PRE: 1354 case ARM::LDC2L_PRE: 1355 case ARM::STC2_OFFSET: 1356 case ARM::STC2L_OFFSET: 1357 case ARM::STC2_PRE: 1358 case ARM::STC2L_PRE: 1359 case ARM::t2LDC_OFFSET: 1360 case ARM::t2LDCL_OFFSET: 1361 case ARM::t2LDC_PRE: 1362 case ARM::t2LDCL_PRE: 1363 case ARM::t2STC_OFFSET: 1364 case ARM::t2STCL_OFFSET: 1365 case ARM::t2STC_PRE: 1366 case ARM::t2STCL_PRE: 1367 case ARM::LDC_OFFSET: 1368 case ARM::LDCL_OFFSET: 1369 case ARM::LDC_PRE: 1370 case ARM::LDCL_PRE: 1371 case ARM::STC_OFFSET: 1372 case ARM::STCL_OFFSET: 1373 case ARM::STC_PRE: 1374 case ARM::STCL_PRE: 1375 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1376 Inst.addOperand(MCOperand::CreateImm(imm)); 1377 break; 1378 case ARM::t2LDC2_POST: 1379 case ARM::t2LDC2L_POST: 1380 case ARM::t2STC2_POST: 1381 case ARM::t2STC2L_POST: 1382 case ARM::LDC2_POST: 1383 case ARM::LDC2L_POST: 1384 case ARM::STC2_POST: 1385 case ARM::STC2L_POST: 1386 case ARM::t2LDC_POST: 1387 case ARM::t2LDCL_POST: 1388 case ARM::t2STC_POST: 1389 case ARM::t2STCL_POST: 1390 case ARM::LDC_POST: 1391 case ARM::LDCL_POST: 1392 case ARM::STC_POST: 1393 case ARM::STCL_POST: 1394 imm |= U << 8; 1395 // fall through. 1396 default: 1397 // The 'option' variant doesn't encode 'U' in the immediate since 1398 // the immediate is unsigned [0,255]. 1399 Inst.addOperand(MCOperand::CreateImm(imm)); 1400 break; 1401 } 1402 1403 switch (Inst.getOpcode()) { 1404 case ARM::LDC_OFFSET: 1405 case ARM::LDC_PRE: 1406 case ARM::LDC_POST: 1407 case ARM::LDC_OPTION: 1408 case ARM::LDCL_OFFSET: 1409 case ARM::LDCL_PRE: 1410 case ARM::LDCL_POST: 1411 case ARM::LDCL_OPTION: 1412 case ARM::STC_OFFSET: 1413 case ARM::STC_PRE: 1414 case ARM::STC_POST: 1415 case ARM::STC_OPTION: 1416 case ARM::STCL_OFFSET: 1417 case ARM::STCL_PRE: 1418 case ARM::STCL_POST: 1419 case ARM::STCL_OPTION: 1420 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1421 return MCDisassembler::Fail; 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return S; 1428 } 1429 1430 static DecodeStatus 1431 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1432 uint64_t Address, const void *Decoder) { 1433 DecodeStatus S = MCDisassembler::Success; 1434 1435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1436 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1437 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1438 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1439 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1440 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1441 unsigned P = fieldFromInstruction(Insn, 24, 1); 1442 unsigned W = fieldFromInstruction(Insn, 21, 1); 1443 1444 // On stores, the writeback operand precedes Rt. 1445 switch (Inst.getOpcode()) { 1446 case ARM::STR_POST_IMM: 1447 case ARM::STR_POST_REG: 1448 case ARM::STRB_POST_IMM: 1449 case ARM::STRB_POST_REG: 1450 case ARM::STRT_POST_REG: 1451 case ARM::STRT_POST_IMM: 1452 case ARM::STRBT_POST_REG: 1453 case ARM::STRBT_POST_IMM: 1454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1455 return MCDisassembler::Fail; 1456 break; 1457 default: 1458 break; 1459 } 1460 1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1462 return MCDisassembler::Fail; 1463 1464 // On loads, the writeback operand comes after Rt. 1465 switch (Inst.getOpcode()) { 1466 case ARM::LDR_POST_IMM: 1467 case ARM::LDR_POST_REG: 1468 case ARM::LDRB_POST_IMM: 1469 case ARM::LDRB_POST_REG: 1470 case ARM::LDRBT_POST_REG: 1471 case ARM::LDRBT_POST_IMM: 1472 case ARM::LDRT_POST_REG: 1473 case ARM::LDRT_POST_IMM: 1474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1475 return MCDisassembler::Fail; 1476 break; 1477 default: 1478 break; 1479 } 1480 1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 1484 ARM_AM::AddrOpc Op = ARM_AM::add; 1485 if (!fieldFromInstruction(Insn, 23, 1)) 1486 Op = ARM_AM::sub; 1487 1488 bool writeback = (P == 0) || (W == 1); 1489 unsigned idx_mode = 0; 1490 if (P && writeback) 1491 idx_mode = ARMII::IndexModePre; 1492 else if (!P && writeback) 1493 idx_mode = ARMII::IndexModePost; 1494 1495 if (writeback && (Rn == 15 || Rn == Rt)) 1496 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1497 1498 if (reg) { 1499 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1500 return MCDisassembler::Fail; 1501 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1502 switch( fieldFromInstruction(Insn, 5, 2)) { 1503 case 0: 1504 Opc = ARM_AM::lsl; 1505 break; 1506 case 1: 1507 Opc = ARM_AM::lsr; 1508 break; 1509 case 2: 1510 Opc = ARM_AM::asr; 1511 break; 1512 case 3: 1513 Opc = ARM_AM::ror; 1514 break; 1515 default: 1516 return MCDisassembler::Fail; 1517 } 1518 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1519 if (Opc == ARM_AM::ror && amt == 0) 1520 Opc = ARM_AM::rrx; 1521 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1522 1523 Inst.addOperand(MCOperand::CreateImm(imm)); 1524 } else { 1525 Inst.addOperand(MCOperand::CreateReg(0)); 1526 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1527 Inst.addOperand(MCOperand::CreateImm(tmp)); 1528 } 1529 1530 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1531 return MCDisassembler::Fail; 1532 1533 return S; 1534 } 1535 1536 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1537 uint64_t Address, const void *Decoder) { 1538 DecodeStatus S = MCDisassembler::Success; 1539 1540 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1541 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1542 unsigned type = fieldFromInstruction(Val, 5, 2); 1543 unsigned imm = fieldFromInstruction(Val, 7, 5); 1544 unsigned U = fieldFromInstruction(Val, 12, 1); 1545 1546 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1547 switch (type) { 1548 case 0: 1549 ShOp = ARM_AM::lsl; 1550 break; 1551 case 1: 1552 ShOp = ARM_AM::lsr; 1553 break; 1554 case 2: 1555 ShOp = ARM_AM::asr; 1556 break; 1557 case 3: 1558 ShOp = ARM_AM::ror; 1559 break; 1560 } 1561 1562 if (ShOp == ARM_AM::ror && imm == 0) 1563 ShOp = ARM_AM::rrx; 1564 1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1566 return MCDisassembler::Fail; 1567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1568 return MCDisassembler::Fail; 1569 unsigned shift; 1570 if (U) 1571 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1572 else 1573 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1574 Inst.addOperand(MCOperand::CreateImm(shift)); 1575 1576 return S; 1577 } 1578 1579 static DecodeStatus 1580 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1581 uint64_t Address, const void *Decoder) { 1582 DecodeStatus S = MCDisassembler::Success; 1583 1584 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1586 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1587 unsigned type = fieldFromInstruction(Insn, 22, 1); 1588 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1589 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1590 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1591 unsigned W = fieldFromInstruction(Insn, 21, 1); 1592 unsigned P = fieldFromInstruction(Insn, 24, 1); 1593 unsigned Rt2 = Rt + 1; 1594 1595 bool writeback = (W == 1) | (P == 0); 1596 1597 // For {LD,ST}RD, Rt must be even, else undefined. 1598 switch (Inst.getOpcode()) { 1599 case ARM::STRD: 1600 case ARM::STRD_PRE: 1601 case ARM::STRD_POST: 1602 case ARM::LDRD: 1603 case ARM::LDRD_PRE: 1604 case ARM::LDRD_POST: 1605 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1606 break; 1607 default: 1608 break; 1609 } 1610 switch (Inst.getOpcode()) { 1611 case ARM::STRD: 1612 case ARM::STRD_PRE: 1613 case ARM::STRD_POST: 1614 if (P == 0 && W == 1) 1615 S = MCDisassembler::SoftFail; 1616 1617 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1618 S = MCDisassembler::SoftFail; 1619 if (type && Rm == 15) 1620 S = MCDisassembler::SoftFail; 1621 if (Rt2 == 15) 1622 S = MCDisassembler::SoftFail; 1623 if (!type && fieldFromInstruction(Insn, 8, 4)) 1624 S = MCDisassembler::SoftFail; 1625 break; 1626 case ARM::STRH: 1627 case ARM::STRH_PRE: 1628 case ARM::STRH_POST: 1629 if (Rt == 15) 1630 S = MCDisassembler::SoftFail; 1631 if (writeback && (Rn == 15 || Rn == Rt)) 1632 S = MCDisassembler::SoftFail; 1633 if (!type && Rm == 15) 1634 S = MCDisassembler::SoftFail; 1635 break; 1636 case ARM::LDRD: 1637 case ARM::LDRD_PRE: 1638 case ARM::LDRD_POST: 1639 if (type && Rn == 15){ 1640 if (Rt2 == 15) 1641 S = MCDisassembler::SoftFail; 1642 break; 1643 } 1644 if (P == 0 && W == 1) 1645 S = MCDisassembler::SoftFail; 1646 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1647 S = MCDisassembler::SoftFail; 1648 if (!type && writeback && Rn == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (writeback && (Rn == Rt || Rn == Rt2)) 1651 S = MCDisassembler::SoftFail; 1652 break; 1653 case ARM::LDRH: 1654 case ARM::LDRH_PRE: 1655 case ARM::LDRH_POST: 1656 if (type && Rn == 15){ 1657 if (Rt == 15) 1658 S = MCDisassembler::SoftFail; 1659 break; 1660 } 1661 if (Rt == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && Rm == 15) 1664 S = MCDisassembler::SoftFail; 1665 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1666 S = MCDisassembler::SoftFail; 1667 break; 1668 case ARM::LDRSH: 1669 case ARM::LDRSH_PRE: 1670 case ARM::LDRSH_POST: 1671 case ARM::LDRSB: 1672 case ARM::LDRSB_PRE: 1673 case ARM::LDRSB_POST: 1674 if (type && Rn == 15){ 1675 if (Rt == 15) 1676 S = MCDisassembler::SoftFail; 1677 break; 1678 } 1679 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1680 S = MCDisassembler::SoftFail; 1681 if (!type && (Rt == 15 || Rm == 15)) 1682 S = MCDisassembler::SoftFail; 1683 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1684 S = MCDisassembler::SoftFail; 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 if (writeback) { // Writeback 1691 if (P) 1692 U |= ARMII::IndexModePre << 9; 1693 else 1694 U |= ARMII::IndexModePost << 9; 1695 1696 // On stores, the writeback operand precedes Rt. 1697 switch (Inst.getOpcode()) { 1698 case ARM::STRD: 1699 case ARM::STRD_PRE: 1700 case ARM::STRD_POST: 1701 case ARM::STRH: 1702 case ARM::STRH_PRE: 1703 case ARM::STRH_POST: 1704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1705 return MCDisassembler::Fail; 1706 break; 1707 default: 1708 break; 1709 } 1710 } 1711 1712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 switch (Inst.getOpcode()) { 1715 case ARM::STRD: 1716 case ARM::STRD_PRE: 1717 case ARM::STRD_POST: 1718 case ARM::LDRD: 1719 case ARM::LDRD_PRE: 1720 case ARM::LDRD_POST: 1721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1722 return MCDisassembler::Fail; 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 if (writeback) { 1729 // On loads, the writeback operand comes after Rt. 1730 switch (Inst.getOpcode()) { 1731 case ARM::LDRD: 1732 case ARM::LDRD_PRE: 1733 case ARM::LDRD_POST: 1734 case ARM::LDRH: 1735 case ARM::LDRH_PRE: 1736 case ARM::LDRH_POST: 1737 case ARM::LDRSH: 1738 case ARM::LDRSH_PRE: 1739 case ARM::LDRSH_POST: 1740 case ARM::LDRSB: 1741 case ARM::LDRSB_PRE: 1742 case ARM::LDRSB_POST: 1743 case ARM::LDRHTr: 1744 case ARM::LDRSBTr: 1745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1746 return MCDisassembler::Fail; 1747 break; 1748 default: 1749 break; 1750 } 1751 } 1752 1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1754 return MCDisassembler::Fail; 1755 1756 if (type) { 1757 Inst.addOperand(MCOperand::CreateReg(0)); 1758 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1759 } else { 1760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 Inst.addOperand(MCOperand::CreateImm(U)); 1763 } 1764 1765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1766 return MCDisassembler::Fail; 1767 1768 return S; 1769 } 1770 1771 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1772 uint64_t Address, const void *Decoder) { 1773 DecodeStatus S = MCDisassembler::Success; 1774 1775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1776 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1777 1778 switch (mode) { 1779 case 0: 1780 mode = ARM_AM::da; 1781 break; 1782 case 1: 1783 mode = ARM_AM::ia; 1784 break; 1785 case 2: 1786 mode = ARM_AM::db; 1787 break; 1788 case 3: 1789 mode = ARM_AM::ib; 1790 break; 1791 } 1792 1793 Inst.addOperand(MCOperand::CreateImm(mode)); 1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 1797 return S; 1798 } 1799 1800 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1801 unsigned Insn, 1802 uint64_t Address, const void *Decoder) { 1803 DecodeStatus S = MCDisassembler::Success; 1804 1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1806 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1807 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1808 1809 if (pred == 0xF) { 1810 switch (Inst.getOpcode()) { 1811 case ARM::LDMDA: 1812 Inst.setOpcode(ARM::RFEDA); 1813 break; 1814 case ARM::LDMDA_UPD: 1815 Inst.setOpcode(ARM::RFEDA_UPD); 1816 break; 1817 case ARM::LDMDB: 1818 Inst.setOpcode(ARM::RFEDB); 1819 break; 1820 case ARM::LDMDB_UPD: 1821 Inst.setOpcode(ARM::RFEDB_UPD); 1822 break; 1823 case ARM::LDMIA: 1824 Inst.setOpcode(ARM::RFEIA); 1825 break; 1826 case ARM::LDMIA_UPD: 1827 Inst.setOpcode(ARM::RFEIA_UPD); 1828 break; 1829 case ARM::LDMIB: 1830 Inst.setOpcode(ARM::RFEIB); 1831 break; 1832 case ARM::LDMIB_UPD: 1833 Inst.setOpcode(ARM::RFEIB_UPD); 1834 break; 1835 case ARM::STMDA: 1836 Inst.setOpcode(ARM::SRSDA); 1837 break; 1838 case ARM::STMDA_UPD: 1839 Inst.setOpcode(ARM::SRSDA_UPD); 1840 break; 1841 case ARM::STMDB: 1842 Inst.setOpcode(ARM::SRSDB); 1843 break; 1844 case ARM::STMDB_UPD: 1845 Inst.setOpcode(ARM::SRSDB_UPD); 1846 break; 1847 case ARM::STMIA: 1848 Inst.setOpcode(ARM::SRSIA); 1849 break; 1850 case ARM::STMIA_UPD: 1851 Inst.setOpcode(ARM::SRSIA_UPD); 1852 break; 1853 case ARM::STMIB: 1854 Inst.setOpcode(ARM::SRSIB); 1855 break; 1856 case ARM::STMIB_UPD: 1857 Inst.setOpcode(ARM::SRSIB_UPD); 1858 break; 1859 default: 1860 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1861 } 1862 1863 // For stores (which become SRS's, the only operand is the mode. 1864 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1865 Inst.addOperand( 1866 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1867 return S; 1868 } 1869 1870 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1871 } 1872 1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1874 return MCDisassembler::Fail; 1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1876 return MCDisassembler::Fail; // Tied 1877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1878 return MCDisassembler::Fail; 1879 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 1882 return S; 1883 } 1884 1885 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1886 uint64_t Address, const void *Decoder) { 1887 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1888 unsigned M = fieldFromInstruction(Insn, 17, 1); 1889 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1890 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1891 1892 DecodeStatus S = MCDisassembler::Success; 1893 1894 // imod == '01' --> UNPREDICTABLE 1895 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1896 // return failure here. The '01' imod value is unprintable, so there's 1897 // nothing useful we could do even if we returned UNPREDICTABLE. 1898 1899 if (imod == 1) return MCDisassembler::Fail; 1900 1901 if (imod && M) { 1902 Inst.setOpcode(ARM::CPS3p); 1903 Inst.addOperand(MCOperand::CreateImm(imod)); 1904 Inst.addOperand(MCOperand::CreateImm(iflags)); 1905 Inst.addOperand(MCOperand::CreateImm(mode)); 1906 } else if (imod && !M) { 1907 Inst.setOpcode(ARM::CPS2p); 1908 Inst.addOperand(MCOperand::CreateImm(imod)); 1909 Inst.addOperand(MCOperand::CreateImm(iflags)); 1910 if (mode) S = MCDisassembler::SoftFail; 1911 } else if (!imod && M) { 1912 Inst.setOpcode(ARM::CPS1p); 1913 Inst.addOperand(MCOperand::CreateImm(mode)); 1914 if (iflags) S = MCDisassembler::SoftFail; 1915 } else { 1916 // imod == '00' && M == '0' --> UNPREDICTABLE 1917 Inst.setOpcode(ARM::CPS1p); 1918 Inst.addOperand(MCOperand::CreateImm(mode)); 1919 S = MCDisassembler::SoftFail; 1920 } 1921 1922 return S; 1923 } 1924 1925 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1926 uint64_t Address, const void *Decoder) { 1927 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1928 unsigned M = fieldFromInstruction(Insn, 8, 1); 1929 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1930 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1931 1932 DecodeStatus S = MCDisassembler::Success; 1933 1934 // imod == '01' --> UNPREDICTABLE 1935 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1936 // return failure here. The '01' imod value is unprintable, so there's 1937 // nothing useful we could do even if we returned UNPREDICTABLE. 1938 1939 if (imod == 1) return MCDisassembler::Fail; 1940 1941 if (imod && M) { 1942 Inst.setOpcode(ARM::t2CPS3p); 1943 Inst.addOperand(MCOperand::CreateImm(imod)); 1944 Inst.addOperand(MCOperand::CreateImm(iflags)); 1945 Inst.addOperand(MCOperand::CreateImm(mode)); 1946 } else if (imod && !M) { 1947 Inst.setOpcode(ARM::t2CPS2p); 1948 Inst.addOperand(MCOperand::CreateImm(imod)); 1949 Inst.addOperand(MCOperand::CreateImm(iflags)); 1950 if (mode) S = MCDisassembler::SoftFail; 1951 } else if (!imod && M) { 1952 Inst.setOpcode(ARM::t2CPS1p); 1953 Inst.addOperand(MCOperand::CreateImm(mode)); 1954 if (iflags) S = MCDisassembler::SoftFail; 1955 } else { 1956 // imod == '00' && M == '0' --> UNPREDICTABLE 1957 Inst.setOpcode(ARM::t2CPS1p); 1958 Inst.addOperand(MCOperand::CreateImm(mode)); 1959 S = MCDisassembler::SoftFail; 1960 } 1961 1962 return S; 1963 } 1964 1965 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 DecodeStatus S = MCDisassembler::Success; 1968 1969 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1970 unsigned imm = 0; 1971 1972 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1973 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1974 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1975 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1976 1977 if (Inst.getOpcode() == ARM::t2MOVTi16) 1978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 1983 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1984 Inst.addOperand(MCOperand::CreateImm(imm)); 1985 1986 return S; 1987 } 1988 1989 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1990 uint64_t Address, const void *Decoder) { 1991 DecodeStatus S = MCDisassembler::Success; 1992 1993 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1994 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1995 unsigned imm = 0; 1996 1997 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 1998 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1999 2000 if (Inst.getOpcode() == ARM::MOVTi16) 2001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2002 return MCDisassembler::Fail; 2003 2004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2005 return MCDisassembler::Fail; 2006 2007 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2008 Inst.addOperand(MCOperand::CreateImm(imm)); 2009 2010 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2011 return MCDisassembler::Fail; 2012 2013 return S; 2014 } 2015 2016 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2017 uint64_t Address, const void *Decoder) { 2018 DecodeStatus S = MCDisassembler::Success; 2019 2020 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2021 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2022 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2023 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2024 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2025 2026 if (pred == 0xF) 2027 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2028 2029 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2030 return MCDisassembler::Fail; 2031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2032 return MCDisassembler::Fail; 2033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2036 return MCDisassembler::Fail; 2037 2038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 2041 return S; 2042 } 2043 2044 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2045 uint64_t Address, const void *Decoder) { 2046 DecodeStatus S = MCDisassembler::Success; 2047 2048 unsigned add = fieldFromInstruction(Val, 12, 1); 2049 unsigned imm = fieldFromInstruction(Val, 0, 12); 2050 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2051 2052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2053 return MCDisassembler::Fail; 2054 2055 if (!add) imm *= -1; 2056 if (imm == 0 && !add) imm = INT32_MIN; 2057 Inst.addOperand(MCOperand::CreateImm(imm)); 2058 if (Rn == 15) 2059 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2060 2061 return S; 2062 } 2063 2064 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2065 uint64_t Address, const void *Decoder) { 2066 DecodeStatus S = MCDisassembler::Success; 2067 2068 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2069 unsigned U = fieldFromInstruction(Val, 8, 1); 2070 unsigned imm = fieldFromInstruction(Val, 0, 8); 2071 2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2073 return MCDisassembler::Fail; 2074 2075 if (U) 2076 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2077 else 2078 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2079 2080 return S; 2081 } 2082 2083 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2084 uint64_t Address, const void *Decoder) { 2085 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2086 } 2087 2088 static DecodeStatus 2089 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2090 uint64_t Address, const void *Decoder) { 2091 DecodeStatus Status = MCDisassembler::Success; 2092 2093 // Note the J1 and J2 values are from the encoded instruction. So here 2094 // change them to I1 and I2 values via as documented: 2095 // I1 = NOT(J1 EOR S); 2096 // I2 = NOT(J2 EOR S); 2097 // and build the imm32 with one trailing zero as documented: 2098 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2099 unsigned S = fieldFromInstruction(Insn, 26, 1); 2100 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2101 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2102 unsigned I1 = !(J1 ^ S); 2103 unsigned I2 = !(J2 ^ S); 2104 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2105 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2106 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2107 int imm32 = SignExtend32<24>(tmp << 1); 2108 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2109 true, 4, Inst, Decoder)) 2110 Inst.addOperand(MCOperand::CreateImm(imm32)); 2111 2112 return Status; 2113 } 2114 2115 static DecodeStatus 2116 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2117 uint64_t Address, const void *Decoder) { 2118 DecodeStatus S = MCDisassembler::Success; 2119 2120 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2121 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2122 2123 if (pred == 0xF) { 2124 Inst.setOpcode(ARM::BLXi); 2125 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2126 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2127 true, 4, Inst, Decoder)) 2128 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2129 return S; 2130 } 2131 2132 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2133 true, 4, Inst, Decoder)) 2134 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2135 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 2138 return S; 2139 } 2140 2141 2142 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2143 uint64_t Address, const void *Decoder) { 2144 DecodeStatus S = MCDisassembler::Success; 2145 2146 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2147 unsigned align = fieldFromInstruction(Val, 4, 2); 2148 2149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2150 return MCDisassembler::Fail; 2151 if (!align) 2152 Inst.addOperand(MCOperand::CreateImm(0)); 2153 else 2154 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2155 2156 return S; 2157 } 2158 2159 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2160 uint64_t Address, const void *Decoder) { 2161 DecodeStatus S = MCDisassembler::Success; 2162 2163 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2164 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2165 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2166 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2167 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2168 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2169 2170 // First output register 2171 switch (Inst.getOpcode()) { 2172 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2173 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2174 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2175 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2176 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2177 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2178 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2179 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2180 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2181 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2182 return MCDisassembler::Fail; 2183 break; 2184 case ARM::VLD2b16: 2185 case ARM::VLD2b32: 2186 case ARM::VLD2b8: 2187 case ARM::VLD2b16wb_fixed: 2188 case ARM::VLD2b16wb_register: 2189 case ARM::VLD2b32wb_fixed: 2190 case ARM::VLD2b32wb_register: 2191 case ARM::VLD2b8wb_fixed: 2192 case ARM::VLD2b8wb_register: 2193 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2194 return MCDisassembler::Fail; 2195 break; 2196 default: 2197 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 } 2200 2201 // Second output register 2202 switch (Inst.getOpcode()) { 2203 case ARM::VLD3d8: 2204 case ARM::VLD3d16: 2205 case ARM::VLD3d32: 2206 case ARM::VLD3d8_UPD: 2207 case ARM::VLD3d16_UPD: 2208 case ARM::VLD3d32_UPD: 2209 case ARM::VLD4d8: 2210 case ARM::VLD4d16: 2211 case ARM::VLD4d32: 2212 case ARM::VLD4d8_UPD: 2213 case ARM::VLD4d16_UPD: 2214 case ARM::VLD4d32_UPD: 2215 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2216 return MCDisassembler::Fail; 2217 break; 2218 case ARM::VLD3q8: 2219 case ARM::VLD3q16: 2220 case ARM::VLD3q32: 2221 case ARM::VLD3q8_UPD: 2222 case ARM::VLD3q16_UPD: 2223 case ARM::VLD3q32_UPD: 2224 case ARM::VLD4q8: 2225 case ARM::VLD4q16: 2226 case ARM::VLD4q32: 2227 case ARM::VLD4q8_UPD: 2228 case ARM::VLD4q16_UPD: 2229 case ARM::VLD4q32_UPD: 2230 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2231 return MCDisassembler::Fail; 2232 default: 2233 break; 2234 } 2235 2236 // Third output register 2237 switch(Inst.getOpcode()) { 2238 case ARM::VLD3d8: 2239 case ARM::VLD3d16: 2240 case ARM::VLD3d32: 2241 case ARM::VLD3d8_UPD: 2242 case ARM::VLD3d16_UPD: 2243 case ARM::VLD3d32_UPD: 2244 case ARM::VLD4d8: 2245 case ARM::VLD4d16: 2246 case ARM::VLD4d32: 2247 case ARM::VLD4d8_UPD: 2248 case ARM::VLD4d16_UPD: 2249 case ARM::VLD4d32_UPD: 2250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 break; 2253 case ARM::VLD3q8: 2254 case ARM::VLD3q16: 2255 case ARM::VLD3q32: 2256 case ARM::VLD3q8_UPD: 2257 case ARM::VLD3q16_UPD: 2258 case ARM::VLD3q32_UPD: 2259 case ARM::VLD4q8: 2260 case ARM::VLD4q16: 2261 case ARM::VLD4q32: 2262 case ARM::VLD4q8_UPD: 2263 case ARM::VLD4q16_UPD: 2264 case ARM::VLD4q32_UPD: 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 break; 2268 default: 2269 break; 2270 } 2271 2272 // Fourth output register 2273 switch (Inst.getOpcode()) { 2274 case ARM::VLD4d8: 2275 case ARM::VLD4d16: 2276 case ARM::VLD4d32: 2277 case ARM::VLD4d8_UPD: 2278 case ARM::VLD4d16_UPD: 2279 case ARM::VLD4d32_UPD: 2280 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2281 return MCDisassembler::Fail; 2282 break; 2283 case ARM::VLD4q8: 2284 case ARM::VLD4q16: 2285 case ARM::VLD4q32: 2286 case ARM::VLD4q8_UPD: 2287 case ARM::VLD4q16_UPD: 2288 case ARM::VLD4q32_UPD: 2289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2290 return MCDisassembler::Fail; 2291 break; 2292 default: 2293 break; 2294 } 2295 2296 // Writeback operand 2297 switch (Inst.getOpcode()) { 2298 case ARM::VLD1d8wb_fixed: 2299 case ARM::VLD1d16wb_fixed: 2300 case ARM::VLD1d32wb_fixed: 2301 case ARM::VLD1d64wb_fixed: 2302 case ARM::VLD1d8wb_register: 2303 case ARM::VLD1d16wb_register: 2304 case ARM::VLD1d32wb_register: 2305 case ARM::VLD1d64wb_register: 2306 case ARM::VLD1q8wb_fixed: 2307 case ARM::VLD1q16wb_fixed: 2308 case ARM::VLD1q32wb_fixed: 2309 case ARM::VLD1q64wb_fixed: 2310 case ARM::VLD1q8wb_register: 2311 case ARM::VLD1q16wb_register: 2312 case ARM::VLD1q32wb_register: 2313 case ARM::VLD1q64wb_register: 2314 case ARM::VLD1d8Twb_fixed: 2315 case ARM::VLD1d8Twb_register: 2316 case ARM::VLD1d16Twb_fixed: 2317 case ARM::VLD1d16Twb_register: 2318 case ARM::VLD1d32Twb_fixed: 2319 case ARM::VLD1d32Twb_register: 2320 case ARM::VLD1d64Twb_fixed: 2321 case ARM::VLD1d64Twb_register: 2322 case ARM::VLD1d8Qwb_fixed: 2323 case ARM::VLD1d8Qwb_register: 2324 case ARM::VLD1d16Qwb_fixed: 2325 case ARM::VLD1d16Qwb_register: 2326 case ARM::VLD1d32Qwb_fixed: 2327 case ARM::VLD1d32Qwb_register: 2328 case ARM::VLD1d64Qwb_fixed: 2329 case ARM::VLD1d64Qwb_register: 2330 case ARM::VLD2d8wb_fixed: 2331 case ARM::VLD2d16wb_fixed: 2332 case ARM::VLD2d32wb_fixed: 2333 case ARM::VLD2q8wb_fixed: 2334 case ARM::VLD2q16wb_fixed: 2335 case ARM::VLD2q32wb_fixed: 2336 case ARM::VLD2d8wb_register: 2337 case ARM::VLD2d16wb_register: 2338 case ARM::VLD2d32wb_register: 2339 case ARM::VLD2q8wb_register: 2340 case ARM::VLD2q16wb_register: 2341 case ARM::VLD2q32wb_register: 2342 case ARM::VLD2b8wb_fixed: 2343 case ARM::VLD2b16wb_fixed: 2344 case ARM::VLD2b32wb_fixed: 2345 case ARM::VLD2b8wb_register: 2346 case ARM::VLD2b16wb_register: 2347 case ARM::VLD2b32wb_register: 2348 Inst.addOperand(MCOperand::CreateImm(0)); 2349 break; 2350 case ARM::VLD3d8_UPD: 2351 case ARM::VLD3d16_UPD: 2352 case ARM::VLD3d32_UPD: 2353 case ARM::VLD3q8_UPD: 2354 case ARM::VLD3q16_UPD: 2355 case ARM::VLD3q32_UPD: 2356 case ARM::VLD4d8_UPD: 2357 case ARM::VLD4d16_UPD: 2358 case ARM::VLD4d32_UPD: 2359 case ARM::VLD4q8_UPD: 2360 case ARM::VLD4q16_UPD: 2361 case ARM::VLD4q32_UPD: 2362 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2363 return MCDisassembler::Fail; 2364 break; 2365 default: 2366 break; 2367 } 2368 2369 // AddrMode6 Base (register+alignment) 2370 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2371 return MCDisassembler::Fail; 2372 2373 // AddrMode6 Offset (register) 2374 switch (Inst.getOpcode()) { 2375 default: 2376 // The below have been updated to have explicit am6offset split 2377 // between fixed and register offset. For those instructions not 2378 // yet updated, we need to add an additional reg0 operand for the 2379 // fixed variant. 2380 // 2381 // The fixed offset encodes as Rm == 0xd, so we check for that. 2382 if (Rm == 0xd) { 2383 Inst.addOperand(MCOperand::CreateReg(0)); 2384 break; 2385 } 2386 // Fall through to handle the register offset variant. 2387 case ARM::VLD1d8wb_fixed: 2388 case ARM::VLD1d16wb_fixed: 2389 case ARM::VLD1d32wb_fixed: 2390 case ARM::VLD1d64wb_fixed: 2391 case ARM::VLD1d8Twb_fixed: 2392 case ARM::VLD1d16Twb_fixed: 2393 case ARM::VLD1d32Twb_fixed: 2394 case ARM::VLD1d64Twb_fixed: 2395 case ARM::VLD1d8Qwb_fixed: 2396 case ARM::VLD1d16Qwb_fixed: 2397 case ARM::VLD1d32Qwb_fixed: 2398 case ARM::VLD1d64Qwb_fixed: 2399 case ARM::VLD1d8wb_register: 2400 case ARM::VLD1d16wb_register: 2401 case ARM::VLD1d32wb_register: 2402 case ARM::VLD1d64wb_register: 2403 case ARM::VLD1q8wb_fixed: 2404 case ARM::VLD1q16wb_fixed: 2405 case ARM::VLD1q32wb_fixed: 2406 case ARM::VLD1q64wb_fixed: 2407 case ARM::VLD1q8wb_register: 2408 case ARM::VLD1q16wb_register: 2409 case ARM::VLD1q32wb_register: 2410 case ARM::VLD1q64wb_register: 2411 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2412 // variant encodes Rm == 0xf. Anything else is a register offset post- 2413 // increment and we need to add the register operand to the instruction. 2414 if (Rm != 0xD && Rm != 0xF && 2415 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 break; 2418 case ARM::VLD2d8wb_fixed: 2419 case ARM::VLD2d16wb_fixed: 2420 case ARM::VLD2d32wb_fixed: 2421 case ARM::VLD2b8wb_fixed: 2422 case ARM::VLD2b16wb_fixed: 2423 case ARM::VLD2b32wb_fixed: 2424 case ARM::VLD2q8wb_fixed: 2425 case ARM::VLD2q16wb_fixed: 2426 case ARM::VLD2q32wb_fixed: 2427 break; 2428 } 2429 2430 return S; 2431 } 2432 2433 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2434 uint64_t Address, const void *Decoder) { 2435 DecodeStatus S = MCDisassembler::Success; 2436 2437 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2438 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2439 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2440 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2441 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2442 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2443 2444 // Writeback Operand 2445 switch (Inst.getOpcode()) { 2446 case ARM::VST1d8wb_fixed: 2447 case ARM::VST1d16wb_fixed: 2448 case ARM::VST1d32wb_fixed: 2449 case ARM::VST1d64wb_fixed: 2450 case ARM::VST1d8wb_register: 2451 case ARM::VST1d16wb_register: 2452 case ARM::VST1d32wb_register: 2453 case ARM::VST1d64wb_register: 2454 case ARM::VST1q8wb_fixed: 2455 case ARM::VST1q16wb_fixed: 2456 case ARM::VST1q32wb_fixed: 2457 case ARM::VST1q64wb_fixed: 2458 case ARM::VST1q8wb_register: 2459 case ARM::VST1q16wb_register: 2460 case ARM::VST1q32wb_register: 2461 case ARM::VST1q64wb_register: 2462 case ARM::VST1d8Twb_fixed: 2463 case ARM::VST1d16Twb_fixed: 2464 case ARM::VST1d32Twb_fixed: 2465 case ARM::VST1d64Twb_fixed: 2466 case ARM::VST1d8Twb_register: 2467 case ARM::VST1d16Twb_register: 2468 case ARM::VST1d32Twb_register: 2469 case ARM::VST1d64Twb_register: 2470 case ARM::VST1d8Qwb_fixed: 2471 case ARM::VST1d16Qwb_fixed: 2472 case ARM::VST1d32Qwb_fixed: 2473 case ARM::VST1d64Qwb_fixed: 2474 case ARM::VST1d8Qwb_register: 2475 case ARM::VST1d16Qwb_register: 2476 case ARM::VST1d32Qwb_register: 2477 case ARM::VST1d64Qwb_register: 2478 case ARM::VST2d8wb_fixed: 2479 case ARM::VST2d16wb_fixed: 2480 case ARM::VST2d32wb_fixed: 2481 case ARM::VST2d8wb_register: 2482 case ARM::VST2d16wb_register: 2483 case ARM::VST2d32wb_register: 2484 case ARM::VST2q8wb_fixed: 2485 case ARM::VST2q16wb_fixed: 2486 case ARM::VST2q32wb_fixed: 2487 case ARM::VST2q8wb_register: 2488 case ARM::VST2q16wb_register: 2489 case ARM::VST2q32wb_register: 2490 case ARM::VST2b8wb_fixed: 2491 case ARM::VST2b16wb_fixed: 2492 case ARM::VST2b32wb_fixed: 2493 case ARM::VST2b8wb_register: 2494 case ARM::VST2b16wb_register: 2495 case ARM::VST2b32wb_register: 2496 if (Rm == 0xF) 2497 return MCDisassembler::Fail; 2498 Inst.addOperand(MCOperand::CreateImm(0)); 2499 break; 2500 case ARM::VST3d8_UPD: 2501 case ARM::VST3d16_UPD: 2502 case ARM::VST3d32_UPD: 2503 case ARM::VST3q8_UPD: 2504 case ARM::VST3q16_UPD: 2505 case ARM::VST3q32_UPD: 2506 case ARM::VST4d8_UPD: 2507 case ARM::VST4d16_UPD: 2508 case ARM::VST4d32_UPD: 2509 case ARM::VST4q8_UPD: 2510 case ARM::VST4q16_UPD: 2511 case ARM::VST4q32_UPD: 2512 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2513 return MCDisassembler::Fail; 2514 break; 2515 default: 2516 break; 2517 } 2518 2519 // AddrMode6 Base (register+alignment) 2520 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2521 return MCDisassembler::Fail; 2522 2523 // AddrMode6 Offset (register) 2524 switch (Inst.getOpcode()) { 2525 default: 2526 if (Rm == 0xD) 2527 Inst.addOperand(MCOperand::CreateReg(0)); 2528 else if (Rm != 0xF) { 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 } 2532 break; 2533 case ARM::VST1d8wb_fixed: 2534 case ARM::VST1d16wb_fixed: 2535 case ARM::VST1d32wb_fixed: 2536 case ARM::VST1d64wb_fixed: 2537 case ARM::VST1q8wb_fixed: 2538 case ARM::VST1q16wb_fixed: 2539 case ARM::VST1q32wb_fixed: 2540 case ARM::VST1q64wb_fixed: 2541 case ARM::VST1d8Twb_fixed: 2542 case ARM::VST1d16Twb_fixed: 2543 case ARM::VST1d32Twb_fixed: 2544 case ARM::VST1d64Twb_fixed: 2545 case ARM::VST1d8Qwb_fixed: 2546 case ARM::VST1d16Qwb_fixed: 2547 case ARM::VST1d32Qwb_fixed: 2548 case ARM::VST1d64Qwb_fixed: 2549 case ARM::VST2d8wb_fixed: 2550 case ARM::VST2d16wb_fixed: 2551 case ARM::VST2d32wb_fixed: 2552 case ARM::VST2q8wb_fixed: 2553 case ARM::VST2q16wb_fixed: 2554 case ARM::VST2q32wb_fixed: 2555 case ARM::VST2b8wb_fixed: 2556 case ARM::VST2b16wb_fixed: 2557 case ARM::VST2b32wb_fixed: 2558 break; 2559 } 2560 2561 2562 // First input register 2563 switch (Inst.getOpcode()) { 2564 case ARM::VST1q16: 2565 case ARM::VST1q32: 2566 case ARM::VST1q64: 2567 case ARM::VST1q8: 2568 case ARM::VST1q16wb_fixed: 2569 case ARM::VST1q16wb_register: 2570 case ARM::VST1q32wb_fixed: 2571 case ARM::VST1q32wb_register: 2572 case ARM::VST1q64wb_fixed: 2573 case ARM::VST1q64wb_register: 2574 case ARM::VST1q8wb_fixed: 2575 case ARM::VST1q8wb_register: 2576 case ARM::VST2d16: 2577 case ARM::VST2d32: 2578 case ARM::VST2d8: 2579 case ARM::VST2d16wb_fixed: 2580 case ARM::VST2d16wb_register: 2581 case ARM::VST2d32wb_fixed: 2582 case ARM::VST2d32wb_register: 2583 case ARM::VST2d8wb_fixed: 2584 case ARM::VST2d8wb_register: 2585 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2586 return MCDisassembler::Fail; 2587 break; 2588 case ARM::VST2b16: 2589 case ARM::VST2b32: 2590 case ARM::VST2b8: 2591 case ARM::VST2b16wb_fixed: 2592 case ARM::VST2b16wb_register: 2593 case ARM::VST2b32wb_fixed: 2594 case ARM::VST2b32wb_register: 2595 case ARM::VST2b8wb_fixed: 2596 case ARM::VST2b8wb_register: 2597 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 break; 2600 default: 2601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2602 return MCDisassembler::Fail; 2603 } 2604 2605 // Second input register 2606 switch (Inst.getOpcode()) { 2607 case ARM::VST3d8: 2608 case ARM::VST3d16: 2609 case ARM::VST3d32: 2610 case ARM::VST3d8_UPD: 2611 case ARM::VST3d16_UPD: 2612 case ARM::VST3d32_UPD: 2613 case ARM::VST4d8: 2614 case ARM::VST4d16: 2615 case ARM::VST4d32: 2616 case ARM::VST4d8_UPD: 2617 case ARM::VST4d16_UPD: 2618 case ARM::VST4d32_UPD: 2619 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2620 return MCDisassembler::Fail; 2621 break; 2622 case ARM::VST3q8: 2623 case ARM::VST3q16: 2624 case ARM::VST3q32: 2625 case ARM::VST3q8_UPD: 2626 case ARM::VST3q16_UPD: 2627 case ARM::VST3q32_UPD: 2628 case ARM::VST4q8: 2629 case ARM::VST4q16: 2630 case ARM::VST4q32: 2631 case ARM::VST4q8_UPD: 2632 case ARM::VST4q16_UPD: 2633 case ARM::VST4q32_UPD: 2634 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2635 return MCDisassembler::Fail; 2636 break; 2637 default: 2638 break; 2639 } 2640 2641 // Third input register 2642 switch (Inst.getOpcode()) { 2643 case ARM::VST3d8: 2644 case ARM::VST3d16: 2645 case ARM::VST3d32: 2646 case ARM::VST3d8_UPD: 2647 case ARM::VST3d16_UPD: 2648 case ARM::VST3d32_UPD: 2649 case ARM::VST4d8: 2650 case ARM::VST4d16: 2651 case ARM::VST4d32: 2652 case ARM::VST4d8_UPD: 2653 case ARM::VST4d16_UPD: 2654 case ARM::VST4d32_UPD: 2655 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2656 return MCDisassembler::Fail; 2657 break; 2658 case ARM::VST3q8: 2659 case ARM::VST3q16: 2660 case ARM::VST3q32: 2661 case ARM::VST3q8_UPD: 2662 case ARM::VST3q16_UPD: 2663 case ARM::VST3q32_UPD: 2664 case ARM::VST4q8: 2665 case ARM::VST4q16: 2666 case ARM::VST4q32: 2667 case ARM::VST4q8_UPD: 2668 case ARM::VST4q16_UPD: 2669 case ARM::VST4q32_UPD: 2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 break; 2673 default: 2674 break; 2675 } 2676 2677 // Fourth input register 2678 switch (Inst.getOpcode()) { 2679 case ARM::VST4d8: 2680 case ARM::VST4d16: 2681 case ARM::VST4d32: 2682 case ARM::VST4d8_UPD: 2683 case ARM::VST4d16_UPD: 2684 case ARM::VST4d32_UPD: 2685 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2686 return MCDisassembler::Fail; 2687 break; 2688 case ARM::VST4q8: 2689 case ARM::VST4q16: 2690 case ARM::VST4q32: 2691 case ARM::VST4q8_UPD: 2692 case ARM::VST4q16_UPD: 2693 case ARM::VST4q32_UPD: 2694 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 break; 2697 default: 2698 break; 2699 } 2700 2701 return S; 2702 } 2703 2704 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2705 uint64_t Address, const void *Decoder) { 2706 DecodeStatus S = MCDisassembler::Success; 2707 2708 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2709 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2710 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2711 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2712 unsigned align = fieldFromInstruction(Insn, 4, 1); 2713 unsigned size = fieldFromInstruction(Insn, 6, 2); 2714 2715 if (size == 0 && align == 1) 2716 return MCDisassembler::Fail; 2717 align *= (1 << size); 2718 2719 switch (Inst.getOpcode()) { 2720 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2721 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2722 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2723 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2724 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 break; 2727 default: 2728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 break; 2731 } 2732 if (Rm != 0xF) { 2733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 } 2736 2737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 Inst.addOperand(MCOperand::CreateImm(align)); 2740 2741 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2742 // variant encodes Rm == 0xf. Anything else is a register offset post- 2743 // increment and we need to add the register operand to the instruction. 2744 if (Rm != 0xD && Rm != 0xF && 2745 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2746 return MCDisassembler::Fail; 2747 2748 return S; 2749 } 2750 2751 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2752 uint64_t Address, const void *Decoder) { 2753 DecodeStatus S = MCDisassembler::Success; 2754 2755 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2756 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2757 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2758 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2759 unsigned align = fieldFromInstruction(Insn, 4, 1); 2760 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2761 align *= 2*size; 2762 2763 switch (Inst.getOpcode()) { 2764 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2765 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2766 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2767 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2768 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2769 return MCDisassembler::Fail; 2770 break; 2771 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2772 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2773 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2774 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2775 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2776 return MCDisassembler::Fail; 2777 break; 2778 default: 2779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 break; 2782 } 2783 2784 if (Rm != 0xF) 2785 Inst.addOperand(MCOperand::CreateImm(0)); 2786 2787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 Inst.addOperand(MCOperand::CreateImm(align)); 2790 2791 if (Rm != 0xD && Rm != 0xF) { 2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 } 2795 2796 return S; 2797 } 2798 2799 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2800 uint64_t Address, const void *Decoder) { 2801 DecodeStatus S = MCDisassembler::Success; 2802 2803 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2804 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2806 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2807 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2808 2809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 if (Rm != 0xF) { 2816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2817 return MCDisassembler::Fail; 2818 } 2819 2820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 Inst.addOperand(MCOperand::CreateImm(0)); 2823 2824 if (Rm == 0xD) 2825 Inst.addOperand(MCOperand::CreateReg(0)); 2826 else if (Rm != 0xF) { 2827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2828 return MCDisassembler::Fail; 2829 } 2830 2831 return S; 2832 } 2833 2834 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2835 uint64_t Address, const void *Decoder) { 2836 DecodeStatus S = MCDisassembler::Success; 2837 2838 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2839 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2840 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2841 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2842 unsigned size = fieldFromInstruction(Insn, 6, 2); 2843 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2844 unsigned align = fieldFromInstruction(Insn, 4, 1); 2845 2846 if (size == 0x3) { 2847 if (align == 0) 2848 return MCDisassembler::Fail; 2849 size = 4; 2850 align = 16; 2851 } else { 2852 if (size == 2) { 2853 size = 1 << size; 2854 align *= 8; 2855 } else { 2856 size = 1 << size; 2857 align *= 4*size; 2858 } 2859 } 2860 2861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2862 return MCDisassembler::Fail; 2863 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2864 return MCDisassembler::Fail; 2865 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2866 return MCDisassembler::Fail; 2867 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2868 return MCDisassembler::Fail; 2869 if (Rm != 0xF) { 2870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2871 return MCDisassembler::Fail; 2872 } 2873 2874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 Inst.addOperand(MCOperand::CreateImm(align)); 2877 2878 if (Rm == 0xD) 2879 Inst.addOperand(MCOperand::CreateReg(0)); 2880 else if (Rm != 0xF) { 2881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2882 return MCDisassembler::Fail; 2883 } 2884 2885 return S; 2886 } 2887 2888 static DecodeStatus 2889 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2890 uint64_t Address, const void *Decoder) { 2891 DecodeStatus S = MCDisassembler::Success; 2892 2893 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2894 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2895 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2896 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2897 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2898 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2899 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2900 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2901 2902 if (Q) { 2903 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2904 return MCDisassembler::Fail; 2905 } else { 2906 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2907 return MCDisassembler::Fail; 2908 } 2909 2910 Inst.addOperand(MCOperand::CreateImm(imm)); 2911 2912 switch (Inst.getOpcode()) { 2913 case ARM::VORRiv4i16: 2914 case ARM::VORRiv2i32: 2915 case ARM::VBICiv4i16: 2916 case ARM::VBICiv2i32: 2917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 break; 2920 case ARM::VORRiv8i16: 2921 case ARM::VORRiv4i32: 2922 case ARM::VBICiv8i16: 2923 case ARM::VBICiv4i32: 2924 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 break; 2927 default: 2928 break; 2929 } 2930 2931 return S; 2932 } 2933 2934 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2935 uint64_t Address, const void *Decoder) { 2936 DecodeStatus S = MCDisassembler::Success; 2937 2938 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2939 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2940 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2941 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2942 unsigned size = fieldFromInstruction(Insn, 18, 2); 2943 2944 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2949 2950 return S; 2951 } 2952 2953 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2954 uint64_t Address, const void *Decoder) { 2955 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2956 return MCDisassembler::Success; 2957 } 2958 2959 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2960 uint64_t Address, const void *Decoder) { 2961 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2962 return MCDisassembler::Success; 2963 } 2964 2965 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2966 uint64_t Address, const void *Decoder) { 2967 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2968 return MCDisassembler::Success; 2969 } 2970 2971 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2972 uint64_t Address, const void *Decoder) { 2973 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2974 return MCDisassembler::Success; 2975 } 2976 2977 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2978 uint64_t Address, const void *Decoder) { 2979 DecodeStatus S = MCDisassembler::Success; 2980 2981 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2982 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2983 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2984 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2985 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2986 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2987 unsigned op = fieldFromInstruction(Insn, 6, 1); 2988 2989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 if (op) { 2992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2993 return MCDisassembler::Fail; // Writeback 2994 } 2995 2996 switch (Inst.getOpcode()) { 2997 case ARM::VTBL2: 2998 case ARM::VTBX2: 2999 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 break; 3002 default: 3003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 } 3006 3007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 3010 return S; 3011 } 3012 3013 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3014 uint64_t Address, const void *Decoder) { 3015 DecodeStatus S = MCDisassembler::Success; 3016 3017 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3018 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3019 3020 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3021 return MCDisassembler::Fail; 3022 3023 switch(Inst.getOpcode()) { 3024 default: 3025 return MCDisassembler::Fail; 3026 case ARM::tADR: 3027 break; // tADR does not explicitly represent the PC as an operand. 3028 case ARM::tADDrSPi: 3029 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3030 break; 3031 } 3032 3033 Inst.addOperand(MCOperand::CreateImm(imm)); 3034 return S; 3035 } 3036 3037 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3038 uint64_t Address, const void *Decoder) { 3039 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3040 true, 2, Inst, Decoder)) 3041 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3042 return MCDisassembler::Success; 3043 } 3044 3045 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3046 uint64_t Address, const void *Decoder) { 3047 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3048 true, 4, Inst, Decoder)) 3049 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3050 return MCDisassembler::Success; 3051 } 3052 3053 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3054 uint64_t Address, const void *Decoder) { 3055 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3056 true, 2, Inst, Decoder)) 3057 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3058 return MCDisassembler::Success; 3059 } 3060 3061 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3062 uint64_t Address, const void *Decoder) { 3063 DecodeStatus S = MCDisassembler::Success; 3064 3065 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3066 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3067 3068 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3069 return MCDisassembler::Fail; 3070 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3071 return MCDisassembler::Fail; 3072 3073 return S; 3074 } 3075 3076 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3077 uint64_t Address, const void *Decoder) { 3078 DecodeStatus S = MCDisassembler::Success; 3079 3080 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3081 unsigned imm = fieldFromInstruction(Val, 3, 5); 3082 3083 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 Inst.addOperand(MCOperand::CreateImm(imm)); 3086 3087 return S; 3088 } 3089 3090 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3091 uint64_t Address, const void *Decoder) { 3092 unsigned imm = Val << 2; 3093 3094 Inst.addOperand(MCOperand::CreateImm(imm)); 3095 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3096 3097 return MCDisassembler::Success; 3098 } 3099 3100 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3101 uint64_t Address, const void *Decoder) { 3102 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3103 Inst.addOperand(MCOperand::CreateImm(Val)); 3104 3105 return MCDisassembler::Success; 3106 } 3107 3108 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3109 uint64_t Address, const void *Decoder) { 3110 DecodeStatus S = MCDisassembler::Success; 3111 3112 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3113 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3114 unsigned imm = fieldFromInstruction(Val, 0, 2); 3115 3116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3117 return MCDisassembler::Fail; 3118 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3119 return MCDisassembler::Fail; 3120 Inst.addOperand(MCOperand::CreateImm(imm)); 3121 3122 return S; 3123 } 3124 3125 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3126 uint64_t Address, const void *Decoder) { 3127 DecodeStatus S = MCDisassembler::Success; 3128 3129 switch (Inst.getOpcode()) { 3130 case ARM::t2PLDs: 3131 case ARM::t2PLDWs: 3132 case ARM::t2PLIs: 3133 break; 3134 default: { 3135 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3136 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 } 3139 } 3140 3141 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3142 if (Rn == 0xF) { 3143 switch (Inst.getOpcode()) { 3144 case ARM::t2LDRBs: 3145 Inst.setOpcode(ARM::t2LDRBpci); 3146 break; 3147 case ARM::t2LDRHs: 3148 Inst.setOpcode(ARM::t2LDRHpci); 3149 break; 3150 case ARM::t2LDRSHs: 3151 Inst.setOpcode(ARM::t2LDRSHpci); 3152 break; 3153 case ARM::t2LDRSBs: 3154 Inst.setOpcode(ARM::t2LDRSBpci); 3155 break; 3156 case ARM::t2PLDs: 3157 Inst.setOpcode(ARM::t2PLDi12); 3158 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3159 break; 3160 default: 3161 return MCDisassembler::Fail; 3162 } 3163 3164 int imm = fieldFromInstruction(Insn, 0, 12); 3165 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3166 Inst.addOperand(MCOperand::CreateImm(imm)); 3167 3168 return S; 3169 } 3170 3171 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3172 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3173 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3174 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3175 return MCDisassembler::Fail; 3176 3177 return S; 3178 } 3179 3180 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder) { 3182 if (Val == 0) 3183 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3184 else { 3185 int imm = Val & 0xFF; 3186 3187 if (!(Val & 0x100)) imm *= -1; 3188 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3189 } 3190 3191 return MCDisassembler::Success; 3192 } 3193 3194 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3195 uint64_t Address, const void *Decoder) { 3196 DecodeStatus S = MCDisassembler::Success; 3197 3198 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3199 unsigned imm = fieldFromInstruction(Val, 0, 9); 3200 3201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3202 return MCDisassembler::Fail; 3203 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3204 return MCDisassembler::Fail; 3205 3206 return S; 3207 } 3208 3209 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3210 uint64_t Address, const void *Decoder) { 3211 DecodeStatus S = MCDisassembler::Success; 3212 3213 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3214 unsigned imm = fieldFromInstruction(Val, 0, 8); 3215 3216 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 3219 Inst.addOperand(MCOperand::CreateImm(imm)); 3220 3221 return S; 3222 } 3223 3224 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3225 uint64_t Address, const void *Decoder) { 3226 int imm = Val & 0xFF; 3227 if (Val == 0) 3228 imm = INT32_MIN; 3229 else if (!(Val & 0x100)) 3230 imm *= -1; 3231 Inst.addOperand(MCOperand::CreateImm(imm)); 3232 3233 return MCDisassembler::Success; 3234 } 3235 3236 3237 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 DecodeStatus S = MCDisassembler::Success; 3240 3241 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3242 unsigned imm = fieldFromInstruction(Val, 0, 9); 3243 3244 // Some instructions always use an additive offset. 3245 switch (Inst.getOpcode()) { 3246 case ARM::t2LDRT: 3247 case ARM::t2LDRBT: 3248 case ARM::t2LDRHT: 3249 case ARM::t2LDRSBT: 3250 case ARM::t2LDRSHT: 3251 case ARM::t2STRT: 3252 case ARM::t2STRBT: 3253 case ARM::t2STRHT: 3254 imm |= 0x100; 3255 break; 3256 default: 3257 break; 3258 } 3259 3260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3263 return MCDisassembler::Fail; 3264 3265 return S; 3266 } 3267 3268 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3269 uint64_t Address, const void *Decoder) { 3270 DecodeStatus S = MCDisassembler::Success; 3271 3272 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3273 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3274 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3275 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3276 addr |= Rn << 9; 3277 unsigned load = fieldFromInstruction(Insn, 20, 1); 3278 3279 if (!load) { 3280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3281 return MCDisassembler::Fail; 3282 } 3283 3284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3285 return MCDisassembler::Fail; 3286 3287 if (load) { 3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3289 return MCDisassembler::Fail; 3290 } 3291 3292 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3293 return MCDisassembler::Fail; 3294 3295 return S; 3296 } 3297 3298 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3299 uint64_t Address, const void *Decoder) { 3300 DecodeStatus S = MCDisassembler::Success; 3301 3302 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3303 unsigned imm = fieldFromInstruction(Val, 0, 12); 3304 3305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 Inst.addOperand(MCOperand::CreateImm(imm)); 3308 3309 return S; 3310 } 3311 3312 3313 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3314 uint64_t Address, const void *Decoder) { 3315 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3316 3317 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3318 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3319 Inst.addOperand(MCOperand::CreateImm(imm)); 3320 3321 return MCDisassembler::Success; 3322 } 3323 3324 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3325 uint64_t Address, const void *Decoder) { 3326 DecodeStatus S = MCDisassembler::Success; 3327 3328 if (Inst.getOpcode() == ARM::tADDrSP) { 3329 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3330 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3331 3332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 } else if (Inst.getOpcode() == ARM::tADDspr) { 3338 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3339 3340 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3341 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 } 3345 3346 return S; 3347 } 3348 3349 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3350 uint64_t Address, const void *Decoder) { 3351 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3352 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3353 3354 Inst.addOperand(MCOperand::CreateImm(imod)); 3355 Inst.addOperand(MCOperand::CreateImm(flags)); 3356 3357 return MCDisassembler::Success; 3358 } 3359 3360 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3361 uint64_t Address, const void *Decoder) { 3362 DecodeStatus S = MCDisassembler::Success; 3363 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3364 unsigned add = fieldFromInstruction(Insn, 4, 1); 3365 3366 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 Inst.addOperand(MCOperand::CreateImm(add)); 3369 3370 return S; 3371 } 3372 3373 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3374 uint64_t Address, const void *Decoder) { 3375 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3376 // Note only one trailing zero not two. Also the J1 and J2 values are from 3377 // the encoded instruction. So here change to I1 and I2 values via: 3378 // I1 = NOT(J1 EOR S); 3379 // I2 = NOT(J2 EOR S); 3380 // and build the imm32 with two trailing zeros as documented: 3381 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3382 unsigned S = (Val >> 23) & 1; 3383 unsigned J1 = (Val >> 22) & 1; 3384 unsigned J2 = (Val >> 21) & 1; 3385 unsigned I1 = !(J1 ^ S); 3386 unsigned I2 = !(J2 ^ S); 3387 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3388 int imm32 = SignExtend32<25>(tmp << 1); 3389 3390 if (!tryAddingSymbolicOperand(Address, 3391 (Address & ~2u) + imm32 + 4, 3392 true, 4, Inst, Decoder)) 3393 Inst.addOperand(MCOperand::CreateImm(imm32)); 3394 return MCDisassembler::Success; 3395 } 3396 3397 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3398 uint64_t Address, const void *Decoder) { 3399 if (Val == 0xA || Val == 0xB) 3400 return MCDisassembler::Fail; 3401 3402 Inst.addOperand(MCOperand::CreateImm(Val)); 3403 return MCDisassembler::Success; 3404 } 3405 3406 static DecodeStatus 3407 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3408 uint64_t Address, const void *Decoder) { 3409 DecodeStatus S = MCDisassembler::Success; 3410 3411 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3412 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3413 3414 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 return S; 3420 } 3421 3422 static DecodeStatus 3423 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3424 uint64_t Address, const void *Decoder) { 3425 DecodeStatus S = MCDisassembler::Success; 3426 3427 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3428 if (pred == 0xE || pred == 0xF) { 3429 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3430 switch (opc) { 3431 default: 3432 return MCDisassembler::Fail; 3433 case 0xf3bf8f4: 3434 Inst.setOpcode(ARM::t2DSB); 3435 break; 3436 case 0xf3bf8f5: 3437 Inst.setOpcode(ARM::t2DMB); 3438 break; 3439 case 0xf3bf8f6: 3440 Inst.setOpcode(ARM::t2ISB); 3441 break; 3442 } 3443 3444 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3445 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3446 } 3447 3448 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3449 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3450 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3451 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3452 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3453 3454 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3457 return MCDisassembler::Fail; 3458 3459 return S; 3460 } 3461 3462 // Decode a shifted immediate operand. These basically consist 3463 // of an 8-bit value, and a 4-bit directive that specifies either 3464 // a splat operation or a rotation. 3465 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3466 uint64_t Address, const void *Decoder) { 3467 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3468 if (ctrl == 0) { 3469 unsigned byte = fieldFromInstruction(Val, 8, 2); 3470 unsigned imm = fieldFromInstruction(Val, 0, 8); 3471 switch (byte) { 3472 case 0: 3473 Inst.addOperand(MCOperand::CreateImm(imm)); 3474 break; 3475 case 1: 3476 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3477 break; 3478 case 2: 3479 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3480 break; 3481 case 3: 3482 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3483 (imm << 8) | imm)); 3484 break; 3485 } 3486 } else { 3487 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3488 unsigned rot = fieldFromInstruction(Val, 7, 5); 3489 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3490 Inst.addOperand(MCOperand::CreateImm(imm)); 3491 } 3492 3493 return MCDisassembler::Success; 3494 } 3495 3496 static DecodeStatus 3497 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3498 uint64_t Address, const void *Decoder){ 3499 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3500 true, 2, Inst, Decoder)) 3501 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3502 return MCDisassembler::Success; 3503 } 3504 3505 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3506 uint64_t Address, const void *Decoder){ 3507 // Val is passed in as S:J1:J2:imm10:imm11 3508 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3509 // the encoded instruction. So here change to I1 and I2 values via: 3510 // I1 = NOT(J1 EOR S); 3511 // I2 = NOT(J2 EOR S); 3512 // and build the imm32 with one trailing zero as documented: 3513 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3514 unsigned S = (Val >> 23) & 1; 3515 unsigned J1 = (Val >> 22) & 1; 3516 unsigned J2 = (Val >> 21) & 1; 3517 unsigned I1 = !(J1 ^ S); 3518 unsigned I2 = !(J2 ^ S); 3519 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3520 int imm32 = SignExtend32<25>(tmp << 1); 3521 3522 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3523 true, 4, Inst, Decoder)) 3524 Inst.addOperand(MCOperand::CreateImm(imm32)); 3525 return MCDisassembler::Success; 3526 } 3527 3528 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3529 uint64_t Address, const void *Decoder) { 3530 if (Val & ~0xf) 3531 return MCDisassembler::Fail; 3532 3533 Inst.addOperand(MCOperand::CreateImm(Val)); 3534 return MCDisassembler::Success; 3535 } 3536 3537 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3538 uint64_t Address, const void *Decoder) { 3539 if (!Val) return MCDisassembler::Fail; 3540 Inst.addOperand(MCOperand::CreateImm(Val)); 3541 return MCDisassembler::Success; 3542 } 3543 3544 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3545 uint64_t Address, const void *Decoder) { 3546 DecodeStatus S = MCDisassembler::Success; 3547 3548 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3549 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3550 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3551 3552 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3553 3554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3555 return MCDisassembler::Fail; 3556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3557 return MCDisassembler::Fail; 3558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 3563 return S; 3564 } 3565 3566 3567 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3568 uint64_t Address, const void *Decoder){ 3569 DecodeStatus S = MCDisassembler::Success; 3570 3571 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3572 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3573 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3574 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3575 3576 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 3579 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3580 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3581 3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3585 return MCDisassembler::Fail; 3586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3587 return MCDisassembler::Fail; 3588 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 3591 return S; 3592 } 3593 3594 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3595 uint64_t Address, const void *Decoder) { 3596 DecodeStatus S = MCDisassembler::Success; 3597 3598 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3599 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3600 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3601 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3602 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3603 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3604 3605 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3606 3607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 3616 return S; 3617 } 3618 3619 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3620 uint64_t Address, const void *Decoder) { 3621 DecodeStatus S = MCDisassembler::Success; 3622 3623 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3625 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3626 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3627 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3628 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3629 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3630 3631 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3632 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3633 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 3643 return S; 3644 } 3645 3646 3647 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3648 uint64_t Address, const void *Decoder) { 3649 DecodeStatus S = MCDisassembler::Success; 3650 3651 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3652 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3653 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3654 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3655 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3656 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3657 3658 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3659 3660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3661 return MCDisassembler::Fail; 3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3663 return MCDisassembler::Fail; 3664 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3665 return MCDisassembler::Fail; 3666 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3667 return MCDisassembler::Fail; 3668 3669 return S; 3670 } 3671 3672 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3673 uint64_t Address, const void *Decoder) { 3674 DecodeStatus S = MCDisassembler::Success; 3675 3676 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3677 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3678 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3679 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3680 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3681 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3682 3683 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3684 3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3688 return MCDisassembler::Fail; 3689 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 3694 return S; 3695 } 3696 3697 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3698 uint64_t Address, const void *Decoder) { 3699 DecodeStatus S = MCDisassembler::Success; 3700 3701 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3702 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3703 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3704 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3705 unsigned size = fieldFromInstruction(Insn, 10, 2); 3706 3707 unsigned align = 0; 3708 unsigned index = 0; 3709 switch (size) { 3710 default: 3711 return MCDisassembler::Fail; 3712 case 0: 3713 if (fieldFromInstruction(Insn, 4, 1)) 3714 return MCDisassembler::Fail; // UNDEFINED 3715 index = fieldFromInstruction(Insn, 5, 3); 3716 break; 3717 case 1: 3718 if (fieldFromInstruction(Insn, 5, 1)) 3719 return MCDisassembler::Fail; // UNDEFINED 3720 index = fieldFromInstruction(Insn, 6, 2); 3721 if (fieldFromInstruction(Insn, 4, 1)) 3722 align = 2; 3723 break; 3724 case 2: 3725 if (fieldFromInstruction(Insn, 6, 1)) 3726 return MCDisassembler::Fail; // UNDEFINED 3727 index = fieldFromInstruction(Insn, 7, 1); 3728 3729 switch (fieldFromInstruction(Insn, 4, 2)) { 3730 case 0 : 3731 align = 0; break; 3732 case 3: 3733 align = 4; break; 3734 default: 3735 return MCDisassembler::Fail; 3736 } 3737 break; 3738 } 3739 3740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3741 return MCDisassembler::Fail; 3742 if (Rm != 0xF) { // Writeback 3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 } 3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3747 return MCDisassembler::Fail; 3748 Inst.addOperand(MCOperand::CreateImm(align)); 3749 if (Rm != 0xF) { 3750 if (Rm != 0xD) { 3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3752 return MCDisassembler::Fail; 3753 } else 3754 Inst.addOperand(MCOperand::CreateReg(0)); 3755 } 3756 3757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 Inst.addOperand(MCOperand::CreateImm(index)); 3760 3761 return S; 3762 } 3763 3764 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3765 uint64_t Address, const void *Decoder) { 3766 DecodeStatus S = MCDisassembler::Success; 3767 3768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3769 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3770 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3771 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3772 unsigned size = fieldFromInstruction(Insn, 10, 2); 3773 3774 unsigned align = 0; 3775 unsigned index = 0; 3776 switch (size) { 3777 default: 3778 return MCDisassembler::Fail; 3779 case 0: 3780 if (fieldFromInstruction(Insn, 4, 1)) 3781 return MCDisassembler::Fail; // UNDEFINED 3782 index = fieldFromInstruction(Insn, 5, 3); 3783 break; 3784 case 1: 3785 if (fieldFromInstruction(Insn, 5, 1)) 3786 return MCDisassembler::Fail; // UNDEFINED 3787 index = fieldFromInstruction(Insn, 6, 2); 3788 if (fieldFromInstruction(Insn, 4, 1)) 3789 align = 2; 3790 break; 3791 case 2: 3792 if (fieldFromInstruction(Insn, 6, 1)) 3793 return MCDisassembler::Fail; // UNDEFINED 3794 index = fieldFromInstruction(Insn, 7, 1); 3795 3796 switch (fieldFromInstruction(Insn, 4, 2)) { 3797 case 0: 3798 align = 0; break; 3799 case 3: 3800 align = 4; break; 3801 default: 3802 return MCDisassembler::Fail; 3803 } 3804 break; 3805 } 3806 3807 if (Rm != 0xF) { // Writeback 3808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 } 3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3812 return MCDisassembler::Fail; 3813 Inst.addOperand(MCOperand::CreateImm(align)); 3814 if (Rm != 0xF) { 3815 if (Rm != 0xD) { 3816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3817 return MCDisassembler::Fail; 3818 } else 3819 Inst.addOperand(MCOperand::CreateReg(0)); 3820 } 3821 3822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3823 return MCDisassembler::Fail; 3824 Inst.addOperand(MCOperand::CreateImm(index)); 3825 3826 return S; 3827 } 3828 3829 3830 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3831 uint64_t Address, const void *Decoder) { 3832 DecodeStatus S = MCDisassembler::Success; 3833 3834 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3835 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3836 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3837 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3838 unsigned size = fieldFromInstruction(Insn, 10, 2); 3839 3840 unsigned align = 0; 3841 unsigned index = 0; 3842 unsigned inc = 1; 3843 switch (size) { 3844 default: 3845 return MCDisassembler::Fail; 3846 case 0: 3847 index = fieldFromInstruction(Insn, 5, 3); 3848 if (fieldFromInstruction(Insn, 4, 1)) 3849 align = 2; 3850 break; 3851 case 1: 3852 index = fieldFromInstruction(Insn, 6, 2); 3853 if (fieldFromInstruction(Insn, 4, 1)) 3854 align = 4; 3855 if (fieldFromInstruction(Insn, 5, 1)) 3856 inc = 2; 3857 break; 3858 case 2: 3859 if (fieldFromInstruction(Insn, 5, 1)) 3860 return MCDisassembler::Fail; // UNDEFINED 3861 index = fieldFromInstruction(Insn, 7, 1); 3862 if (fieldFromInstruction(Insn, 4, 1) != 0) 3863 align = 8; 3864 if (fieldFromInstruction(Insn, 6, 1)) 3865 inc = 2; 3866 break; 3867 } 3868 3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 if (Rm != 0xF) { // Writeback 3874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3875 return MCDisassembler::Fail; 3876 } 3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 Inst.addOperand(MCOperand::CreateImm(align)); 3880 if (Rm != 0xF) { 3881 if (Rm != 0xD) { 3882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3883 return MCDisassembler::Fail; 3884 } else 3885 Inst.addOperand(MCOperand::CreateReg(0)); 3886 } 3887 3888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 Inst.addOperand(MCOperand::CreateImm(index)); 3893 3894 return S; 3895 } 3896 3897 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3898 uint64_t Address, const void *Decoder) { 3899 DecodeStatus S = MCDisassembler::Success; 3900 3901 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3902 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3903 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3904 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3905 unsigned size = fieldFromInstruction(Insn, 10, 2); 3906 3907 unsigned align = 0; 3908 unsigned index = 0; 3909 unsigned inc = 1; 3910 switch (size) { 3911 default: 3912 return MCDisassembler::Fail; 3913 case 0: 3914 index = fieldFromInstruction(Insn, 5, 3); 3915 if (fieldFromInstruction(Insn, 4, 1)) 3916 align = 2; 3917 break; 3918 case 1: 3919 index = fieldFromInstruction(Insn, 6, 2); 3920 if (fieldFromInstruction(Insn, 4, 1)) 3921 align = 4; 3922 if (fieldFromInstruction(Insn, 5, 1)) 3923 inc = 2; 3924 break; 3925 case 2: 3926 if (fieldFromInstruction(Insn, 5, 1)) 3927 return MCDisassembler::Fail; // UNDEFINED 3928 index = fieldFromInstruction(Insn, 7, 1); 3929 if (fieldFromInstruction(Insn, 4, 1) != 0) 3930 align = 8; 3931 if (fieldFromInstruction(Insn, 6, 1)) 3932 inc = 2; 3933 break; 3934 } 3935 3936 if (Rm != 0xF) { // Writeback 3937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3938 return MCDisassembler::Fail; 3939 } 3940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3941 return MCDisassembler::Fail; 3942 Inst.addOperand(MCOperand::CreateImm(align)); 3943 if (Rm != 0xF) { 3944 if (Rm != 0xD) { 3945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3946 return MCDisassembler::Fail; 3947 } else 3948 Inst.addOperand(MCOperand::CreateReg(0)); 3949 } 3950 3951 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3952 return MCDisassembler::Fail; 3953 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 Inst.addOperand(MCOperand::CreateImm(index)); 3956 3957 return S; 3958 } 3959 3960 3961 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3962 uint64_t Address, const void *Decoder) { 3963 DecodeStatus S = MCDisassembler::Success; 3964 3965 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3966 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3967 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3968 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3969 unsigned size = fieldFromInstruction(Insn, 10, 2); 3970 3971 unsigned align = 0; 3972 unsigned index = 0; 3973 unsigned inc = 1; 3974 switch (size) { 3975 default: 3976 return MCDisassembler::Fail; 3977 case 0: 3978 if (fieldFromInstruction(Insn, 4, 1)) 3979 return MCDisassembler::Fail; // UNDEFINED 3980 index = fieldFromInstruction(Insn, 5, 3); 3981 break; 3982 case 1: 3983 if (fieldFromInstruction(Insn, 4, 1)) 3984 return MCDisassembler::Fail; // UNDEFINED 3985 index = fieldFromInstruction(Insn, 6, 2); 3986 if (fieldFromInstruction(Insn, 5, 1)) 3987 inc = 2; 3988 break; 3989 case 2: 3990 if (fieldFromInstruction(Insn, 4, 2)) 3991 return MCDisassembler::Fail; // UNDEFINED 3992 index = fieldFromInstruction(Insn, 7, 1); 3993 if (fieldFromInstruction(Insn, 6, 1)) 3994 inc = 2; 3995 break; 3996 } 3997 3998 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3999 return MCDisassembler::Fail; 4000 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 4005 if (Rm != 0xF) { // Writeback 4006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 } 4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 Inst.addOperand(MCOperand::CreateImm(align)); 4012 if (Rm != 0xF) { 4013 if (Rm != 0xD) { 4014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 } else 4017 Inst.addOperand(MCOperand::CreateReg(0)); 4018 } 4019 4020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 Inst.addOperand(MCOperand::CreateImm(index)); 4027 4028 return S; 4029 } 4030 4031 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4032 uint64_t Address, const void *Decoder) { 4033 DecodeStatus S = MCDisassembler::Success; 4034 4035 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4036 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4037 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4038 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4039 unsigned size = fieldFromInstruction(Insn, 10, 2); 4040 4041 unsigned align = 0; 4042 unsigned index = 0; 4043 unsigned inc = 1; 4044 switch (size) { 4045 default: 4046 return MCDisassembler::Fail; 4047 case 0: 4048 if (fieldFromInstruction(Insn, 4, 1)) 4049 return MCDisassembler::Fail; // UNDEFINED 4050 index = fieldFromInstruction(Insn, 5, 3); 4051 break; 4052 case 1: 4053 if (fieldFromInstruction(Insn, 4, 1)) 4054 return MCDisassembler::Fail; // UNDEFINED 4055 index = fieldFromInstruction(Insn, 6, 2); 4056 if (fieldFromInstruction(Insn, 5, 1)) 4057 inc = 2; 4058 break; 4059 case 2: 4060 if (fieldFromInstruction(Insn, 4, 2)) 4061 return MCDisassembler::Fail; // UNDEFINED 4062 index = fieldFromInstruction(Insn, 7, 1); 4063 if (fieldFromInstruction(Insn, 6, 1)) 4064 inc = 2; 4065 break; 4066 } 4067 4068 if (Rm != 0xF) { // Writeback 4069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4070 return MCDisassembler::Fail; 4071 } 4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4073 return MCDisassembler::Fail; 4074 Inst.addOperand(MCOperand::CreateImm(align)); 4075 if (Rm != 0xF) { 4076 if (Rm != 0xD) { 4077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4078 return MCDisassembler::Fail; 4079 } else 4080 Inst.addOperand(MCOperand::CreateReg(0)); 4081 } 4082 4083 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4084 return MCDisassembler::Fail; 4085 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4088 return MCDisassembler::Fail; 4089 Inst.addOperand(MCOperand::CreateImm(index)); 4090 4091 return S; 4092 } 4093 4094 4095 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4096 uint64_t Address, const void *Decoder) { 4097 DecodeStatus S = MCDisassembler::Success; 4098 4099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4100 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4102 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4103 unsigned size = fieldFromInstruction(Insn, 10, 2); 4104 4105 unsigned align = 0; 4106 unsigned index = 0; 4107 unsigned inc = 1; 4108 switch (size) { 4109 default: 4110 return MCDisassembler::Fail; 4111 case 0: 4112 if (fieldFromInstruction(Insn, 4, 1)) 4113 align = 4; 4114 index = fieldFromInstruction(Insn, 5, 3); 4115 break; 4116 case 1: 4117 if (fieldFromInstruction(Insn, 4, 1)) 4118 align = 8; 4119 index = fieldFromInstruction(Insn, 6, 2); 4120 if (fieldFromInstruction(Insn, 5, 1)) 4121 inc = 2; 4122 break; 4123 case 2: 4124 switch (fieldFromInstruction(Insn, 4, 2)) { 4125 case 0: 4126 align = 0; break; 4127 case 3: 4128 return MCDisassembler::Fail; 4129 default: 4130 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4131 } 4132 4133 index = fieldFromInstruction(Insn, 7, 1); 4134 if (fieldFromInstruction(Insn, 6, 1)) 4135 inc = 2; 4136 break; 4137 } 4138 4139 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4140 return MCDisassembler::Fail; 4141 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4142 return MCDisassembler::Fail; 4143 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 4148 if (Rm != 0xF) { // Writeback 4149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4150 return MCDisassembler::Fail; 4151 } 4152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 Inst.addOperand(MCOperand::CreateImm(align)); 4155 if (Rm != 0xF) { 4156 if (Rm != 0xD) { 4157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4158 return MCDisassembler::Fail; 4159 } else 4160 Inst.addOperand(MCOperand::CreateReg(0)); 4161 } 4162 4163 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4168 return MCDisassembler::Fail; 4169 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 Inst.addOperand(MCOperand::CreateImm(index)); 4172 4173 return S; 4174 } 4175 4176 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4177 uint64_t Address, const void *Decoder) { 4178 DecodeStatus S = MCDisassembler::Success; 4179 4180 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4181 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4182 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4183 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4184 unsigned size = fieldFromInstruction(Insn, 10, 2); 4185 4186 unsigned align = 0; 4187 unsigned index = 0; 4188 unsigned inc = 1; 4189 switch (size) { 4190 default: 4191 return MCDisassembler::Fail; 4192 case 0: 4193 if (fieldFromInstruction(Insn, 4, 1)) 4194 align = 4; 4195 index = fieldFromInstruction(Insn, 5, 3); 4196 break; 4197 case 1: 4198 if (fieldFromInstruction(Insn, 4, 1)) 4199 align = 8; 4200 index = fieldFromInstruction(Insn, 6, 2); 4201 if (fieldFromInstruction(Insn, 5, 1)) 4202 inc = 2; 4203 break; 4204 case 2: 4205 switch (fieldFromInstruction(Insn, 4, 2)) { 4206 case 0: 4207 align = 0; break; 4208 case 3: 4209 return MCDisassembler::Fail; 4210 default: 4211 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4212 } 4213 4214 index = fieldFromInstruction(Insn, 7, 1); 4215 if (fieldFromInstruction(Insn, 6, 1)) 4216 inc = 2; 4217 break; 4218 } 4219 4220 if (Rm != 0xF) { // Writeback 4221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4222 return MCDisassembler::Fail; 4223 } 4224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4225 return MCDisassembler::Fail; 4226 Inst.addOperand(MCOperand::CreateImm(align)); 4227 if (Rm != 0xF) { 4228 if (Rm != 0xD) { 4229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 } else 4232 Inst.addOperand(MCOperand::CreateReg(0)); 4233 } 4234 4235 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4236 return MCDisassembler::Fail; 4237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 Inst.addOperand(MCOperand::CreateImm(index)); 4244 4245 return S; 4246 } 4247 4248 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4249 uint64_t Address, const void *Decoder) { 4250 DecodeStatus S = MCDisassembler::Success; 4251 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4252 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4253 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4254 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4255 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4256 4257 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4258 S = MCDisassembler::SoftFail; 4259 4260 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4261 return MCDisassembler::Fail; 4262 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4267 return MCDisassembler::Fail; 4268 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 4271 return S; 4272 } 4273 4274 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4275 uint64_t Address, const void *Decoder) { 4276 DecodeStatus S = MCDisassembler::Success; 4277 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4278 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4279 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4280 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4281 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4282 4283 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4284 S = MCDisassembler::SoftFail; 4285 4286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 4297 return S; 4298 } 4299 4300 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4301 uint64_t Address, const void *Decoder) { 4302 DecodeStatus S = MCDisassembler::Success; 4303 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4304 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4305 4306 if (pred == 0xF) { 4307 pred = 0xE; 4308 S = MCDisassembler::SoftFail; 4309 } 4310 4311 if (mask == 0x0) { 4312 mask |= 0x8; 4313 S = MCDisassembler::SoftFail; 4314 } 4315 4316 Inst.addOperand(MCOperand::CreateImm(pred)); 4317 Inst.addOperand(MCOperand::CreateImm(mask)); 4318 return S; 4319 } 4320 4321 static DecodeStatus 4322 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4323 uint64_t Address, const void *Decoder) { 4324 DecodeStatus S = MCDisassembler::Success; 4325 4326 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4327 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4328 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4329 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4330 unsigned W = fieldFromInstruction(Insn, 21, 1); 4331 unsigned U = fieldFromInstruction(Insn, 23, 1); 4332 unsigned P = fieldFromInstruction(Insn, 24, 1); 4333 bool writeback = (W == 1) | (P == 0); 4334 4335 addr |= (U << 8) | (Rn << 9); 4336 4337 if (writeback && (Rn == Rt || Rn == Rt2)) 4338 Check(S, MCDisassembler::SoftFail); 4339 if (Rt == Rt2) 4340 Check(S, MCDisassembler::SoftFail); 4341 4342 // Rt 4343 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4344 return MCDisassembler::Fail; 4345 // Rt2 4346 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4347 return MCDisassembler::Fail; 4348 // Writeback operand 4349 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 // addr 4352 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4353 return MCDisassembler::Fail; 4354 4355 return S; 4356 } 4357 4358 static DecodeStatus 4359 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4360 uint64_t Address, const void *Decoder) { 4361 DecodeStatus S = MCDisassembler::Success; 4362 4363 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4364 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4365 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4366 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4367 unsigned W = fieldFromInstruction(Insn, 21, 1); 4368 unsigned U = fieldFromInstruction(Insn, 23, 1); 4369 unsigned P = fieldFromInstruction(Insn, 24, 1); 4370 bool writeback = (W == 1) | (P == 0); 4371 4372 addr |= (U << 8) | (Rn << 9); 4373 4374 if (writeback && (Rn == Rt || Rn == Rt2)) 4375 Check(S, MCDisassembler::SoftFail); 4376 4377 // Writeback operand 4378 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4379 return MCDisassembler::Fail; 4380 // Rt 4381 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4382 return MCDisassembler::Fail; 4383 // Rt2 4384 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 // addr 4387 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4388 return MCDisassembler::Fail; 4389 4390 return S; 4391 } 4392 4393 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4394 uint64_t Address, const void *Decoder) { 4395 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4396 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4397 if (sign1 != sign2) return MCDisassembler::Fail; 4398 4399 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4400 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4401 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4402 Val |= sign1 << 12; 4403 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4404 4405 return MCDisassembler::Success; 4406 } 4407 4408 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4409 uint64_t Address, 4410 const void *Decoder) { 4411 DecodeStatus S = MCDisassembler::Success; 4412 4413 // Shift of "asr #32" is not allowed in Thumb2 mode. 4414 if (Val == 0x20) S = MCDisassembler::SoftFail; 4415 Inst.addOperand(MCOperand::CreateImm(Val)); 4416 return S; 4417 } 4418 4419 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4420 uint64_t Address, const void *Decoder) { 4421 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4422 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4423 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4424 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4425 4426 if (pred == 0xF) 4427 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4428 4429 DecodeStatus S = MCDisassembler::Success; 4430 4431 if (Rt == Rn || Rn == Rt2) 4432 S = MCDisassembler::SoftFail; 4433 4434 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4435 return MCDisassembler::Fail; 4436 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4437 return MCDisassembler::Fail; 4438 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4439 return MCDisassembler::Fail; 4440 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 4443 return S; 4444 } 4445 4446 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4447 uint64_t Address, const void *Decoder) { 4448 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4449 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4450 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4451 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4452 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4453 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4454 4455 DecodeStatus S = MCDisassembler::Success; 4456 4457 // VMOVv2f32 is ambiguous with these decodings. 4458 if (!(imm & 0x38) && cmode == 0xF) { 4459 Inst.setOpcode(ARM::VMOVv2f32); 4460 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4461 } 4462 4463 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4464 4465 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4466 return MCDisassembler::Fail; 4467 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4468 return MCDisassembler::Fail; 4469 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4470 4471 return S; 4472 } 4473 4474 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4475 uint64_t Address, const void *Decoder) { 4476 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4477 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4478 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4479 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4480 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4481 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4482 4483 DecodeStatus S = MCDisassembler::Success; 4484 4485 // VMOVv4f32 is ambiguous with these decodings. 4486 if (!(imm & 0x38) && cmode == 0xF) { 4487 Inst.setOpcode(ARM::VMOVv4f32); 4488 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4489 } 4490 4491 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4492 4493 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4494 return MCDisassembler::Fail; 4495 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4496 return MCDisassembler::Fail; 4497 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4498 4499 return S; 4500 } 4501 4502 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4503 const void *Decoder) 4504 { 4505 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4506 if (Imm > 4) return MCDisassembler::Fail; 4507 Inst.addOperand(MCOperand::CreateImm(Imm)); 4508 return MCDisassembler::Success; 4509 } 4510 4511 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4512 uint64_t Address, const void *Decoder) { 4513 DecodeStatus S = MCDisassembler::Success; 4514 4515 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4516 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4517 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4518 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4519 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4520 4521 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4522 S = MCDisassembler::SoftFail; 4523 4524 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4525 return MCDisassembler::Fail; 4526 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4533 return MCDisassembler::Fail; 4534 4535 return S; 4536 } 4537 4538 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4539 uint64_t Address, const void *Decoder) { 4540 4541 DecodeStatus S = MCDisassembler::Success; 4542 4543 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4544 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4545 unsigned cop = fieldFromInstruction(Val, 8, 4); 4546 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4547 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4548 4549 if ((cop & ~0x1) == 0xa) 4550 return MCDisassembler::Fail; 4551 4552 if (Rt == Rt2) 4553 S = MCDisassembler::SoftFail; 4554 4555 Inst.addOperand(MCOperand::CreateImm(cop)); 4556 Inst.addOperand(MCOperand::CreateImm(opc1)); 4557 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 Inst.addOperand(MCOperand::CreateImm(CRm)); 4562 4563 return S; 4564 } 4565 4566