[ARM GlobalISel] Widen G_GEP index operand

llvm-svn: 360127

[ARM GlobalISel] Legalize extensions to < 32 bits

Make it legal to extend from e.g. s1 to s8 or s16.

llvm-svn: 359766

[ARM GlobalISel] Widen small shift operands

The legalizer was already widening the shift amount. Add tests for that
behaviour, and also support widening the shifted value.

llvm-svn: 359542

[ARM GlobalISel] 64-bit memops should be aligned

We currently use only VLDR/VSTR for all 64-bit loads/stores, so the
memory operands must be word-aligned. Mark aligned operations as legal
and narrow

[ARM GlobalISel] 64-bit memops should be aligned

We currently use only VLDR/VSTR for all 64-bit loads/stores, so the
memory operands must be word-aligned. Mark aligned operations as legal
and narrow non-aligned ones to 32 bits.

While we're here, also mark non-power-of-2 loads/stores as unsupported.

llvm-svn: 356872

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[ARM GlobalISel] Support G_CTLZ for Thumb2

Same as ARM mode but with different opcode.

llvm-svn: 355191

[ARM GlobalISel] Support global variables for Thumb2

Add the same level of support as for ARM mode (i.e. still no TLS
support).

In most cases, it is sufficient to replace the opcodes with the
t2-eq

[ARM GlobalISel] Support global variables for Thumb2

Add the same level of support as for ARM mode (i.e. still no TLS
support).

In most cases, it is sufficient to replace the opcodes with the
t2-equivalent, but there are some idiosyncrasies that I decided to
preserve because I don't understand the full implications:
* For ARM we use LDRi12 to load from constant pools, but for Thumb we
use t2LDRpci (I'm not sure if the ideal would be to use t2LDRi12 for
Thumb as well, or to use LDRcp for ARM).
* For Thumb we don't have an equivalent for MOV|LDRLIT_ga_pcrel_ldr, so
we have to generate MOV|LDRLIT_ga_pcrel plus a load from GOT.

The tests are in separate files because they're hard enough to read even
without doubling the number of checks.

llvm-svn: 355077

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[ARM GlobalISel] Support floating point for Thumb2

This is exactly the same as arm mode, so for the instruction selector
tests we just extract them to a new file and run with the same checks
for bot

[ARM GlobalISel] Support floating point for Thumb2

This is exactly the same as arm mode, so for the instruction selector
tests we just extract them to a new file and run with the same checks
for both arm and thumb mode.

For the legalizer we need to update the tests for soft float a bit, but
only because BL and tBL are slightly different. We could be pedantic and
check that we get a well-formed BL for arm mode and a tBL for thumb, but
for the purposes of the legalizer test it's sufficient to just skip over
the predicate operands in the checks. Also note that we have the
pedantic checks in the divmod test, so we're covered.

llvm-svn: 354665

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[ARM GlobalISel] Support G_FRAME_INDEX for Thumb2

Same as arm mode.

llvm-svn: 354579

[ARM GlobalISel] Support G_PHI for Thumb2

Same as arm mode.

llvm-svn: 354310

[ARM GlobalISel] Support branches for Thumb2

Just like arm mode, but with different opcodes.

llvm-svn: 354113

GlobalISel: Add alignment to LegalityQuery MMOs

This allows targets to specify the minimum alignment required for the
load/store.

llvm-svn: 354071

[ARM GlobalISel] Support G_SELECT for Thumb2

Same as arm mode, but slightly different opcodes.

llvm-svn: 353938

[ARM GlobalISel] Support G_ICMP for Thumb2

Mark as legal and use the t2* equivalents of the arm mode instructions,
e.g. t2CMPrr instead of plain CMPrr.

llvm-svn: 353392

[ARM GlobalISel] Support G_GEP for Thumb2

Same as ARM, but use a different opcode in the instruction selection.

llvm-svn: 353151

GlobalISel: Allow bitcount ops to have different result type

For AMDGPU the result is always 32-bit for 64-bit inputs.

llvm-svn: 352717

[ARM GlobalISel] Support integer division for Thumb2

Support G_SDIV, G_UDIV, G_SREM and G_UREM.

The only significant difference between arm and thumb mode is that we
need to check a different subta

[ARM GlobalISel] Support integer division for Thumb2

Support G_SDIV, G_UDIV, G_SREM and G_UREM.

The only significant difference between arm and thumb mode is that we
need to check a different subtarget feature.

llvm-svn: 352346

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[ARM GlobalISel] Support shifts for Thumb2

Same as ARM.

On this occasion we split some of the instruction select tests for more
complicated instructions into their own files, so we can reuse them f

[ARM GlobalISel] Support shifts for Thumb2

Same as ARM.

On this occasion we split some of the instruction select tests for more
complicated instructions into their own files, so we can reuse them for
ARM and Thumb mode. Likewise for the legalizer tests.

llvm-svn: 352188

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[ARM GlobalISel] Remove rebase artifact from r351882. NFC

r351882 introduced some superfluous calls to mark G_INTTOPTR and
G_PTRTOINT as legal (looks like a rebase mishap). Remove them.

llvm-svn: 3

[ARM GlobalISel] Remove rebase artifact from r351882. NFC

r351882 introduced some superfluous calls to mark G_INTTOPTR and
G_PTRTOINT as legal (looks like a rebase mishap). Remove them.

llvm-svn: 352187

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GlobalISel: Allow shift amount to be a different type

For AMDGPU the shift amount is never 64-bit, and
this needs to use a 32-bit shift.

X86 uses i8, but seemed to be hacking around this before.

l

GlobalISel: Allow shift amount to be a different type

For AMDGPU the shift amount is never 64-bit, and
this needs to use a 32-bit shift.

X86 uses i8, but seemed to be hacking around this before.

llvm-svn: 351882

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[ARM GlobalISel] Support G_CONSTANT for Thumb2

All we have to do is mark it as legal.

This allows us to select a lot of new patterns handled by TableGen. This
patch adds tests for them and splits u

[ARM GlobalISel] Support G_CONSTANT for Thumb2

All we have to do is mark it as legal.

This allows us to select a lot of new patterns handled by TableGen. This
patch adds tests for them and splits up the existing test file for
binary operators into 2 files, one for arithmetic ops and one for
logical ones.

llvm-svn: 349610

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[ARM GlobalISel] Thumb2: casts between int and ptr

Mark as legal and add tests. Nothing special to do.

llvm-svn: 349147

[ARM GlobalISel] Allow simple binary ops in Thumb2

Mark G_ADD, G_SUB, G_MUL, G_AND, G_OR and G_XOR as legal for both ARM
and Thumb2.

Extract the legalizer tests for these opcodes into another file.

[ARM GlobalISel] Allow simple binary ops in Thumb2

Mark G_ADD, G_SUB, G_MUL, G_AND, G_OR and G_XOR as legal for both ARM
and Thumb2.

Extract the legalizer tests for these opcodes into another file.

Add tests for the instruction selector.

llvm-svn: 349142

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[ARM GlobalISel] Support exts and truncs for Thumb2

Mark G_SEXT, G_ZEXT and G_ANYEXT to 32 bits as legal and add support for
them in the instruction selector. This uses handwritten code again
becaus

[ARM GlobalISel] Support exts and truncs for Thumb2

Mark G_SEXT, G_ZEXT and G_ANYEXT to 32 bits as legal and add support for
them in the instruction selector. This uses handwritten code again
because the patterns that are generated with TableGen are tuned for what
the DAG combiner would produce and not for simple sext/zext nodes.
Luckily, we only need to update the opcodes to use the Thumb2 variants,
everything else can be reused from ARM.

llvm-svn: 349026

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[ARM GlobalISel] Select load/store for Thumb2

Unfortunately we can't use TableGen for this because it doesn't yet
support predicates on the source pattern root. Therefore, add a bit of
handwritten c

[ARM GlobalISel] Select load/store for Thumb2

Unfortunately we can't use TableGen for this because it doesn't yet
support predicates on the source pattern root. Therefore, add a bit of
handwritten code to the instruction selector to handle the most basic
cases.

Also mark them as legal and extract their legalizer test cases to a new
test file.

llvm-svn: 348920

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