1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void 37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, 38 const LegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, Unsupported}); 44 } 45 } 46 47 static LegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported}, 52 {8, WidenScalar}, 53 {9, Unsupported}, 54 {16, WidenScalar}, 55 {17, Unsupported}}; 56 addAndInterleaveWithUnsupported(result, v); 57 auto Largest = result.back().first; 58 result.push_back({Largest + 1, Unsupported}); 59 return result; 60 } 61 62 static bool AEABI(const ARMSubtarget &ST) { 63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 64 } 65 66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 67 using namespace TargetOpcode; 68 69 const LLT p0 = LLT::pointer(0, 32); 70 71 const LLT s1 = LLT::scalar(1); 72 const LLT s8 = LLT::scalar(8); 73 const LLT s16 = LLT::scalar(16); 74 const LLT s32 = LLT::scalar(32); 75 const LLT s64 = LLT::scalar(64); 76 77 if (ST.isThumb1Only()) { 78 // Thumb1 is not supported yet. 79 computeTables(); 80 verify(*ST.getInstrInfo()); 81 return; 82 } 83 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 85 .legalForCartesianProduct({s32}, {s1, s8, s16}); 86 87 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) 88 .legalFor({s32}) 89 .minScalar(0, s32); 90 91 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 92 .legalFor({{s32, s32}}) 93 .clampScalar(1, s32, s32); 94 95 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 96 (ST.isThumb() && ST.hasDivideInThumbMode()); 97 if (HasHWDivide) 98 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 99 .legalFor({s32}) 100 .clampScalar(0, s32, s32); 101 else 102 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 103 .libcallFor({s32}) 104 .clampScalar(0, s32, s32); 105 106 for (unsigned Op : {G_SREM, G_UREM}) { 107 setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 108 if (HasHWDivide) 109 setAction({Op, s32}, Lower); 110 else if (AEABI(ST)) 111 setAction({Op, s32}, Custom); 112 else 113 setAction({Op, s32}, Libcall); 114 } 115 116 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); 117 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); 118 119 getActionDefinitionsBuilder(G_CONSTANT) 120 .legalFor({s32, p0}) 121 .clampScalar(0, s32, s32); 122 123 getActionDefinitionsBuilder(G_ICMP) 124 .legalForCartesianProduct({s1}, {s32, p0}) 125 .minScalar(1, s32); 126 127 getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0}, 128 {s1}); 129 130 // We're keeping these builders around because we'll want to add support for 131 // floating point to them. 132 auto &LoadStoreBuilder = 133 getActionDefinitionsBuilder({G_LOAD, G_STORE}) 134 .legalForTypesWithMemDesc({ 135 {s1, p0, 8, 8}, 136 {s8, p0, 8, 8}, 137 {s16, p0, 16, 8}, 138 {s32, p0, 32, 8}, 139 {p0, p0, 32, 8}}); 140 141 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 142 143 auto &PhiBuilder = 144 getActionDefinitionsBuilder(G_PHI) 145 .legalFor({s32, p0}) 146 .minScalar(0, s32); 147 148 getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}}); 149 150 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 151 152 if (ST.isThumb()) { 153 // FIXME: merge with the code for non-Thumb. 154 computeTables(); 155 verify(*ST.getInstrInfo()); 156 return; 157 } 158 159 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 160 161 if (ST.hasV5TOps()) { 162 getActionDefinitionsBuilder(G_CTLZ) 163 .legalFor({s32, s32}) 164 .clampScalar(1, s32, s32) 165 .clampScalar(0, s32, s32); 166 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 167 .lowerFor({s32, s32}) 168 .clampScalar(1, s32, s32) 169 .clampScalar(0, s32, s32); 170 } else { 171 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 172 .libcallFor({s32, s32}) 173 .clampScalar(1, s32, s32) 174 .clampScalar(0, s32, s32); 175 getActionDefinitionsBuilder(G_CTLZ) 176 .lowerFor({s32, s32}) 177 .clampScalar(1, s32, s32) 178 .clampScalar(0, s32, s32); 179 } 180 181 if (!ST.useSoftFloat() && ST.hasVFP2()) { 182 getActionDefinitionsBuilder( 183 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 184 .legalFor({s32, s64}); 185 186 LoadStoreBuilder.legalFor({{s64, p0}}); 187 PhiBuilder.legalFor({s64}); 188 189 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 190 {s32, s64}); 191 192 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 193 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 194 195 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 196 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 197 198 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 199 .legalForCartesianProduct({s32}, {s32, s64}); 200 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 201 .legalForCartesianProduct({s32, s64}, {s32}); 202 } else { 203 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 204 .libcallFor({s32, s64}); 205 206 LoadStoreBuilder.maxScalar(0, s32); 207 208 for (auto Ty : {s32, s64}) 209 setAction({G_FNEG, Ty}, Lower); 210 211 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 212 213 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 214 {s32, s64}); 215 216 if (AEABI(ST)) 217 setFCmpLibcallsAEABI(); 218 else 219 setFCmpLibcallsGNU(); 220 221 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 222 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 223 224 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 225 .libcallForCartesianProduct({s32}, {s32, s64}); 226 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 227 .libcallForCartesianProduct({s32, s64}, {s32}); 228 } 229 230 if (!ST.useSoftFloat() && ST.hasVFP4()) 231 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 232 else 233 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 234 235 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 236 237 computeTables(); 238 verify(*ST.getInstrInfo()); 239 } 240 241 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 242 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 243 // default-initialized. 244 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 245 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 246 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 247 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 248 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 249 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 250 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 251 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 252 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 253 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 254 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 255 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 256 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 257 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 258 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 259 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 260 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 261 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 262 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 263 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 264 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 265 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 266 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 267 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 268 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 269 270 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 271 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 272 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 273 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 274 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 275 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 276 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 277 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 278 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 279 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 280 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 281 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 282 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 283 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 284 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 285 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 286 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 287 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 288 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 289 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 290 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 291 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 292 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 293 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 294 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 295 } 296 297 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 298 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 299 // default-initialized. 300 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 301 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 302 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 303 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 304 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 305 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 306 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 307 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 308 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 309 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 310 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 311 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 312 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 313 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 314 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 315 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 316 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 317 318 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 319 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 320 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 321 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 322 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 323 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 324 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 325 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 326 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 327 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 328 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 329 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 330 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 331 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 332 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 333 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 334 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 335 } 336 337 ARMLegalizerInfo::FCmpLibcallsList 338 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 339 unsigned Size) const { 340 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 341 if (Size == 32) 342 return FCmp32Libcalls[Predicate]; 343 if (Size == 64) 344 return FCmp64Libcalls[Predicate]; 345 llvm_unreachable("Unsupported size for FCmp predicate"); 346 } 347 348 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 349 MachineRegisterInfo &MRI, 350 MachineIRBuilder &MIRBuilder, 351 GISelChangeObserver &Observer) const { 352 using namespace TargetOpcode; 353 354 MIRBuilder.setInstr(MI); 355 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 356 357 switch (MI.getOpcode()) { 358 default: 359 return false; 360 case G_SREM: 361 case G_UREM: { 362 unsigned OriginalResult = MI.getOperand(0).getReg(); 363 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 364 if (Size != 32) 365 return false; 366 367 auto Libcall = 368 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 369 370 // Our divmod libcalls return a struct containing the quotient and the 371 // remainder. We need to create a virtual register for it. 372 Type *ArgTy = Type::getInt32Ty(Ctx); 373 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 374 auto RetVal = MRI.createGenericVirtualRegister( 375 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 376 377 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 378 {{MI.getOperand(1).getReg(), ArgTy}, 379 {MI.getOperand(2).getReg(), ArgTy}}); 380 if (Status != LegalizerHelper::Legalized) 381 return false; 382 383 // The remainder is the second result of divmod. Split the return value into 384 // a new, unused register for the quotient and the destination of the 385 // original instruction for the remainder. 386 MIRBuilder.buildUnmerge( 387 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 388 RetVal); 389 break; 390 } 391 case G_FCMP: { 392 assert(MRI.getType(MI.getOperand(2).getReg()) == 393 MRI.getType(MI.getOperand(3).getReg()) && 394 "Mismatched operands for G_FCMP"); 395 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 396 397 auto OriginalResult = MI.getOperand(0).getReg(); 398 auto Predicate = 399 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 400 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 401 402 if (Libcalls.empty()) { 403 assert((Predicate == CmpInst::FCMP_TRUE || 404 Predicate == CmpInst::FCMP_FALSE) && 405 "Predicate needs libcalls, but none specified"); 406 MIRBuilder.buildConstant(OriginalResult, 407 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 408 MI.eraseFromParent(); 409 return true; 410 } 411 412 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 413 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 414 auto *RetTy = Type::getInt32Ty(Ctx); 415 416 SmallVector<unsigned, 2> Results; 417 for (auto Libcall : Libcalls) { 418 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 419 auto Status = 420 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 421 {{MI.getOperand(2).getReg(), ArgTy}, 422 {MI.getOperand(3).getReg(), ArgTy}}); 423 424 if (Status != LegalizerHelper::Legalized) 425 return false; 426 427 auto ProcessedResult = 428 Libcalls.size() == 1 429 ? OriginalResult 430 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 431 432 // We have a result, but we need to transform it into a proper 1-bit 0 or 433 // 1, taking into account the different peculiarities of the values 434 // returned by the comparison functions. 435 CmpInst::Predicate ResultPred = Libcall.Predicate; 436 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 437 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 438 // to keep the types consistent. 439 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 440 } else { 441 // We need to compare against 0. 442 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 443 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 444 MIRBuilder.buildConstant(Zero, 0); 445 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 446 } 447 Results.push_back(ProcessedResult); 448 } 449 450 if (Results.size() != 1) { 451 assert(Results.size() == 2 && "Unexpected number of results"); 452 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 453 } 454 break; 455 } 456 case G_FCONSTANT: { 457 // Convert to integer constants, while preserving the binary representation. 458 auto AsInteger = 459 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 460 MIRBuilder.buildConstant(MI.getOperand(0).getReg(), 461 *ConstantInt::get(Ctx, AsInteger)); 462 break; 463 } 464 } 465 466 MI.eraseFromParent(); 467 return true; 468 } 469