1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void 37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, 38 const LegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, Unsupported}); 44 } 45 } 46 47 static LegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported}, 52 {8, WidenScalar}, 53 {9, Unsupported}, 54 {16, WidenScalar}, 55 {17, Unsupported}}; 56 addAndInterleaveWithUnsupported(result, v); 57 auto Largest = result.back().first; 58 result.push_back({Largest + 1, Unsupported}); 59 return result; 60 } 61 62 static bool AEABI(const ARMSubtarget &ST) { 63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 64 } 65 66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 67 using namespace TargetOpcode; 68 69 const LLT p0 = LLT::pointer(0, 32); 70 71 const LLT s1 = LLT::scalar(1); 72 const LLT s8 = LLT::scalar(8); 73 const LLT s16 = LLT::scalar(16); 74 const LLT s32 = LLT::scalar(32); 75 const LLT s64 = LLT::scalar(64); 76 77 if (ST.isThumb1Only()) { 78 // Thumb1 is not supported yet. 79 computeTables(); 80 verify(*ST.getInstrInfo()); 81 return; 82 } 83 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 85 .legalForCartesianProduct({s32}, {s1, s8, s16}); 86 87 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) 88 .legalFor({s32}) 89 .minScalar(0, s32); 90 91 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); 92 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); 93 94 getActionDefinitionsBuilder(G_CONSTANT) 95 .legalFor({s32, p0}) 96 .clampScalar(0, s32, s32); 97 98 // We're keeping these builders around because we'll want to add support for 99 // floating point to them. 100 auto &LoadStoreBuilder = 101 getActionDefinitionsBuilder({G_LOAD, G_STORE}) 102 .legalForTypesWithMemSize({ 103 {s1, p0, 8}, 104 {s8, p0, 8}, 105 {s16, p0, 16}, 106 {s32, p0, 32}, 107 {p0, p0, 32}}); 108 109 if (ST.isThumb()) { 110 // FIXME: merge with the code for non-Thumb. 111 computeTables(); 112 verify(*ST.getInstrInfo()); 113 return; 114 } 115 116 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 117 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 118 119 if (ST.hasDivideInARMMode()) 120 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 121 .legalFor({s32}) 122 .clampScalar(0, s32, s32); 123 else 124 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 125 .libcallFor({s32}) 126 .clampScalar(0, s32, s32); 127 128 for (unsigned Op : {G_SREM, G_UREM}) { 129 setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 130 if (ST.hasDivideInARMMode()) 131 setAction({Op, s32}, Lower); 132 else if (AEABI(ST)) 133 setAction({Op, s32}, Custom); 134 else 135 setAction({Op, s32}, Libcall); 136 } 137 138 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); 139 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); 140 141 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 142 .legalFor({{s32, s32}}) 143 .clampScalar(1, s32, s32); 144 145 if (ST.hasV5TOps()) { 146 getActionDefinitionsBuilder(G_CTLZ) 147 .legalFor({s32}) 148 .clampScalar(0, s32, s32); 149 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 150 .lowerFor({s32}) 151 .clampScalar(0, s32, s32); 152 } else { 153 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 154 .libcallFor({s32}) 155 .clampScalar(0, s32, s32); 156 getActionDefinitionsBuilder(G_CTLZ) 157 .lowerFor({s32}) 158 .clampScalar(0, s32, s32); 159 } 160 161 getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}}); 162 163 getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0}, 164 {s1}); 165 166 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 167 168 getActionDefinitionsBuilder(G_ICMP) 169 .legalForCartesianProduct({s1}, {s32, p0}) 170 .minScalar(1, s32); 171 172 // We're keeping these builders around because we'll want to add support for 173 // floating point to them. 174 auto &PhiBuilder = 175 getActionDefinitionsBuilder(G_PHI).legalFor({s32, p0}).minScalar(0, s32); 176 177 if (!ST.useSoftFloat() && ST.hasVFP2()) { 178 getActionDefinitionsBuilder( 179 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 180 .legalFor({s32, s64}); 181 182 LoadStoreBuilder.legalFor({{s64, p0}}); 183 PhiBuilder.legalFor({s64}); 184 185 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 186 {s32, s64}); 187 188 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 189 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 190 191 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 192 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 193 194 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 195 .legalForCartesianProduct({s32}, {s32, s64}); 196 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 197 .legalForCartesianProduct({s32, s64}, {s32}); 198 } else { 199 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 200 .libcallFor({s32, s64}); 201 202 LoadStoreBuilder.maxScalar(0, s32); 203 204 for (auto Ty : {s32, s64}) 205 setAction({G_FNEG, Ty}, Lower); 206 207 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 208 209 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 210 {s32, s64}); 211 212 if (AEABI(ST)) 213 setFCmpLibcallsAEABI(); 214 else 215 setFCmpLibcallsGNU(); 216 217 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 218 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 219 220 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 221 .libcallForCartesianProduct({s32}, {s32, s64}); 222 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 223 .libcallForCartesianProduct({s32, s64}, {s32}); 224 } 225 226 if (!ST.useSoftFloat() && ST.hasVFP4()) 227 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 228 else 229 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 230 231 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 232 233 computeTables(); 234 verify(*ST.getInstrInfo()); 235 } 236 237 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 238 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 239 // default-initialized. 240 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 241 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 242 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 243 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 244 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 245 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 246 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 247 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 248 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 249 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 250 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 251 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 252 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 253 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 254 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 255 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 256 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 257 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 258 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 259 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 260 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 261 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 262 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 263 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 264 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 265 266 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 267 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 268 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 269 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 270 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 271 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 272 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 273 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 274 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 275 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 276 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 277 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 278 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 279 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 280 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 281 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 282 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 283 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 284 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 285 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 286 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 287 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 288 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 289 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 290 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 291 } 292 293 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 294 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 295 // default-initialized. 296 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 297 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 298 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 299 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 300 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 301 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 302 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 303 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 304 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 305 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 306 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 307 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 308 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 309 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 310 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 311 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 312 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 313 314 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 315 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 316 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 317 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 318 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 319 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 320 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 321 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 322 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 323 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 324 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 325 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 326 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 327 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 328 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 329 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 330 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 331 } 332 333 ARMLegalizerInfo::FCmpLibcallsList 334 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 335 unsigned Size) const { 336 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 337 if (Size == 32) 338 return FCmp32Libcalls[Predicate]; 339 if (Size == 64) 340 return FCmp64Libcalls[Predicate]; 341 llvm_unreachable("Unsupported size for FCmp predicate"); 342 } 343 344 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 345 MachineRegisterInfo &MRI, 346 MachineIRBuilder &MIRBuilder, 347 GISelChangeObserver &Observer) const { 348 using namespace TargetOpcode; 349 350 MIRBuilder.setInstr(MI); 351 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 352 353 switch (MI.getOpcode()) { 354 default: 355 return false; 356 case G_SREM: 357 case G_UREM: { 358 unsigned OriginalResult = MI.getOperand(0).getReg(); 359 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 360 if (Size != 32) 361 return false; 362 363 auto Libcall = 364 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 365 366 // Our divmod libcalls return a struct containing the quotient and the 367 // remainder. We need to create a virtual register for it. 368 Type *ArgTy = Type::getInt32Ty(Ctx); 369 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 370 auto RetVal = MRI.createGenericVirtualRegister( 371 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 372 373 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 374 {{MI.getOperand(1).getReg(), ArgTy}, 375 {MI.getOperand(2).getReg(), ArgTy}}); 376 if (Status != LegalizerHelper::Legalized) 377 return false; 378 379 // The remainder is the second result of divmod. Split the return value into 380 // a new, unused register for the quotient and the destination of the 381 // original instruction for the remainder. 382 MIRBuilder.buildUnmerge( 383 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 384 RetVal); 385 break; 386 } 387 case G_FCMP: { 388 assert(MRI.getType(MI.getOperand(2).getReg()) == 389 MRI.getType(MI.getOperand(3).getReg()) && 390 "Mismatched operands for G_FCMP"); 391 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 392 393 auto OriginalResult = MI.getOperand(0).getReg(); 394 auto Predicate = 395 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 396 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 397 398 if (Libcalls.empty()) { 399 assert((Predicate == CmpInst::FCMP_TRUE || 400 Predicate == CmpInst::FCMP_FALSE) && 401 "Predicate needs libcalls, but none specified"); 402 MIRBuilder.buildConstant(OriginalResult, 403 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 404 MI.eraseFromParent(); 405 return true; 406 } 407 408 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 409 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 410 auto *RetTy = Type::getInt32Ty(Ctx); 411 412 SmallVector<unsigned, 2> Results; 413 for (auto Libcall : Libcalls) { 414 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 415 auto Status = 416 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 417 {{MI.getOperand(2).getReg(), ArgTy}, 418 {MI.getOperand(3).getReg(), ArgTy}}); 419 420 if (Status != LegalizerHelper::Legalized) 421 return false; 422 423 auto ProcessedResult = 424 Libcalls.size() == 1 425 ? OriginalResult 426 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 427 428 // We have a result, but we need to transform it into a proper 1-bit 0 or 429 // 1, taking into account the different peculiarities of the values 430 // returned by the comparison functions. 431 CmpInst::Predicate ResultPred = Libcall.Predicate; 432 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 433 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 434 // to keep the types consistent. 435 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 436 } else { 437 // We need to compare against 0. 438 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 439 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 440 MIRBuilder.buildConstant(Zero, 0); 441 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 442 } 443 Results.push_back(ProcessedResult); 444 } 445 446 if (Results.size() != 1) { 447 assert(Results.size() == 2 && "Unexpected number of results"); 448 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 449 } 450 break; 451 } 452 case G_FCONSTANT: { 453 // Convert to integer constants, while preserving the binary representation. 454 auto AsInteger = 455 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 456 MIRBuilder.buildConstant(MI.getOperand(0).getReg(), 457 *ConstantInt::get(Ctx, AsInteger)); 458 break; 459 } 460 } 461 462 MI.eraseFromParent(); 463 return true; 464 } 465