1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void 37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, 38 const LegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, Unsupported}); 44 } 45 } 46 47 static LegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported}, 52 {8, WidenScalar}, 53 {9, Unsupported}, 54 {16, WidenScalar}, 55 {17, Unsupported}}; 56 addAndInterleaveWithUnsupported(result, v); 57 auto Largest = result.back().first; 58 result.push_back({Largest + 1, Unsupported}); 59 return result; 60 } 61 62 static bool AEABI(const ARMSubtarget &ST) { 63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 64 } 65 66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 67 using namespace TargetOpcode; 68 69 const LLT p0 = LLT::pointer(0, 32); 70 71 const LLT s1 = LLT::scalar(1); 72 const LLT s8 = LLT::scalar(8); 73 const LLT s16 = LLT::scalar(16); 74 const LLT s32 = LLT::scalar(32); 75 const LLT s64 = LLT::scalar(64); 76 77 if (ST.isThumb1Only()) { 78 // Thumb1 is not supported yet. 79 computeTables(); 80 verify(*ST.getInstrInfo()); 81 return; 82 } 83 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 85 .legalForCartesianProduct({s32}, {s1, s8, s16}); 86 87 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) 88 .legalFor({s32}) 89 .minScalar(0, s32); 90 91 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 92 .legalFor({{s32, s32}}) 93 .clampScalar(1, s32, s32); 94 95 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) || 96 (ST.isThumb() && ST.hasDivideInThumbMode()); 97 if (HasHWDivide) 98 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 99 .legalFor({s32}) 100 .clampScalar(0, s32, s32); 101 else 102 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 103 .libcallFor({s32}) 104 .clampScalar(0, s32, s32); 105 106 for (unsigned Op : {G_SREM, G_UREM}) { 107 setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 108 if (HasHWDivide) 109 setAction({Op, s32}, Lower); 110 else if (AEABI(ST)) 111 setAction({Op, s32}, Custom); 112 else 113 setAction({Op, s32}, Libcall); 114 } 115 116 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); 117 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); 118 119 getActionDefinitionsBuilder(G_CONSTANT) 120 .legalFor({s32, p0}) 121 .clampScalar(0, s32, s32); 122 123 getActionDefinitionsBuilder(G_ICMP) 124 .legalForCartesianProduct({s1}, {s32, p0}) 125 .minScalar(1, s32); 126 127 getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0}, 128 {s1}); 129 130 // We're keeping these builders around because we'll want to add support for 131 // floating point to them. 132 auto &LoadStoreBuilder = 133 getActionDefinitionsBuilder({G_LOAD, G_STORE}) 134 .legalForTypesWithMemDesc({ 135 {s1, p0, 8, 8}, 136 {s8, p0, 8, 8}, 137 {s16, p0, 16, 8}, 138 {s32, p0, 32, 8}, 139 {p0, p0, 32, 8}}); 140 141 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 142 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 143 144 auto &PhiBuilder = 145 getActionDefinitionsBuilder(G_PHI) 146 .legalFor({s32, p0}) 147 .minScalar(0, s32); 148 149 getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}}); 150 151 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 152 153 if (!ST.useSoftFloat() && ST.hasVFP2()) { 154 getActionDefinitionsBuilder( 155 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 156 .legalFor({s32, s64}); 157 158 LoadStoreBuilder.legalFor({{s64, p0}}); 159 PhiBuilder.legalFor({s64}); 160 161 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 162 {s32, s64}); 163 164 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 165 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 166 167 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 168 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 169 170 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 171 .legalForCartesianProduct({s32}, {s32, s64}); 172 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 173 .legalForCartesianProduct({s32, s64}, {s32}); 174 } else { 175 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 176 .libcallFor({s32, s64}); 177 178 LoadStoreBuilder.maxScalar(0, s32); 179 180 for (auto Ty : {s32, s64}) 181 setAction({G_FNEG, Ty}, Lower); 182 183 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 184 185 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 186 {s32, s64}); 187 188 if (AEABI(ST)) 189 setFCmpLibcallsAEABI(); 190 else 191 setFCmpLibcallsGNU(); 192 193 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 194 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 195 196 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 197 .libcallForCartesianProduct({s32}, {s32, s64}); 198 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 199 .libcallForCartesianProduct({s32, s64}, {s32}); 200 } 201 202 if (!ST.useSoftFloat() && ST.hasVFP4()) 203 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 204 else 205 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 206 207 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 208 209 if (ST.hasV5TOps()) { 210 getActionDefinitionsBuilder(G_CTLZ) 211 .legalFor({s32, s32}) 212 .clampScalar(1, s32, s32) 213 .clampScalar(0, s32, s32); 214 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 215 .lowerFor({s32, s32}) 216 .clampScalar(1, s32, s32) 217 .clampScalar(0, s32, s32); 218 } else { 219 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 220 .libcallFor({s32, s32}) 221 .clampScalar(1, s32, s32) 222 .clampScalar(0, s32, s32); 223 getActionDefinitionsBuilder(G_CTLZ) 224 .lowerFor({s32, s32}) 225 .clampScalar(1, s32, s32) 226 .clampScalar(0, s32, s32); 227 } 228 229 computeTables(); 230 verify(*ST.getInstrInfo()); 231 } 232 233 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 234 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 235 // default-initialized. 236 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 237 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 238 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 239 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 240 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 241 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 242 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 243 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 244 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 245 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 246 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 247 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 248 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 249 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 250 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 251 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 252 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 253 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 254 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 255 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 256 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 257 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 258 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 259 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 260 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 261 262 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 263 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 264 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 265 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 266 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 267 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 268 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 269 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 270 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 271 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 272 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 273 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 274 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 275 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 276 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 277 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 278 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 279 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 280 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 281 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 282 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 283 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 284 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 285 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 286 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 287 } 288 289 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 290 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 291 // default-initialized. 292 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 293 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 294 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 295 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 296 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 297 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 298 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 299 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 300 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 301 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 302 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 303 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 304 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 305 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 306 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 307 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 308 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 309 310 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 311 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 312 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 313 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 314 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 315 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 316 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 317 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 318 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 319 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 320 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 321 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 322 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 323 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 324 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 325 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 326 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 327 } 328 329 ARMLegalizerInfo::FCmpLibcallsList 330 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 331 unsigned Size) const { 332 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 333 if (Size == 32) 334 return FCmp32Libcalls[Predicate]; 335 if (Size == 64) 336 return FCmp64Libcalls[Predicate]; 337 llvm_unreachable("Unsupported size for FCmp predicate"); 338 } 339 340 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 341 MachineRegisterInfo &MRI, 342 MachineIRBuilder &MIRBuilder, 343 GISelChangeObserver &Observer) const { 344 using namespace TargetOpcode; 345 346 MIRBuilder.setInstr(MI); 347 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 348 349 switch (MI.getOpcode()) { 350 default: 351 return false; 352 case G_SREM: 353 case G_UREM: { 354 unsigned OriginalResult = MI.getOperand(0).getReg(); 355 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 356 if (Size != 32) 357 return false; 358 359 auto Libcall = 360 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 361 362 // Our divmod libcalls return a struct containing the quotient and the 363 // remainder. We need to create a virtual register for it. 364 Type *ArgTy = Type::getInt32Ty(Ctx); 365 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 366 auto RetVal = MRI.createGenericVirtualRegister( 367 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 368 369 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 370 {{MI.getOperand(1).getReg(), ArgTy}, 371 {MI.getOperand(2).getReg(), ArgTy}}); 372 if (Status != LegalizerHelper::Legalized) 373 return false; 374 375 // The remainder is the second result of divmod. Split the return value into 376 // a new, unused register for the quotient and the destination of the 377 // original instruction for the remainder. 378 MIRBuilder.buildUnmerge( 379 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 380 RetVal); 381 break; 382 } 383 case G_FCMP: { 384 assert(MRI.getType(MI.getOperand(2).getReg()) == 385 MRI.getType(MI.getOperand(3).getReg()) && 386 "Mismatched operands for G_FCMP"); 387 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 388 389 auto OriginalResult = MI.getOperand(0).getReg(); 390 auto Predicate = 391 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 392 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 393 394 if (Libcalls.empty()) { 395 assert((Predicate == CmpInst::FCMP_TRUE || 396 Predicate == CmpInst::FCMP_FALSE) && 397 "Predicate needs libcalls, but none specified"); 398 MIRBuilder.buildConstant(OriginalResult, 399 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 400 MI.eraseFromParent(); 401 return true; 402 } 403 404 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 405 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 406 auto *RetTy = Type::getInt32Ty(Ctx); 407 408 SmallVector<unsigned, 2> Results; 409 for (auto Libcall : Libcalls) { 410 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 411 auto Status = 412 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 413 {{MI.getOperand(2).getReg(), ArgTy}, 414 {MI.getOperand(3).getReg(), ArgTy}}); 415 416 if (Status != LegalizerHelper::Legalized) 417 return false; 418 419 auto ProcessedResult = 420 Libcalls.size() == 1 421 ? OriginalResult 422 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 423 424 // We have a result, but we need to transform it into a proper 1-bit 0 or 425 // 1, taking into account the different peculiarities of the values 426 // returned by the comparison functions. 427 CmpInst::Predicate ResultPred = Libcall.Predicate; 428 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 429 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 430 // to keep the types consistent. 431 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 432 } else { 433 // We need to compare against 0. 434 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 435 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 436 MIRBuilder.buildConstant(Zero, 0); 437 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 438 } 439 Results.push_back(ProcessedResult); 440 } 441 442 if (Results.size() != 1) { 443 assert(Results.size() == 2 && "Unexpected number of results"); 444 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 445 } 446 break; 447 } 448 case G_FCONSTANT: { 449 // Convert to integer constants, while preserving the binary representation. 450 auto AsInteger = 451 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 452 MIRBuilder.buildConstant(MI.getOperand(0).getReg(), 453 *ConstantInt::get(Ctx, AsInteger)); 454 break; 455 } 456 } 457 458 MI.eraseFromParent(); 459 return true; 460 } 461