1 //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements the targeting of the Machinelegalizer class for ARM. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMLegalizerInfo.h" 14 #include "ARMCallLowering.h" 15 #include "ARMSubtarget.h" 16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 17 #include "llvm/CodeGen/LowLevelType.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetOpcodes.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Type.h" 23 24 using namespace llvm; 25 using namespace LegalizeActions; 26 27 /// FIXME: The following static functions are SizeChangeStrategy functions 28 /// that are meant to temporarily mimic the behaviour of the old legalization 29 /// based on doubling/halving non-legal types as closely as possible. This is 30 /// not entirly possible as only legalizing the types that are exactly a power 31 /// of 2 times the size of the legal types would require specifying all those 32 /// sizes explicitly. 33 /// In practice, not specifying those isn't a problem, and the below functions 34 /// should disappear quickly as we add support for legalizing non-power-of-2 35 /// sized types further. 36 static void 37 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, 38 const LegalizerInfo::SizeAndActionsVec &v) { 39 for (unsigned i = 0; i < v.size(); ++i) { 40 result.push_back(v[i]); 41 if (i + 1 < v[i].first && i + 1 < v.size() && 42 v[i + 1].first != v[i].first + 1) 43 result.push_back({v[i].first + 1, Unsupported}); 44 } 45 } 46 47 static LegalizerInfo::SizeAndActionsVec 48 widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) { 49 assert(v.size() >= 1); 50 assert(v[0].first > 17); 51 LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported}, 52 {8, WidenScalar}, 53 {9, Unsupported}, 54 {16, WidenScalar}, 55 {17, Unsupported}}; 56 addAndInterleaveWithUnsupported(result, v); 57 auto Largest = result.back().first; 58 result.push_back({Largest + 1, Unsupported}); 59 return result; 60 } 61 62 static bool AEABI(const ARMSubtarget &ST) { 63 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); 64 } 65 66 ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { 67 using namespace TargetOpcode; 68 69 const LLT p0 = LLT::pointer(0, 32); 70 71 const LLT s1 = LLT::scalar(1); 72 const LLT s8 = LLT::scalar(8); 73 const LLT s16 = LLT::scalar(16); 74 const LLT s32 = LLT::scalar(32); 75 const LLT s64 = LLT::scalar(64); 76 77 if (ST.isThumb1Only()) { 78 // Thumb1 is not supported yet. 79 computeTables(); 80 verify(*ST.getInstrInfo()); 81 return; 82 } 83 84 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) 85 .legalForCartesianProduct({s32}, {s1, s8, s16}); 86 87 getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) 88 .legalFor({s32}) 89 .minScalar(0, s32); 90 91 getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); 92 getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); 93 94 getActionDefinitionsBuilder(G_CONSTANT) 95 .legalFor({s32, p0}) 96 .clampScalar(0, s32, s32); 97 98 // We're keeping these builders around because we'll want to add support for 99 // floating point to them. 100 auto &LoadStoreBuilder = 101 getActionDefinitionsBuilder({G_LOAD, G_STORE}) 102 .legalForTypesWithMemSize({ 103 {s1, p0, 8}, 104 {s8, p0, 8}, 105 {s16, p0, 16}, 106 {s32, p0, 32}, 107 {p0, p0, 32}}); 108 109 if (ST.isThumb()) { 110 // FIXME: merge with the code for non-Thumb. 111 computeTables(); 112 verify(*ST.getInstrInfo()); 113 return; 114 } 115 116 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0}); 117 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); 118 119 if (ST.hasDivideInARMMode()) 120 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 121 .legalFor({s32}) 122 .clampScalar(0, s32, s32); 123 else 124 getActionDefinitionsBuilder({G_SDIV, G_UDIV}) 125 .libcallFor({s32}) 126 .clampScalar(0, s32, s32); 127 128 for (unsigned Op : {G_SREM, G_UREM}) { 129 setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16); 130 if (ST.hasDivideInARMMode()) 131 setAction({Op, s32}, Lower); 132 else if (AEABI(ST)) 133 setAction({Op, s32}, Custom); 134 else 135 setAction({Op, s32}, Libcall); 136 } 137 138 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) 139 .legalFor({{s32, s32}}) 140 .clampScalar(1, s32, s32); 141 142 if (ST.hasV5TOps()) { 143 getActionDefinitionsBuilder(G_CTLZ) 144 .legalFor({s32}) 145 .clampScalar(0, s32, s32); 146 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 147 .lowerFor({s32}) 148 .clampScalar(0, s32, s32); 149 } else { 150 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) 151 .libcallFor({s32}) 152 .clampScalar(0, s32, s32); 153 getActionDefinitionsBuilder(G_CTLZ) 154 .lowerFor({s32}) 155 .clampScalar(0, s32, s32); 156 } 157 158 getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}}); 159 160 getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({s32, p0}, 161 {s1}); 162 163 getActionDefinitionsBuilder(G_BRCOND).legalFor({s1}); 164 165 getActionDefinitionsBuilder(G_ICMP) 166 .legalForCartesianProduct({s1}, {s32, p0}) 167 .minScalar(1, s32); 168 169 // We're keeping these builders around because we'll want to add support for 170 // floating point to them. 171 auto &PhiBuilder = 172 getActionDefinitionsBuilder(G_PHI).legalFor({s32, p0}).minScalar(0, s32); 173 174 if (!ST.useSoftFloat() && ST.hasVFP2()) { 175 getActionDefinitionsBuilder( 176 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG}) 177 .legalFor({s32, s64}); 178 179 LoadStoreBuilder.legalFor({{s64, p0}}); 180 PhiBuilder.legalFor({s64}); 181 182 getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1}, 183 {s32, s64}); 184 185 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); 186 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); 187 188 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); 189 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); 190 191 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 192 .legalForCartesianProduct({s32}, {s32, s64}); 193 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 194 .legalForCartesianProduct({s32, s64}, {s32}); 195 } else { 196 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) 197 .libcallFor({s32, s64}); 198 199 LoadStoreBuilder.maxScalar(0, s32); 200 201 for (auto Ty : {s32, s64}) 202 setAction({G_FNEG, Ty}, Lower); 203 204 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64}); 205 206 getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1}, 207 {s32, s64}); 208 209 if (AEABI(ST)) 210 setFCmpLibcallsAEABI(); 211 else 212 setFCmpLibcallsGNU(); 213 214 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}}); 215 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}}); 216 217 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI}) 218 .libcallForCartesianProduct({s32}, {s32, s64}); 219 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) 220 .libcallForCartesianProduct({s32, s64}, {s32}); 221 } 222 223 if (!ST.useSoftFloat() && ST.hasVFP4()) 224 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64}); 225 else 226 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64}); 227 228 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64}); 229 230 computeTables(); 231 verify(*ST.getInstrInfo()); 232 } 233 234 void ARMLegalizerInfo::setFCmpLibcallsAEABI() { 235 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 236 // default-initialized. 237 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 238 FCmp32Libcalls[CmpInst::FCMP_OEQ] = { 239 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}}; 240 FCmp32Libcalls[CmpInst::FCMP_OGE] = { 241 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 242 FCmp32Libcalls[CmpInst::FCMP_OGT] = { 243 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 244 FCmp32Libcalls[CmpInst::FCMP_OLE] = { 245 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}}; 246 FCmp32Libcalls[CmpInst::FCMP_OLT] = { 247 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 248 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 249 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}}; 250 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}}; 251 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}}; 252 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}}; 253 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}}; 254 FCmp32Libcalls[CmpInst::FCMP_UNO] = { 255 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 256 FCmp32Libcalls[CmpInst::FCMP_ONE] = { 257 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}, 258 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}}; 259 FCmp32Libcalls[CmpInst::FCMP_UEQ] = { 260 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}, 261 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}}; 262 263 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 264 FCmp64Libcalls[CmpInst::FCMP_OEQ] = { 265 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}}; 266 FCmp64Libcalls[CmpInst::FCMP_OGE] = { 267 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 268 FCmp64Libcalls[CmpInst::FCMP_OGT] = { 269 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 270 FCmp64Libcalls[CmpInst::FCMP_OLE] = { 271 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}}; 272 FCmp64Libcalls[CmpInst::FCMP_OLT] = { 273 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 274 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 275 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}}; 276 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}}; 277 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}}; 278 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}}; 279 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}}; 280 FCmp64Libcalls[CmpInst::FCMP_UNO] = { 281 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 282 FCmp64Libcalls[CmpInst::FCMP_ONE] = { 283 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}, 284 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}}; 285 FCmp64Libcalls[CmpInst::FCMP_UEQ] = { 286 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}, 287 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}}; 288 } 289 290 void ARMLegalizerInfo::setFCmpLibcallsGNU() { 291 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be 292 // default-initialized. 293 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 294 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}}; 295 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}}; 296 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}}; 297 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}}; 298 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 299 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; 300 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}}; 301 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}}; 302 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}}; 303 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}}; 304 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}}; 305 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}}; 306 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}, 307 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}}; 308 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}, 309 {RTLIB::UO_F32, CmpInst::ICMP_NE}}; 310 311 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1); 312 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}}; 313 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}}; 314 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}}; 315 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}}; 316 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 317 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}}; 318 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}}; 319 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}}; 320 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}}; 321 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}}; 322 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}}; 323 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}}; 324 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}, 325 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}}; 326 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}, 327 {RTLIB::UO_F64, CmpInst::ICMP_NE}}; 328 } 329 330 ARMLegalizerInfo::FCmpLibcallsList 331 ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate, 332 unsigned Size) const { 333 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate"); 334 if (Size == 32) 335 return FCmp32Libcalls[Predicate]; 336 if (Size == 64) 337 return FCmp64Libcalls[Predicate]; 338 llvm_unreachable("Unsupported size for FCmp predicate"); 339 } 340 341 bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI, 342 MachineRegisterInfo &MRI, 343 MachineIRBuilder &MIRBuilder, 344 GISelChangeObserver &Observer) const { 345 using namespace TargetOpcode; 346 347 MIRBuilder.setInstr(MI); 348 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 349 350 switch (MI.getOpcode()) { 351 default: 352 return false; 353 case G_SREM: 354 case G_UREM: { 355 unsigned OriginalResult = MI.getOperand(0).getReg(); 356 auto Size = MRI.getType(OriginalResult).getSizeInBits(); 357 if (Size != 32) 358 return false; 359 360 auto Libcall = 361 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 362 363 // Our divmod libcalls return a struct containing the quotient and the 364 // remainder. We need to create a virtual register for it. 365 Type *ArgTy = Type::getInt32Ty(Ctx); 366 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true); 367 auto RetVal = MRI.createGenericVirtualRegister( 368 getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout())); 369 370 auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy}, 371 {{MI.getOperand(1).getReg(), ArgTy}, 372 {MI.getOperand(2).getReg(), ArgTy}}); 373 if (Status != LegalizerHelper::Legalized) 374 return false; 375 376 // The remainder is the second result of divmod. Split the return value into 377 // a new, unused register for the quotient and the destination of the 378 // original instruction for the remainder. 379 MIRBuilder.buildUnmerge( 380 {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult}, 381 RetVal); 382 break; 383 } 384 case G_FCMP: { 385 assert(MRI.getType(MI.getOperand(2).getReg()) == 386 MRI.getType(MI.getOperand(3).getReg()) && 387 "Mismatched operands for G_FCMP"); 388 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 389 390 auto OriginalResult = MI.getOperand(0).getReg(); 391 auto Predicate = 392 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 393 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); 394 395 if (Libcalls.empty()) { 396 assert((Predicate == CmpInst::FCMP_TRUE || 397 Predicate == CmpInst::FCMP_FALSE) && 398 "Predicate needs libcalls, but none specified"); 399 MIRBuilder.buildConstant(OriginalResult, 400 Predicate == CmpInst::FCMP_TRUE ? 1 : 0); 401 MI.eraseFromParent(); 402 return true; 403 } 404 405 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); 406 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); 407 auto *RetTy = Type::getInt32Ty(Ctx); 408 409 SmallVector<unsigned, 2> Results; 410 for (auto Libcall : Libcalls) { 411 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32)); 412 auto Status = 413 createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy}, 414 {{MI.getOperand(2).getReg(), ArgTy}, 415 {MI.getOperand(3).getReg(), ArgTy}}); 416 417 if (Status != LegalizerHelper::Legalized) 418 return false; 419 420 auto ProcessedResult = 421 Libcalls.size() == 1 422 ? OriginalResult 423 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult)); 424 425 // We have a result, but we need to transform it into a proper 1-bit 0 or 426 // 1, taking into account the different peculiarities of the values 427 // returned by the comparison functions. 428 CmpInst::Predicate ResultPred = Libcall.Predicate; 429 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) { 430 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit 431 // to keep the types consistent. 432 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult); 433 } else { 434 // We need to compare against 0. 435 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate"); 436 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32)); 437 MIRBuilder.buildConstant(Zero, 0); 438 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero); 439 } 440 Results.push_back(ProcessedResult); 441 } 442 443 if (Results.size() != 1) { 444 assert(Results.size() == 2 && "Unexpected number of results"); 445 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]); 446 } 447 break; 448 } 449 case G_FCONSTANT: { 450 // Convert to integer constants, while preserving the binary representation. 451 auto AsInteger = 452 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); 453 MIRBuilder.buildConstant(MI.getOperand(0).getReg(), 454 *ConstantInt::get(Ctx, AsInteger)); 455 break; 456 } 457 } 458 459 MI.eraseFromParent(); 460 return true; 461 } 462