History log of /dpdk/drivers/net/mlx5/mlx5_flow.c (Results 376 – 400 of 626)
Revision Date Author Comments
# 46a5e6bc 08-Nov-2019 Suanming Mou <suanmingm@mellanox.com>

net/mlx5: prepare meter flow tables

This commit prepare the meter table and suffix table.

A flow with meter will be split to three flows. The three flows are
created on differnet tables. The packet

net/mlx5: prepare meter flow tables

This commit prepare the meter table and suffix table.

A flow with meter will be split to three flows. The three flows are
created on differnet tables. The packets transfer between the flows
on the tables as below:

Prefix flow -> Meter flow -> Suffix flow

Prefix flow does the user defined match and the meter action. The meter
action colors the packet and set its destination to meter table to be
processed by the meter flow.
The meter flow judges if the packet can be passed or not. If packet can
be passed, it will be transferred to the suffix table.
The suffix flow on the suffix table will apply the left user defined
actions to the packet.

The ingress egress and transfer all have the independent meter and
suffix tables.

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 27efd5de 08-Nov-2019 Suanming Mou <suanmingm@mellanox.com>

net/mlx5: allocate flow meter registers

Meter need the metadata REG_C to have the color match between the prefix
flow and the meter flow.

As the user define or metadata feature will both use the RE

net/mlx5: allocate flow meter registers

Meter need the metadata REG_C to have the color match between the prefix
flow and the meter flow.

As the user define or metadata feature will both use the REG_C in the
suffix flow, the color match register meter uses will not impact the
register use in the later sub flow.

Another case is that tag is add before meter flow. In this case, meter
should not touch the register the tag action is using. To avoid that
case, meter should reserve the REG_C's used by user defined MLX5_APP_TAG.

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# dd3c774f 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: add metadata register copy table

While reg_c[meta] can be copied to reg_b simply by modify-header
action (it is supported by hardware), it is not possible to copy
reg_c[mark] to the STE fl

net/mlx5: add metadata register copy table

While reg_c[meta] can be copied to reg_b simply by modify-header
action (it is supported by hardware), it is not possible to copy
reg_c[mark] to the STE flow_tag as flow_tag is not a metadata
register and this is not supported by hardware. Instead, it
should be manually set by a flow per each unique MARK ID. For
this purpose, there should be a dedicated flow table -
RX_CP_TBL and all the Rx flow should pass by the table
to properly copy values from the register to flow tag field.

And for each MARK action, a copy flow should be added
to RX_CP_TBL according to the MARK ID like:
(if reg_c[mark] == mark_id),
flow_tag := mark_id / reg_b := reg_c[meta] / jump to RX_ACT_TBL

For SET_META action, there can be only one default flow like:
reg_b := reg_c[meta] / jump to RX_ACT_TBL

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 71e254bc 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: split Rx flows to provide metadata copy

Values set by MARK and SET_META actions should be carried over
to the VF representor in case of flow miss on Tx path. However,
as not all metadata r

net/mlx5: split Rx flows to provide metadata copy

Values set by MARK and SET_META actions should be carried over
to the VF representor in case of flow miss on Tx path. However,
as not all metadata registers are preserved across the different
domains (NIC Rx/Tx and E-Switch FDB), as a workaround, those
values should be carried by reg_c's which are preserved across
domains and copied to STE flow_tag (MARK) and reg_b (META) fields
in the last stage of flow steering, in order to scatter those
values to flow_tag and flow_table_metadata of CQE.

While reg_c[meta] can be copied to reg_b simply by modify-header
action (it is supported by hardware), it is not possible to copy
reg_c[mark] to the STE flow_tag as flow_tag is not a metadata
register and this is not supported by hardware. Instead, it should
be manually set by a flow per MARK ID. For this purpose, there
should be a dedicated flow table - RX_CP_TBL and all the Rx flow
should pass by the table to properly copy values.

As the last action of Rx flow steering must be a terminal action
such as QUEUE, RSS or DROP, if a user flow has Q/RSS action, the
flow must be split in order to pass by the RX_CP_TBL. And the
remained Q/RSS action will be performed by another dedicated
action table - RX_ACT_TBL.

For example, for an ingress flow:
pattern,
actions_having_QRSS
it must be split into two flows. The first one is,
pattern,
actions_except_QRSS / copy (reg_c[2] := flow_id) / jump to RX_CP_TBL
and the second one in RX_ACT_TBL.
(if reg_c[2] == flow_id),
action_QRSS
where flow_id is uniquely allocated and managed identifier.

This patch implements the Rx flow splitting and build the RX_ACT_TBL.
Also, per each egress flow on NIC Tx, a copy action (reg_c[]= reg_a)
should be added in order to transfer metadata from WQE.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 59c5779d 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: introduce flow splitters chain

The mlx5 hardware has some limitations and flow might
require to be split into multiple internal subflows.
For example this is needed to provide the meter ob

net/mlx5: introduce flow splitters chain

The mlx5 hardware has some limitations and flow might
require to be split into multiple internal subflows.
For example this is needed to provide the meter object
sharing between multiple flows or to provide metadata
register copying before final queue/rss action.

The multiple features might require several level of
splitting. For example, hairpin feature splits the
original flow into two ones - rx and tx parts. Then
RSS feature should split rx part into multiple subflows
with extended item sets. Then, metering feature might
require splitting each RSS subflow into meter jump
chain, and then metadata extensive support might
require the final subflows splitting. So, we have
to organize the chain of splitting subroutines to
abstract each level of splitting.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 3e8edd0e 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: update metadata register ID query

The NIC might support up to 8 extensive metadata registers.
These registers are supposed to be used by multiple features.
There is register id query routi

net/mlx5: update metadata register ID query

The NIC might support up to 8 extensive metadata registers.
These registers are supposed to be used by multiple features.
There is register id query routine to allow determine which
register is actually used by specified feature.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 5e61bcdd 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: check metadata registers availability

The metadata registers reg_c provide support for TAG and
SET_TAG features. Although there are 8 registers are available
on the current mlx5 devices, s

net/mlx5: check metadata registers availability

The metadata registers reg_c provide support for TAG and
SET_TAG features. Although there are 8 registers are available
on the current mlx5 devices, some of them can be reserved.
The availability should be queried by iterative trial-and-error
implemented by mlx5_flow_discover_mreg_c() routine.

If reg_c is available, it can be regarded inclusively that
the extensive metadata support is possible. E.g. metadata
register copy action, supporting 16 modify header actions
(instead of 8 by default) preserving register across
different domains (FDB and NIC) and so on.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 123e69b0 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: update flow functions

Update flow creation/destroy functions for future reuse.
List operations can be skipped inside functions and done
separately out of flow creation.

Signed-off-by: Yon

net/mlx5: update flow functions

Update flow creation/destroy functions for future reuse.
List operations can be skipped inside functions and done
separately out of flow creation.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# e205c95f 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: refactor flow structure

Some rte_flow fields which are local to subflows have been moved to
mlx5_flow structure. RSS attributes are grouped by mlx5_flow_rss structure.
tag_resource is move

net/mlx5: refactor flow structure

Some rte_flow fields which are local to subflows have been moved to
mlx5_flow structure. RSS attributes are grouped by mlx5_flow_rss structure.
tag_resource is moved to mlx5_flow_dv structure.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# cff811c7 07-Nov-2019 Viacheslav Ovsiienko <viacheslavo@mellanox.com>

net/mlx5: convert internal tag endianness

Public API RTE_FLOW_ACTION_TYPE_TAG and RTE_FLOW_ITEM_TYPE_TAG
present data in host-endian format, as all metadata related
entities. The internal mlx5 tag r

net/mlx5: convert internal tag endianness

Public API RTE_FLOW_ACTION_TYPE_TAG and RTE_FLOW_ITEM_TYPE_TAG
present data in host-endian format, as all metadata related
entities. The internal mlx5 tag related action and item should
use the same endianness to be conformed.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

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# 80be0700 06-Nov-2019 Wisam Jaddo <wisamm@mellanox.com>

net/mlx5: add missing packet type for GENEVE

HW ptype are missing TUNNEL_GENEVE support

Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item")

Signed-off-by: Wisam Jaddo <wisamm@mellanox.

net/mlx5: add missing packet type for GENEVE

HW ptype are missing TUNNEL_GENEVE support

Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item")

Signed-off-by: Wisam Jaddo <wisamm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# 0be2fba2 05-Nov-2019 Xiaoyu Min <jackmin@mellanox.com>

net/mlx5: allow pattern start from IP

Some applications, i.e. OVS, have rule like:

[1] pattern ipv4 / end actions ...

which intends to match ipv4 only on non-vlan ethernet and MLX5 NIC
supports th

net/mlx5: allow pattern start from IP

Some applications, i.e. OVS, have rule like:

[1] pattern ipv4 / end actions ...

which intends to match ipv4 only on non-vlan ethernet and MLX5 NIC
supports this.

So PMD should accept this.

Fixes: 906a2efae8da ("net/mlx5: validate flow rule item order")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# fba32130 05-Nov-2019 Xiaoyu Min <jackmin@mellanox.com>

net/mlx5: improve flow item IP validation

Currently PMD doesn't check whether the user specified ethernet type is
conflicting with the followed IPv4/IPv6 items, which leads to HW refuse
to create ru

net/mlx5: improve flow item IP validation

Currently PMD doesn't check whether the user specified ethernet type is
conflicting with the followed IPv4/IPv6 items, which leads to HW refuse
to create rule, for example:

... pattern eth type is 0x86dd / ipv4 / end ...

ethernet type is IPv6 but IPv4 is following, this should be validated
as failure and report corresponding error in detail.

Fixes: 23c1d42c7138 ("net/mlx5: split flow validation to dedicated function")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>

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# 06fa6988 30-Oct-2019 Dekel Peled <dekelp@mellanox.com>

net/mlx5: remove redundant new line in logs

DRV_LOG macro is used to print log messages, one per line.
In several locations this macro is used with redundant '\n' character
at the end of the log mes

net/mlx5: remove redundant new line in logs

DRV_LOG macro is used to print log messages, one per line.
In several locations this macro is used with redundant '\n' character
at the end of the log message, causing blank lines between log lines.

This patch removes the '\n' character where it is redundant.

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# d85c7b5e 30-Oct-2019 Ori Kam <orika@mellanox.com>

net/mlx5: split hairpin flows

Since the encap action is not supported in RX, we need to split the
hairpin flow into RX and TX.

Signed-off-by: Ori Kam <orika@mellanox.com>
Acked-by: Viacheslav Ovsii

net/mlx5: split hairpin flows

Since the encap action is not supported in RX, we need to split the
hairpin flow into RX and TX.

Signed-off-by: Ori Kam <orika@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# 3c84f34e 30-Oct-2019 Ori Kam <orika@mellanox.com>

net/mlx5: add default flows for hairpin

When using hairpin all traffic from TX hairpin queues should jump
to dedecated table where matching can be done using regesters.

Signed-off-by: Ori Kam <orik

net/mlx5: add default flows for hairpin

When using hairpin all traffic from TX hairpin queues should jump
to dedecated table where matching can be done using regesters.

Signed-off-by: Ori Kam <orika@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# 70d84dc7 30-Oct-2019 Ori Kam <orika@mellanox.com>

net/mlx5: add internal tag item and action

This commit introduce the setting and matching on registers.
This item and and action will be used with number of different
features like hairpin, metering

net/mlx5: add internal tag item and action

This commit introduce the setting and matching on registers.
This item and and action will be used with number of different
features like hairpin, metering, metadata.

Signed-off-by: Ori Kam <orika@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# e59a5dbc 16-Oct-2019 Moti Haimovsky <motih@mellanox.com>

net/mlx5: add flow match on GENEVE item

This commit adds support for matching flows on Geneve headers.

Signed-off-by: Moti Haimovsky <motih@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo

net/mlx5: add flow match on GENEVE item

This commit adds support for matching flows on Geneve headers.

Signed-off-by: Moti Haimovsky <motih@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# 906a2efa 11-Sep-2019 Xiaoyu Min <jackmin@mellanox.com>

net/mlx5: validate flow rule item order

The Item order validation between L2 and L3 is missing, which leading to
the following flow rule is accepted:

testpmd> flow create 0 ingress pattern ipv4 /

net/mlx5: validate flow rule item order

The Item order validation between L2 and L3 is missing, which leading to
the following flow rule is accepted:

testpmd> flow create 0 ingress pattern ipv4 / eth / end actions drop /
end

Only the outer L3 layer should check whether the L2 layer is present,
because the L3 layer could directly follow the tunnel layer
without L2 layer.

Meanwhile inner L2 layer should check whether there is inner L3 layer
before it.

Fixes: 23c1d42c7138 ("net/mlx5: split flow validation to dedicated function")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# b67b4ecb 11-Sep-2019 Dekel Peled <dekelp@mellanox.com>

net/mlx5: skip table zero to improve insertion rate

E-switch tables one and above provide higher insertion rate
than table zero, as well as enhanced functionality.

This patch adds a mechanism to ut

net/mlx5: skip table zero to improve insertion rate

E-switch tables one and above provide higher insertion rate
than table zero, as well as enhanced functionality.

This patch adds a mechanism to utilize these advantages, by creating
a default rule on port start, which directs all packets from e-switch
table zero to table one.
Other flow rules, requested for group n, will be created in
e-switch table n+1.
Jump action to e-switch group n will be created to group n+1.

Utility function mlx5_flow_group_to_table() is added to translate the
rte_flow group value to HW table value, and is called by PMD flow
engine on flow rule validation and creation.

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# e4fcdcd6 09-Sep-2019 Moti Haimovsky <motih@mellanox.com>

net/mlx5: support flow action search in a list

This commit adds a helper routine that supports searching for a
specific action in a list of actions.

Signed-off-by: Moti Haimovsky <motih@mellanox.co

net/mlx5: support flow action search in a list

This commit adds a helper routine that supports searching for a
specific action in a list of actions.

Signed-off-by: Moti Haimovsky <motih@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# e6ed9dfd 15-Aug-2019 Dekel Peled <dekelp@mellanox.com>

net/mlx5: fix drop action validation

Function mlx5_flow_validate_action_drop() checks if another fate
action is already present in this flow rule, using defined value
MLX5_FLOW_FATE_ACTIONS.

This p

net/mlx5: fix drop action validation

Function mlx5_flow_validate_action_drop() checks if another fate
action is already present in this flow rule, using defined value
MLX5_FLOW_FATE_ACTIONS.

This patch enhances the check using value
(MLX5_FLOW_FATE_ACTIONS | MLX5_FLOW_FATE_ESWITCH_ACTIONS)
to make sure all relevant fate actions are checked.

Fixes: 23c1d42c7138 ("net/mlx5: split flow validation to dedicated function")
Cc: stable@dpdk.org

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# 725a4284 08-Aug-2019 Xiaoyu Min <jackmin@mellanox.com>

net/mlx5: fix missing packet type for IP-in-IP

The hw ptype information is missed for IP-in-IP tunnel.
It should be RTE_PTYPE_TUNNEL_IP ptype.

Fixes: 5e33bebdd8d3 ("net/mlx5: support IP-in-IP tunne

net/mlx5: fix missing packet type for IP-in-IP

The hw ptype information is missed for IP-in-IP tunnel.
It should be RTE_PTYPE_TUNNEL_IP ptype.

Fixes: 5e33bebdd8d3 ("net/mlx5: support IP-in-IP tunnel")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# c3318f52 24-Jul-2019 Xiaoyu Min <jackmin@mellanox.com>

net/mlx5: fix RSS expand for IP-in-IP

The RSS expand function for IP-in-IP tunnel type is missed,
which leads to create following flow failed:

flow create 0 ingress pattern eth / ipv4 proto is 4

net/mlx5: fix RSS expand for IP-in-IP

The RSS expand function for IP-in-IP tunnel type is missed,
which leads to create following flow failed:

flow create 0 ingress pattern eth / ipv4 proto is 4 /
ipv4 / udp / end actions rss queues 0 1 end level 2
types ip ipv4-other udp ipv4 ipv4-frag end /
mark id 221 / count / end

In order to make RSS expand function working correctly,
now the way to check whether a IP tunnel existing is to
check whether there is the second IPv4/IPv6 item and whether the
first IPv4/IPv6 item's next protocl is IPPROTO_IPIP/IPPROTO_IPV6.
For example:
... pattern eth / ipv4 proto is 4 / ipv4 / ....

Fixes: 5e33bebdd8d3 ("net/mlx5: support IP-in-IP tunnel")

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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# a3970d31 29-Jul-2019 Dekel Peled <dekelp@mellanox.com>

net/mlx5: fix validation of VLAN PCP item

Function mlx5_flow_validate_item_vlan() validates the user setting
is supported by NIC, using a mask with TCI mask 0x0fff.
This check will reject a flow rul

net/mlx5: fix validation of VLAN PCP item

Function mlx5_flow_validate_item_vlan() validates the user setting
is supported by NIC, using a mask with TCI mask 0x0fff.
This check will reject a flow rule specifying a vlan pcp item.

This patch updates mlx5_flow_validate_item_vlan() to use mask 0xffff,
so flow rules with vlan pcp item are accepted.

Fixes: 23c1d42c7138 ("net/mlx5: split flow validation to dedicated function")
Cc: stable@dpdk.org

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

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