1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <netinet/in.h> 7 #include <sys/queue.h> 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 12 /* Verbs header. */ 13 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 14 #ifdef PEDANTIC 15 #pragma GCC diagnostic ignored "-Wpedantic" 16 #endif 17 #include <infiniband/verbs.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <rte_common.h> 23 #include <rte_ether.h> 24 #include <rte_ethdev_driver.h> 25 #include <rte_flow.h> 26 #include <rte_flow_driver.h> 27 #include <rte_malloc.h> 28 #include <rte_ip.h> 29 30 #include "mlx5.h" 31 #include "mlx5_defs.h" 32 #include "mlx5_flow.h" 33 #include "mlx5_glue.h" 34 #include "mlx5_prm.h" 35 #include "mlx5_rxtx.h" 36 37 /* Dev ops structure defined in mlx5.c */ 38 extern const struct eth_dev_ops mlx5_dev_ops; 39 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 40 41 /** Device flow drivers. */ 42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 43 extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops; 44 #endif 45 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 46 47 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 48 49 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 50 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 51 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 52 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 53 #endif 54 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 55 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 56 }; 57 58 enum mlx5_expansion { 59 MLX5_EXPANSION_ROOT, 60 MLX5_EXPANSION_ROOT_OUTER, 61 MLX5_EXPANSION_ROOT_ETH_VLAN, 62 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 63 MLX5_EXPANSION_OUTER_ETH, 64 MLX5_EXPANSION_OUTER_ETH_VLAN, 65 MLX5_EXPANSION_OUTER_VLAN, 66 MLX5_EXPANSION_OUTER_IPV4, 67 MLX5_EXPANSION_OUTER_IPV4_UDP, 68 MLX5_EXPANSION_OUTER_IPV4_TCP, 69 MLX5_EXPANSION_OUTER_IPV6, 70 MLX5_EXPANSION_OUTER_IPV6_UDP, 71 MLX5_EXPANSION_OUTER_IPV6_TCP, 72 MLX5_EXPANSION_VXLAN, 73 MLX5_EXPANSION_VXLAN_GPE, 74 MLX5_EXPANSION_GRE, 75 MLX5_EXPANSION_MPLS, 76 MLX5_EXPANSION_ETH, 77 MLX5_EXPANSION_ETH_VLAN, 78 MLX5_EXPANSION_VLAN, 79 MLX5_EXPANSION_IPV4, 80 MLX5_EXPANSION_IPV4_UDP, 81 MLX5_EXPANSION_IPV4_TCP, 82 MLX5_EXPANSION_IPV6, 83 MLX5_EXPANSION_IPV6_UDP, 84 MLX5_EXPANSION_IPV6_TCP, 85 }; 86 87 /** Supported expansion of items. */ 88 static const struct rte_flow_expand_node mlx5_support_expansion[] = { 89 [MLX5_EXPANSION_ROOT] = { 90 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 91 MLX5_EXPANSION_IPV4, 92 MLX5_EXPANSION_IPV6), 93 .type = RTE_FLOW_ITEM_TYPE_END, 94 }, 95 [MLX5_EXPANSION_ROOT_OUTER] = { 96 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 97 MLX5_EXPANSION_OUTER_IPV4, 98 MLX5_EXPANSION_OUTER_IPV6), 99 .type = RTE_FLOW_ITEM_TYPE_END, 100 }, 101 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 102 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 103 .type = RTE_FLOW_ITEM_TYPE_END, 104 }, 105 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 106 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH_VLAN), 107 .type = RTE_FLOW_ITEM_TYPE_END, 108 }, 109 [MLX5_EXPANSION_OUTER_ETH] = { 110 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 111 MLX5_EXPANSION_OUTER_IPV6, 112 MLX5_EXPANSION_MPLS), 113 .type = RTE_FLOW_ITEM_TYPE_ETH, 114 .rss_types = 0, 115 }, 116 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 117 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 118 .type = RTE_FLOW_ITEM_TYPE_ETH, 119 .rss_types = 0, 120 }, 121 [MLX5_EXPANSION_OUTER_VLAN] = { 122 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 123 MLX5_EXPANSION_OUTER_IPV6), 124 .type = RTE_FLOW_ITEM_TYPE_VLAN, 125 }, 126 [MLX5_EXPANSION_OUTER_IPV4] = { 127 .next = RTE_FLOW_EXPAND_RSS_NEXT 128 (MLX5_EXPANSION_OUTER_IPV4_UDP, 129 MLX5_EXPANSION_OUTER_IPV4_TCP, 130 MLX5_EXPANSION_GRE, 131 MLX5_EXPANSION_IPV4, 132 MLX5_EXPANSION_IPV6), 133 .type = RTE_FLOW_ITEM_TYPE_IPV4, 134 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 135 ETH_RSS_NONFRAG_IPV4_OTHER, 136 }, 137 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 138 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 139 MLX5_EXPANSION_VXLAN_GPE), 140 .type = RTE_FLOW_ITEM_TYPE_UDP, 141 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 142 }, 143 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 144 .type = RTE_FLOW_ITEM_TYPE_TCP, 145 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 146 }, 147 [MLX5_EXPANSION_OUTER_IPV6] = { 148 .next = RTE_FLOW_EXPAND_RSS_NEXT 149 (MLX5_EXPANSION_OUTER_IPV6_UDP, 150 MLX5_EXPANSION_OUTER_IPV6_TCP, 151 MLX5_EXPANSION_IPV4, 152 MLX5_EXPANSION_IPV6), 153 .type = RTE_FLOW_ITEM_TYPE_IPV6, 154 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 155 ETH_RSS_NONFRAG_IPV6_OTHER, 156 }, 157 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 158 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 159 MLX5_EXPANSION_VXLAN_GPE), 160 .type = RTE_FLOW_ITEM_TYPE_UDP, 161 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 162 }, 163 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 164 .type = RTE_FLOW_ITEM_TYPE_TCP, 165 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 166 }, 167 [MLX5_EXPANSION_VXLAN] = { 168 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 169 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 170 }, 171 [MLX5_EXPANSION_VXLAN_GPE] = { 172 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 173 MLX5_EXPANSION_IPV4, 174 MLX5_EXPANSION_IPV6), 175 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 176 }, 177 [MLX5_EXPANSION_GRE] = { 178 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4), 179 .type = RTE_FLOW_ITEM_TYPE_GRE, 180 }, 181 [MLX5_EXPANSION_MPLS] = { 182 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 183 MLX5_EXPANSION_IPV6), 184 .type = RTE_FLOW_ITEM_TYPE_MPLS, 185 }, 186 [MLX5_EXPANSION_ETH] = { 187 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 188 MLX5_EXPANSION_IPV6), 189 .type = RTE_FLOW_ITEM_TYPE_ETH, 190 }, 191 [MLX5_EXPANSION_ETH_VLAN] = { 192 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 193 .type = RTE_FLOW_ITEM_TYPE_ETH, 194 }, 195 [MLX5_EXPANSION_VLAN] = { 196 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 197 MLX5_EXPANSION_IPV6), 198 .type = RTE_FLOW_ITEM_TYPE_VLAN, 199 }, 200 [MLX5_EXPANSION_IPV4] = { 201 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 202 MLX5_EXPANSION_IPV4_TCP), 203 .type = RTE_FLOW_ITEM_TYPE_IPV4, 204 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 205 ETH_RSS_NONFRAG_IPV4_OTHER, 206 }, 207 [MLX5_EXPANSION_IPV4_UDP] = { 208 .type = RTE_FLOW_ITEM_TYPE_UDP, 209 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 210 }, 211 [MLX5_EXPANSION_IPV4_TCP] = { 212 .type = RTE_FLOW_ITEM_TYPE_TCP, 213 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 214 }, 215 [MLX5_EXPANSION_IPV6] = { 216 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 217 MLX5_EXPANSION_IPV6_TCP), 218 .type = RTE_FLOW_ITEM_TYPE_IPV6, 219 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 220 ETH_RSS_NONFRAG_IPV6_OTHER, 221 }, 222 [MLX5_EXPANSION_IPV6_UDP] = { 223 .type = RTE_FLOW_ITEM_TYPE_UDP, 224 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 225 }, 226 [MLX5_EXPANSION_IPV6_TCP] = { 227 .type = RTE_FLOW_ITEM_TYPE_TCP, 228 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 229 }, 230 }; 231 232 static const struct rte_flow_ops mlx5_flow_ops = { 233 .validate = mlx5_flow_validate, 234 .create = mlx5_flow_create, 235 .destroy = mlx5_flow_destroy, 236 .flush = mlx5_flow_flush, 237 .isolate = mlx5_flow_isolate, 238 .query = mlx5_flow_query, 239 }; 240 241 /* Convert FDIR request to Generic flow. */ 242 struct mlx5_fdir { 243 struct rte_flow_attr attr; 244 struct rte_flow_item items[4]; 245 struct rte_flow_item_eth l2; 246 struct rte_flow_item_eth l2_mask; 247 union { 248 struct rte_flow_item_ipv4 ipv4; 249 struct rte_flow_item_ipv6 ipv6; 250 } l3; 251 union { 252 struct rte_flow_item_ipv4 ipv4; 253 struct rte_flow_item_ipv6 ipv6; 254 } l3_mask; 255 union { 256 struct rte_flow_item_udp udp; 257 struct rte_flow_item_tcp tcp; 258 } l4; 259 union { 260 struct rte_flow_item_udp udp; 261 struct rte_flow_item_tcp tcp; 262 } l4_mask; 263 struct rte_flow_action actions[2]; 264 struct rte_flow_action_queue queue; 265 }; 266 267 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 268 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 269 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 270 }; 271 272 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 273 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 274 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 275 { 9, 10, 11 }, { 12, 13, 14 }, 276 }; 277 278 /* Tunnel information. */ 279 struct mlx5_flow_tunnel_info { 280 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 281 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 282 }; 283 284 static struct mlx5_flow_tunnel_info tunnels_info[] = { 285 { 286 .tunnel = MLX5_FLOW_LAYER_VXLAN, 287 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 288 }, 289 { 290 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 291 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 292 }, 293 { 294 .tunnel = MLX5_FLOW_LAYER_GRE, 295 .ptype = RTE_PTYPE_TUNNEL_GRE, 296 }, 297 { 298 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 299 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 300 }, 301 { 302 .tunnel = MLX5_FLOW_LAYER_MPLS, 303 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 304 }, 305 { 306 .tunnel = MLX5_FLOW_LAYER_NVGRE, 307 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 308 }, 309 { 310 .tunnel = MLX5_FLOW_LAYER_IPIP, 311 .ptype = RTE_PTYPE_TUNNEL_IP, 312 }, 313 { 314 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 315 .ptype = RTE_PTYPE_TUNNEL_IP, 316 }, 317 }; 318 319 enum mlx5_feature_name { 320 MLX5_HAIRPIN_RX, 321 MLX5_HAIRPIN_TX, 322 MLX5_APPLICATION, 323 }; 324 325 /** 326 * Translate tag ID to register. 327 * 328 * @param[in] dev 329 * Pointer to the Ethernet device structure. 330 * @param[in] feature 331 * The feature that request the register. 332 * @param[in] id 333 * The request register ID. 334 * @param[out] error 335 * Error description in case of any. 336 * 337 * @return 338 * The request register on success, a negative errno 339 * value otherwise and rte_errno is set. 340 */ 341 __rte_unused 342 static enum modify_reg flow_get_reg_id(struct rte_eth_dev *dev, 343 enum mlx5_feature_name feature, 344 uint32_t id, 345 struct rte_flow_error *error) 346 { 347 static enum modify_reg id2reg[] = { 348 [0] = REG_A, 349 [1] = REG_C_2, 350 [2] = REG_C_3, 351 [3] = REG_C_4, 352 [4] = REG_B,}; 353 354 dev = (void *)dev; 355 switch (feature) { 356 case MLX5_HAIRPIN_RX: 357 return REG_B; 358 case MLX5_HAIRPIN_TX: 359 return REG_A; 360 case MLX5_APPLICATION: 361 if (id > 4) 362 return rte_flow_error_set(error, EINVAL, 363 RTE_FLOW_ERROR_TYPE_ITEM, 364 NULL, "invalid tag id"); 365 return id2reg[id]; 366 } 367 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 368 NULL, "invalid feature name"); 369 } 370 371 /** 372 * Discover the maximum number of priority available. 373 * 374 * @param[in] dev 375 * Pointer to the Ethernet device structure. 376 * 377 * @return 378 * number of supported flow priority on success, a negative errno 379 * value otherwise and rte_errno is set. 380 */ 381 int 382 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 383 { 384 struct mlx5_priv *priv = dev->data->dev_private; 385 struct { 386 struct ibv_flow_attr attr; 387 struct ibv_flow_spec_eth eth; 388 struct ibv_flow_spec_action_drop drop; 389 } flow_attr = { 390 .attr = { 391 .num_of_specs = 2, 392 .port = (uint8_t)priv->ibv_port, 393 }, 394 .eth = { 395 .type = IBV_FLOW_SPEC_ETH, 396 .size = sizeof(struct ibv_flow_spec_eth), 397 }, 398 .drop = { 399 .size = sizeof(struct ibv_flow_spec_action_drop), 400 .type = IBV_FLOW_SPEC_ACTION_DROP, 401 }, 402 }; 403 struct ibv_flow *flow; 404 struct mlx5_hrxq *drop = mlx5_hrxq_drop_new(dev); 405 uint16_t vprio[] = { 8, 16 }; 406 int i; 407 int priority = 0; 408 409 if (!drop) { 410 rte_errno = ENOTSUP; 411 return -rte_errno; 412 } 413 for (i = 0; i != RTE_DIM(vprio); i++) { 414 flow_attr.attr.priority = vprio[i] - 1; 415 flow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr); 416 if (!flow) 417 break; 418 claim_zero(mlx5_glue->destroy_flow(flow)); 419 priority = vprio[i]; 420 } 421 mlx5_hrxq_drop_release(dev); 422 switch (priority) { 423 case 8: 424 priority = RTE_DIM(priority_map_3); 425 break; 426 case 16: 427 priority = RTE_DIM(priority_map_5); 428 break; 429 default: 430 rte_errno = ENOTSUP; 431 DRV_LOG(ERR, 432 "port %u verbs maximum priority: %d expected 8/16", 433 dev->data->port_id, priority); 434 return -rte_errno; 435 } 436 DRV_LOG(INFO, "port %u flow maximum priority: %d", 437 dev->data->port_id, priority); 438 return priority; 439 } 440 441 /** 442 * Adjust flow priority based on the highest layer and the request priority. 443 * 444 * @param[in] dev 445 * Pointer to the Ethernet device structure. 446 * @param[in] priority 447 * The rule base priority. 448 * @param[in] subpriority 449 * The priority based on the items. 450 * 451 * @return 452 * The new priority. 453 */ 454 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 455 uint32_t subpriority) 456 { 457 uint32_t res = 0; 458 struct mlx5_priv *priv = dev->data->dev_private; 459 460 switch (priv->config.flow_prio) { 461 case RTE_DIM(priority_map_3): 462 res = priority_map_3[priority][subpriority]; 463 break; 464 case RTE_DIM(priority_map_5): 465 res = priority_map_5[priority][subpriority]; 466 break; 467 } 468 return res; 469 } 470 471 /** 472 * Verify the @p item specifications (spec, last, mask) are compatible with the 473 * NIC capabilities. 474 * 475 * @param[in] item 476 * Item specification. 477 * @param[in] mask 478 * @p item->mask or flow default bit-masks. 479 * @param[in] nic_mask 480 * Bit-masks covering supported fields by the NIC to compare with user mask. 481 * @param[in] size 482 * Bit-masks size in bytes. 483 * @param[out] error 484 * Pointer to error structure. 485 * 486 * @return 487 * 0 on success, a negative errno value otherwise and rte_errno is set. 488 */ 489 int 490 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 491 const uint8_t *mask, 492 const uint8_t *nic_mask, 493 unsigned int size, 494 struct rte_flow_error *error) 495 { 496 unsigned int i; 497 498 assert(nic_mask); 499 for (i = 0; i < size; ++i) 500 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 501 return rte_flow_error_set(error, ENOTSUP, 502 RTE_FLOW_ERROR_TYPE_ITEM, 503 item, 504 "mask enables non supported" 505 " bits"); 506 if (!item->spec && (item->mask || item->last)) 507 return rte_flow_error_set(error, EINVAL, 508 RTE_FLOW_ERROR_TYPE_ITEM, item, 509 "mask/last without a spec is not" 510 " supported"); 511 if (item->spec && item->last) { 512 uint8_t spec[size]; 513 uint8_t last[size]; 514 unsigned int i; 515 int ret; 516 517 for (i = 0; i < size; ++i) { 518 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 519 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 520 } 521 ret = memcmp(spec, last, size); 522 if (ret != 0) 523 return rte_flow_error_set(error, EINVAL, 524 RTE_FLOW_ERROR_TYPE_ITEM, 525 item, 526 "range is not valid"); 527 } 528 return 0; 529 } 530 531 /** 532 * Adjust the hash fields according to the @p flow information. 533 * 534 * @param[in] dev_flow. 535 * Pointer to the mlx5_flow. 536 * @param[in] tunnel 537 * 1 when the hash field is for a tunnel item. 538 * @param[in] layer_types 539 * ETH_RSS_* types. 540 * @param[in] hash_fields 541 * Item hash fields. 542 * 543 * @return 544 * The hash fields that should be used. 545 */ 546 uint64_t 547 mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, 548 int tunnel __rte_unused, uint64_t layer_types, 549 uint64_t hash_fields) 550 { 551 struct rte_flow *flow = dev_flow->flow; 552 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 553 int rss_request_inner = flow->rss.level >= 2; 554 555 /* Check RSS hash level for tunnel. */ 556 if (tunnel && rss_request_inner) 557 hash_fields |= IBV_RX_HASH_INNER; 558 else if (tunnel || rss_request_inner) 559 return 0; 560 #endif 561 /* Check if requested layer matches RSS hash fields. */ 562 if (!(flow->rss.types & layer_types)) 563 return 0; 564 return hash_fields; 565 } 566 567 /** 568 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 569 * if several tunnel rules are used on this queue, the tunnel ptype will be 570 * cleared. 571 * 572 * @param rxq_ctrl 573 * Rx queue to update. 574 */ 575 static void 576 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 577 { 578 unsigned int i; 579 uint32_t tunnel_ptype = 0; 580 581 /* Look up for the ptype to use. */ 582 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 583 if (!rxq_ctrl->flow_tunnels_n[i]) 584 continue; 585 if (!tunnel_ptype) { 586 tunnel_ptype = tunnels_info[i].ptype; 587 } else { 588 tunnel_ptype = 0; 589 break; 590 } 591 } 592 rxq_ctrl->rxq.tunnel = tunnel_ptype; 593 } 594 595 /** 596 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 597 * flow. 598 * 599 * @param[in] dev 600 * Pointer to the Ethernet device structure. 601 * @param[in] dev_flow 602 * Pointer to device flow structure. 603 */ 604 static void 605 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow) 606 { 607 struct mlx5_priv *priv = dev->data->dev_private; 608 struct rte_flow *flow = dev_flow->flow; 609 const int mark = !!(dev_flow->actions & 610 (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK)); 611 const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL); 612 unsigned int i; 613 614 for (i = 0; i != flow->rss.queue_num; ++i) { 615 int idx = (*flow->queue)[i]; 616 struct mlx5_rxq_ctrl *rxq_ctrl = 617 container_of((*priv->rxqs)[idx], 618 struct mlx5_rxq_ctrl, rxq); 619 620 if (mark) { 621 rxq_ctrl->rxq.mark = 1; 622 rxq_ctrl->flow_mark_n++; 623 } 624 if (tunnel) { 625 unsigned int j; 626 627 /* Increase the counter matching the flow. */ 628 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 629 if ((tunnels_info[j].tunnel & 630 dev_flow->layers) == 631 tunnels_info[j].tunnel) { 632 rxq_ctrl->flow_tunnels_n[j]++; 633 break; 634 } 635 } 636 flow_rxq_tunnel_ptype_update(rxq_ctrl); 637 } 638 } 639 } 640 641 /** 642 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 643 * 644 * @param[in] dev 645 * Pointer to the Ethernet device structure. 646 * @param[in] flow 647 * Pointer to flow structure. 648 */ 649 static void 650 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 651 { 652 struct mlx5_flow *dev_flow; 653 654 LIST_FOREACH(dev_flow, &flow->dev_flows, next) 655 flow_drv_rxq_flags_set(dev, dev_flow); 656 } 657 658 /** 659 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 660 * device flow if no other flow uses it with the same kind of request. 661 * 662 * @param dev 663 * Pointer to Ethernet device. 664 * @param[in] dev_flow 665 * Pointer to the device flow. 666 */ 667 static void 668 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow) 669 { 670 struct mlx5_priv *priv = dev->data->dev_private; 671 struct rte_flow *flow = dev_flow->flow; 672 const int mark = !!(dev_flow->actions & 673 (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK)); 674 const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL); 675 unsigned int i; 676 677 assert(dev->data->dev_started); 678 for (i = 0; i != flow->rss.queue_num; ++i) { 679 int idx = (*flow->queue)[i]; 680 struct mlx5_rxq_ctrl *rxq_ctrl = 681 container_of((*priv->rxqs)[idx], 682 struct mlx5_rxq_ctrl, rxq); 683 684 if (mark) { 685 rxq_ctrl->flow_mark_n--; 686 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 687 } 688 if (tunnel) { 689 unsigned int j; 690 691 /* Decrease the counter matching the flow. */ 692 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 693 if ((tunnels_info[j].tunnel & 694 dev_flow->layers) == 695 tunnels_info[j].tunnel) { 696 rxq_ctrl->flow_tunnels_n[j]--; 697 break; 698 } 699 } 700 flow_rxq_tunnel_ptype_update(rxq_ctrl); 701 } 702 } 703 } 704 705 /** 706 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 707 * @p flow if no other flow uses it with the same kind of request. 708 * 709 * @param dev 710 * Pointer to Ethernet device. 711 * @param[in] flow 712 * Pointer to the flow. 713 */ 714 static void 715 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 716 { 717 struct mlx5_flow *dev_flow; 718 719 LIST_FOREACH(dev_flow, &flow->dev_flows, next) 720 flow_drv_rxq_flags_trim(dev, dev_flow); 721 } 722 723 /** 724 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 725 * 726 * @param dev 727 * Pointer to Ethernet device. 728 */ 729 static void 730 flow_rxq_flags_clear(struct rte_eth_dev *dev) 731 { 732 struct mlx5_priv *priv = dev->data->dev_private; 733 unsigned int i; 734 735 for (i = 0; i != priv->rxqs_n; ++i) { 736 struct mlx5_rxq_ctrl *rxq_ctrl; 737 unsigned int j; 738 739 if (!(*priv->rxqs)[i]) 740 continue; 741 rxq_ctrl = container_of((*priv->rxqs)[i], 742 struct mlx5_rxq_ctrl, rxq); 743 rxq_ctrl->flow_mark_n = 0; 744 rxq_ctrl->rxq.mark = 0; 745 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 746 rxq_ctrl->flow_tunnels_n[j] = 0; 747 rxq_ctrl->rxq.tunnel = 0; 748 } 749 } 750 751 /* 752 * return a pointer to the desired action in the list of actions. 753 * 754 * @param[in] actions 755 * The list of actions to search the action in. 756 * @param[in] action 757 * The action to find. 758 * 759 * @return 760 * Pointer to the action in the list, if found. NULL otherwise. 761 */ 762 const struct rte_flow_action * 763 mlx5_flow_find_action(const struct rte_flow_action *actions, 764 enum rte_flow_action_type action) 765 { 766 if (actions == NULL) 767 return NULL; 768 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 769 if (actions->type == action) 770 return actions; 771 return NULL; 772 } 773 774 /* 775 * Validate the flag action. 776 * 777 * @param[in] action_flags 778 * Bit-fields that holds the actions detected until now. 779 * @param[in] attr 780 * Attributes of flow that includes this action. 781 * @param[out] error 782 * Pointer to error structure. 783 * 784 * @return 785 * 0 on success, a negative errno value otherwise and rte_errno is set. 786 */ 787 int 788 mlx5_flow_validate_action_flag(uint64_t action_flags, 789 const struct rte_flow_attr *attr, 790 struct rte_flow_error *error) 791 { 792 793 if (action_flags & MLX5_FLOW_ACTION_DROP) 794 return rte_flow_error_set(error, EINVAL, 795 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 796 "can't drop and flag in same flow"); 797 if (action_flags & MLX5_FLOW_ACTION_MARK) 798 return rte_flow_error_set(error, EINVAL, 799 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 800 "can't mark and flag in same flow"); 801 if (action_flags & MLX5_FLOW_ACTION_FLAG) 802 return rte_flow_error_set(error, EINVAL, 803 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 804 "can't have 2 flag" 805 " actions in same flow"); 806 if (attr->egress) 807 return rte_flow_error_set(error, ENOTSUP, 808 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 809 "flag action not supported for " 810 "egress"); 811 return 0; 812 } 813 814 /* 815 * Validate the mark action. 816 * 817 * @param[in] action 818 * Pointer to the queue action. 819 * @param[in] action_flags 820 * Bit-fields that holds the actions detected until now. 821 * @param[in] attr 822 * Attributes of flow that includes this action. 823 * @param[out] error 824 * Pointer to error structure. 825 * 826 * @return 827 * 0 on success, a negative errno value otherwise and rte_errno is set. 828 */ 829 int 830 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 831 uint64_t action_flags, 832 const struct rte_flow_attr *attr, 833 struct rte_flow_error *error) 834 { 835 const struct rte_flow_action_mark *mark = action->conf; 836 837 if (!mark) 838 return rte_flow_error_set(error, EINVAL, 839 RTE_FLOW_ERROR_TYPE_ACTION, 840 action, 841 "configuration cannot be null"); 842 if (mark->id >= MLX5_FLOW_MARK_MAX) 843 return rte_flow_error_set(error, EINVAL, 844 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 845 &mark->id, 846 "mark id must in 0 <= id < " 847 RTE_STR(MLX5_FLOW_MARK_MAX)); 848 if (action_flags & MLX5_FLOW_ACTION_DROP) 849 return rte_flow_error_set(error, EINVAL, 850 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 851 "can't drop and mark in same flow"); 852 if (action_flags & MLX5_FLOW_ACTION_FLAG) 853 return rte_flow_error_set(error, EINVAL, 854 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 855 "can't flag and mark in same flow"); 856 if (action_flags & MLX5_FLOW_ACTION_MARK) 857 return rte_flow_error_set(error, EINVAL, 858 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 859 "can't have 2 mark actions in same" 860 " flow"); 861 if (attr->egress) 862 return rte_flow_error_set(error, ENOTSUP, 863 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 864 "mark action not supported for " 865 "egress"); 866 return 0; 867 } 868 869 /* 870 * Validate the drop action. 871 * 872 * @param[in] action_flags 873 * Bit-fields that holds the actions detected until now. 874 * @param[in] attr 875 * Attributes of flow that includes this action. 876 * @param[out] error 877 * Pointer to error structure. 878 * 879 * @return 880 * 0 on success, a negative errno value otherwise and rte_errno is set. 881 */ 882 int 883 mlx5_flow_validate_action_drop(uint64_t action_flags, 884 const struct rte_flow_attr *attr, 885 struct rte_flow_error *error) 886 { 887 if (action_flags & MLX5_FLOW_ACTION_FLAG) 888 return rte_flow_error_set(error, EINVAL, 889 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 890 "can't drop and flag in same flow"); 891 if (action_flags & MLX5_FLOW_ACTION_MARK) 892 return rte_flow_error_set(error, EINVAL, 893 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 894 "can't drop and mark in same flow"); 895 if (action_flags & (MLX5_FLOW_FATE_ACTIONS | 896 MLX5_FLOW_FATE_ESWITCH_ACTIONS)) 897 return rte_flow_error_set(error, EINVAL, 898 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 899 "can't have 2 fate actions in" 900 " same flow"); 901 if (attr->egress) 902 return rte_flow_error_set(error, ENOTSUP, 903 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 904 "drop action not supported for " 905 "egress"); 906 return 0; 907 } 908 909 /* 910 * Validate the queue action. 911 * 912 * @param[in] action 913 * Pointer to the queue action. 914 * @param[in] action_flags 915 * Bit-fields that holds the actions detected until now. 916 * @param[in] dev 917 * Pointer to the Ethernet device structure. 918 * @param[in] attr 919 * Attributes of flow that includes this action. 920 * @param[out] error 921 * Pointer to error structure. 922 * 923 * @return 924 * 0 on success, a negative errno value otherwise and rte_errno is set. 925 */ 926 int 927 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 928 uint64_t action_flags, 929 struct rte_eth_dev *dev, 930 const struct rte_flow_attr *attr, 931 struct rte_flow_error *error) 932 { 933 struct mlx5_priv *priv = dev->data->dev_private; 934 const struct rte_flow_action_queue *queue = action->conf; 935 936 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 937 return rte_flow_error_set(error, EINVAL, 938 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 939 "can't have 2 fate actions in" 940 " same flow"); 941 if (!priv->rxqs_n) 942 return rte_flow_error_set(error, EINVAL, 943 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 944 NULL, "No Rx queues configured"); 945 if (queue->index >= priv->rxqs_n) 946 return rte_flow_error_set(error, EINVAL, 947 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 948 &queue->index, 949 "queue index out of range"); 950 if (!(*priv->rxqs)[queue->index]) 951 return rte_flow_error_set(error, EINVAL, 952 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 953 &queue->index, 954 "queue is not configured"); 955 if (attr->egress) 956 return rte_flow_error_set(error, ENOTSUP, 957 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 958 "queue action not supported for " 959 "egress"); 960 return 0; 961 } 962 963 /* 964 * Validate the rss action. 965 * 966 * @param[in] action 967 * Pointer to the queue action. 968 * @param[in] action_flags 969 * Bit-fields that holds the actions detected until now. 970 * @param[in] dev 971 * Pointer to the Ethernet device structure. 972 * @param[in] attr 973 * Attributes of flow that includes this action. 974 * @param[in] item_flags 975 * Items that were detected. 976 * @param[out] error 977 * Pointer to error structure. 978 * 979 * @return 980 * 0 on success, a negative errno value otherwise and rte_errno is set. 981 */ 982 int 983 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 984 uint64_t action_flags, 985 struct rte_eth_dev *dev, 986 const struct rte_flow_attr *attr, 987 uint64_t item_flags, 988 struct rte_flow_error *error) 989 { 990 struct mlx5_priv *priv = dev->data->dev_private; 991 const struct rte_flow_action_rss *rss = action->conf; 992 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 993 unsigned int i; 994 995 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 996 return rte_flow_error_set(error, EINVAL, 997 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 998 "can't have 2 fate actions" 999 " in same flow"); 1000 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1001 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1002 return rte_flow_error_set(error, ENOTSUP, 1003 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1004 &rss->func, 1005 "RSS hash function not supported"); 1006 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1007 if (rss->level > 2) 1008 #else 1009 if (rss->level > 1) 1010 #endif 1011 return rte_flow_error_set(error, ENOTSUP, 1012 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1013 &rss->level, 1014 "tunnel RSS is not supported"); 1015 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1016 if (rss->key_len == 0 && rss->key != NULL) 1017 return rte_flow_error_set(error, ENOTSUP, 1018 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1019 &rss->key_len, 1020 "RSS hash key length 0"); 1021 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1022 return rte_flow_error_set(error, ENOTSUP, 1023 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1024 &rss->key_len, 1025 "RSS hash key too small"); 1026 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1027 return rte_flow_error_set(error, ENOTSUP, 1028 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1029 &rss->key_len, 1030 "RSS hash key too large"); 1031 if (rss->queue_num > priv->config.ind_table_max_size) 1032 return rte_flow_error_set(error, ENOTSUP, 1033 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1034 &rss->queue_num, 1035 "number of queues too large"); 1036 if (rss->types & MLX5_RSS_HF_MASK) 1037 return rte_flow_error_set(error, ENOTSUP, 1038 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1039 &rss->types, 1040 "some RSS protocols are not" 1041 " supported"); 1042 if (!priv->rxqs_n) 1043 return rte_flow_error_set(error, EINVAL, 1044 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1045 NULL, "No Rx queues configured"); 1046 if (!rss->queue_num) 1047 return rte_flow_error_set(error, EINVAL, 1048 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1049 NULL, "No queues configured"); 1050 for (i = 0; i != rss->queue_num; ++i) { 1051 if (!(*priv->rxqs)[rss->queue[i]]) 1052 return rte_flow_error_set 1053 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1054 &rss->queue[i], "queue is not configured"); 1055 } 1056 if (attr->egress) 1057 return rte_flow_error_set(error, ENOTSUP, 1058 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1059 "rss action not supported for " 1060 "egress"); 1061 if (rss->level > 1 && !tunnel) 1062 return rte_flow_error_set(error, EINVAL, 1063 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1064 "inner RSS is not supported for " 1065 "non-tunnel flows"); 1066 return 0; 1067 } 1068 1069 /* 1070 * Validate the count action. 1071 * 1072 * @param[in] dev 1073 * Pointer to the Ethernet device structure. 1074 * @param[in] attr 1075 * Attributes of flow that includes this action. 1076 * @param[out] error 1077 * Pointer to error structure. 1078 * 1079 * @return 1080 * 0 on success, a negative errno value otherwise and rte_errno is set. 1081 */ 1082 int 1083 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1084 const struct rte_flow_attr *attr, 1085 struct rte_flow_error *error) 1086 { 1087 if (attr->egress) 1088 return rte_flow_error_set(error, ENOTSUP, 1089 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1090 "count action not supported for " 1091 "egress"); 1092 return 0; 1093 } 1094 1095 /** 1096 * Verify the @p attributes will be correctly understood by the NIC and store 1097 * them in the @p flow if everything is correct. 1098 * 1099 * @param[in] dev 1100 * Pointer to the Ethernet device structure. 1101 * @param[in] attributes 1102 * Pointer to flow attributes 1103 * @param[out] error 1104 * Pointer to error structure. 1105 * 1106 * @return 1107 * 0 on success, a negative errno value otherwise and rte_errno is set. 1108 */ 1109 int 1110 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1111 const struct rte_flow_attr *attributes, 1112 struct rte_flow_error *error) 1113 { 1114 struct mlx5_priv *priv = dev->data->dev_private; 1115 uint32_t priority_max = priv->config.flow_prio - 1; 1116 1117 if (attributes->group) 1118 return rte_flow_error_set(error, ENOTSUP, 1119 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1120 NULL, "groups is not supported"); 1121 if (attributes->priority != MLX5_FLOW_PRIO_RSVD && 1122 attributes->priority >= priority_max) 1123 return rte_flow_error_set(error, ENOTSUP, 1124 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1125 NULL, "priority out of range"); 1126 if (attributes->egress) 1127 return rte_flow_error_set(error, ENOTSUP, 1128 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1129 "egress is not supported"); 1130 if (attributes->transfer && !priv->config.dv_esw_en) 1131 return rte_flow_error_set(error, ENOTSUP, 1132 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1133 NULL, "transfer is not supported"); 1134 if (!attributes->ingress) 1135 return rte_flow_error_set(error, EINVAL, 1136 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1137 NULL, 1138 "ingress attribute is mandatory"); 1139 return 0; 1140 } 1141 1142 /** 1143 * Validate ICMP6 item. 1144 * 1145 * @param[in] item 1146 * Item specification. 1147 * @param[in] item_flags 1148 * Bit-fields that holds the items detected until now. 1149 * @param[out] error 1150 * Pointer to error structure. 1151 * 1152 * @return 1153 * 0 on success, a negative errno value otherwise and rte_errno is set. 1154 */ 1155 int 1156 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1157 uint64_t item_flags, 1158 uint8_t target_protocol, 1159 struct rte_flow_error *error) 1160 { 1161 const struct rte_flow_item_icmp6 *mask = item->mask; 1162 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1163 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1164 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1165 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1166 MLX5_FLOW_LAYER_OUTER_L4; 1167 int ret; 1168 1169 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1170 return rte_flow_error_set(error, EINVAL, 1171 RTE_FLOW_ERROR_TYPE_ITEM, item, 1172 "protocol filtering not compatible" 1173 " with ICMP6 layer"); 1174 if (!(item_flags & l3m)) 1175 return rte_flow_error_set(error, EINVAL, 1176 RTE_FLOW_ERROR_TYPE_ITEM, item, 1177 "IPv6 is mandatory to filter on" 1178 " ICMP6"); 1179 if (item_flags & l4m) 1180 return rte_flow_error_set(error, EINVAL, 1181 RTE_FLOW_ERROR_TYPE_ITEM, item, 1182 "multiple L4 layers not supported"); 1183 if (!mask) 1184 mask = &rte_flow_item_icmp6_mask; 1185 ret = mlx5_flow_item_acceptable 1186 (item, (const uint8_t *)mask, 1187 (const uint8_t *)&rte_flow_item_icmp6_mask, 1188 sizeof(struct rte_flow_item_icmp6), error); 1189 if (ret < 0) 1190 return ret; 1191 return 0; 1192 } 1193 1194 /** 1195 * Validate ICMP item. 1196 * 1197 * @param[in] item 1198 * Item specification. 1199 * @param[in] item_flags 1200 * Bit-fields that holds the items detected until now. 1201 * @param[out] error 1202 * Pointer to error structure. 1203 * 1204 * @return 1205 * 0 on success, a negative errno value otherwise and rte_errno is set. 1206 */ 1207 int 1208 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1209 uint64_t item_flags, 1210 uint8_t target_protocol, 1211 struct rte_flow_error *error) 1212 { 1213 const struct rte_flow_item_icmp *mask = item->mask; 1214 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1215 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1216 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1217 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1218 MLX5_FLOW_LAYER_OUTER_L4; 1219 int ret; 1220 1221 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1222 return rte_flow_error_set(error, EINVAL, 1223 RTE_FLOW_ERROR_TYPE_ITEM, item, 1224 "protocol filtering not compatible" 1225 " with ICMP layer"); 1226 if (!(item_flags & l3m)) 1227 return rte_flow_error_set(error, EINVAL, 1228 RTE_FLOW_ERROR_TYPE_ITEM, item, 1229 "IPv4 is mandatory to filter" 1230 " on ICMP"); 1231 if (item_flags & l4m) 1232 return rte_flow_error_set(error, EINVAL, 1233 RTE_FLOW_ERROR_TYPE_ITEM, item, 1234 "multiple L4 layers not supported"); 1235 if (!mask) 1236 mask = &rte_flow_item_icmp_mask; 1237 ret = mlx5_flow_item_acceptable 1238 (item, (const uint8_t *)mask, 1239 (const uint8_t *)&rte_flow_item_icmp_mask, 1240 sizeof(struct rte_flow_item_icmp), error); 1241 if (ret < 0) 1242 return ret; 1243 return 0; 1244 } 1245 1246 /** 1247 * Validate Ethernet item. 1248 * 1249 * @param[in] item 1250 * Item specification. 1251 * @param[in] item_flags 1252 * Bit-fields that holds the items detected until now. 1253 * @param[out] error 1254 * Pointer to error structure. 1255 * 1256 * @return 1257 * 0 on success, a negative errno value otherwise and rte_errno is set. 1258 */ 1259 int 1260 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1261 uint64_t item_flags, 1262 struct rte_flow_error *error) 1263 { 1264 const struct rte_flow_item_eth *mask = item->mask; 1265 const struct rte_flow_item_eth nic_mask = { 1266 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1267 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1268 .type = RTE_BE16(0xffff), 1269 }; 1270 int ret; 1271 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1272 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1273 MLX5_FLOW_LAYER_OUTER_L2; 1274 1275 if (item_flags & ethm) 1276 return rte_flow_error_set(error, ENOTSUP, 1277 RTE_FLOW_ERROR_TYPE_ITEM, item, 1278 "multiple L2 layers not supported"); 1279 if (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3)) 1280 return rte_flow_error_set(error, EINVAL, 1281 RTE_FLOW_ERROR_TYPE_ITEM, item, 1282 "inner L2 layer should not " 1283 "follow inner L3 layers"); 1284 if (!mask) 1285 mask = &rte_flow_item_eth_mask; 1286 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1287 (const uint8_t *)&nic_mask, 1288 sizeof(struct rte_flow_item_eth), 1289 error); 1290 return ret; 1291 } 1292 1293 /** 1294 * Validate VLAN item. 1295 * 1296 * @param[in] item 1297 * Item specification. 1298 * @param[in] item_flags 1299 * Bit-fields that holds the items detected until now. 1300 * @param[in] dev 1301 * Ethernet device flow is being created on. 1302 * @param[out] error 1303 * Pointer to error structure. 1304 * 1305 * @return 1306 * 0 on success, a negative errno value otherwise and rte_errno is set. 1307 */ 1308 int 1309 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1310 uint64_t item_flags, 1311 struct rte_eth_dev *dev, 1312 struct rte_flow_error *error) 1313 { 1314 const struct rte_flow_item_vlan *spec = item->spec; 1315 const struct rte_flow_item_vlan *mask = item->mask; 1316 const struct rte_flow_item_vlan nic_mask = { 1317 .tci = RTE_BE16(UINT16_MAX), 1318 .inner_type = RTE_BE16(UINT16_MAX), 1319 }; 1320 uint16_t vlan_tag = 0; 1321 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1322 int ret; 1323 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1324 MLX5_FLOW_LAYER_INNER_L4) : 1325 (MLX5_FLOW_LAYER_OUTER_L3 | 1326 MLX5_FLOW_LAYER_OUTER_L4); 1327 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1328 MLX5_FLOW_LAYER_OUTER_VLAN; 1329 1330 const uint64_t l2m = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1331 MLX5_FLOW_LAYER_OUTER_L2; 1332 if (item_flags & vlanm) 1333 return rte_flow_error_set(error, EINVAL, 1334 RTE_FLOW_ERROR_TYPE_ITEM, item, 1335 "multiple VLAN layers not supported"); 1336 else if ((item_flags & l34m) != 0) 1337 return rte_flow_error_set(error, EINVAL, 1338 RTE_FLOW_ERROR_TYPE_ITEM, item, 1339 "L2 layer cannot follow L3/L4 layer"); 1340 else if ((item_flags & l2m) == 0) 1341 return rte_flow_error_set(error, EINVAL, 1342 RTE_FLOW_ERROR_TYPE_ITEM, item, 1343 "no L2 layer before VLAN"); 1344 if (!mask) 1345 mask = &rte_flow_item_vlan_mask; 1346 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1347 (const uint8_t *)&nic_mask, 1348 sizeof(struct rte_flow_item_vlan), 1349 error); 1350 if (ret) 1351 return ret; 1352 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1353 struct mlx5_priv *priv = dev->data->dev_private; 1354 1355 if (priv->vmwa_context) { 1356 /* 1357 * Non-NULL context means we have a virtual machine 1358 * and SR-IOV enabled, we have to create VLAN interface 1359 * to make hypervisor to setup E-Switch vport 1360 * context correctly. We avoid creating the multiple 1361 * VLAN interfaces, so we cannot support VLAN tag mask. 1362 */ 1363 return rte_flow_error_set(error, EINVAL, 1364 RTE_FLOW_ERROR_TYPE_ITEM, 1365 item, 1366 "VLAN tag mask is not" 1367 " supported in virtual" 1368 " environment"); 1369 } 1370 } 1371 if (spec) { 1372 vlan_tag = spec->tci; 1373 vlan_tag &= mask->tci; 1374 } 1375 /* 1376 * From verbs perspective an empty VLAN is equivalent 1377 * to a packet without VLAN layer. 1378 */ 1379 if (!vlan_tag) 1380 return rte_flow_error_set(error, EINVAL, 1381 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 1382 item->spec, 1383 "VLAN cannot be empty"); 1384 return 0; 1385 } 1386 1387 /** 1388 * Validate IPV4 item. 1389 * 1390 * @param[in] item 1391 * Item specification. 1392 * @param[in] item_flags 1393 * Bit-fields that holds the items detected until now. 1394 * @param[in] acc_mask 1395 * Acceptable mask, if NULL default internal default mask 1396 * will be used to check whether item fields are supported. 1397 * @param[out] error 1398 * Pointer to error structure. 1399 * 1400 * @return 1401 * 0 on success, a negative errno value otherwise and rte_errno is set. 1402 */ 1403 int 1404 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1405 uint64_t item_flags, 1406 uint64_t last_item, 1407 uint16_t ether_type, 1408 const struct rte_flow_item_ipv4 *acc_mask, 1409 struct rte_flow_error *error) 1410 { 1411 const struct rte_flow_item_ipv4 *mask = item->mask; 1412 const struct rte_flow_item_ipv4 *spec = item->spec; 1413 const struct rte_flow_item_ipv4 nic_mask = { 1414 .hdr = { 1415 .src_addr = RTE_BE32(0xffffffff), 1416 .dst_addr = RTE_BE32(0xffffffff), 1417 .type_of_service = 0xff, 1418 .next_proto_id = 0xff, 1419 }, 1420 }; 1421 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1422 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1423 MLX5_FLOW_LAYER_OUTER_L3; 1424 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1425 MLX5_FLOW_LAYER_OUTER_L4; 1426 int ret; 1427 uint8_t next_proto = 0xFF; 1428 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1429 MLX5_FLOW_LAYER_OUTER_VLAN | 1430 MLX5_FLOW_LAYER_INNER_VLAN); 1431 1432 if ((last_item & l2_vlan) && ether_type && 1433 ether_type != RTE_ETHER_TYPE_IPV4) 1434 return rte_flow_error_set(error, EINVAL, 1435 RTE_FLOW_ERROR_TYPE_ITEM, item, 1436 "IPv4 cannot follow L2/VLAN layer " 1437 "which ether type is not IPv4"); 1438 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 1439 if (mask && spec) 1440 next_proto = mask->hdr.next_proto_id & 1441 spec->hdr.next_proto_id; 1442 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1443 return rte_flow_error_set(error, EINVAL, 1444 RTE_FLOW_ERROR_TYPE_ITEM, 1445 item, 1446 "multiple tunnel " 1447 "not supported"); 1448 } 1449 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 1450 return rte_flow_error_set(error, EINVAL, 1451 RTE_FLOW_ERROR_TYPE_ITEM, item, 1452 "wrong tunnel type - IPv6 specified " 1453 "but IPv4 item provided"); 1454 if (item_flags & l3m) 1455 return rte_flow_error_set(error, ENOTSUP, 1456 RTE_FLOW_ERROR_TYPE_ITEM, item, 1457 "multiple L3 layers not supported"); 1458 else if (item_flags & l4m) 1459 return rte_flow_error_set(error, EINVAL, 1460 RTE_FLOW_ERROR_TYPE_ITEM, item, 1461 "L3 cannot follow an L4 layer."); 1462 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1463 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1464 return rte_flow_error_set(error, EINVAL, 1465 RTE_FLOW_ERROR_TYPE_ITEM, item, 1466 "L3 cannot follow an NVGRE layer."); 1467 else if (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L2)) 1468 return rte_flow_error_set(error, EINVAL, 1469 RTE_FLOW_ERROR_TYPE_ITEM, item, 1470 "no L2 layer before IPV4"); 1471 if (!mask) 1472 mask = &rte_flow_item_ipv4_mask; 1473 else if (mask->hdr.next_proto_id != 0 && 1474 mask->hdr.next_proto_id != 0xff) 1475 return rte_flow_error_set(error, EINVAL, 1476 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 1477 "partial mask is not supported" 1478 " for protocol"); 1479 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1480 acc_mask ? (const uint8_t *)acc_mask 1481 : (const uint8_t *)&nic_mask, 1482 sizeof(struct rte_flow_item_ipv4), 1483 error); 1484 if (ret < 0) 1485 return ret; 1486 return 0; 1487 } 1488 1489 /** 1490 * Validate IPV6 item. 1491 * 1492 * @param[in] item 1493 * Item specification. 1494 * @param[in] item_flags 1495 * Bit-fields that holds the items detected until now. 1496 * @param[in] acc_mask 1497 * Acceptable mask, if NULL default internal default mask 1498 * will be used to check whether item fields are supported. 1499 * @param[out] error 1500 * Pointer to error structure. 1501 * 1502 * @return 1503 * 0 on success, a negative errno value otherwise and rte_errno is set. 1504 */ 1505 int 1506 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1507 uint64_t item_flags, 1508 uint64_t last_item, 1509 uint16_t ether_type, 1510 const struct rte_flow_item_ipv6 *acc_mask, 1511 struct rte_flow_error *error) 1512 { 1513 const struct rte_flow_item_ipv6 *mask = item->mask; 1514 const struct rte_flow_item_ipv6 *spec = item->spec; 1515 const struct rte_flow_item_ipv6 nic_mask = { 1516 .hdr = { 1517 .src_addr = 1518 "\xff\xff\xff\xff\xff\xff\xff\xff" 1519 "\xff\xff\xff\xff\xff\xff\xff\xff", 1520 .dst_addr = 1521 "\xff\xff\xff\xff\xff\xff\xff\xff" 1522 "\xff\xff\xff\xff\xff\xff\xff\xff", 1523 .vtc_flow = RTE_BE32(0xffffffff), 1524 .proto = 0xff, 1525 .hop_limits = 0xff, 1526 }, 1527 }; 1528 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1529 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1530 MLX5_FLOW_LAYER_OUTER_L3; 1531 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1532 MLX5_FLOW_LAYER_OUTER_L4; 1533 int ret; 1534 uint8_t next_proto = 0xFF; 1535 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1536 MLX5_FLOW_LAYER_OUTER_VLAN | 1537 MLX5_FLOW_LAYER_INNER_VLAN); 1538 1539 if ((last_item & l2_vlan) && ether_type && 1540 ether_type != RTE_ETHER_TYPE_IPV6) 1541 return rte_flow_error_set(error, EINVAL, 1542 RTE_FLOW_ERROR_TYPE_ITEM, item, 1543 "IPv6 cannot follow L2/VLAN layer " 1544 "which ether type is not IPv6"); 1545 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 1546 if (mask && spec) 1547 next_proto = mask->hdr.proto & spec->hdr.proto; 1548 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1549 return rte_flow_error_set(error, EINVAL, 1550 RTE_FLOW_ERROR_TYPE_ITEM, 1551 item, 1552 "multiple tunnel " 1553 "not supported"); 1554 } 1555 if (item_flags & MLX5_FLOW_LAYER_IPIP) 1556 return rte_flow_error_set(error, EINVAL, 1557 RTE_FLOW_ERROR_TYPE_ITEM, item, 1558 "wrong tunnel type - IPv4 specified " 1559 "but IPv6 item provided"); 1560 if (item_flags & l3m) 1561 return rte_flow_error_set(error, ENOTSUP, 1562 RTE_FLOW_ERROR_TYPE_ITEM, item, 1563 "multiple L3 layers not supported"); 1564 else if (item_flags & l4m) 1565 return rte_flow_error_set(error, EINVAL, 1566 RTE_FLOW_ERROR_TYPE_ITEM, item, 1567 "L3 cannot follow an L4 layer."); 1568 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1569 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1570 return rte_flow_error_set(error, EINVAL, 1571 RTE_FLOW_ERROR_TYPE_ITEM, item, 1572 "L3 cannot follow an NVGRE layer."); 1573 else if (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L2)) 1574 return rte_flow_error_set(error, EINVAL, 1575 RTE_FLOW_ERROR_TYPE_ITEM, item, 1576 "no L2 layer before IPV6"); 1577 if (!mask) 1578 mask = &rte_flow_item_ipv6_mask; 1579 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1580 acc_mask ? (const uint8_t *)acc_mask 1581 : (const uint8_t *)&nic_mask, 1582 sizeof(struct rte_flow_item_ipv6), 1583 error); 1584 if (ret < 0) 1585 return ret; 1586 return 0; 1587 } 1588 1589 /** 1590 * Validate UDP item. 1591 * 1592 * @param[in] item 1593 * Item specification. 1594 * @param[in] item_flags 1595 * Bit-fields that holds the items detected until now. 1596 * @param[in] target_protocol 1597 * The next protocol in the previous item. 1598 * @param[in] flow_mask 1599 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 1600 * @param[out] error 1601 * Pointer to error structure. 1602 * 1603 * @return 1604 * 0 on success, a negative errno value otherwise and rte_errno is set. 1605 */ 1606 int 1607 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1608 uint64_t item_flags, 1609 uint8_t target_protocol, 1610 struct rte_flow_error *error) 1611 { 1612 const struct rte_flow_item_udp *mask = item->mask; 1613 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1614 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1615 MLX5_FLOW_LAYER_OUTER_L3; 1616 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1617 MLX5_FLOW_LAYER_OUTER_L4; 1618 int ret; 1619 1620 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 1621 return rte_flow_error_set(error, EINVAL, 1622 RTE_FLOW_ERROR_TYPE_ITEM, item, 1623 "protocol filtering not compatible" 1624 " with UDP layer"); 1625 if (!(item_flags & l3m)) 1626 return rte_flow_error_set(error, EINVAL, 1627 RTE_FLOW_ERROR_TYPE_ITEM, item, 1628 "L3 is mandatory to filter on L4"); 1629 if (item_flags & l4m) 1630 return rte_flow_error_set(error, EINVAL, 1631 RTE_FLOW_ERROR_TYPE_ITEM, item, 1632 "multiple L4 layers not supported"); 1633 if (!mask) 1634 mask = &rte_flow_item_udp_mask; 1635 ret = mlx5_flow_item_acceptable 1636 (item, (const uint8_t *)mask, 1637 (const uint8_t *)&rte_flow_item_udp_mask, 1638 sizeof(struct rte_flow_item_udp), error); 1639 if (ret < 0) 1640 return ret; 1641 return 0; 1642 } 1643 1644 /** 1645 * Validate TCP item. 1646 * 1647 * @param[in] item 1648 * Item specification. 1649 * @param[in] item_flags 1650 * Bit-fields that holds the items detected until now. 1651 * @param[in] target_protocol 1652 * The next protocol in the previous item. 1653 * @param[out] error 1654 * Pointer to error structure. 1655 * 1656 * @return 1657 * 0 on success, a negative errno value otherwise and rte_errno is set. 1658 */ 1659 int 1660 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1661 uint64_t item_flags, 1662 uint8_t target_protocol, 1663 const struct rte_flow_item_tcp *flow_mask, 1664 struct rte_flow_error *error) 1665 { 1666 const struct rte_flow_item_tcp *mask = item->mask; 1667 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1668 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1669 MLX5_FLOW_LAYER_OUTER_L3; 1670 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1671 MLX5_FLOW_LAYER_OUTER_L4; 1672 int ret; 1673 1674 assert(flow_mask); 1675 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 1676 return rte_flow_error_set(error, EINVAL, 1677 RTE_FLOW_ERROR_TYPE_ITEM, item, 1678 "protocol filtering not compatible" 1679 " with TCP layer"); 1680 if (!(item_flags & l3m)) 1681 return rte_flow_error_set(error, EINVAL, 1682 RTE_FLOW_ERROR_TYPE_ITEM, item, 1683 "L3 is mandatory to filter on L4"); 1684 if (item_flags & l4m) 1685 return rte_flow_error_set(error, EINVAL, 1686 RTE_FLOW_ERROR_TYPE_ITEM, item, 1687 "multiple L4 layers not supported"); 1688 if (!mask) 1689 mask = &rte_flow_item_tcp_mask; 1690 ret = mlx5_flow_item_acceptable 1691 (item, (const uint8_t *)mask, 1692 (const uint8_t *)flow_mask, 1693 sizeof(struct rte_flow_item_tcp), error); 1694 if (ret < 0) 1695 return ret; 1696 return 0; 1697 } 1698 1699 /** 1700 * Validate VXLAN item. 1701 * 1702 * @param[in] item 1703 * Item specification. 1704 * @param[in] item_flags 1705 * Bit-fields that holds the items detected until now. 1706 * @param[in] target_protocol 1707 * The next protocol in the previous item. 1708 * @param[out] error 1709 * Pointer to error structure. 1710 * 1711 * @return 1712 * 0 on success, a negative errno value otherwise and rte_errno is set. 1713 */ 1714 int 1715 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1716 uint64_t item_flags, 1717 struct rte_flow_error *error) 1718 { 1719 const struct rte_flow_item_vxlan *spec = item->spec; 1720 const struct rte_flow_item_vxlan *mask = item->mask; 1721 int ret; 1722 union vni { 1723 uint32_t vlan_id; 1724 uint8_t vni[4]; 1725 } id = { .vlan_id = 0, }; 1726 uint32_t vlan_id = 0; 1727 1728 1729 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1730 return rte_flow_error_set(error, ENOTSUP, 1731 RTE_FLOW_ERROR_TYPE_ITEM, item, 1732 "multiple tunnel layers not" 1733 " supported"); 1734 /* 1735 * Verify only UDPv4 is present as defined in 1736 * https://tools.ietf.org/html/rfc7348 1737 */ 1738 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1739 return rte_flow_error_set(error, EINVAL, 1740 RTE_FLOW_ERROR_TYPE_ITEM, item, 1741 "no outer UDP layer found"); 1742 if (!mask) 1743 mask = &rte_flow_item_vxlan_mask; 1744 ret = mlx5_flow_item_acceptable 1745 (item, (const uint8_t *)mask, 1746 (const uint8_t *)&rte_flow_item_vxlan_mask, 1747 sizeof(struct rte_flow_item_vxlan), 1748 error); 1749 if (ret < 0) 1750 return ret; 1751 if (spec) { 1752 memcpy(&id.vni[1], spec->vni, 3); 1753 vlan_id = id.vlan_id; 1754 memcpy(&id.vni[1], mask->vni, 3); 1755 vlan_id &= id.vlan_id; 1756 } 1757 /* 1758 * Tunnel id 0 is equivalent as not adding a VXLAN layer, if 1759 * only this layer is defined in the Verbs specification it is 1760 * interpreted as wildcard and all packets will match this 1761 * rule, if it follows a full stack layer (ex: eth / ipv4 / 1762 * udp), all packets matching the layers before will also 1763 * match this rule. To avoid such situation, VNI 0 is 1764 * currently refused. 1765 */ 1766 if (!vlan_id) 1767 return rte_flow_error_set(error, ENOTSUP, 1768 RTE_FLOW_ERROR_TYPE_ITEM, item, 1769 "VXLAN vni cannot be 0"); 1770 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1771 return rte_flow_error_set(error, ENOTSUP, 1772 RTE_FLOW_ERROR_TYPE_ITEM, item, 1773 "VXLAN tunnel must be fully defined"); 1774 return 0; 1775 } 1776 1777 /** 1778 * Validate VXLAN_GPE item. 1779 * 1780 * @param[in] item 1781 * Item specification. 1782 * @param[in] item_flags 1783 * Bit-fields that holds the items detected until now. 1784 * @param[in] priv 1785 * Pointer to the private data structure. 1786 * @param[in] target_protocol 1787 * The next protocol in the previous item. 1788 * @param[out] error 1789 * Pointer to error structure. 1790 * 1791 * @return 1792 * 0 on success, a negative errno value otherwise and rte_errno is set. 1793 */ 1794 int 1795 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1796 uint64_t item_flags, 1797 struct rte_eth_dev *dev, 1798 struct rte_flow_error *error) 1799 { 1800 struct mlx5_priv *priv = dev->data->dev_private; 1801 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 1802 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 1803 int ret; 1804 union vni { 1805 uint32_t vlan_id; 1806 uint8_t vni[4]; 1807 } id = { .vlan_id = 0, }; 1808 uint32_t vlan_id = 0; 1809 1810 if (!priv->config.l3_vxlan_en) 1811 return rte_flow_error_set(error, ENOTSUP, 1812 RTE_FLOW_ERROR_TYPE_ITEM, item, 1813 "L3 VXLAN is not enabled by device" 1814 " parameter and/or not configured in" 1815 " firmware"); 1816 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1817 return rte_flow_error_set(error, ENOTSUP, 1818 RTE_FLOW_ERROR_TYPE_ITEM, item, 1819 "multiple tunnel layers not" 1820 " supported"); 1821 /* 1822 * Verify only UDPv4 is present as defined in 1823 * https://tools.ietf.org/html/rfc7348 1824 */ 1825 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1826 return rte_flow_error_set(error, EINVAL, 1827 RTE_FLOW_ERROR_TYPE_ITEM, item, 1828 "no outer UDP layer found"); 1829 if (!mask) 1830 mask = &rte_flow_item_vxlan_gpe_mask; 1831 ret = mlx5_flow_item_acceptable 1832 (item, (const uint8_t *)mask, 1833 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 1834 sizeof(struct rte_flow_item_vxlan_gpe), 1835 error); 1836 if (ret < 0) 1837 return ret; 1838 if (spec) { 1839 if (spec->protocol) 1840 return rte_flow_error_set(error, ENOTSUP, 1841 RTE_FLOW_ERROR_TYPE_ITEM, 1842 item, 1843 "VxLAN-GPE protocol" 1844 " not supported"); 1845 memcpy(&id.vni[1], spec->vni, 3); 1846 vlan_id = id.vlan_id; 1847 memcpy(&id.vni[1], mask->vni, 3); 1848 vlan_id &= id.vlan_id; 1849 } 1850 /* 1851 * Tunnel id 0 is equivalent as not adding a VXLAN layer, if only this 1852 * layer is defined in the Verbs specification it is interpreted as 1853 * wildcard and all packets will match this rule, if it follows a full 1854 * stack layer (ex: eth / ipv4 / udp), all packets matching the layers 1855 * before will also match this rule. To avoid such situation, VNI 0 1856 * is currently refused. 1857 */ 1858 if (!vlan_id) 1859 return rte_flow_error_set(error, ENOTSUP, 1860 RTE_FLOW_ERROR_TYPE_ITEM, item, 1861 "VXLAN-GPE vni cannot be 0"); 1862 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1863 return rte_flow_error_set(error, ENOTSUP, 1864 RTE_FLOW_ERROR_TYPE_ITEM, item, 1865 "VXLAN-GPE tunnel must be fully" 1866 " defined"); 1867 return 0; 1868 } 1869 /** 1870 * Validate GRE Key item. 1871 * 1872 * @param[in] item 1873 * Item specification. 1874 * @param[in] item_flags 1875 * Bit flags to mark detected items. 1876 * @param[in] gre_item 1877 * Pointer to gre_item 1878 * @param[out] error 1879 * Pointer to error structure. 1880 * 1881 * @return 1882 * 0 on success, a negative errno value otherwise and rte_errno is set. 1883 */ 1884 int 1885 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1886 uint64_t item_flags, 1887 const struct rte_flow_item *gre_item, 1888 struct rte_flow_error *error) 1889 { 1890 const rte_be32_t *mask = item->mask; 1891 int ret = 0; 1892 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 1893 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 1894 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 1895 1896 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 1897 return rte_flow_error_set(error, ENOTSUP, 1898 RTE_FLOW_ERROR_TYPE_ITEM, item, 1899 "Multiple GRE key not support"); 1900 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 1901 return rte_flow_error_set(error, ENOTSUP, 1902 RTE_FLOW_ERROR_TYPE_ITEM, item, 1903 "No preceding GRE header"); 1904 if (item_flags & MLX5_FLOW_LAYER_INNER) 1905 return rte_flow_error_set(error, ENOTSUP, 1906 RTE_FLOW_ERROR_TYPE_ITEM, item, 1907 "GRE key following a wrong item"); 1908 if (!gre_mask) 1909 gre_mask = &rte_flow_item_gre_mask; 1910 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 1911 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 1912 return rte_flow_error_set(error, EINVAL, 1913 RTE_FLOW_ERROR_TYPE_ITEM, item, 1914 "Key bit must be on"); 1915 1916 if (!mask) 1917 mask = &gre_key_default_mask; 1918 ret = mlx5_flow_item_acceptable 1919 (item, (const uint8_t *)mask, 1920 (const uint8_t *)&gre_key_default_mask, 1921 sizeof(rte_be32_t), error); 1922 return ret; 1923 } 1924 1925 /** 1926 * Validate GRE item. 1927 * 1928 * @param[in] item 1929 * Item specification. 1930 * @param[in] item_flags 1931 * Bit flags to mark detected items. 1932 * @param[in] target_protocol 1933 * The next protocol in the previous item. 1934 * @param[out] error 1935 * Pointer to error structure. 1936 * 1937 * @return 1938 * 0 on success, a negative errno value otherwise and rte_errno is set. 1939 */ 1940 int 1941 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1942 uint64_t item_flags, 1943 uint8_t target_protocol, 1944 struct rte_flow_error *error) 1945 { 1946 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 1947 const struct rte_flow_item_gre *mask = item->mask; 1948 int ret; 1949 const struct rte_flow_item_gre nic_mask = { 1950 .c_rsvd0_ver = RTE_BE16(0xB000), 1951 .protocol = RTE_BE16(UINT16_MAX), 1952 }; 1953 1954 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 1955 return rte_flow_error_set(error, EINVAL, 1956 RTE_FLOW_ERROR_TYPE_ITEM, item, 1957 "protocol filtering not compatible" 1958 " with this GRE layer"); 1959 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1960 return rte_flow_error_set(error, ENOTSUP, 1961 RTE_FLOW_ERROR_TYPE_ITEM, item, 1962 "multiple tunnel layers not" 1963 " supported"); 1964 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 1965 return rte_flow_error_set(error, ENOTSUP, 1966 RTE_FLOW_ERROR_TYPE_ITEM, item, 1967 "L3 Layer is missing"); 1968 if (!mask) 1969 mask = &rte_flow_item_gre_mask; 1970 ret = mlx5_flow_item_acceptable 1971 (item, (const uint8_t *)mask, 1972 (const uint8_t *)&nic_mask, 1973 sizeof(struct rte_flow_item_gre), error); 1974 if (ret < 0) 1975 return ret; 1976 #ifndef HAVE_MLX5DV_DR 1977 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 1978 if (spec && (spec->protocol & mask->protocol)) 1979 return rte_flow_error_set(error, ENOTSUP, 1980 RTE_FLOW_ERROR_TYPE_ITEM, item, 1981 "without MPLS support the" 1982 " specification cannot be used for" 1983 " filtering"); 1984 #endif 1985 #endif 1986 return 0; 1987 } 1988 1989 /** 1990 * Validate Geneve item. 1991 * 1992 * @param[in] item 1993 * Item specification. 1994 * @param[in] itemFlags 1995 * Bit-fields that holds the items detected until now. 1996 * @param[in] enPriv 1997 * Pointer to the private data structure. 1998 * @param[out] error 1999 * Pointer to error structure. 2000 * 2001 * @return 2002 * 0 on success, a negative errno value otherwise and rte_errno is set. 2003 */ 2004 2005 int 2006 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2007 uint64_t item_flags, 2008 struct rte_eth_dev *dev, 2009 struct rte_flow_error *error) 2010 { 2011 struct mlx5_priv *priv = dev->data->dev_private; 2012 const struct rte_flow_item_geneve *spec = item->spec; 2013 const struct rte_flow_item_geneve *mask = item->mask; 2014 int ret; 2015 uint16_t gbhdr; 2016 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2017 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2018 const struct rte_flow_item_geneve nic_mask = { 2019 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2020 .vni = "\xff\xff\xff", 2021 .protocol = RTE_BE16(UINT16_MAX), 2022 }; 2023 2024 if (!(priv->config.hca_attr.flex_parser_protocols & 2025 MLX5_HCA_FLEX_GENEVE_ENABLED) || 2026 !priv->config.hca_attr.tunnel_stateless_geneve_rx) 2027 return rte_flow_error_set(error, ENOTSUP, 2028 RTE_FLOW_ERROR_TYPE_ITEM, item, 2029 "L3 Geneve is not enabled by device" 2030 " parameter and/or not configured in" 2031 " firmware"); 2032 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2033 return rte_flow_error_set(error, ENOTSUP, 2034 RTE_FLOW_ERROR_TYPE_ITEM, item, 2035 "multiple tunnel layers not" 2036 " supported"); 2037 /* 2038 * Verify only UDPv4 is present as defined in 2039 * https://tools.ietf.org/html/rfc7348 2040 */ 2041 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2042 return rte_flow_error_set(error, EINVAL, 2043 RTE_FLOW_ERROR_TYPE_ITEM, item, 2044 "no outer UDP layer found"); 2045 if (!mask) 2046 mask = &rte_flow_item_geneve_mask; 2047 ret = mlx5_flow_item_acceptable 2048 (item, (const uint8_t *)mask, 2049 (const uint8_t *)&nic_mask, 2050 sizeof(struct rte_flow_item_geneve), error); 2051 if (ret) 2052 return ret; 2053 if (spec) { 2054 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2055 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2056 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2057 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2058 return rte_flow_error_set(error, ENOTSUP, 2059 RTE_FLOW_ERROR_TYPE_ITEM, 2060 item, 2061 "Geneve protocol unsupported" 2062 " fields are being used"); 2063 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2064 return rte_flow_error_set 2065 (error, ENOTSUP, 2066 RTE_FLOW_ERROR_TYPE_ITEM, 2067 item, 2068 "Unsupported Geneve options length"); 2069 } 2070 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2071 return rte_flow_error_set 2072 (error, ENOTSUP, 2073 RTE_FLOW_ERROR_TYPE_ITEM, item, 2074 "Geneve tunnel must be fully defined"); 2075 return 0; 2076 } 2077 2078 /** 2079 * Validate MPLS item. 2080 * 2081 * @param[in] dev 2082 * Pointer to the rte_eth_dev structure. 2083 * @param[in] item 2084 * Item specification. 2085 * @param[in] item_flags 2086 * Bit-fields that holds the items detected until now. 2087 * @param[in] prev_layer 2088 * The protocol layer indicated in previous item. 2089 * @param[out] error 2090 * Pointer to error structure. 2091 * 2092 * @return 2093 * 0 on success, a negative errno value otherwise and rte_errno is set. 2094 */ 2095 int 2096 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 2097 const struct rte_flow_item *item __rte_unused, 2098 uint64_t item_flags __rte_unused, 2099 uint64_t prev_layer __rte_unused, 2100 struct rte_flow_error *error) 2101 { 2102 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2103 const struct rte_flow_item_mpls *mask = item->mask; 2104 struct mlx5_priv *priv = dev->data->dev_private; 2105 int ret; 2106 2107 if (!priv->config.mpls_en) 2108 return rte_flow_error_set(error, ENOTSUP, 2109 RTE_FLOW_ERROR_TYPE_ITEM, item, 2110 "MPLS not supported or" 2111 " disabled in firmware" 2112 " configuration."); 2113 /* MPLS over IP, UDP, GRE is allowed */ 2114 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 2115 MLX5_FLOW_LAYER_OUTER_L4_UDP | 2116 MLX5_FLOW_LAYER_GRE))) 2117 return rte_flow_error_set(error, EINVAL, 2118 RTE_FLOW_ERROR_TYPE_ITEM, item, 2119 "protocol filtering not compatible" 2120 " with MPLS layer"); 2121 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 2122 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 2123 !(item_flags & MLX5_FLOW_LAYER_GRE)) 2124 return rte_flow_error_set(error, ENOTSUP, 2125 RTE_FLOW_ERROR_TYPE_ITEM, item, 2126 "multiple tunnel layers not" 2127 " supported"); 2128 if (!mask) 2129 mask = &rte_flow_item_mpls_mask; 2130 ret = mlx5_flow_item_acceptable 2131 (item, (const uint8_t *)mask, 2132 (const uint8_t *)&rte_flow_item_mpls_mask, 2133 sizeof(struct rte_flow_item_mpls), error); 2134 if (ret < 0) 2135 return ret; 2136 return 0; 2137 #endif 2138 return rte_flow_error_set(error, ENOTSUP, 2139 RTE_FLOW_ERROR_TYPE_ITEM, item, 2140 "MPLS is not supported by Verbs, please" 2141 " update."); 2142 } 2143 2144 /** 2145 * Validate NVGRE item. 2146 * 2147 * @param[in] item 2148 * Item specification. 2149 * @param[in] item_flags 2150 * Bit flags to mark detected items. 2151 * @param[in] target_protocol 2152 * The next protocol in the previous item. 2153 * @param[out] error 2154 * Pointer to error structure. 2155 * 2156 * @return 2157 * 0 on success, a negative errno value otherwise and rte_errno is set. 2158 */ 2159 int 2160 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 2161 uint64_t item_flags, 2162 uint8_t target_protocol, 2163 struct rte_flow_error *error) 2164 { 2165 const struct rte_flow_item_nvgre *mask = item->mask; 2166 int ret; 2167 2168 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2169 return rte_flow_error_set(error, EINVAL, 2170 RTE_FLOW_ERROR_TYPE_ITEM, item, 2171 "protocol filtering not compatible" 2172 " with this GRE layer"); 2173 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2174 return rte_flow_error_set(error, ENOTSUP, 2175 RTE_FLOW_ERROR_TYPE_ITEM, item, 2176 "multiple tunnel layers not" 2177 " supported"); 2178 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2179 return rte_flow_error_set(error, ENOTSUP, 2180 RTE_FLOW_ERROR_TYPE_ITEM, item, 2181 "L3 Layer is missing"); 2182 if (!mask) 2183 mask = &rte_flow_item_nvgre_mask; 2184 ret = mlx5_flow_item_acceptable 2185 (item, (const uint8_t *)mask, 2186 (const uint8_t *)&rte_flow_item_nvgre_mask, 2187 sizeof(struct rte_flow_item_nvgre), error); 2188 if (ret < 0) 2189 return ret; 2190 return 0; 2191 } 2192 2193 static int 2194 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 2195 const struct rte_flow_attr *attr __rte_unused, 2196 const struct rte_flow_item items[] __rte_unused, 2197 const struct rte_flow_action actions[] __rte_unused, 2198 bool external __rte_unused, 2199 struct rte_flow_error *error) 2200 { 2201 return rte_flow_error_set(error, ENOTSUP, 2202 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2203 } 2204 2205 static struct mlx5_flow * 2206 flow_null_prepare(const struct rte_flow_attr *attr __rte_unused, 2207 const struct rte_flow_item items[] __rte_unused, 2208 const struct rte_flow_action actions[] __rte_unused, 2209 struct rte_flow_error *error) 2210 { 2211 rte_flow_error_set(error, ENOTSUP, 2212 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2213 return NULL; 2214 } 2215 2216 static int 2217 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 2218 struct mlx5_flow *dev_flow __rte_unused, 2219 const struct rte_flow_attr *attr __rte_unused, 2220 const struct rte_flow_item items[] __rte_unused, 2221 const struct rte_flow_action actions[] __rte_unused, 2222 struct rte_flow_error *error) 2223 { 2224 return rte_flow_error_set(error, ENOTSUP, 2225 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2226 } 2227 2228 static int 2229 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 2230 struct rte_flow *flow __rte_unused, 2231 struct rte_flow_error *error) 2232 { 2233 return rte_flow_error_set(error, ENOTSUP, 2234 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2235 } 2236 2237 static void 2238 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 2239 struct rte_flow *flow __rte_unused) 2240 { 2241 } 2242 2243 static void 2244 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 2245 struct rte_flow *flow __rte_unused) 2246 { 2247 } 2248 2249 static int 2250 flow_null_query(struct rte_eth_dev *dev __rte_unused, 2251 struct rte_flow *flow __rte_unused, 2252 const struct rte_flow_action *actions __rte_unused, 2253 void *data __rte_unused, 2254 struct rte_flow_error *error) 2255 { 2256 return rte_flow_error_set(error, ENOTSUP, 2257 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2258 } 2259 2260 /* Void driver to protect from null pointer reference. */ 2261 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 2262 .validate = flow_null_validate, 2263 .prepare = flow_null_prepare, 2264 .translate = flow_null_translate, 2265 .apply = flow_null_apply, 2266 .remove = flow_null_remove, 2267 .destroy = flow_null_destroy, 2268 .query = flow_null_query, 2269 }; 2270 2271 /** 2272 * Select flow driver type according to flow attributes and device 2273 * configuration. 2274 * 2275 * @param[in] dev 2276 * Pointer to the dev structure. 2277 * @param[in] attr 2278 * Pointer to the flow attributes. 2279 * 2280 * @return 2281 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 2282 */ 2283 static enum mlx5_flow_drv_type 2284 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 2285 { 2286 struct mlx5_priv *priv = dev->data->dev_private; 2287 enum mlx5_flow_drv_type type = MLX5_FLOW_TYPE_MAX; 2288 2289 if (attr->transfer && priv->config.dv_esw_en) 2290 type = MLX5_FLOW_TYPE_DV; 2291 if (!attr->transfer) 2292 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 2293 MLX5_FLOW_TYPE_VERBS; 2294 return type; 2295 } 2296 2297 #define flow_get_drv_ops(type) flow_drv_ops[type] 2298 2299 /** 2300 * Flow driver validation API. This abstracts calling driver specific functions. 2301 * The type of flow driver is determined according to flow attributes. 2302 * 2303 * @param[in] dev 2304 * Pointer to the dev structure. 2305 * @param[in] attr 2306 * Pointer to the flow attributes. 2307 * @param[in] items 2308 * Pointer to the list of items. 2309 * @param[in] actions 2310 * Pointer to the list of actions. 2311 * @param[in] external 2312 * This flow rule is created by request external to PMD. 2313 * @param[out] error 2314 * Pointer to the error structure. 2315 * 2316 * @return 2317 * 0 on success, a negative errno value otherwise and rte_errno is set. 2318 */ 2319 static inline int 2320 flow_drv_validate(struct rte_eth_dev *dev, 2321 const struct rte_flow_attr *attr, 2322 const struct rte_flow_item items[], 2323 const struct rte_flow_action actions[], 2324 bool external, struct rte_flow_error *error) 2325 { 2326 const struct mlx5_flow_driver_ops *fops; 2327 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 2328 2329 fops = flow_get_drv_ops(type); 2330 return fops->validate(dev, attr, items, actions, external, error); 2331 } 2332 2333 /** 2334 * Flow driver preparation API. This abstracts calling driver specific 2335 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2336 * calculates the size of memory required for device flow, allocates the memory, 2337 * initializes the device flow and returns the pointer. 2338 * 2339 * @note 2340 * This function initializes device flow structure such as dv or verbs in 2341 * struct mlx5_flow. However, it is caller's responsibility to initialize the 2342 * rest. For example, adding returning device flow to flow->dev_flow list and 2343 * setting backward reference to the flow should be done out of this function. 2344 * layers field is not filled either. 2345 * 2346 * @param[in] attr 2347 * Pointer to the flow attributes. 2348 * @param[in] items 2349 * Pointer to the list of items. 2350 * @param[in] actions 2351 * Pointer to the list of actions. 2352 * @param[out] error 2353 * Pointer to the error structure. 2354 * 2355 * @return 2356 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 2357 */ 2358 static inline struct mlx5_flow * 2359 flow_drv_prepare(const struct rte_flow *flow, 2360 const struct rte_flow_attr *attr, 2361 const struct rte_flow_item items[], 2362 const struct rte_flow_action actions[], 2363 struct rte_flow_error *error) 2364 { 2365 const struct mlx5_flow_driver_ops *fops; 2366 enum mlx5_flow_drv_type type = flow->drv_type; 2367 2368 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2369 fops = flow_get_drv_ops(type); 2370 return fops->prepare(attr, items, actions, error); 2371 } 2372 2373 /** 2374 * Flow driver translation API. This abstracts calling driver specific 2375 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2376 * translates a generic flow into a driver flow. flow_drv_prepare() must 2377 * precede. 2378 * 2379 * @note 2380 * dev_flow->layers could be filled as a result of parsing during translation 2381 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 2382 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 2383 * flow->actions could be overwritten even though all the expanded dev_flows 2384 * have the same actions. 2385 * 2386 * @param[in] dev 2387 * Pointer to the rte dev structure. 2388 * @param[in, out] dev_flow 2389 * Pointer to the mlx5 flow. 2390 * @param[in] attr 2391 * Pointer to the flow attributes. 2392 * @param[in] items 2393 * Pointer to the list of items. 2394 * @param[in] actions 2395 * Pointer to the list of actions. 2396 * @param[out] error 2397 * Pointer to the error structure. 2398 * 2399 * @return 2400 * 0 on success, a negative errno value otherwise and rte_errno is set. 2401 */ 2402 static inline int 2403 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 2404 const struct rte_flow_attr *attr, 2405 const struct rte_flow_item items[], 2406 const struct rte_flow_action actions[], 2407 struct rte_flow_error *error) 2408 { 2409 const struct mlx5_flow_driver_ops *fops; 2410 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 2411 2412 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2413 fops = flow_get_drv_ops(type); 2414 return fops->translate(dev, dev_flow, attr, items, actions, error); 2415 } 2416 2417 /** 2418 * Flow driver apply API. This abstracts calling driver specific functions. 2419 * Parent flow (rte_flow) should have driver type (drv_type). It applies 2420 * translated driver flows on to device. flow_drv_translate() must precede. 2421 * 2422 * @param[in] dev 2423 * Pointer to Ethernet device structure. 2424 * @param[in, out] flow 2425 * Pointer to flow structure. 2426 * @param[out] error 2427 * Pointer to error structure. 2428 * 2429 * @return 2430 * 0 on success, a negative errno value otherwise and rte_errno is set. 2431 */ 2432 static inline int 2433 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 2434 struct rte_flow_error *error) 2435 { 2436 const struct mlx5_flow_driver_ops *fops; 2437 enum mlx5_flow_drv_type type = flow->drv_type; 2438 2439 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2440 fops = flow_get_drv_ops(type); 2441 return fops->apply(dev, flow, error); 2442 } 2443 2444 /** 2445 * Flow driver remove API. This abstracts calling driver specific functions. 2446 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2447 * on device. All the resources of the flow should be freed by calling 2448 * flow_drv_destroy(). 2449 * 2450 * @param[in] dev 2451 * Pointer to Ethernet device. 2452 * @param[in, out] flow 2453 * Pointer to flow structure. 2454 */ 2455 static inline void 2456 flow_drv_remove(struct rte_eth_dev *dev, struct rte_flow *flow) 2457 { 2458 const struct mlx5_flow_driver_ops *fops; 2459 enum mlx5_flow_drv_type type = flow->drv_type; 2460 2461 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2462 fops = flow_get_drv_ops(type); 2463 fops->remove(dev, flow); 2464 } 2465 2466 /** 2467 * Flow driver destroy API. This abstracts calling driver specific functions. 2468 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2469 * on device and releases resources of the flow. 2470 * 2471 * @param[in] dev 2472 * Pointer to Ethernet device. 2473 * @param[in, out] flow 2474 * Pointer to flow structure. 2475 */ 2476 static inline void 2477 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 2478 { 2479 const struct mlx5_flow_driver_ops *fops; 2480 enum mlx5_flow_drv_type type = flow->drv_type; 2481 2482 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2483 fops = flow_get_drv_ops(type); 2484 fops->destroy(dev, flow); 2485 } 2486 2487 /** 2488 * Validate a flow supported by the NIC. 2489 * 2490 * @see rte_flow_validate() 2491 * @see rte_flow_ops 2492 */ 2493 int 2494 mlx5_flow_validate(struct rte_eth_dev *dev, 2495 const struct rte_flow_attr *attr, 2496 const struct rte_flow_item items[], 2497 const struct rte_flow_action actions[], 2498 struct rte_flow_error *error) 2499 { 2500 int ret; 2501 2502 ret = flow_drv_validate(dev, attr, items, actions, true, error); 2503 if (ret < 0) 2504 return ret; 2505 return 0; 2506 } 2507 2508 /** 2509 * Get RSS action from the action list. 2510 * 2511 * @param[in] actions 2512 * Pointer to the list of actions. 2513 * 2514 * @return 2515 * Pointer to the RSS action if exist, else return NULL. 2516 */ 2517 static const struct rte_flow_action_rss* 2518 flow_get_rss_action(const struct rte_flow_action actions[]) 2519 { 2520 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2521 switch (actions->type) { 2522 case RTE_FLOW_ACTION_TYPE_RSS: 2523 return (const struct rte_flow_action_rss *) 2524 actions->conf; 2525 default: 2526 break; 2527 } 2528 } 2529 return NULL; 2530 } 2531 2532 static unsigned int 2533 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 2534 { 2535 const struct rte_flow_item *item; 2536 unsigned int has_vlan = 0; 2537 2538 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2539 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 2540 has_vlan = 1; 2541 break; 2542 } 2543 } 2544 if (has_vlan) 2545 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 2546 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 2547 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 2548 MLX5_EXPANSION_ROOT_OUTER; 2549 } 2550 2551 /** 2552 * Check if the flow should be splited due to hairpin. 2553 * The reason for the split is that in current HW we can't 2554 * support encap on Rx, so if a flow have encap we move it 2555 * to Tx. 2556 * 2557 * @param dev 2558 * Pointer to Ethernet device. 2559 * @param[in] attr 2560 * Flow rule attributes. 2561 * @param[in] actions 2562 * Associated actions (list terminated by the END action). 2563 * 2564 * @return 2565 * > 0 the number of actions and the flow should be split, 2566 * 0 when no split required. 2567 */ 2568 static int 2569 flow_check_hairpin_split(struct rte_eth_dev *dev, 2570 const struct rte_flow_attr *attr, 2571 const struct rte_flow_action actions[]) 2572 { 2573 int queue_action = 0; 2574 int action_n = 0; 2575 int encap = 0; 2576 const struct rte_flow_action_queue *queue; 2577 const struct rte_flow_action_rss *rss; 2578 const struct rte_flow_action_raw_encap *raw_encap; 2579 2580 if (!attr->ingress) 2581 return 0; 2582 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2583 switch (actions->type) { 2584 case RTE_FLOW_ACTION_TYPE_QUEUE: 2585 queue = actions->conf; 2586 if (mlx5_rxq_get_type(dev, queue->index) != 2587 MLX5_RXQ_TYPE_HAIRPIN) 2588 return 0; 2589 queue_action = 1; 2590 action_n++; 2591 break; 2592 case RTE_FLOW_ACTION_TYPE_RSS: 2593 rss = actions->conf; 2594 if (mlx5_rxq_get_type(dev, rss->queue[0]) != 2595 MLX5_RXQ_TYPE_HAIRPIN) 2596 return 0; 2597 queue_action = 1; 2598 action_n++; 2599 break; 2600 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 2601 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 2602 encap = 1; 2603 action_n++; 2604 break; 2605 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 2606 raw_encap = actions->conf; 2607 if (raw_encap->size > 2608 (sizeof(struct rte_flow_item_eth) + 2609 sizeof(struct rte_flow_item_ipv4))) 2610 encap = 1; 2611 action_n++; 2612 break; 2613 default: 2614 action_n++; 2615 break; 2616 } 2617 } 2618 if (encap == 1 && queue_action) 2619 return action_n; 2620 return 0; 2621 } 2622 2623 #define MLX5_MAX_SPLIT_ACTIONS 24 2624 #define MLX5_MAX_SPLIT_ITEMS 24 2625 2626 /** 2627 * Split the hairpin flow. 2628 * Since HW can't support encap on Rx we move the encap to Tx. 2629 * If the count action is after the encap then we also 2630 * move the count action. in this case the count will also measure 2631 * the outer bytes. 2632 * 2633 * @param dev 2634 * Pointer to Ethernet device. 2635 * @param[in] actions 2636 * Associated actions (list terminated by the END action). 2637 * @param[out] actions_rx 2638 * Rx flow actions. 2639 * @param[out] actions_tx 2640 * Tx flow actions.. 2641 * @param[out] pattern_tx 2642 * The pattern items for the Tx flow. 2643 * @param[out] flow_id 2644 * The flow ID connected to this flow. 2645 * 2646 * @return 2647 * 0 on success. 2648 */ 2649 static int 2650 flow_hairpin_split(struct rte_eth_dev *dev, 2651 const struct rte_flow_action actions[], 2652 struct rte_flow_action actions_rx[], 2653 struct rte_flow_action actions_tx[], 2654 struct rte_flow_item pattern_tx[], 2655 uint32_t *flow_id) 2656 { 2657 struct mlx5_priv *priv = dev->data->dev_private; 2658 const struct rte_flow_action_raw_encap *raw_encap; 2659 const struct rte_flow_action_raw_decap *raw_decap; 2660 struct mlx5_rte_flow_action_set_tag *set_tag; 2661 struct rte_flow_action *tag_action; 2662 struct mlx5_rte_flow_item_tag *tag_item; 2663 struct rte_flow_item *item; 2664 char *addr; 2665 struct rte_flow_error error; 2666 int encap = 0; 2667 2668 mlx5_flow_id_get(priv->sh->flow_id_pool, flow_id); 2669 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2670 switch (actions->type) { 2671 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 2672 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 2673 rte_memcpy(actions_tx, actions, 2674 sizeof(struct rte_flow_action)); 2675 actions_tx++; 2676 break; 2677 case RTE_FLOW_ACTION_TYPE_COUNT: 2678 if (encap) { 2679 rte_memcpy(actions_tx, actions, 2680 sizeof(struct rte_flow_action)); 2681 actions_tx++; 2682 } else { 2683 rte_memcpy(actions_rx, actions, 2684 sizeof(struct rte_flow_action)); 2685 actions_rx++; 2686 } 2687 break; 2688 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 2689 raw_encap = actions->conf; 2690 if (raw_encap->size > 2691 (sizeof(struct rte_flow_item_eth) + 2692 sizeof(struct rte_flow_item_ipv4))) { 2693 memcpy(actions_tx, actions, 2694 sizeof(struct rte_flow_action)); 2695 actions_tx++; 2696 encap = 1; 2697 } else { 2698 rte_memcpy(actions_rx, actions, 2699 sizeof(struct rte_flow_action)); 2700 actions_rx++; 2701 } 2702 break; 2703 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 2704 raw_decap = actions->conf; 2705 if (raw_decap->size < 2706 (sizeof(struct rte_flow_item_eth) + 2707 sizeof(struct rte_flow_item_ipv4))) { 2708 memcpy(actions_tx, actions, 2709 sizeof(struct rte_flow_action)); 2710 actions_tx++; 2711 } else { 2712 rte_memcpy(actions_rx, actions, 2713 sizeof(struct rte_flow_action)); 2714 actions_rx++; 2715 } 2716 break; 2717 default: 2718 rte_memcpy(actions_rx, actions, 2719 sizeof(struct rte_flow_action)); 2720 actions_rx++; 2721 break; 2722 } 2723 } 2724 /* Add set meta action and end action for the Rx flow. */ 2725 tag_action = actions_rx; 2726 tag_action->type = MLX5_RTE_FLOW_ACTION_TYPE_TAG; 2727 actions_rx++; 2728 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 2729 actions_rx++; 2730 set_tag = (void *)actions_rx; 2731 set_tag->id = flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, &error); 2732 set_tag->data = rte_cpu_to_be_32(*flow_id); 2733 tag_action->conf = set_tag; 2734 /* Create Tx item list. */ 2735 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 2736 addr = (void *)&pattern_tx[2]; 2737 item = pattern_tx; 2738 item->type = MLX5_RTE_FLOW_ITEM_TYPE_TAG; 2739 tag_item = (void *)addr; 2740 tag_item->data = rte_cpu_to_be_32(*flow_id); 2741 tag_item->id = flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, &error); 2742 item->spec = tag_item; 2743 addr += sizeof(struct mlx5_rte_flow_item_tag); 2744 tag_item = (void *)addr; 2745 tag_item->data = UINT32_MAX; 2746 tag_item->id = UINT16_MAX; 2747 item->mask = tag_item; 2748 addr += sizeof(struct mlx5_rte_flow_item_tag); 2749 item->last = NULL; 2750 item++; 2751 item->type = RTE_FLOW_ITEM_TYPE_END; 2752 return 0; 2753 } 2754 2755 /** 2756 * Create a flow and add it to @p list. 2757 * 2758 * @param dev 2759 * Pointer to Ethernet device. 2760 * @param list 2761 * Pointer to a TAILQ flow list. 2762 * @param[in] attr 2763 * Flow rule attributes. 2764 * @param[in] items 2765 * Pattern specification (list terminated by the END pattern item). 2766 * @param[in] actions 2767 * Associated actions (list terminated by the END action). 2768 * @param[in] external 2769 * This flow rule is created by request external to PMD. 2770 * @param[out] error 2771 * Perform verbose error reporting if not NULL. 2772 * 2773 * @return 2774 * A flow on success, NULL otherwise and rte_errno is set. 2775 */ 2776 static struct rte_flow * 2777 flow_list_create(struct rte_eth_dev *dev, struct mlx5_flows *list, 2778 const struct rte_flow_attr *attr, 2779 const struct rte_flow_item items[], 2780 const struct rte_flow_action actions[], 2781 bool external, struct rte_flow_error *error) 2782 { 2783 struct mlx5_priv *priv = dev->data->dev_private; 2784 struct rte_flow *flow = NULL; 2785 struct mlx5_flow *dev_flow; 2786 const struct rte_flow_action_rss *rss; 2787 union { 2788 struct rte_flow_expand_rss buf; 2789 uint8_t buffer[2048]; 2790 } expand_buffer; 2791 union { 2792 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 2793 uint8_t buffer[2048]; 2794 } actions_rx; 2795 union { 2796 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 2797 uint8_t buffer[2048]; 2798 } actions_hairpin_tx; 2799 union { 2800 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 2801 uint8_t buffer[2048]; 2802 } items_tx; 2803 struct rte_flow_expand_rss *buf = &expand_buffer.buf; 2804 const struct rte_flow_action *p_actions_rx = actions; 2805 int ret; 2806 uint32_t i; 2807 uint32_t flow_size; 2808 int hairpin_flow = 0; 2809 uint32_t hairpin_id = 0; 2810 struct rte_flow_attr attr_tx = { .priority = 0 }; 2811 2812 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 2813 if (hairpin_flow > 0) { 2814 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 2815 rte_errno = EINVAL; 2816 return NULL; 2817 } 2818 flow_hairpin_split(dev, actions, actions_rx.actions, 2819 actions_hairpin_tx.actions, items_tx.items, 2820 &hairpin_id); 2821 p_actions_rx = actions_rx.actions; 2822 } 2823 ret = flow_drv_validate(dev, attr, items, p_actions_rx, external, 2824 error); 2825 if (ret < 0) 2826 goto error_before_flow; 2827 flow_size = sizeof(struct rte_flow); 2828 rss = flow_get_rss_action(p_actions_rx); 2829 if (rss) 2830 flow_size += RTE_ALIGN_CEIL(rss->queue_num * sizeof(uint16_t), 2831 sizeof(void *)); 2832 else 2833 flow_size += RTE_ALIGN_CEIL(sizeof(uint16_t), sizeof(void *)); 2834 flow = rte_calloc(__func__, 1, flow_size, 0); 2835 if (!flow) { 2836 rte_errno = ENOMEM; 2837 goto error_before_flow; 2838 } 2839 flow->drv_type = flow_get_drv_type(dev, attr); 2840 flow->ingress = attr->ingress; 2841 flow->transfer = attr->transfer; 2842 if (hairpin_id != 0) 2843 flow->hairpin_flow_id = hairpin_id; 2844 assert(flow->drv_type > MLX5_FLOW_TYPE_MIN && 2845 flow->drv_type < MLX5_FLOW_TYPE_MAX); 2846 flow->queue = (void *)(flow + 1); 2847 LIST_INIT(&flow->dev_flows); 2848 if (rss && rss->types) { 2849 unsigned int graph_root; 2850 2851 graph_root = find_graph_root(items, rss->level); 2852 ret = rte_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 2853 items, rss->types, 2854 mlx5_support_expansion, 2855 graph_root); 2856 assert(ret > 0 && 2857 (unsigned int)ret < sizeof(expand_buffer.buffer)); 2858 } else { 2859 buf->entries = 1; 2860 buf->entry[0].pattern = (void *)(uintptr_t)items; 2861 } 2862 for (i = 0; i < buf->entries; ++i) { 2863 dev_flow = flow_drv_prepare(flow, attr, buf->entry[i].pattern, 2864 p_actions_rx, error); 2865 if (!dev_flow) 2866 goto error; 2867 dev_flow->flow = flow; 2868 dev_flow->external = external; 2869 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next); 2870 ret = flow_drv_translate(dev, dev_flow, attr, 2871 buf->entry[i].pattern, 2872 p_actions_rx, error); 2873 if (ret < 0) 2874 goto error; 2875 } 2876 /* Create the tx flow. */ 2877 if (hairpin_flow) { 2878 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 2879 attr_tx.ingress = 0; 2880 attr_tx.egress = 1; 2881 dev_flow = flow_drv_prepare(flow, &attr_tx, items_tx.items, 2882 actions_hairpin_tx.actions, error); 2883 if (!dev_flow) 2884 goto error; 2885 dev_flow->flow = flow; 2886 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next); 2887 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 2888 items_tx.items, 2889 actions_hairpin_tx.actions, error); 2890 if (ret < 0) 2891 goto error; 2892 } 2893 if (dev->data->dev_started) { 2894 ret = flow_drv_apply(dev, flow, error); 2895 if (ret < 0) 2896 goto error; 2897 } 2898 TAILQ_INSERT_TAIL(list, flow, next); 2899 flow_rxq_flags_set(dev, flow); 2900 return flow; 2901 error_before_flow: 2902 if (hairpin_id) 2903 mlx5_flow_id_release(priv->sh->flow_id_pool, 2904 hairpin_id); 2905 return NULL; 2906 error: 2907 ret = rte_errno; /* Save rte_errno before cleanup. */ 2908 if (flow->hairpin_flow_id) 2909 mlx5_flow_id_release(priv->sh->flow_id_pool, 2910 flow->hairpin_flow_id); 2911 assert(flow); 2912 flow_drv_destroy(dev, flow); 2913 rte_free(flow); 2914 rte_errno = ret; /* Restore rte_errno. */ 2915 return NULL; 2916 } 2917 2918 /** 2919 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 2920 * incoming packets to table 1. 2921 * 2922 * Other flow rules, requested for group n, will be created in 2923 * e-switch table n+1. 2924 * Jump action to e-switch group n will be created to group n+1. 2925 * 2926 * Used when working in switchdev mode, to utilise advantages of table 1 2927 * and above. 2928 * 2929 * @param dev 2930 * Pointer to Ethernet device. 2931 * 2932 * @return 2933 * Pointer to flow on success, NULL otherwise and rte_errno is set. 2934 */ 2935 struct rte_flow * 2936 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 2937 { 2938 const struct rte_flow_attr attr = { 2939 .group = 0, 2940 .priority = 0, 2941 .ingress = 1, 2942 .egress = 0, 2943 .transfer = 1, 2944 }; 2945 const struct rte_flow_item pattern = { 2946 .type = RTE_FLOW_ITEM_TYPE_END, 2947 }; 2948 struct rte_flow_action_jump jump = { 2949 .group = 1, 2950 }; 2951 const struct rte_flow_action actions[] = { 2952 { 2953 .type = RTE_FLOW_ACTION_TYPE_JUMP, 2954 .conf = &jump, 2955 }, 2956 { 2957 .type = RTE_FLOW_ACTION_TYPE_END, 2958 }, 2959 }; 2960 struct mlx5_priv *priv = dev->data->dev_private; 2961 struct rte_flow_error error; 2962 2963 return flow_list_create(dev, &priv->ctrl_flows, &attr, &pattern, 2964 actions, false, &error); 2965 } 2966 2967 /** 2968 * Create a flow. 2969 * 2970 * @see rte_flow_create() 2971 * @see rte_flow_ops 2972 */ 2973 struct rte_flow * 2974 mlx5_flow_create(struct rte_eth_dev *dev, 2975 const struct rte_flow_attr *attr, 2976 const struct rte_flow_item items[], 2977 const struct rte_flow_action actions[], 2978 struct rte_flow_error *error) 2979 { 2980 struct mlx5_priv *priv = dev->data->dev_private; 2981 2982 return flow_list_create(dev, &priv->flows, 2983 attr, items, actions, true, error); 2984 } 2985 2986 /** 2987 * Destroy a flow in a list. 2988 * 2989 * @param dev 2990 * Pointer to Ethernet device. 2991 * @param list 2992 * Pointer to a TAILQ flow list. 2993 * @param[in] flow 2994 * Flow to destroy. 2995 */ 2996 static void 2997 flow_list_destroy(struct rte_eth_dev *dev, struct mlx5_flows *list, 2998 struct rte_flow *flow) 2999 { 3000 struct mlx5_priv *priv = dev->data->dev_private; 3001 3002 /* 3003 * Update RX queue flags only if port is started, otherwise it is 3004 * already clean. 3005 */ 3006 if (dev->data->dev_started) 3007 flow_rxq_flags_trim(dev, flow); 3008 if (flow->hairpin_flow_id) 3009 mlx5_flow_id_release(priv->sh->flow_id_pool, 3010 flow->hairpin_flow_id); 3011 flow_drv_destroy(dev, flow); 3012 TAILQ_REMOVE(list, flow, next); 3013 rte_free(flow->fdir); 3014 rte_free(flow); 3015 } 3016 3017 /** 3018 * Destroy all flows. 3019 * 3020 * @param dev 3021 * Pointer to Ethernet device. 3022 * @param list 3023 * Pointer to a TAILQ flow list. 3024 */ 3025 void 3026 mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list) 3027 { 3028 while (!TAILQ_EMPTY(list)) { 3029 struct rte_flow *flow; 3030 3031 flow = TAILQ_FIRST(list); 3032 flow_list_destroy(dev, list, flow); 3033 } 3034 } 3035 3036 /** 3037 * Remove all flows. 3038 * 3039 * @param dev 3040 * Pointer to Ethernet device. 3041 * @param list 3042 * Pointer to a TAILQ flow list. 3043 */ 3044 void 3045 mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list) 3046 { 3047 struct rte_flow *flow; 3048 3049 TAILQ_FOREACH_REVERSE(flow, list, mlx5_flows, next) 3050 flow_drv_remove(dev, flow); 3051 flow_rxq_flags_clear(dev); 3052 } 3053 3054 /** 3055 * Add all flows. 3056 * 3057 * @param dev 3058 * Pointer to Ethernet device. 3059 * @param list 3060 * Pointer to a TAILQ flow list. 3061 * 3062 * @return 3063 * 0 on success, a negative errno value otherwise and rte_errno is set. 3064 */ 3065 int 3066 mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list) 3067 { 3068 struct rte_flow *flow; 3069 struct rte_flow_error error; 3070 int ret = 0; 3071 3072 TAILQ_FOREACH(flow, list, next) { 3073 ret = flow_drv_apply(dev, flow, &error); 3074 if (ret < 0) 3075 goto error; 3076 flow_rxq_flags_set(dev, flow); 3077 } 3078 return 0; 3079 error: 3080 ret = rte_errno; /* Save rte_errno before cleanup. */ 3081 mlx5_flow_stop(dev, list); 3082 rte_errno = ret; /* Restore rte_errno. */ 3083 return -rte_errno; 3084 } 3085 3086 /** 3087 * Verify the flow list is empty 3088 * 3089 * @param dev 3090 * Pointer to Ethernet device. 3091 * 3092 * @return the number of flows not released. 3093 */ 3094 int 3095 mlx5_flow_verify(struct rte_eth_dev *dev) 3096 { 3097 struct mlx5_priv *priv = dev->data->dev_private; 3098 struct rte_flow *flow; 3099 int ret = 0; 3100 3101 TAILQ_FOREACH(flow, &priv->flows, next) { 3102 DRV_LOG(DEBUG, "port %u flow %p still referenced", 3103 dev->data->port_id, (void *)flow); 3104 ++ret; 3105 } 3106 return ret; 3107 } 3108 3109 /** 3110 * Enable default hairpin egress flow. 3111 * 3112 * @param dev 3113 * Pointer to Ethernet device. 3114 * @param queue 3115 * The queue index. 3116 * 3117 * @return 3118 * 0 on success, a negative errno value otherwise and rte_errno is set. 3119 */ 3120 int 3121 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 3122 uint32_t queue) 3123 { 3124 struct mlx5_priv *priv = dev->data->dev_private; 3125 const struct rte_flow_attr attr = { 3126 .egress = 1, 3127 .priority = 0, 3128 }; 3129 struct mlx5_rte_flow_item_tx_queue queue_spec = { 3130 .queue = queue, 3131 }; 3132 struct mlx5_rte_flow_item_tx_queue queue_mask = { 3133 .queue = UINT32_MAX, 3134 }; 3135 struct rte_flow_item items[] = { 3136 { 3137 .type = MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 3138 .spec = &queue_spec, 3139 .last = NULL, 3140 .mask = &queue_mask, 3141 }, 3142 { 3143 .type = RTE_FLOW_ITEM_TYPE_END, 3144 }, 3145 }; 3146 struct rte_flow_action_jump jump = { 3147 .group = MLX5_HAIRPIN_TX_TABLE, 3148 }; 3149 struct rte_flow_action actions[2]; 3150 struct rte_flow *flow; 3151 struct rte_flow_error error; 3152 3153 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 3154 actions[0].conf = &jump; 3155 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 3156 flow = flow_list_create(dev, &priv->ctrl_flows, 3157 &attr, items, actions, false, &error); 3158 if (!flow) { 3159 DRV_LOG(DEBUG, 3160 "Failed to create ctrl flow: rte_errno(%d)," 3161 " type(%d), message(%s)", 3162 rte_errno, error.type, 3163 error.message ? error.message : " (no stated reason)"); 3164 return -rte_errno; 3165 } 3166 return 0; 3167 } 3168 3169 /** 3170 * Enable a control flow configured from the control plane. 3171 * 3172 * @param dev 3173 * Pointer to Ethernet device. 3174 * @param eth_spec 3175 * An Ethernet flow spec to apply. 3176 * @param eth_mask 3177 * An Ethernet flow mask to apply. 3178 * @param vlan_spec 3179 * A VLAN flow spec to apply. 3180 * @param vlan_mask 3181 * A VLAN flow mask to apply. 3182 * 3183 * @return 3184 * 0 on success, a negative errno value otherwise and rte_errno is set. 3185 */ 3186 int 3187 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 3188 struct rte_flow_item_eth *eth_spec, 3189 struct rte_flow_item_eth *eth_mask, 3190 struct rte_flow_item_vlan *vlan_spec, 3191 struct rte_flow_item_vlan *vlan_mask) 3192 { 3193 struct mlx5_priv *priv = dev->data->dev_private; 3194 const struct rte_flow_attr attr = { 3195 .ingress = 1, 3196 .priority = MLX5_FLOW_PRIO_RSVD, 3197 }; 3198 struct rte_flow_item items[] = { 3199 { 3200 .type = RTE_FLOW_ITEM_TYPE_ETH, 3201 .spec = eth_spec, 3202 .last = NULL, 3203 .mask = eth_mask, 3204 }, 3205 { 3206 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 3207 RTE_FLOW_ITEM_TYPE_END, 3208 .spec = vlan_spec, 3209 .last = NULL, 3210 .mask = vlan_mask, 3211 }, 3212 { 3213 .type = RTE_FLOW_ITEM_TYPE_END, 3214 }, 3215 }; 3216 uint16_t queue[priv->reta_idx_n]; 3217 struct rte_flow_action_rss action_rss = { 3218 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 3219 .level = 0, 3220 .types = priv->rss_conf.rss_hf, 3221 .key_len = priv->rss_conf.rss_key_len, 3222 .queue_num = priv->reta_idx_n, 3223 .key = priv->rss_conf.rss_key, 3224 .queue = queue, 3225 }; 3226 struct rte_flow_action actions[] = { 3227 { 3228 .type = RTE_FLOW_ACTION_TYPE_RSS, 3229 .conf = &action_rss, 3230 }, 3231 { 3232 .type = RTE_FLOW_ACTION_TYPE_END, 3233 }, 3234 }; 3235 struct rte_flow *flow; 3236 struct rte_flow_error error; 3237 unsigned int i; 3238 3239 if (!priv->reta_idx_n || !priv->rxqs_n) { 3240 return 0; 3241 } 3242 for (i = 0; i != priv->reta_idx_n; ++i) 3243 queue[i] = (*priv->reta_idx)[i]; 3244 flow = flow_list_create(dev, &priv->ctrl_flows, 3245 &attr, items, actions, false, &error); 3246 if (!flow) 3247 return -rte_errno; 3248 return 0; 3249 } 3250 3251 /** 3252 * Enable a flow control configured from the control plane. 3253 * 3254 * @param dev 3255 * Pointer to Ethernet device. 3256 * @param eth_spec 3257 * An Ethernet flow spec to apply. 3258 * @param eth_mask 3259 * An Ethernet flow mask to apply. 3260 * 3261 * @return 3262 * 0 on success, a negative errno value otherwise and rte_errno is set. 3263 */ 3264 int 3265 mlx5_ctrl_flow(struct rte_eth_dev *dev, 3266 struct rte_flow_item_eth *eth_spec, 3267 struct rte_flow_item_eth *eth_mask) 3268 { 3269 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 3270 } 3271 3272 /** 3273 * Destroy a flow. 3274 * 3275 * @see rte_flow_destroy() 3276 * @see rte_flow_ops 3277 */ 3278 int 3279 mlx5_flow_destroy(struct rte_eth_dev *dev, 3280 struct rte_flow *flow, 3281 struct rte_flow_error *error __rte_unused) 3282 { 3283 struct mlx5_priv *priv = dev->data->dev_private; 3284 3285 flow_list_destroy(dev, &priv->flows, flow); 3286 return 0; 3287 } 3288 3289 /** 3290 * Destroy all flows. 3291 * 3292 * @see rte_flow_flush() 3293 * @see rte_flow_ops 3294 */ 3295 int 3296 mlx5_flow_flush(struct rte_eth_dev *dev, 3297 struct rte_flow_error *error __rte_unused) 3298 { 3299 struct mlx5_priv *priv = dev->data->dev_private; 3300 3301 mlx5_flow_list_flush(dev, &priv->flows); 3302 return 0; 3303 } 3304 3305 /** 3306 * Isolated mode. 3307 * 3308 * @see rte_flow_isolate() 3309 * @see rte_flow_ops 3310 */ 3311 int 3312 mlx5_flow_isolate(struct rte_eth_dev *dev, 3313 int enable, 3314 struct rte_flow_error *error) 3315 { 3316 struct mlx5_priv *priv = dev->data->dev_private; 3317 3318 if (dev->data->dev_started) { 3319 rte_flow_error_set(error, EBUSY, 3320 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 3321 NULL, 3322 "port must be stopped first"); 3323 return -rte_errno; 3324 } 3325 priv->isolated = !!enable; 3326 if (enable) 3327 dev->dev_ops = &mlx5_dev_ops_isolate; 3328 else 3329 dev->dev_ops = &mlx5_dev_ops; 3330 return 0; 3331 } 3332 3333 /** 3334 * Query a flow. 3335 * 3336 * @see rte_flow_query() 3337 * @see rte_flow_ops 3338 */ 3339 static int 3340 flow_drv_query(struct rte_eth_dev *dev, 3341 struct rte_flow *flow, 3342 const struct rte_flow_action *actions, 3343 void *data, 3344 struct rte_flow_error *error) 3345 { 3346 const struct mlx5_flow_driver_ops *fops; 3347 enum mlx5_flow_drv_type ftype = flow->drv_type; 3348 3349 assert(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 3350 fops = flow_get_drv_ops(ftype); 3351 3352 return fops->query(dev, flow, actions, data, error); 3353 } 3354 3355 /** 3356 * Query a flow. 3357 * 3358 * @see rte_flow_query() 3359 * @see rte_flow_ops 3360 */ 3361 int 3362 mlx5_flow_query(struct rte_eth_dev *dev, 3363 struct rte_flow *flow, 3364 const struct rte_flow_action *actions, 3365 void *data, 3366 struct rte_flow_error *error) 3367 { 3368 int ret; 3369 3370 ret = flow_drv_query(dev, flow, actions, data, error); 3371 if (ret < 0) 3372 return ret; 3373 return 0; 3374 } 3375 3376 /** 3377 * Convert a flow director filter to a generic flow. 3378 * 3379 * @param dev 3380 * Pointer to Ethernet device. 3381 * @param fdir_filter 3382 * Flow director filter to add. 3383 * @param attributes 3384 * Generic flow parameters structure. 3385 * 3386 * @return 3387 * 0 on success, a negative errno value otherwise and rte_errno is set. 3388 */ 3389 static int 3390 flow_fdir_filter_convert(struct rte_eth_dev *dev, 3391 const struct rte_eth_fdir_filter *fdir_filter, 3392 struct mlx5_fdir *attributes) 3393 { 3394 struct mlx5_priv *priv = dev->data->dev_private; 3395 const struct rte_eth_fdir_input *input = &fdir_filter->input; 3396 const struct rte_eth_fdir_masks *mask = 3397 &dev->data->dev_conf.fdir_conf.mask; 3398 3399 /* Validate queue number. */ 3400 if (fdir_filter->action.rx_queue >= priv->rxqs_n) { 3401 DRV_LOG(ERR, "port %u invalid queue number %d", 3402 dev->data->port_id, fdir_filter->action.rx_queue); 3403 rte_errno = EINVAL; 3404 return -rte_errno; 3405 } 3406 attributes->attr.ingress = 1; 3407 attributes->items[0] = (struct rte_flow_item) { 3408 .type = RTE_FLOW_ITEM_TYPE_ETH, 3409 .spec = &attributes->l2, 3410 .mask = &attributes->l2_mask, 3411 }; 3412 switch (fdir_filter->action.behavior) { 3413 case RTE_ETH_FDIR_ACCEPT: 3414 attributes->actions[0] = (struct rte_flow_action){ 3415 .type = RTE_FLOW_ACTION_TYPE_QUEUE, 3416 .conf = &attributes->queue, 3417 }; 3418 break; 3419 case RTE_ETH_FDIR_REJECT: 3420 attributes->actions[0] = (struct rte_flow_action){ 3421 .type = RTE_FLOW_ACTION_TYPE_DROP, 3422 }; 3423 break; 3424 default: 3425 DRV_LOG(ERR, "port %u invalid behavior %d", 3426 dev->data->port_id, 3427 fdir_filter->action.behavior); 3428 rte_errno = ENOTSUP; 3429 return -rte_errno; 3430 } 3431 attributes->queue.index = fdir_filter->action.rx_queue; 3432 /* Handle L3. */ 3433 switch (fdir_filter->input.flow_type) { 3434 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3435 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3436 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3437 attributes->l3.ipv4.hdr = (struct rte_ipv4_hdr){ 3438 .src_addr = input->flow.ip4_flow.src_ip, 3439 .dst_addr = input->flow.ip4_flow.dst_ip, 3440 .time_to_live = input->flow.ip4_flow.ttl, 3441 .type_of_service = input->flow.ip4_flow.tos, 3442 }; 3443 attributes->l3_mask.ipv4.hdr = (struct rte_ipv4_hdr){ 3444 .src_addr = mask->ipv4_mask.src_ip, 3445 .dst_addr = mask->ipv4_mask.dst_ip, 3446 .time_to_live = mask->ipv4_mask.ttl, 3447 .type_of_service = mask->ipv4_mask.tos, 3448 .next_proto_id = mask->ipv4_mask.proto, 3449 }; 3450 attributes->items[1] = (struct rte_flow_item){ 3451 .type = RTE_FLOW_ITEM_TYPE_IPV4, 3452 .spec = &attributes->l3, 3453 .mask = &attributes->l3_mask, 3454 }; 3455 break; 3456 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3457 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3458 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3459 attributes->l3.ipv6.hdr = (struct rte_ipv6_hdr){ 3460 .hop_limits = input->flow.ipv6_flow.hop_limits, 3461 .proto = input->flow.ipv6_flow.proto, 3462 }; 3463 3464 memcpy(attributes->l3.ipv6.hdr.src_addr, 3465 input->flow.ipv6_flow.src_ip, 3466 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 3467 memcpy(attributes->l3.ipv6.hdr.dst_addr, 3468 input->flow.ipv6_flow.dst_ip, 3469 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 3470 memcpy(attributes->l3_mask.ipv6.hdr.src_addr, 3471 mask->ipv6_mask.src_ip, 3472 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 3473 memcpy(attributes->l3_mask.ipv6.hdr.dst_addr, 3474 mask->ipv6_mask.dst_ip, 3475 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 3476 attributes->items[1] = (struct rte_flow_item){ 3477 .type = RTE_FLOW_ITEM_TYPE_IPV6, 3478 .spec = &attributes->l3, 3479 .mask = &attributes->l3_mask, 3480 }; 3481 break; 3482 default: 3483 DRV_LOG(ERR, "port %u invalid flow type%d", 3484 dev->data->port_id, fdir_filter->input.flow_type); 3485 rte_errno = ENOTSUP; 3486 return -rte_errno; 3487 } 3488 /* Handle L4. */ 3489 switch (fdir_filter->input.flow_type) { 3490 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3491 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 3492 .src_port = input->flow.udp4_flow.src_port, 3493 .dst_port = input->flow.udp4_flow.dst_port, 3494 }; 3495 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 3496 .src_port = mask->src_port_mask, 3497 .dst_port = mask->dst_port_mask, 3498 }; 3499 attributes->items[2] = (struct rte_flow_item){ 3500 .type = RTE_FLOW_ITEM_TYPE_UDP, 3501 .spec = &attributes->l4, 3502 .mask = &attributes->l4_mask, 3503 }; 3504 break; 3505 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3506 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 3507 .src_port = input->flow.tcp4_flow.src_port, 3508 .dst_port = input->flow.tcp4_flow.dst_port, 3509 }; 3510 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 3511 .src_port = mask->src_port_mask, 3512 .dst_port = mask->dst_port_mask, 3513 }; 3514 attributes->items[2] = (struct rte_flow_item){ 3515 .type = RTE_FLOW_ITEM_TYPE_TCP, 3516 .spec = &attributes->l4, 3517 .mask = &attributes->l4_mask, 3518 }; 3519 break; 3520 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3521 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 3522 .src_port = input->flow.udp6_flow.src_port, 3523 .dst_port = input->flow.udp6_flow.dst_port, 3524 }; 3525 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 3526 .src_port = mask->src_port_mask, 3527 .dst_port = mask->dst_port_mask, 3528 }; 3529 attributes->items[2] = (struct rte_flow_item){ 3530 .type = RTE_FLOW_ITEM_TYPE_UDP, 3531 .spec = &attributes->l4, 3532 .mask = &attributes->l4_mask, 3533 }; 3534 break; 3535 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3536 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 3537 .src_port = input->flow.tcp6_flow.src_port, 3538 .dst_port = input->flow.tcp6_flow.dst_port, 3539 }; 3540 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 3541 .src_port = mask->src_port_mask, 3542 .dst_port = mask->dst_port_mask, 3543 }; 3544 attributes->items[2] = (struct rte_flow_item){ 3545 .type = RTE_FLOW_ITEM_TYPE_TCP, 3546 .spec = &attributes->l4, 3547 .mask = &attributes->l4_mask, 3548 }; 3549 break; 3550 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3551 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3552 break; 3553 default: 3554 DRV_LOG(ERR, "port %u invalid flow type%d", 3555 dev->data->port_id, fdir_filter->input.flow_type); 3556 rte_errno = ENOTSUP; 3557 return -rte_errno; 3558 } 3559 return 0; 3560 } 3561 3562 #define FLOW_FDIR_CMP(f1, f2, fld) \ 3563 memcmp(&(f1)->fld, &(f2)->fld, sizeof(f1->fld)) 3564 3565 /** 3566 * Compare two FDIR flows. If items and actions are identical, the two flows are 3567 * regarded as same. 3568 * 3569 * @param dev 3570 * Pointer to Ethernet device. 3571 * @param f1 3572 * FDIR flow to compare. 3573 * @param f2 3574 * FDIR flow to compare. 3575 * 3576 * @return 3577 * Zero on match, 1 otherwise. 3578 */ 3579 static int 3580 flow_fdir_cmp(const struct mlx5_fdir *f1, const struct mlx5_fdir *f2) 3581 { 3582 if (FLOW_FDIR_CMP(f1, f2, attr) || 3583 FLOW_FDIR_CMP(f1, f2, l2) || 3584 FLOW_FDIR_CMP(f1, f2, l2_mask) || 3585 FLOW_FDIR_CMP(f1, f2, l3) || 3586 FLOW_FDIR_CMP(f1, f2, l3_mask) || 3587 FLOW_FDIR_CMP(f1, f2, l4) || 3588 FLOW_FDIR_CMP(f1, f2, l4_mask) || 3589 FLOW_FDIR_CMP(f1, f2, actions[0].type)) 3590 return 1; 3591 if (f1->actions[0].type == RTE_FLOW_ACTION_TYPE_QUEUE && 3592 FLOW_FDIR_CMP(f1, f2, queue)) 3593 return 1; 3594 return 0; 3595 } 3596 3597 /** 3598 * Search device flow list to find out a matched FDIR flow. 3599 * 3600 * @param dev 3601 * Pointer to Ethernet device. 3602 * @param fdir_flow 3603 * FDIR flow to lookup. 3604 * 3605 * @return 3606 * Pointer of flow if found, NULL otherwise. 3607 */ 3608 static struct rte_flow * 3609 flow_fdir_filter_lookup(struct rte_eth_dev *dev, struct mlx5_fdir *fdir_flow) 3610 { 3611 struct mlx5_priv *priv = dev->data->dev_private; 3612 struct rte_flow *flow = NULL; 3613 3614 assert(fdir_flow); 3615 TAILQ_FOREACH(flow, &priv->flows, next) { 3616 if (flow->fdir && !flow_fdir_cmp(flow->fdir, fdir_flow)) { 3617 DRV_LOG(DEBUG, "port %u found FDIR flow %p", 3618 dev->data->port_id, (void *)flow); 3619 break; 3620 } 3621 } 3622 return flow; 3623 } 3624 3625 /** 3626 * Add new flow director filter and store it in list. 3627 * 3628 * @param dev 3629 * Pointer to Ethernet device. 3630 * @param fdir_filter 3631 * Flow director filter to add. 3632 * 3633 * @return 3634 * 0 on success, a negative errno value otherwise and rte_errno is set. 3635 */ 3636 static int 3637 flow_fdir_filter_add(struct rte_eth_dev *dev, 3638 const struct rte_eth_fdir_filter *fdir_filter) 3639 { 3640 struct mlx5_priv *priv = dev->data->dev_private; 3641 struct mlx5_fdir *fdir_flow; 3642 struct rte_flow *flow; 3643 int ret; 3644 3645 fdir_flow = rte_zmalloc(__func__, sizeof(*fdir_flow), 0); 3646 if (!fdir_flow) { 3647 rte_errno = ENOMEM; 3648 return -rte_errno; 3649 } 3650 ret = flow_fdir_filter_convert(dev, fdir_filter, fdir_flow); 3651 if (ret) 3652 goto error; 3653 flow = flow_fdir_filter_lookup(dev, fdir_flow); 3654 if (flow) { 3655 rte_errno = EEXIST; 3656 goto error; 3657 } 3658 flow = flow_list_create(dev, &priv->flows, &fdir_flow->attr, 3659 fdir_flow->items, fdir_flow->actions, true, 3660 NULL); 3661 if (!flow) 3662 goto error; 3663 assert(!flow->fdir); 3664 flow->fdir = fdir_flow; 3665 DRV_LOG(DEBUG, "port %u created FDIR flow %p", 3666 dev->data->port_id, (void *)flow); 3667 return 0; 3668 error: 3669 rte_free(fdir_flow); 3670 return -rte_errno; 3671 } 3672 3673 /** 3674 * Delete specific filter. 3675 * 3676 * @param dev 3677 * Pointer to Ethernet device. 3678 * @param fdir_filter 3679 * Filter to be deleted. 3680 * 3681 * @return 3682 * 0 on success, a negative errno value otherwise and rte_errno is set. 3683 */ 3684 static int 3685 flow_fdir_filter_delete(struct rte_eth_dev *dev, 3686 const struct rte_eth_fdir_filter *fdir_filter) 3687 { 3688 struct mlx5_priv *priv = dev->data->dev_private; 3689 struct rte_flow *flow; 3690 struct mlx5_fdir fdir_flow = { 3691 .attr.group = 0, 3692 }; 3693 int ret; 3694 3695 ret = flow_fdir_filter_convert(dev, fdir_filter, &fdir_flow); 3696 if (ret) 3697 return -rte_errno; 3698 flow = flow_fdir_filter_lookup(dev, &fdir_flow); 3699 if (!flow) { 3700 rte_errno = ENOENT; 3701 return -rte_errno; 3702 } 3703 flow_list_destroy(dev, &priv->flows, flow); 3704 DRV_LOG(DEBUG, "port %u deleted FDIR flow %p", 3705 dev->data->port_id, (void *)flow); 3706 return 0; 3707 } 3708 3709 /** 3710 * Update queue for specific filter. 3711 * 3712 * @param dev 3713 * Pointer to Ethernet device. 3714 * @param fdir_filter 3715 * Filter to be updated. 3716 * 3717 * @return 3718 * 0 on success, a negative errno value otherwise and rte_errno is set. 3719 */ 3720 static int 3721 flow_fdir_filter_update(struct rte_eth_dev *dev, 3722 const struct rte_eth_fdir_filter *fdir_filter) 3723 { 3724 int ret; 3725 3726 ret = flow_fdir_filter_delete(dev, fdir_filter); 3727 if (ret) 3728 return ret; 3729 return flow_fdir_filter_add(dev, fdir_filter); 3730 } 3731 3732 /** 3733 * Flush all filters. 3734 * 3735 * @param dev 3736 * Pointer to Ethernet device. 3737 */ 3738 static void 3739 flow_fdir_filter_flush(struct rte_eth_dev *dev) 3740 { 3741 struct mlx5_priv *priv = dev->data->dev_private; 3742 3743 mlx5_flow_list_flush(dev, &priv->flows); 3744 } 3745 3746 /** 3747 * Get flow director information. 3748 * 3749 * @param dev 3750 * Pointer to Ethernet device. 3751 * @param[out] fdir_info 3752 * Resulting flow director information. 3753 */ 3754 static void 3755 flow_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info) 3756 { 3757 struct rte_eth_fdir_masks *mask = 3758 &dev->data->dev_conf.fdir_conf.mask; 3759 3760 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode; 3761 fdir_info->guarant_spc = 0; 3762 rte_memcpy(&fdir_info->mask, mask, sizeof(fdir_info->mask)); 3763 fdir_info->max_flexpayload = 0; 3764 fdir_info->flow_types_mask[0] = 0; 3765 fdir_info->flex_payload_unit = 0; 3766 fdir_info->max_flex_payload_segment_num = 0; 3767 fdir_info->flex_payload_limit = 0; 3768 memset(&fdir_info->flex_conf, 0, sizeof(fdir_info->flex_conf)); 3769 } 3770 3771 /** 3772 * Deal with flow director operations. 3773 * 3774 * @param dev 3775 * Pointer to Ethernet device. 3776 * @param filter_op 3777 * Operation to perform. 3778 * @param arg 3779 * Pointer to operation-specific structure. 3780 * 3781 * @return 3782 * 0 on success, a negative errno value otherwise and rte_errno is set. 3783 */ 3784 static int 3785 flow_fdir_ctrl_func(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 3786 void *arg) 3787 { 3788 enum rte_fdir_mode fdir_mode = 3789 dev->data->dev_conf.fdir_conf.mode; 3790 3791 if (filter_op == RTE_ETH_FILTER_NOP) 3792 return 0; 3793 if (fdir_mode != RTE_FDIR_MODE_PERFECT && 3794 fdir_mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3795 DRV_LOG(ERR, "port %u flow director mode %d not supported", 3796 dev->data->port_id, fdir_mode); 3797 rte_errno = EINVAL; 3798 return -rte_errno; 3799 } 3800 switch (filter_op) { 3801 case RTE_ETH_FILTER_ADD: 3802 return flow_fdir_filter_add(dev, arg); 3803 case RTE_ETH_FILTER_UPDATE: 3804 return flow_fdir_filter_update(dev, arg); 3805 case RTE_ETH_FILTER_DELETE: 3806 return flow_fdir_filter_delete(dev, arg); 3807 case RTE_ETH_FILTER_FLUSH: 3808 flow_fdir_filter_flush(dev); 3809 break; 3810 case RTE_ETH_FILTER_INFO: 3811 flow_fdir_info_get(dev, arg); 3812 break; 3813 default: 3814 DRV_LOG(DEBUG, "port %u unknown operation %u", 3815 dev->data->port_id, filter_op); 3816 rte_errno = EINVAL; 3817 return -rte_errno; 3818 } 3819 return 0; 3820 } 3821 3822 /** 3823 * Manage filter operations. 3824 * 3825 * @param dev 3826 * Pointer to Ethernet device structure. 3827 * @param filter_type 3828 * Filter type. 3829 * @param filter_op 3830 * Operation to perform. 3831 * @param arg 3832 * Pointer to operation-specific structure. 3833 * 3834 * @return 3835 * 0 on success, a negative errno value otherwise and rte_errno is set. 3836 */ 3837 int 3838 mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 3839 enum rte_filter_type filter_type, 3840 enum rte_filter_op filter_op, 3841 void *arg) 3842 { 3843 switch (filter_type) { 3844 case RTE_ETH_FILTER_GENERIC: 3845 if (filter_op != RTE_ETH_FILTER_GET) { 3846 rte_errno = EINVAL; 3847 return -rte_errno; 3848 } 3849 *(const void **)arg = &mlx5_flow_ops; 3850 return 0; 3851 case RTE_ETH_FILTER_FDIR: 3852 return flow_fdir_ctrl_func(dev, filter_op, arg); 3853 default: 3854 DRV_LOG(ERR, "port %u filter type (%d) not supported", 3855 dev->data->port_id, filter_type); 3856 rte_errno = ENOTSUP; 3857 return -rte_errno; 3858 } 3859 return 0; 3860 } 3861 3862 #define MLX5_POOL_QUERY_FREQ_US 1000000 3863 3864 /** 3865 * Set the periodic procedure for triggering asynchronous batch queries for all 3866 * the counter pools. 3867 * 3868 * @param[in] sh 3869 * Pointer to mlx5_ibv_shared object. 3870 */ 3871 void 3872 mlx5_set_query_alarm(struct mlx5_ibv_shared *sh) 3873 { 3874 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(sh, 0, 0); 3875 uint32_t pools_n = rte_atomic16_read(&cont->n_valid); 3876 uint32_t us; 3877 3878 cont = MLX5_CNT_CONTAINER(sh, 1, 0); 3879 pools_n += rte_atomic16_read(&cont->n_valid); 3880 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 3881 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 3882 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 3883 sh->cmng.query_thread_on = 0; 3884 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 3885 } else { 3886 sh->cmng.query_thread_on = 1; 3887 } 3888 } 3889 3890 /** 3891 * The periodic procedure for triggering asynchronous batch queries for all the 3892 * counter pools. This function is probably called by the host thread. 3893 * 3894 * @param[in] arg 3895 * The parameter for the alarm process. 3896 */ 3897 void 3898 mlx5_flow_query_alarm(void *arg) 3899 { 3900 struct mlx5_ibv_shared *sh = arg; 3901 struct mlx5_devx_obj *dcs; 3902 uint16_t offset; 3903 int ret; 3904 uint8_t batch = sh->cmng.batch; 3905 uint16_t pool_index = sh->cmng.pool_index; 3906 struct mlx5_pools_container *cont; 3907 struct mlx5_pools_container *mcont; 3908 struct mlx5_flow_counter_pool *pool; 3909 3910 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 3911 goto set_alarm; 3912 next_container: 3913 cont = MLX5_CNT_CONTAINER(sh, batch, 1); 3914 mcont = MLX5_CNT_CONTAINER(sh, batch, 0); 3915 /* Check if resize was done and need to flip a container. */ 3916 if (cont != mcont) { 3917 if (cont->pools) { 3918 /* Clean the old container. */ 3919 rte_free(cont->pools); 3920 memset(cont, 0, sizeof(*cont)); 3921 } 3922 rte_cio_wmb(); 3923 /* Flip the host container. */ 3924 sh->cmng.mhi[batch] ^= (uint8_t)2; 3925 cont = mcont; 3926 } 3927 if (!cont->pools) { 3928 /* 2 empty containers case is unexpected. */ 3929 if (unlikely(batch != sh->cmng.batch)) 3930 goto set_alarm; 3931 batch ^= 0x1; 3932 pool_index = 0; 3933 goto next_container; 3934 } 3935 pool = cont->pools[pool_index]; 3936 if (pool->raw_hw) 3937 /* There is a pool query in progress. */ 3938 goto set_alarm; 3939 pool->raw_hw = 3940 LIST_FIRST(&sh->cmng.free_stat_raws); 3941 if (!pool->raw_hw) 3942 /* No free counter statistics raw memory. */ 3943 goto set_alarm; 3944 dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read 3945 (&pool->a64_dcs); 3946 offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL; 3947 ret = mlx5_devx_cmd_flow_counter_query(dcs, 0, MLX5_COUNTERS_PER_POOL - 3948 offset, NULL, NULL, 3949 pool->raw_hw->mem_mng->dm->id, 3950 (void *)(uintptr_t) 3951 (pool->raw_hw->data + offset), 3952 sh->devx_comp, 3953 (uint64_t)(uintptr_t)pool); 3954 if (ret) { 3955 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 3956 " %d", pool->min_dcs->id); 3957 pool->raw_hw = NULL; 3958 goto set_alarm; 3959 } 3960 pool->raw_hw->min_dcs_id = dcs->id; 3961 LIST_REMOVE(pool->raw_hw, next); 3962 sh->cmng.pending_queries++; 3963 pool_index++; 3964 if (pool_index >= rte_atomic16_read(&cont->n_valid)) { 3965 batch ^= 0x1; 3966 pool_index = 0; 3967 } 3968 set_alarm: 3969 sh->cmng.batch = batch; 3970 sh->cmng.pool_index = pool_index; 3971 mlx5_set_query_alarm(sh); 3972 } 3973 3974 /** 3975 * Handler for the HW respond about ready values from an asynchronous batch 3976 * query. This function is probably called by the host thread. 3977 * 3978 * @param[in] sh 3979 * The pointer to the shared IB device context. 3980 * @param[in] async_id 3981 * The Devx async ID. 3982 * @param[in] status 3983 * The status of the completion. 3984 */ 3985 void 3986 mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 3987 uint64_t async_id, int status) 3988 { 3989 struct mlx5_flow_counter_pool *pool = 3990 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 3991 struct mlx5_counter_stats_raw *raw_to_free; 3992 3993 if (unlikely(status)) { 3994 raw_to_free = pool->raw_hw; 3995 } else { 3996 raw_to_free = pool->raw; 3997 rte_spinlock_lock(&pool->sl); 3998 pool->raw = pool->raw_hw; 3999 rte_spinlock_unlock(&pool->sl); 4000 rte_atomic64_add(&pool->query_gen, 1); 4001 /* Be sure the new raw counters data is updated in memory. */ 4002 rte_cio_wmb(); 4003 } 4004 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 4005 pool->raw_hw = NULL; 4006 sh->cmng.pending_queries--; 4007 } 4008 4009 /** 4010 * Translate the rte_flow group index to HW table value. 4011 * 4012 * @param[in] attributes 4013 * Pointer to flow attributes 4014 * @param[in] external 4015 * Value is part of flow rule created by request external to PMD. 4016 * @param[in] group 4017 * rte_flow group index value. 4018 * @param[out] table 4019 * HW table value. 4020 * @param[out] error 4021 * Pointer to error structure. 4022 * 4023 * @return 4024 * 0 on success, a negative errno value otherwise and rte_errno is set. 4025 */ 4026 int 4027 mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, bool external, 4028 uint32_t group, uint32_t *table, 4029 struct rte_flow_error *error) 4030 { 4031 if (attributes->transfer && external) { 4032 if (group == UINT32_MAX) 4033 return rte_flow_error_set 4034 (error, EINVAL, 4035 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 4036 NULL, 4037 "group index not supported"); 4038 *table = group + 1; 4039 } else { 4040 *table = group; 4041 } 4042 return 0; 4043 } 4044