drivers: replace GCC pragma with cast

"GCC diagnostic ignored" pragmas have been commonly sprinkled
over the code.
Clang supports GCC's pragma for compatibility with existing
source code, so #pragma

drivers: replace GCC pragma with cast

"GCC diagnostic ignored" pragmas have been commonly sprinkled
over the code.
Clang supports GCC's pragma for compatibility with existing
source code, so #pragma GCC diagnostic and #pragma clang
diagnostic are synonyms for Clang
(https://clang.llvm.org/docs/UsersManual.html).

Now that effort is being made to make the code compatible with MSVC
these expressions would become more complex. It makes sense to hide
this complexity behind macros. This makes maintenance easier as these
macros are defined in a single place. As a plus the code becomes
more readable as well.

Signed-off-by: Andre Muezerie <andremue@linux.microsoft.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>

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net/mlx5: fix unneeded stub flow table allocation

The HWS non-template flow API is reusing some implementation of
template API to unify code logic. So for each rule creation, a stub
/ temporary tabl

net/mlx5: fix unneeded stub flow table allocation

The HWS non-template flow API is reusing some implementation of
template API to unify code logic. So for each rule creation, a stub
/ temporary table is used in order to reuse the actions construction.

Since this is temporary and used only internally, there is no need to
save the table permanently. Only parts of them are mandatory, so the
allocation / free from the heap of RTE memory is a waste and causes
a lot of overhead. By using the pre-allocated workspace and set the
needed fields expliticly will save the overhead and help to speed up
the rule insertion rate.

Fixes: 27d171b88031 ("net/mlx5: abstract flow action and enable reconfigure")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: fix Rx queue reference count in flushing flows

Some indirect table and hrxq is created in the rule creation with
QUEUE or RSS action. When stopping a port, the 'dev_started' is set
to 0 in

net/mlx5: fix Rx queue reference count in flushing flows

Some indirect table and hrxq is created in the rule creation with
QUEUE or RSS action. When stopping a port, the 'dev_started' is set
to 0 in the beginning. The mlx5_ind_table_obj_release() should still
do the dereference of the queue(s) when it is called in the polling
of flow rule deletion, due to the fact that a flow with Q/RSS action
is always referring to the active Rx queues.

The callback now can only pass one input parameter. Using a global
flag per device to indicate that the user flows flushing is in
progress. Then the reference count of the queue(s) should be
decreased.

Fixes: 3a2f674b6aa8 ("net/mlx5: add queue and RSS HW steering action")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: fix Rx queue control management

With the shared Rx queue feature introduced, the control and private
Rx queue structures are decoupled, each control structure can be
shared for multiple qu

net/mlx5: fix Rx queue control management

With the shared Rx queue feature introduced, the control and private
Rx queue structures are decoupled, each control structure can be
shared for multiple queue for all representors inside a domain.

So it should be only managed by the shared context instead of any
private data of each device. The previous workaround is using a flag
to check the owner (allocator) of the structure and handle it only
on that device closing stage.

A proper formal solution is to add a reference count for each control
structure and only free the structure when there is no reference to
it to get rid of the UAF issue.

Fixes: f957ac996435 ("net/mlx5: workaround list management of Rx queue control")
Fixes: bcc220cb57d7 ("net/mlx5: fix shared Rx queue list management")
CC: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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net/mlx5: fix MAC address initialization with GCC 15

Offending patch added code which broke compilation on GCC 15,
where MAC address was initialized with a string, causing the following
errors:

../

net/mlx5: fix MAC address initialization with GCC 15

Offending patch added code which broke compilation on GCC 15,
where MAC address was initialized with a string, causing the following
errors:

../drivers/net/mlx5/mlx5_flow.c:
In function ‘mlx5_legacy_dmac_flow_create’:
../drivers/net/mlx5/mlx5_flow.c:8568:44:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
8568 | .hdr.dst_addr.addr_bytes =
"\xff\xff\xff\xff\xff\xff",
|
^~~~~~~~~~~~~~~~~~~~~~~~~~

../drivers/net/mlx5/mlx5_flow.c: In function
‘mlx5_legacy_dmac_vlan_flow_create’:
../drivers/net/mlx5/mlx5_flow.c:8583:44:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
8583 | .hdr.dst_addr.addr_bytes =
"\xff\xff\xff\xff\xff\xff",
|
^~~~~~~~~~~~~~~~~~~~~~~~~~

This patch fixes this issue by converting it to array initialization.

Fixes: cf99567fe566 ("net/mlx5: add legacy unicast flow rules management")

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>

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net/mlx5: add legacy unicast flow rule registration

Whenever a unicast DMAC or unicast DMAC with VLAN ID control flow rule
is created when working with Verbs or DV flow engine,
add this flow rule to

net/mlx5: add legacy unicast flow rule registration

Whenever a unicast DMAC or unicast DMAC with VLAN ID control flow rule
is created when working with Verbs or DV flow engine,
add this flow rule to the control flow rule list,
with information required for recognizing it.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net/mlx5: add legacy unicast flow rules management

This patch adds the following internal functions for creation of
unicast DMAC flow rules:

- mlx5_legacy_dmac_flow_create() - simple wrapper over

net/mlx5: add legacy unicast flow rules management

This patch adds the following internal functions for creation of
unicast DMAC flow rules:

- mlx5_legacy_dmac_flow_create() - simple wrapper over
mlx5_ctrl_flow().
- mlx5_legacy_dmac_vlan_flow_create() - simple wrapper over
mlx5_ctrl_flow_vlan().

These will be used as a basis for implementing dynamic
additions of unicast DMAC or unicast DMAC with VLAN
control flow rules when new addresses/VLANs are added.

Also, this path adds the following internal functions
for destructions of unicast DMAC flow rules:

- mlx5_legacy_ctrl_flow_destroy() - assuming a flow rule is on the
control flow rule list, destroy it.
- mlx5_legacy_dmac_flow_destroy() - find and destroy a flow rule
with given unicast DMAC.
- mlx5_legacy_dmac_flow_destroy() - find and destroy a flow rule
with given unicast DMAC and VLAN ID.

These will be used as a basis for implementing dynamic
removals of unicast DMAC or unicast DMAC with VLAN
control flow rules when addresses/VLANs are removed.

At the moment, no relevant flow rules are registered on the list
when working with Verbs or DV flow engine.
This will be added in the follow up commit.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net/mlx5: rename control flow rules types

All structs and enumerations used for managenement of
HWS control flow rules do not really depend on HWS itself.
In order to allow their reuse with Verbs an

net/mlx5: rename control flow rules types

All structs and enumerations used for managenement of
HWS control flow rules do not really depend on HWS itself.
In order to allow their reuse with Verbs and DV flow engines and
allow fine-grained creation/destruction of unicast DMAC (with VLAN)
flow rules with these flow engines, this patch renames all related
structs and enumerations.
All are renamed as follows:

- Enum mlx5_hw_ctrl_flow_type renamed to mlx5_ctrl_flow_type.
- Enum prefix MLX5_HW_CTRL_FLOW_TYPE_ changes to
MLX5_CTRL_FLOW_TYPE_
- Struct mlx5_hw_ctrl_flow_info renamed to mlx5_ctrl_flow_info.
- Struct mlx5_hw_ctrl_flow renamed to mlx5_ctrl_flow_entry.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net/mlx5: add checking if unicast flow rule exists

Add 2 internal functions for checking if:

- unicast DMAC control flow rule or
- unicast DMAC with VLAN control flow rule,

was created.

Signed-of

net/mlx5: add checking if unicast flow rule exists

Add 2 internal functions for checking if:

- unicast DMAC control flow rule or
- unicast DMAC with VLAN control flow rule,

was created.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net: use IPv6 address structure for packet headers

The rte_ipv6_hdr uses ad-hoc uint8_t[16] arrays to represent addresses.
Replace these arrays with the newly added rte_ipv6_addr structure. Adapt
al

net: use IPv6 address structure for packet headers

The rte_ipv6_hdr uses ad-hoc uint8_t[16] arrays to represent addresses.
Replace these arrays with the newly added rte_ipv6_addr structure. Adapt
all code accordingly.

Signed-off-by: Robin Jarry <rjarry@redhat.com>

show more ...

net/mlx5: fix NVGRE item validation for template API

The template API NVGRE item can support full mask.
This patch updates default NVGRE item mask for the template API.

Fixes: 80c676259a04 ("net/ml

net/mlx5: fix NVGRE item validation for template API

The template API NVGRE item can support full mask.
This patch updates default NVGRE item mask for the template API.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>

show more ...

net/mlx5: add metadata split for compatibility

The method will not create any new flow rule implicitly during split
stage, but only generate needed items, actions and attributes based
on the detecti

net/mlx5: add metadata split for compatibility

The method will not create any new flow rule implicitly during split
stage, but only generate needed items, actions and attributes based
on the detection.

All the rules will still be created in the flow_hw_list_create().

In the meanwhile, once the mark action is specified in the FDB rule,
a new rule in the NIC Rx will be created to:
1. match the mark value on REG_C_x in FDB and set it into Rx
flow tag field.
2. copy the metadata in REG_C_x' into the REG_B.

If there is no mark, the default rule with only copying metadata
will be hit if there is Queue or RSS action in the NIC Rx rule.

Regarding the NIC Tx, only the metadata is relevant and it will be
copied in NIC Tx from REG_A into some REG_C_x. The current HWS
implementation already has already supported in the default copy
rule or the default SQ miss rule in the NIC Tx root table.

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

ethdev: convert string initialization

gcc 15 experimental [1], with -Wextra flag, gives warning in variable
initialization as string [2].

The warning has a point when initialized variable is intend

ethdev: convert string initialization

gcc 15 experimental [1], with -Wextra flag, gives warning in variable
initialization as string [2].

The warning has a point when initialized variable is intended to use as
string, since assignment is missing the required null terminator for
this case. But warning is useless for our usecase.

In this patch only updated a few instance to show the issue, there are
many instances to fix, if we prefer to go this way.
Other option is to disable warning but it can be useful for actual
string usecases, so I prefer to keep it.

Converted string initialization to array initialization.

[1]
gcc (GCC) 15.0.0 20241003 (experimental)

[2]
../lib/ethdev/rte_flow.h:906:36:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
906 | .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~

../lib/ethdev/rte_flow.h:907:36:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
907 | .hdr.src_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~

../lib/ethdev/rte_flow.h:1009:25:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
1009 | "\xff\xff\xff\xff\xff\xff\xff\xff"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

../lib/ethdev/rte_flow.h:1012:25:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
1012 | "\xff\xff\xff\xff\xff\xff\xff\xff"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

../lib/ethdev/rte_flow.h:1135:20:
error: initializer-string for array of ‘unsigned char’ is too long
[-Werror=unterminated-string-initialization]
1135 | .hdr.vni = "\xff\xff\xff",
| ^~~~~~~~~~~~~~

Signed-off-by: Ferruh Yigit <ferruh.yigit@amd.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: fix shared Rx queue data access race

The rxq_data resources were shared for shared Rx queue with the same
group and queue ID.
The cq_ci:24 of rxq_data was unalignment with other fields in

net/mlx5: fix shared Rx queue data access race

The rxq_data resources were shared for shared Rx queue with the same
group and queue ID.
The cq_ci:24 of rxq_data was unalignment with other fields in the one
32-bit data, like the dynf_meta and delay_drop.

32bit: xxxx xxxI IIII IIII IIII IIII IIII IIIx
^ .... .... .... .... ...^
| cq_ci |

The issue is that while the control thread updates the dynf_meta:1 or
delay_drop:1 value during port start, another data thread updates the
cq_ci at the same time, it causes the bytes race condition with
different thread, and cq_ci value may be overwritten and updated the
abnormal value into HW CQ DB.

This patch separates the cq_ci from the configuration data spaces, and
adds checking for delay_drop and dynf_meta if shared Rx queue if
started.

Fixes: 02a6195cbeaa ("net/mlx5: support enhanced CQE compression in Rx burst")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net/mlx5: fix GRE option HWS flow item validation

1. GRE_OPTION flow item validation required both item spec and mask.

HWS pattern template provides item mask only.

The patch removes spec requirem

net/mlx5: fix GRE option HWS flow item validation

1. GRE_OPTION flow item validation required both item spec and mask.

HWS pattern template provides item mask only.

The patch removes spec requirement in HWS GRE_OPTION item validation.

2. In non-HWS setup, GRE_OPTION flow item validation for the checksum and
sequence item parameters require group value.
HWS pattern template does not have a group.

The patch removes group validations for GRE_OPTION item.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: fix VXLAN HWS flow item validation

HWS can match entire VXLAN, VXLAN-GPE and VXLAN-GBP headers.
No need for mask validation.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")

net/mlx5: fix VXLAN HWS flow item validation

HWS can match entire VXLAN, VXLAN-GPE and VXLAN-GBP headers.
No need for mask validation.

Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: fix start without duplicate flow patterns

When devargs "allow_duplicate_pattern=0" is specified, PMD won't
allow duplicated flows to be inserted and return EEXIST as rte_errno.

The queue/

net/mlx5: fix start without duplicate flow patterns

When devargs "allow_duplicate_pattern=0" is specified, PMD won't
allow duplicated flows to be inserted and return EEXIST as rte_errno.

The queue/RSS split table is shared globally by all representors and
PMD didn't prepend port information into it, so all the following ports
tries to insert the same flows and cause PMD insertion failure.

Using the hash list to manage it can solve the issue.

Fixes: ddb68e47331e ("net/mlx5: add extended metadata mode for HWS")
Cc: stable@dpdk.org

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

show more ...

net/mlx5: extract flow queue index validation

Extract validation of queue index out of validation of
RTE_FLOW_ACTION_TYPE_QUEUE action to allow reuse in template API
flow rule creation implementatio

net/mlx5: extract flow queue index validation

Extract validation of queue index out of validation of
RTE_FLOW_ACTION_TYPE_QUEUE action to allow reuse in template API
flow rule creation implementation.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

show more ...

net/mlx5: abstract flow action and enable reconfigure

reuse HWS actions translation code in order to create
the actions for lower layer.
All actions are handled as non masked.
Therefore, will be tra

net/mlx5: abstract flow action and enable reconfigure

reuse HWS actions translation code in order to create
the actions for lower layer.
All actions are handled as non masked.
Therefore, will be translated in the rule construct
phase shared with the template code
and not during the action template translate.

Currently there is no option to reconfigure in template API’s.
To support non template API and template API simultaneously,
There is a need to enable the user to reconfigure after default
configuration was applied by the driver on port start.

Fix flow create ptr
In SWS the return flow pointer is the flow index,
in HWS the return flow pointer is the flow data pointer.
Currently the return value of non template code did not
Enable destroy or quary.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: introduce HWS for non-template flow API

Implement the frame and needed building
blocks for non template to hws API's.

Added validate, list_create and list_destroy to mlx5_flow_hw_drv_ops.

net/mlx5: introduce HWS for non-template flow API

Implement the frame and needed building
blocks for non template to hws API's.

Added validate, list_create and list_destroy to mlx5_flow_hw_drv_ops.
Rename old list_create/list_destroy functions to legacy_*
and added a call from verbs/dv ops to the legacy functions.

Updated rte_flow_hw as needed.
Added rte_flow_nt2hws structure for non-template rule data.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: validate HWS template items

HWS item validation scheme is based on existing DV items validation.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnows

net/mlx5: validate HWS template items

HWS item validation scheme is based on existing DV items validation.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

net/mlx5: validate flow actions in table creation

Add basic actions validation before creating flow table.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnows

net/mlx5: validate flow actions in table creation

Add basic actions validation before creating flow table.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...

drivers: use stdatomic API

Replace the use of gcc builtin __atomic_xxx intrinsics with
corresponding rte_atomic_xxx optional rte stdatomic API.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microso

drivers: use stdatomic API

Replace the use of gcc builtin __atomic_xxx intrinsics with
corresponding rte_atomic_xxx optional rte stdatomic API.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>

show more ...

net/mlx5: fix age position in hairpin split

When splitting a hairpin rule implicitly, the count action will
be on either Tx or Rx subflow based on the encapsulation checking.

Once there is a flow r

net/mlx5: fix age position in hairpin split

When splitting a hairpin rule implicitly, the count action will
be on either Tx or Rx subflow based on the encapsulation checking.

Once there is a flow rule with both count and age action, one counter
will be reused. If there is only age action and the ASO flow hit is
supported, the flow hit will be chosen instead of a counter.

In the previous flow splitting, the age would always be in the Rx
part, while the count would be on the Tx part when there is an encap.

Before this commit, 2 issues can be observed with a hairpin split:
1. On the root table, one counter was used on both Rx and Tx parts
for age and count actions. Then one ingress packet will be
counted twice.
2. On the non-root table, an extra ASO flow hit was used on the Rx
part. This would cause some overhead.

The age and count actions should be in the same subflow instead of 2.

Fixes: daed4b6e3db2 ("net/mlx5: use aging by counter when counter exists")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>

show more ...

net/mlx5: support flow table resizing

Support template table API in PMD.
The patch allows to increase existing table capacity.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz

net/mlx5: support flow table resizing

Support template table API in PMD.
The patch allows to increase existing table capacity.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

show more ...