1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 /* 37 * Shared array for quick translation between port_id and vport mask/values 38 * used for HWS rules. 39 */ 40 struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; 41 42 struct tunnel_default_miss_ctx { 43 uint16_t *queue; 44 __extension__ 45 union { 46 struct rte_flow_action_rss action_rss; 47 struct rte_flow_action_queue miss_queue; 48 struct rte_flow_action_jump miss_jump; 49 uint8_t raw[0]; 50 }; 51 }; 52 53 void 54 mlx5_indirect_list_handles_release(struct rte_eth_dev *dev) 55 { 56 struct mlx5_priv *priv = dev->data->dev_private; 57 #ifdef HAVE_MLX5_HWS_SUPPORT 58 struct rte_flow_error error; 59 #endif 60 61 while (!LIST_EMPTY(&priv->indirect_list_head)) { 62 struct mlx5_indirect_list *e = 63 LIST_FIRST(&priv->indirect_list_head); 64 65 LIST_REMOVE(e, entry); 66 switch (e->type) { 67 #ifdef HAVE_MLX5_HWS_SUPPORT 68 case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR: 69 mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)e); 70 break; 71 case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY: 72 mlx5_destroy_legacy_indirect(dev, e); 73 break; 74 case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT: 75 mlx5_reformat_action_destroy(dev, 76 (struct rte_flow_action_list_handle *)e, &error); 77 break; 78 #endif 79 default: 80 DRV_LOG(ERR, "invalid indirect list type"); 81 MLX5_ASSERT(false); 82 break; 83 } 84 } 85 } 86 87 static int 88 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 89 struct rte_flow *flow, 90 const struct rte_flow_attr *attr, 91 const struct rte_flow_action *app_actions, 92 uint32_t flow_idx, 93 const struct mlx5_flow_tunnel *tunnel, 94 struct tunnel_default_miss_ctx *ctx, 95 struct rte_flow_error *error); 96 static struct mlx5_flow_tunnel * 97 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 98 static void 99 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 100 static uint32_t 101 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 102 const struct mlx5_flow_tunnel *tunnel, 103 uint32_t group, uint32_t *table, 104 struct rte_flow_error *error); 105 106 /** Device flow drivers. */ 107 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 108 109 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 110 111 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 112 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 113 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 114 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 115 #endif 116 #ifdef HAVE_MLX5_HWS_SUPPORT 117 [MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops, 118 #endif 119 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 120 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 121 }; 122 123 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 124 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 125 (const int []){ \ 126 __VA_ARGS__, 0, \ 127 } 128 129 /** Node object of input graph for mlx5_flow_expand_rss(). */ 130 struct mlx5_flow_expand_node { 131 const int *const next; 132 /**< 133 * List of next node indexes. Index 0 is interpreted as a terminator. 134 */ 135 const enum rte_flow_item_type type; 136 /**< Pattern item type of current node. */ 137 uint64_t rss_types; 138 /**< 139 * RSS types bit-field associated with this node 140 * (see RTE_ETH_RSS_* definitions). 141 */ 142 uint64_t node_flags; 143 /**< 144 * Bit-fields that define how the node is used in the expansion. 145 * (see MLX5_EXPANSION_NODE_* definitions). 146 */ 147 }; 148 149 /** Keep same format with mlx5_flow_expand_rss to share the buffer for expansion. */ 150 struct mlx5_flow_expand_sqn { 151 uint32_t entries; /** Number of entries */ 152 struct { 153 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 154 uint32_t priority; /**< Priority offset for each expansion. */ 155 } entry[]; 156 }; 157 158 /* Optional expand field. The expansion alg will not go deeper. */ 159 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 160 161 /* The node is not added implicitly as expansion to the flow pattern. 162 * If the node type does not match the flow pattern item type, the 163 * expansion alg will go deeper to its next items. 164 * In the current implementation, the list of next nodes indexes can 165 * have up to one node with this flag set and it has to be the last 166 * node index (before the list terminator). 167 */ 168 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 169 170 /** Object returned by mlx5_flow_expand_rss(). */ 171 struct mlx5_flow_expand_rss { 172 uint32_t entries; 173 /**< Number of entries @p patterns and @p priorities. */ 174 struct { 175 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 176 uint32_t priority; /**< Priority offset for each expansion. */ 177 } entry[]; 178 }; 179 180 static void 181 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 182 183 static const struct mlx5_flow_expand_node * 184 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 185 unsigned int item_idx, 186 const struct mlx5_flow_expand_node graph[], 187 const struct mlx5_flow_expand_node *node); 188 189 static __rte_always_inline int 190 mlx5_need_cache_flow(const struct mlx5_priv *priv, 191 const struct rte_flow_attr *attr) 192 { 193 return priv->isolated && priv->sh->config.dv_flow_en == 1 && 194 (attr ? !attr->group : true) && 195 priv->mode_info.mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY && 196 (!priv->sh->config.dv_esw_en || !priv->sh->config.fdb_def_rule); 197 } 198 199 static bool 200 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 201 { 202 switch (item->type) { 203 case RTE_FLOW_ITEM_TYPE_ETH: 204 case RTE_FLOW_ITEM_TYPE_VLAN: 205 case RTE_FLOW_ITEM_TYPE_IPV4: 206 case RTE_FLOW_ITEM_TYPE_IPV6: 207 case RTE_FLOW_ITEM_TYPE_UDP: 208 case RTE_FLOW_ITEM_TYPE_TCP: 209 case RTE_FLOW_ITEM_TYPE_ESP: 210 case RTE_FLOW_ITEM_TYPE_ICMP: 211 case RTE_FLOW_ITEM_TYPE_ICMP6: 212 case RTE_FLOW_ITEM_TYPE_VXLAN: 213 case RTE_FLOW_ITEM_TYPE_NVGRE: 214 case RTE_FLOW_ITEM_TYPE_GRE: 215 case RTE_FLOW_ITEM_TYPE_GENEVE: 216 case RTE_FLOW_ITEM_TYPE_MPLS: 217 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 218 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 219 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 220 case RTE_FLOW_ITEM_TYPE_GTP: 221 return true; 222 default: 223 break; 224 } 225 return false; 226 } 227 228 /** 229 * Network Service Header (NSH) and its next protocol values 230 * are described in RFC-8393. 231 */ 232 static enum rte_flow_item_type 233 mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 234 { 235 enum rte_flow_item_type type; 236 237 switch (proto_mask & proto_spec) { 238 case 0: 239 type = RTE_FLOW_ITEM_TYPE_VOID; 240 break; 241 case RTE_VXLAN_GPE_TYPE_IPV4: 242 type = RTE_FLOW_ITEM_TYPE_IPV4; 243 break; 244 case RTE_VXLAN_GPE_TYPE_IPV6: 245 type = RTE_VXLAN_GPE_TYPE_IPV6; 246 break; 247 case RTE_VXLAN_GPE_TYPE_ETH: 248 type = RTE_FLOW_ITEM_TYPE_ETH; 249 break; 250 default: 251 type = RTE_FLOW_ITEM_TYPE_END; 252 } 253 return type; 254 } 255 256 static enum rte_flow_item_type 257 mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 258 { 259 enum rte_flow_item_type type; 260 261 switch (proto_mask & proto_spec) { 262 case 0: 263 type = RTE_FLOW_ITEM_TYPE_VOID; 264 break; 265 case IPPROTO_UDP: 266 type = RTE_FLOW_ITEM_TYPE_UDP; 267 break; 268 case IPPROTO_TCP: 269 type = RTE_FLOW_ITEM_TYPE_TCP; 270 break; 271 case IPPROTO_IPIP: 272 type = RTE_FLOW_ITEM_TYPE_IPV4; 273 break; 274 case IPPROTO_IPV6: 275 type = RTE_FLOW_ITEM_TYPE_IPV6; 276 break; 277 case IPPROTO_ESP: 278 type = RTE_FLOW_ITEM_TYPE_ESP; 279 break; 280 default: 281 type = RTE_FLOW_ITEM_TYPE_END; 282 } 283 return type; 284 } 285 286 static enum rte_flow_item_type 287 mlx5_ethertype_to_item_type(rte_be16_t type_spec, 288 rte_be16_t type_mask, bool is_tunnel) 289 { 290 enum rte_flow_item_type type; 291 292 switch (rte_be_to_cpu_16(type_spec & type_mask)) { 293 case 0: 294 type = RTE_FLOW_ITEM_TYPE_VOID; 295 break; 296 case RTE_ETHER_TYPE_TEB: 297 type = is_tunnel ? 298 RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END; 299 break; 300 case RTE_ETHER_TYPE_VLAN: 301 type = !is_tunnel ? 302 RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END; 303 break; 304 case RTE_ETHER_TYPE_IPV4: 305 type = RTE_FLOW_ITEM_TYPE_IPV4; 306 break; 307 case RTE_ETHER_TYPE_IPV6: 308 type = RTE_FLOW_ITEM_TYPE_IPV6; 309 break; 310 default: 311 type = RTE_FLOW_ITEM_TYPE_END; 312 } 313 return type; 314 } 315 316 static enum rte_flow_item_type 317 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 318 { 319 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ 320 do { \ 321 const void *m = item->mask; \ 322 const void *s = item->spec; \ 323 mask = m ? \ 324 ((const struct rte_flow_item_##type *)m)->fld : \ 325 rte_flow_item_##type##_mask.fld; \ 326 spec = ((const struct rte_flow_item_##type *)s)->fld; \ 327 } while (0) 328 329 enum rte_flow_item_type ret; 330 uint16_t spec, mask; 331 332 if (item == NULL || item->spec == NULL) 333 return RTE_FLOW_ITEM_TYPE_VOID; 334 switch (item->type) { 335 case RTE_FLOW_ITEM_TYPE_ETH: 336 MLX5_XSET_ITEM_MASK_SPEC(eth, hdr.ether_type); 337 if (!mask) 338 return RTE_FLOW_ITEM_TYPE_VOID; 339 ret = mlx5_ethertype_to_item_type(spec, mask, false); 340 break; 341 case RTE_FLOW_ITEM_TYPE_VLAN: 342 MLX5_XSET_ITEM_MASK_SPEC(vlan, hdr.eth_proto); 343 if (!mask) 344 return RTE_FLOW_ITEM_TYPE_VOID; 345 ret = mlx5_ethertype_to_item_type(spec, mask, false); 346 break; 347 case RTE_FLOW_ITEM_TYPE_IPV4: 348 MLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id); 349 if (!mask) 350 return RTE_FLOW_ITEM_TYPE_VOID; 351 ret = mlx5_inet_proto_to_item_type(spec, mask); 352 break; 353 case RTE_FLOW_ITEM_TYPE_IPV6: 354 MLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto); 355 if (!mask) 356 return RTE_FLOW_ITEM_TYPE_VOID; 357 ret = mlx5_inet_proto_to_item_type(spec, mask); 358 break; 359 case RTE_FLOW_ITEM_TYPE_GENEVE: 360 MLX5_XSET_ITEM_MASK_SPEC(geneve, protocol); 361 ret = mlx5_ethertype_to_item_type(spec, mask, true); 362 break; 363 case RTE_FLOW_ITEM_TYPE_GRE: 364 MLX5_XSET_ITEM_MASK_SPEC(gre, protocol); 365 ret = mlx5_ethertype_to_item_type(spec, mask, true); 366 break; 367 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 368 MLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, hdr.proto); 369 ret = mlx5_nsh_proto_to_item_type(spec, mask); 370 break; 371 default: 372 ret = RTE_FLOW_ITEM_TYPE_VOID; 373 break; 374 } 375 return ret; 376 #undef MLX5_XSET_ITEM_MASK_SPEC 377 } 378 379 static const int * 380 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 381 const int *next_node) 382 { 383 const struct mlx5_flow_expand_node *node = NULL; 384 const int *next = next_node; 385 386 while (next && *next) { 387 /* 388 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 389 * flag set, because they were not found in the flow pattern. 390 */ 391 node = &graph[*next]; 392 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 393 break; 394 next = node->next; 395 } 396 return next; 397 } 398 399 #define MLX5_RSS_EXP_ELT_N 32 400 401 /** 402 * Expand RSS flows into several possible flows according to the RSS hash 403 * fields requested and the driver capabilities. 404 * 405 * @param[out] buf 406 * Buffer to store the result expansion. 407 * @param[in] size 408 * Buffer size in bytes. If 0, @p buf can be NULL. 409 * @param[in] pattern 410 * User flow pattern. 411 * @param[in] types 412 * RSS types to expand (see RTE_ETH_RSS_* definitions). 413 * @param[in] graph 414 * Input graph to expand @p pattern according to @p types. 415 * @param[in] graph_root_index 416 * Index of root node in @p graph, typically 0. 417 * 418 * @return 419 * A positive value representing the size of @p buf in bytes regardless of 420 * @p size on success, a negative errno value otherwise and rte_errno is 421 * set, the following errors are defined: 422 * 423 * -E2BIG: graph-depth @p graph is too deep. 424 * -EINVAL: @p size has not enough space for expanded pattern. 425 */ 426 static int 427 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 428 const struct rte_flow_item *pattern, uint64_t types, 429 const struct mlx5_flow_expand_node graph[], 430 int graph_root_index) 431 { 432 const struct rte_flow_item *item; 433 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 434 const int *next_node; 435 const int *stack[MLX5_RSS_EXP_ELT_N]; 436 int stack_pos = 0; 437 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 438 unsigned int i, item_idx, last_expand_item_idx = 0; 439 size_t lsize; 440 size_t user_pattern_size = 0; 441 void *addr = NULL; 442 const struct mlx5_flow_expand_node *next = NULL; 443 struct rte_flow_item missed_item; 444 int missed = 0; 445 int elt = 0; 446 const struct rte_flow_item *last_expand_item = NULL; 447 448 memset(&missed_item, 0, sizeof(missed_item)); 449 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 450 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 451 if (lsize > size) 452 return -EINVAL; 453 buf->entry[0].priority = 0; 454 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 455 buf->entries = 0; 456 addr = buf->entry[0].pattern; 457 for (item = pattern, item_idx = 0; 458 item->type != RTE_FLOW_ITEM_TYPE_END; 459 item++, item_idx++) { 460 if (!mlx5_flow_is_rss_expandable_item(item)) { 461 user_pattern_size += sizeof(*item); 462 continue; 463 } 464 last_expand_item = item; 465 last_expand_item_idx = item_idx; 466 i = 0; 467 while (node->next && node->next[i]) { 468 next = &graph[node->next[i]]; 469 if (next->type == item->type) 470 break; 471 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 472 node = next; 473 i = 0; 474 } else { 475 ++i; 476 } 477 } 478 if (next) 479 node = next; 480 user_pattern_size += sizeof(*item); 481 } 482 user_pattern_size += sizeof(*item); /* Handle END item. */ 483 lsize += user_pattern_size; 484 if (lsize > size) 485 return -EINVAL; 486 /* Copy the user pattern in the first entry of the buffer. */ 487 rte_memcpy(addr, pattern, user_pattern_size); 488 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 489 buf->entries = 1; 490 /* Start expanding. */ 491 memset(flow_items, 0, sizeof(flow_items)); 492 user_pattern_size -= sizeof(*item); 493 /* 494 * Check if the last valid item has spec set, need complete pattern, 495 * and the pattern can be used for expansion. 496 */ 497 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 498 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 499 /* Item type END indicates expansion is not required. */ 500 return lsize; 501 } 502 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 503 next = NULL; 504 missed = 1; 505 i = 0; 506 while (node->next && node->next[i]) { 507 next = &graph[node->next[i]]; 508 if (next->type == missed_item.type) { 509 flow_items[0].type = missed_item.type; 510 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 511 break; 512 } 513 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 514 node = next; 515 i = 0; 516 } else { 517 ++i; 518 } 519 next = NULL; 520 } 521 } 522 if (next && missed) { 523 elt = 2; /* missed item + item end. */ 524 node = next; 525 lsize += elt * sizeof(*item) + user_pattern_size; 526 if (lsize > size) 527 return -EINVAL; 528 if (node->rss_types & types) { 529 buf->entry[buf->entries].priority = 1; 530 buf->entry[buf->entries].pattern = addr; 531 buf->entries++; 532 rte_memcpy(addr, buf->entry[0].pattern, 533 user_pattern_size); 534 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 535 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 536 addr = (void *)(((uintptr_t)addr) + 537 elt * sizeof(*item)); 538 } 539 } else if (last_expand_item != NULL) { 540 node = mlx5_flow_expand_rss_adjust_node(pattern, 541 last_expand_item_idx, graph, node); 542 } 543 memset(flow_items, 0, sizeof(flow_items)); 544 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 545 node->next); 546 stack[stack_pos] = next_node; 547 node = next_node ? &graph[*next_node] : NULL; 548 while (node) { 549 flow_items[stack_pos].type = node->type; 550 if (node->rss_types & types) { 551 size_t n; 552 /* 553 * compute the number of items to copy from the 554 * expansion and copy it. 555 * When the stack_pos is 0, there are 1 element in it, 556 * plus the addition END item. 557 */ 558 elt = stack_pos + 2; 559 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 560 lsize += elt * sizeof(*item) + user_pattern_size; 561 if (lsize > size) 562 return -EINVAL; 563 n = elt * sizeof(*item); 564 MLX5_ASSERT((buf->entries) < MLX5_RSS_EXP_ELT_N); 565 buf->entry[buf->entries].priority = 566 stack_pos + 1 + missed; 567 buf->entry[buf->entries].pattern = addr; 568 buf->entries++; 569 rte_memcpy(addr, buf->entry[0].pattern, 570 user_pattern_size); 571 addr = (void *)(((uintptr_t)addr) + 572 user_pattern_size); 573 rte_memcpy(addr, &missed_item, 574 missed * sizeof(*item)); 575 addr = (void *)(((uintptr_t)addr) + 576 missed * sizeof(*item)); 577 rte_memcpy(addr, flow_items, n); 578 addr = (void *)(((uintptr_t)addr) + n); 579 } 580 /* Go deeper. */ 581 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 582 node->next) { 583 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 584 node->next); 585 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 586 rte_errno = E2BIG; 587 return -rte_errno; 588 } 589 stack[stack_pos] = next_node; 590 } else if (*(next_node + 1)) { 591 /* Follow up with the next possibility. */ 592 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 593 ++next_node); 594 } else if (!stack_pos) { 595 /* 596 * Completing the traverse over the different paths. 597 * The next_node is advanced to the terminator. 598 */ 599 ++next_node; 600 } else { 601 /* Move to the next path. */ 602 while (stack_pos) { 603 next_node = stack[--stack_pos]; 604 next_node++; 605 if (*next_node) 606 break; 607 } 608 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 609 next_node); 610 stack[stack_pos] = next_node; 611 } 612 node = next_node && *next_node ? &graph[*next_node] : NULL; 613 }; 614 return lsize; 615 } 616 617 /** 618 * Expand SQN flows into several possible flows according to the Tx queue 619 * number 620 * 621 * @param[in] buf 622 * Buffer to store the result expansion. 623 * @param[in] size 624 * Buffer size in bytes. If 0, @p buf can be NULL. 625 * @param[in] pattern 626 * User flow pattern. 627 * @param[in] sq_specs 628 * Buffer to store sq spec. 629 * 630 * @return 631 * 0 for success and negative value for failure 632 * 633 */ 634 static int 635 mlx5_flow_expand_sqn(struct mlx5_flow_expand_sqn *buf, size_t size, 636 const struct rte_flow_item *pattern, 637 struct mlx5_rte_flow_item_sq *sq_specs) 638 { 639 const struct rte_flow_item *item; 640 bool port_representor = false; 641 size_t user_pattern_size = 0; 642 struct rte_eth_dev *dev; 643 struct mlx5_priv *priv; 644 void *addr = NULL; 645 uint16_t port_id; 646 size_t lsize; 647 int elt = 2; 648 uint16_t i; 649 650 buf->entries = 0; 651 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 652 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 653 const struct rte_flow_item_ethdev *pid_v = item->spec; 654 655 if (!pid_v) 656 return 0; 657 port_id = pid_v->port_id; 658 port_representor = true; 659 } 660 user_pattern_size += sizeof(*item); 661 } 662 if (!port_representor) 663 return 0; 664 dev = &rte_eth_devices[port_id]; 665 priv = dev->data->dev_private; 666 buf->entry[0].pattern = (void *)&buf->entry[priv->txqs_n]; 667 lsize = offsetof(struct mlx5_flow_expand_sqn, entry) + 668 sizeof(buf->entry[0]) * priv->txqs_n; 669 if (lsize + (user_pattern_size + sizeof(struct rte_flow_item) * elt) * priv->txqs_n > size) 670 return -EINVAL; 671 addr = buf->entry[0].pattern; 672 for (i = 0; i != priv->txqs_n; ++i) { 673 struct rte_flow_item pattern_add[] = { 674 { 675 .type = (enum rte_flow_item_type) 676 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 677 .spec = &sq_specs[i], 678 }, 679 { 680 .type = RTE_FLOW_ITEM_TYPE_END, 681 }, 682 }; 683 struct mlx5_txq_ctrl *txq = mlx5_txq_get(dev, i); 684 685 if (txq == NULL) 686 return -EINVAL; 687 buf->entry[i].pattern = addr; 688 sq_specs[i].queue = mlx5_txq_get_sqn(txq); 689 mlx5_txq_release(dev, i); 690 rte_memcpy(addr, pattern, user_pattern_size); 691 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 692 rte_memcpy(addr, pattern_add, sizeof(struct rte_flow_item) * elt); 693 addr = (void *)(((uintptr_t)addr) + sizeof(struct rte_flow_item) * elt); 694 buf->entries++; 695 } 696 return 0; 697 } 698 699 enum mlx5_expansion { 700 MLX5_EXPANSION_ROOT, 701 MLX5_EXPANSION_ROOT_OUTER, 702 MLX5_EXPANSION_OUTER_ETH, 703 MLX5_EXPANSION_OUTER_VLAN, 704 MLX5_EXPANSION_OUTER_IPV4, 705 MLX5_EXPANSION_OUTER_IPV4_UDP, 706 MLX5_EXPANSION_OUTER_IPV4_TCP, 707 MLX5_EXPANSION_OUTER_IPV4_ESP, 708 MLX5_EXPANSION_OUTER_IPV4_ICMP, 709 MLX5_EXPANSION_OUTER_IPV6, 710 MLX5_EXPANSION_OUTER_IPV6_UDP, 711 MLX5_EXPANSION_OUTER_IPV6_TCP, 712 MLX5_EXPANSION_OUTER_IPV6_ESP, 713 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 714 MLX5_EXPANSION_VXLAN, 715 MLX5_EXPANSION_STD_VXLAN, 716 MLX5_EXPANSION_L3_VXLAN, 717 MLX5_EXPANSION_VXLAN_GPE, 718 MLX5_EXPANSION_GRE, 719 MLX5_EXPANSION_NVGRE, 720 MLX5_EXPANSION_GRE_KEY, 721 MLX5_EXPANSION_MPLS, 722 MLX5_EXPANSION_ETH, 723 MLX5_EXPANSION_VLAN, 724 MLX5_EXPANSION_IPV4, 725 MLX5_EXPANSION_IPV4_UDP, 726 MLX5_EXPANSION_IPV4_TCP, 727 MLX5_EXPANSION_IPV4_ESP, 728 MLX5_EXPANSION_IPV4_ICMP, 729 MLX5_EXPANSION_IPV6, 730 MLX5_EXPANSION_IPV6_UDP, 731 MLX5_EXPANSION_IPV6_TCP, 732 MLX5_EXPANSION_IPV6_ESP, 733 MLX5_EXPANSION_IPV6_ICMP6, 734 MLX5_EXPANSION_IPV6_FRAG_EXT, 735 MLX5_EXPANSION_GTP, 736 MLX5_EXPANSION_GENEVE, 737 }; 738 739 /** Supported expansion of items. */ 740 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 741 [MLX5_EXPANSION_ROOT] = { 742 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 743 MLX5_EXPANSION_IPV4, 744 MLX5_EXPANSION_IPV6), 745 .type = RTE_FLOW_ITEM_TYPE_END, 746 }, 747 [MLX5_EXPANSION_ROOT_OUTER] = { 748 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 749 MLX5_EXPANSION_OUTER_IPV4, 750 MLX5_EXPANSION_OUTER_IPV6), 751 .type = RTE_FLOW_ITEM_TYPE_END, 752 }, 753 [MLX5_EXPANSION_OUTER_ETH] = { 754 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 755 .type = RTE_FLOW_ITEM_TYPE_ETH, 756 .rss_types = 0, 757 }, 758 [MLX5_EXPANSION_OUTER_VLAN] = { 759 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 760 MLX5_EXPANSION_OUTER_IPV6), 761 .type = RTE_FLOW_ITEM_TYPE_VLAN, 762 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 763 }, 764 [MLX5_EXPANSION_OUTER_IPV4] = { 765 .next = MLX5_FLOW_EXPAND_RSS_NEXT 766 (MLX5_EXPANSION_OUTER_IPV4_UDP, 767 MLX5_EXPANSION_OUTER_IPV4_TCP, 768 MLX5_EXPANSION_OUTER_IPV4_ESP, 769 MLX5_EXPANSION_OUTER_IPV4_ICMP, 770 MLX5_EXPANSION_GRE, 771 MLX5_EXPANSION_NVGRE, 772 MLX5_EXPANSION_IPV4, 773 MLX5_EXPANSION_IPV6), 774 .type = RTE_FLOW_ITEM_TYPE_IPV4, 775 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 776 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 777 }, 778 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 779 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 780 MLX5_EXPANSION_VXLAN_GPE, 781 MLX5_EXPANSION_MPLS, 782 MLX5_EXPANSION_GENEVE, 783 MLX5_EXPANSION_GTP), 784 .type = RTE_FLOW_ITEM_TYPE_UDP, 785 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 786 }, 787 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 788 .type = RTE_FLOW_ITEM_TYPE_TCP, 789 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 790 }, 791 [MLX5_EXPANSION_OUTER_IPV4_ESP] = { 792 .type = RTE_FLOW_ITEM_TYPE_ESP, 793 .rss_types = RTE_ETH_RSS_ESP, 794 }, 795 [MLX5_EXPANSION_OUTER_IPV4_ICMP] = { 796 .type = RTE_FLOW_ITEM_TYPE_ICMP, 797 }, 798 [MLX5_EXPANSION_OUTER_IPV6] = { 799 .next = MLX5_FLOW_EXPAND_RSS_NEXT 800 (MLX5_EXPANSION_OUTER_IPV6_UDP, 801 MLX5_EXPANSION_OUTER_IPV6_TCP, 802 MLX5_EXPANSION_OUTER_IPV6_ESP, 803 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 804 MLX5_EXPANSION_IPV4, 805 MLX5_EXPANSION_IPV6, 806 MLX5_EXPANSION_GRE, 807 MLX5_EXPANSION_NVGRE), 808 .type = RTE_FLOW_ITEM_TYPE_IPV6, 809 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 810 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 811 }, 812 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 813 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 814 MLX5_EXPANSION_VXLAN_GPE, 815 MLX5_EXPANSION_MPLS, 816 MLX5_EXPANSION_GENEVE, 817 MLX5_EXPANSION_GTP), 818 .type = RTE_FLOW_ITEM_TYPE_UDP, 819 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 820 }, 821 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 822 .type = RTE_FLOW_ITEM_TYPE_TCP, 823 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 824 }, 825 [MLX5_EXPANSION_OUTER_IPV6_ESP] = { 826 .type = RTE_FLOW_ITEM_TYPE_ESP, 827 .rss_types = RTE_ETH_RSS_ESP, 828 }, 829 [MLX5_EXPANSION_OUTER_IPV6_ICMP6] = { 830 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 831 }, 832 [MLX5_EXPANSION_VXLAN] = { 833 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 834 MLX5_EXPANSION_IPV4, 835 MLX5_EXPANSION_IPV6), 836 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 837 }, 838 [MLX5_EXPANSION_STD_VXLAN] = { 839 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 840 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 841 }, 842 [MLX5_EXPANSION_L3_VXLAN] = { 843 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 844 MLX5_EXPANSION_IPV6), 845 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 846 }, 847 [MLX5_EXPANSION_VXLAN_GPE] = { 848 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 849 MLX5_EXPANSION_IPV4, 850 MLX5_EXPANSION_IPV6), 851 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 852 }, 853 [MLX5_EXPANSION_GRE] = { 854 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 855 MLX5_EXPANSION_IPV4, 856 MLX5_EXPANSION_IPV6, 857 MLX5_EXPANSION_GRE_KEY, 858 MLX5_EXPANSION_MPLS), 859 .type = RTE_FLOW_ITEM_TYPE_GRE, 860 }, 861 [MLX5_EXPANSION_GRE_KEY] = { 862 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 863 MLX5_EXPANSION_IPV6, 864 MLX5_EXPANSION_MPLS), 865 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 866 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 867 }, 868 [MLX5_EXPANSION_NVGRE] = { 869 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 870 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 871 }, 872 [MLX5_EXPANSION_MPLS] = { 873 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 874 MLX5_EXPANSION_IPV6, 875 MLX5_EXPANSION_ETH), 876 .type = RTE_FLOW_ITEM_TYPE_MPLS, 877 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 878 }, 879 [MLX5_EXPANSION_ETH] = { 880 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 881 .type = RTE_FLOW_ITEM_TYPE_ETH, 882 }, 883 [MLX5_EXPANSION_VLAN] = { 884 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 885 MLX5_EXPANSION_IPV6), 886 .type = RTE_FLOW_ITEM_TYPE_VLAN, 887 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 888 }, 889 [MLX5_EXPANSION_IPV4] = { 890 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 891 MLX5_EXPANSION_IPV4_TCP, 892 MLX5_EXPANSION_IPV4_ESP, 893 MLX5_EXPANSION_IPV4_ICMP), 894 .type = RTE_FLOW_ITEM_TYPE_IPV4, 895 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 896 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 897 }, 898 [MLX5_EXPANSION_IPV4_UDP] = { 899 .type = RTE_FLOW_ITEM_TYPE_UDP, 900 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 901 }, 902 [MLX5_EXPANSION_IPV4_TCP] = { 903 .type = RTE_FLOW_ITEM_TYPE_TCP, 904 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 905 }, 906 [MLX5_EXPANSION_IPV4_ESP] = { 907 .type = RTE_FLOW_ITEM_TYPE_ESP, 908 .rss_types = RTE_ETH_RSS_ESP, 909 }, 910 [MLX5_EXPANSION_IPV4_ICMP] = { 911 .type = RTE_FLOW_ITEM_TYPE_ICMP, 912 }, 913 [MLX5_EXPANSION_IPV6] = { 914 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 915 MLX5_EXPANSION_IPV6_TCP, 916 MLX5_EXPANSION_IPV6_ESP, 917 MLX5_EXPANSION_IPV6_ICMP6, 918 MLX5_EXPANSION_IPV6_FRAG_EXT), 919 .type = RTE_FLOW_ITEM_TYPE_IPV6, 920 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 921 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 922 }, 923 [MLX5_EXPANSION_IPV6_UDP] = { 924 .type = RTE_FLOW_ITEM_TYPE_UDP, 925 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 926 }, 927 [MLX5_EXPANSION_IPV6_TCP] = { 928 .type = RTE_FLOW_ITEM_TYPE_TCP, 929 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 930 }, 931 [MLX5_EXPANSION_IPV6_ESP] = { 932 .type = RTE_FLOW_ITEM_TYPE_ESP, 933 .rss_types = RTE_ETH_RSS_ESP, 934 }, 935 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 936 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 937 }, 938 [MLX5_EXPANSION_IPV6_ICMP6] = { 939 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 940 }, 941 [MLX5_EXPANSION_GTP] = { 942 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 943 MLX5_EXPANSION_IPV6), 944 .type = RTE_FLOW_ITEM_TYPE_GTP, 945 }, 946 [MLX5_EXPANSION_GENEVE] = { 947 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 948 MLX5_EXPANSION_IPV4, 949 MLX5_EXPANSION_IPV6), 950 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 951 }, 952 }; 953 954 static struct rte_flow_action_handle * 955 mlx5_action_handle_create(struct rte_eth_dev *dev, 956 const struct rte_flow_indir_action_conf *conf, 957 const struct rte_flow_action *action, 958 struct rte_flow_error *error); 959 static int mlx5_action_handle_destroy 960 (struct rte_eth_dev *dev, 961 struct rte_flow_action_handle *handle, 962 struct rte_flow_error *error); 963 static int mlx5_action_handle_update 964 (struct rte_eth_dev *dev, 965 struct rte_flow_action_handle *handle, 966 const void *update, 967 struct rte_flow_error *error); 968 static int mlx5_action_handle_query 969 (struct rte_eth_dev *dev, 970 const struct rte_flow_action_handle *handle, 971 void *data, 972 struct rte_flow_error *error); 973 static int 974 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 975 struct rte_flow_tunnel *app_tunnel, 976 struct rte_flow_action **actions, 977 uint32_t *num_of_actions, 978 struct rte_flow_error *error); 979 static int 980 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 981 struct rte_flow_tunnel *app_tunnel, 982 struct rte_flow_item **items, 983 uint32_t *num_of_items, 984 struct rte_flow_error *error); 985 static int 986 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 987 struct rte_flow_item *pmd_items, 988 uint32_t num_items, struct rte_flow_error *err); 989 static int 990 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 991 struct rte_flow_action *pmd_actions, 992 uint32_t num_actions, 993 struct rte_flow_error *err); 994 static int 995 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 996 struct rte_mbuf *m, 997 struct rte_flow_restore_info *info, 998 struct rte_flow_error *err); 999 static struct rte_flow_item_flex_handle * 1000 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 1001 const struct rte_flow_item_flex_conf *conf, 1002 struct rte_flow_error *error); 1003 static int 1004 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 1005 const struct rte_flow_item_flex_handle *handle, 1006 struct rte_flow_error *error); 1007 static int 1008 mlx5_flow_info_get(struct rte_eth_dev *dev, 1009 struct rte_flow_port_info *port_info, 1010 struct rte_flow_queue_info *queue_info, 1011 struct rte_flow_error *error); 1012 static int 1013 mlx5_flow_port_configure(struct rte_eth_dev *dev, 1014 const struct rte_flow_port_attr *port_attr, 1015 uint16_t nb_queue, 1016 const struct rte_flow_queue_attr *queue_attr[], 1017 struct rte_flow_error *err); 1018 1019 static struct rte_flow_pattern_template * 1020 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 1021 const struct rte_flow_pattern_template_attr *attr, 1022 const struct rte_flow_item items[], 1023 struct rte_flow_error *error); 1024 1025 static int 1026 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 1027 struct rte_flow_pattern_template *template, 1028 struct rte_flow_error *error); 1029 static struct rte_flow_actions_template * 1030 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 1031 const struct rte_flow_actions_template_attr *attr, 1032 const struct rte_flow_action actions[], 1033 const struct rte_flow_action masks[], 1034 struct rte_flow_error *error); 1035 static int 1036 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 1037 struct rte_flow_actions_template *template, 1038 struct rte_flow_error *error); 1039 1040 static struct rte_flow_template_table * 1041 mlx5_flow_table_create(struct rte_eth_dev *dev, 1042 const struct rte_flow_template_table_attr *attr, 1043 struct rte_flow_pattern_template *item_templates[], 1044 uint8_t nb_item_templates, 1045 struct rte_flow_actions_template *action_templates[], 1046 uint8_t nb_action_templates, 1047 struct rte_flow_error *error); 1048 static int 1049 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 1050 struct rte_flow_template_table *table, 1051 struct rte_flow_error *error); 1052 static int 1053 mlx5_flow_group_set_miss_actions(struct rte_eth_dev *dev, 1054 uint32_t group_id, 1055 const struct rte_flow_group_attr *attr, 1056 const struct rte_flow_action actions[], 1057 struct rte_flow_error *error); 1058 1059 static int 1060 mlx5_action_handle_query_update(struct rte_eth_dev *dev, 1061 struct rte_flow_action_handle *handle, 1062 const void *update, void *query, 1063 enum rte_flow_query_update_mode qu_mode, 1064 struct rte_flow_error *error); 1065 1066 static struct rte_flow_action_list_handle * 1067 mlx5_action_list_handle_create(struct rte_eth_dev *dev, 1068 const struct rte_flow_indir_action_conf *conf, 1069 const struct rte_flow_action *actions, 1070 struct rte_flow_error *error); 1071 1072 static int 1073 mlx5_action_list_handle_destroy(struct rte_eth_dev *dev, 1074 struct rte_flow_action_list_handle *handle, 1075 struct rte_flow_error *error); 1076 1077 static int 1078 mlx5_flow_action_list_handle_query_update(struct rte_eth_dev *dev, 1079 const 1080 struct rte_flow_action_list_handle *handle, 1081 const void **update, void **query, 1082 enum rte_flow_query_update_mode mode, 1083 struct rte_flow_error *error); 1084 1085 static int 1086 mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, 1087 const struct rte_flow_template_table *table, 1088 const struct rte_flow_item pattern[], 1089 uint8_t pattern_template_index, 1090 uint32_t *hash, struct rte_flow_error *error); 1091 static int 1092 mlx5_flow_calc_encap_hash(struct rte_eth_dev *dev, 1093 const struct rte_flow_item pattern[], 1094 enum rte_flow_encap_hash_field dest_field, 1095 uint8_t *hash, 1096 struct rte_flow_error *error); 1097 1098 static int 1099 mlx5_template_table_resize(struct rte_eth_dev *dev, 1100 struct rte_flow_template_table *table, 1101 uint32_t nb_rules, struct rte_flow_error *error); 1102 static int 1103 mlx5_flow_async_update_resized(struct rte_eth_dev *dev, uint32_t queue, 1104 const struct rte_flow_op_attr *attr, 1105 struct rte_flow *rule, void *user_data, 1106 struct rte_flow_error *error); 1107 static int 1108 mlx5_table_resize_complete(struct rte_eth_dev *dev, 1109 struct rte_flow_template_table *table, 1110 struct rte_flow_error *error); 1111 1112 static const struct rte_flow_ops mlx5_flow_ops = { 1113 .validate = mlx5_flow_validate, 1114 .create = mlx5_flow_create, 1115 .destroy = mlx5_flow_destroy, 1116 .flush = mlx5_flow_flush, 1117 .isolate = mlx5_flow_isolate, 1118 .query = mlx5_flow_query, 1119 .dev_dump = mlx5_flow_dev_dump, 1120 .get_q_aged_flows = mlx5_flow_get_q_aged_flows, 1121 .get_aged_flows = mlx5_flow_get_aged_flows, 1122 .action_handle_create = mlx5_action_handle_create, 1123 .action_handle_destroy = mlx5_action_handle_destroy, 1124 .action_handle_update = mlx5_action_handle_update, 1125 .action_handle_query = mlx5_action_handle_query, 1126 .action_handle_query_update = mlx5_action_handle_query_update, 1127 .action_list_handle_create = mlx5_action_list_handle_create, 1128 .action_list_handle_destroy = mlx5_action_list_handle_destroy, 1129 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 1130 .tunnel_match = mlx5_flow_tunnel_match, 1131 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 1132 .tunnel_item_release = mlx5_flow_tunnel_item_release, 1133 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 1134 .flex_item_create = mlx5_flow_flex_item_create, 1135 .flex_item_release = mlx5_flow_flex_item_release, 1136 .info_get = mlx5_flow_info_get, 1137 .pick_transfer_proxy = mlx5_flow_pick_transfer_proxy, 1138 .configure = mlx5_flow_port_configure, 1139 .pattern_template_create = mlx5_flow_pattern_template_create, 1140 .pattern_template_destroy = mlx5_flow_pattern_template_destroy, 1141 .actions_template_create = mlx5_flow_actions_template_create, 1142 .actions_template_destroy = mlx5_flow_actions_template_destroy, 1143 .template_table_create = mlx5_flow_table_create, 1144 .template_table_destroy = mlx5_flow_table_destroy, 1145 .group_set_miss_actions = mlx5_flow_group_set_miss_actions, 1146 .action_list_handle_query_update = 1147 mlx5_flow_action_list_handle_query_update, 1148 .flow_calc_table_hash = mlx5_flow_calc_table_hash, 1149 .flow_calc_encap_hash = mlx5_flow_calc_encap_hash, 1150 .flow_template_table_resize = mlx5_template_table_resize, 1151 .flow_update_resized = mlx5_flow_async_update_resized, 1152 .flow_template_table_resize_complete = mlx5_table_resize_complete, 1153 }; 1154 1155 /* Tunnel information. */ 1156 struct mlx5_flow_tunnel_info { 1157 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 1158 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 1159 }; 1160 1161 static struct mlx5_flow_tunnel_info tunnels_info[] = { 1162 { 1163 .tunnel = MLX5_FLOW_LAYER_VXLAN, 1164 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 1165 }, 1166 { 1167 .tunnel = MLX5_FLOW_LAYER_GENEVE, 1168 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 1169 }, 1170 { 1171 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 1172 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 1173 }, 1174 { 1175 .tunnel = MLX5_FLOW_LAYER_GRE, 1176 .ptype = RTE_PTYPE_TUNNEL_GRE, 1177 }, 1178 { 1179 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 1180 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 1181 }, 1182 { 1183 .tunnel = MLX5_FLOW_LAYER_MPLS, 1184 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 1185 }, 1186 { 1187 .tunnel = MLX5_FLOW_LAYER_NVGRE, 1188 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 1189 }, 1190 { 1191 .tunnel = MLX5_FLOW_LAYER_IPIP, 1192 .ptype = RTE_PTYPE_TUNNEL_IP, 1193 }, 1194 { 1195 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 1196 .ptype = RTE_PTYPE_TUNNEL_IP, 1197 }, 1198 { 1199 .tunnel = MLX5_FLOW_LAYER_GTP, 1200 .ptype = RTE_PTYPE_TUNNEL_GTPU, 1201 }, 1202 }; 1203 1204 1205 1206 /** 1207 * Translate tag ID to register. 1208 * 1209 * @param[in] dev 1210 * Pointer to the Ethernet device structure. 1211 * @param[in] feature 1212 * The feature that request the register. 1213 * @param[in] id 1214 * The request register ID. 1215 * @param[out] error 1216 * Error description in case of any. 1217 * 1218 * @return 1219 * The request register on success, a negative errno 1220 * value otherwise and rte_errno is set. 1221 */ 1222 int 1223 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1224 enum mlx5_feature_name feature, 1225 uint32_t id, 1226 struct rte_flow_error *error) 1227 { 1228 struct mlx5_priv *priv = dev->data->dev_private; 1229 struct mlx5_sh_config *config = &priv->sh->config; 1230 struct mlx5_dev_registers *reg = &priv->sh->registers; 1231 enum modify_reg start_reg; 1232 bool skip_mtr_reg = false; 1233 1234 switch (feature) { 1235 case MLX5_HAIRPIN_RX: 1236 return REG_B; 1237 case MLX5_HAIRPIN_TX: 1238 return REG_A; 1239 case MLX5_METADATA_RX: 1240 switch (config->dv_xmeta_en) { 1241 case MLX5_XMETA_MODE_LEGACY: 1242 return REG_B; 1243 case MLX5_XMETA_MODE_META16: 1244 return REG_C_0; 1245 case MLX5_XMETA_MODE_META32: 1246 return REG_C_1; 1247 case MLX5_XMETA_MODE_META32_HWS: 1248 return REG_C_1; 1249 } 1250 break; 1251 case MLX5_METADATA_TX: 1252 if (config->dv_flow_en == 2 && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { 1253 return REG_C_1; 1254 } else { 1255 return REG_A; 1256 } 1257 case MLX5_METADATA_FDB: 1258 switch (config->dv_xmeta_en) { 1259 case MLX5_XMETA_MODE_LEGACY: 1260 return REG_NON; 1261 case MLX5_XMETA_MODE_META16: 1262 return REG_C_0; 1263 case MLX5_XMETA_MODE_META32: 1264 return REG_C_1; 1265 case MLX5_XMETA_MODE_META32_HWS: 1266 return REG_C_1; 1267 } 1268 break; 1269 case MLX5_FLOW_MARK: 1270 switch (config->dv_xmeta_en) { 1271 case MLX5_XMETA_MODE_LEGACY: 1272 case MLX5_XMETA_MODE_META32_HWS: 1273 return REG_NON; 1274 case MLX5_XMETA_MODE_META16: 1275 return REG_C_1; 1276 case MLX5_XMETA_MODE_META32: 1277 return REG_C_0; 1278 } 1279 break; 1280 case MLX5_MTR_ID: 1281 /* 1282 * If meter color and meter id share one register, flow match 1283 * should use the meter color register for match. 1284 */ 1285 if (priv->mtr_reg_share) 1286 return reg->aso_reg; 1287 else 1288 return reg->aso_reg != REG_C_2 ? REG_C_2 : 1289 REG_C_3; 1290 case MLX5_MTR_COLOR: 1291 case MLX5_ASO_FLOW_HIT: 1292 case MLX5_ASO_CONNTRACK: 1293 case MLX5_SAMPLE_ID: 1294 /* All features use the same REG_C. */ 1295 MLX5_ASSERT(reg->aso_reg != REG_NON); 1296 return reg->aso_reg; 1297 case MLX5_COPY_MARK: 1298 /* 1299 * Metadata COPY_MARK register using is in meter suffix sub 1300 * flow while with meter. It's safe to share the same register. 1301 */ 1302 return reg->aso_reg != REG_C_2 ? REG_C_2 : REG_C_3; 1303 case MLX5_APP_TAG: 1304 /* 1305 * If meter is enable, it will engage the register for color 1306 * match and flow match. If meter color match is not using the 1307 * REG_C_2, need to skip the REG_C_x be used by meter color 1308 * match. 1309 * If meter is disable, free to use all available registers. 1310 */ 1311 start_reg = reg->aso_reg != REG_C_2 ? REG_C_2 : 1312 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 1313 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 1314 if (id > (uint32_t)(REG_C_7 - start_reg)) 1315 return rte_flow_error_set(error, EINVAL, 1316 RTE_FLOW_ERROR_TYPE_ITEM, 1317 NULL, "invalid tag id"); 1318 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 1319 return rte_flow_error_set(error, ENOTSUP, 1320 RTE_FLOW_ERROR_TYPE_ITEM, 1321 NULL, "unsupported tag id"); 1322 /* 1323 * This case means meter is using the REG_C_x great than 2. 1324 * Take care not to conflict with meter color REG_C_x. 1325 * If the available index REG_C_y >= REG_C_x, skip the 1326 * color register. 1327 */ 1328 if (skip_mtr_reg && priv->sh->flow_mreg_c 1329 [id + start_reg - REG_C_0] >= reg->aso_reg) { 1330 if (id >= (uint32_t)(REG_C_7 - start_reg)) 1331 return rte_flow_error_set(error, EINVAL, 1332 RTE_FLOW_ERROR_TYPE_ITEM, 1333 NULL, "invalid tag id"); 1334 if (priv->sh->flow_mreg_c 1335 [id + 1 + start_reg - REG_C_0] != REG_NON) 1336 return priv->sh->flow_mreg_c 1337 [id + 1 + start_reg - REG_C_0]; 1338 return rte_flow_error_set(error, ENOTSUP, 1339 RTE_FLOW_ERROR_TYPE_ITEM, 1340 NULL, "unsupported tag id"); 1341 } 1342 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 1343 } 1344 MLX5_ASSERT(false); 1345 return rte_flow_error_set(error, EINVAL, 1346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 1347 NULL, "invalid feature name"); 1348 } 1349 1350 /** 1351 * Check extensive flow metadata register support. 1352 * 1353 * @param dev 1354 * Pointer to rte_eth_dev structure. 1355 * 1356 * @return 1357 * True if device supports extensive flow metadata register, otherwise false. 1358 */ 1359 bool 1360 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1361 { 1362 struct mlx5_priv *priv = dev->data->dev_private; 1363 1364 /* 1365 * Having available reg_c can be regarded inclusively as supporting 1366 * extensive flow metadata register, which could mean, 1367 * - metadata register copy action by modify header. 1368 * - 16 modify header actions is supported. 1369 * - reg_c's are preserved across different domain (FDB and NIC) on 1370 * packet loopback by flow lookup miss. 1371 */ 1372 return priv->sh->flow_mreg_c[2] != REG_NON; 1373 } 1374 1375 /** 1376 * Get the lowest priority. 1377 * 1378 * @param[in] dev 1379 * Pointer to the Ethernet device structure. 1380 * @param[in] attributes 1381 * Pointer to device flow rule attributes. 1382 * 1383 * @return 1384 * The value of lowest priority of flow. 1385 */ 1386 uint32_t 1387 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1388 const struct rte_flow_attr *attr) 1389 { 1390 struct mlx5_priv *priv = dev->data->dev_private; 1391 1392 if (!attr->group && !(attr->transfer && priv->fdb_def_rule)) 1393 return priv->sh->flow_max_priority - 2; 1394 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1395 } 1396 1397 /** 1398 * Calculate matcher priority of the flow. 1399 * 1400 * @param[in] dev 1401 * Pointer to the Ethernet device structure. 1402 * @param[in] attr 1403 * Pointer to device flow rule attributes. 1404 * @param[in] subpriority 1405 * The priority based on the items. 1406 * @param[in] external 1407 * Flow is user flow. 1408 * @return 1409 * The matcher priority of the flow. 1410 */ 1411 uint16_t 1412 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1413 const struct rte_flow_attr *attr, 1414 uint32_t subpriority, bool external) 1415 { 1416 uint16_t priority = (uint16_t)attr->priority; 1417 struct mlx5_priv *priv = dev->data->dev_private; 1418 1419 /* NIC root rules */ 1420 if (!attr->group && !attr->transfer) { 1421 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1422 priority = priv->sh->flow_max_priority - 1; 1423 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1424 /* FDB root rules */ 1425 } else if (attr->transfer && (!external || !priv->fdb_def_rule) && 1426 attr->group == 0 && 1427 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1428 return (priv->sh->flow_max_priority - 1) * 3; 1429 } 1430 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1431 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1432 return priority * 3 + subpriority; 1433 } 1434 1435 /** 1436 * Verify the @p item specifications (spec, last, mask) are compatible with the 1437 * NIC capabilities. 1438 * 1439 * @param[in] item 1440 * Item specification. 1441 * @param[in] mask 1442 * @p item->mask or flow default bit-masks. 1443 * @param[in] nic_mask 1444 * Bit-masks covering supported fields by the NIC to compare with user mask. 1445 * @param[in] size 1446 * Bit-masks size in bytes. 1447 * @param[in] range_accepted 1448 * True if range of values is accepted for specific fields, false otherwise. 1449 * @param[out] error 1450 * Pointer to error structure. 1451 * 1452 * @return 1453 * 0 on success, a negative errno value otherwise and rte_errno is set. 1454 */ 1455 int 1456 mlx5_flow_item_acceptable(const struct rte_eth_dev *dev, 1457 const struct rte_flow_item *item, 1458 const uint8_t *mask, 1459 const uint8_t *nic_mask, 1460 unsigned int size, 1461 bool range_accepted, 1462 struct rte_flow_error *error) 1463 { 1464 unsigned int i; 1465 1466 MLX5_ASSERT(nic_mask); 1467 for (i = 0; i < size; ++i) 1468 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1469 return rte_flow_error_set(error, ENOTSUP, 1470 RTE_FLOW_ERROR_TYPE_ITEM, 1471 item, 1472 "mask enables non supported" 1473 " bits"); 1474 if (mlx5_hws_active(dev)) 1475 return 0; 1476 if (!item->spec && (item->mask || item->last)) 1477 return rte_flow_error_set(error, EINVAL, 1478 RTE_FLOW_ERROR_TYPE_ITEM, item, 1479 "mask/last without a spec is not" 1480 " supported"); 1481 if (item->spec && item->last && !range_accepted) { 1482 uint8_t spec[size]; 1483 uint8_t last[size]; 1484 unsigned int i; 1485 int ret; 1486 1487 for (i = 0; i < size; ++i) { 1488 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1489 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1490 } 1491 ret = memcmp(spec, last, size); 1492 if (ret != 0) 1493 return rte_flow_error_set(error, EINVAL, 1494 RTE_FLOW_ERROR_TYPE_ITEM, 1495 item, 1496 "range is not valid"); 1497 } 1498 return 0; 1499 } 1500 1501 /** 1502 * Adjust the hash fields according to the @p flow information. 1503 * 1504 * @param[in] dev_flow. 1505 * Pointer to the mlx5_flow. 1506 * @param[in] tunnel 1507 * 1 when the hash field is for a tunnel item. 1508 * @param[in] layer_types 1509 * RTE_ETH_RSS_* types. 1510 * @param[in] hash_fields 1511 * Item hash fields. 1512 * 1513 * @return 1514 * The hash fields that should be used. 1515 */ 1516 uint64_t 1517 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1518 int tunnel __rte_unused, uint64_t layer_types, 1519 uint64_t hash_fields) 1520 { 1521 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1522 int rss_request_inner = rss_desc->level >= 2; 1523 1524 /* Check RSS hash level for tunnel. */ 1525 if (tunnel && rss_request_inner) 1526 hash_fields |= IBV_RX_HASH_INNER; 1527 else if (tunnel || rss_request_inner) 1528 return 0; 1529 #endif 1530 /* Check if requested layer matches RSS hash fields. */ 1531 if (!(rss_desc->types & layer_types)) 1532 return 0; 1533 return hash_fields; 1534 } 1535 1536 /** 1537 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1538 * if several tunnel rules are used on this queue, the tunnel ptype will be 1539 * cleared. 1540 * 1541 * @param rxq_ctrl 1542 * Rx queue to update. 1543 */ 1544 static void 1545 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1546 { 1547 unsigned int i; 1548 uint32_t tunnel_ptype = 0; 1549 1550 /* Look up for the ptype to use. */ 1551 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1552 if (!rxq_ctrl->flow_tunnels_n[i]) 1553 continue; 1554 if (!tunnel_ptype) { 1555 tunnel_ptype = tunnels_info[i].ptype; 1556 } else { 1557 tunnel_ptype = 0; 1558 break; 1559 } 1560 } 1561 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1562 } 1563 1564 /** 1565 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device 1566 * flow. 1567 * 1568 * @param[in] dev 1569 * Pointer to the Ethernet device structure. 1570 * @param[in] dev_handle 1571 * Pointer to device flow handle structure. 1572 */ 1573 void 1574 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1575 struct mlx5_flow_handle *dev_handle) 1576 { 1577 struct mlx5_priv *priv = dev->data->dev_private; 1578 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1579 struct mlx5_ind_table_obj *ind_tbl = NULL; 1580 unsigned int i; 1581 1582 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1583 struct mlx5_hrxq *hrxq; 1584 1585 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1586 dev_handle->rix_hrxq); 1587 if (hrxq) 1588 ind_tbl = hrxq->ind_table; 1589 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1590 struct mlx5_shared_action_rss *shared_rss; 1591 1592 shared_rss = mlx5_ipool_get 1593 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1594 dev_handle->rix_srss); 1595 if (shared_rss) 1596 ind_tbl = shared_rss->ind_tbl; 1597 } 1598 if (!ind_tbl) 1599 return; 1600 for (i = 0; i != ind_tbl->queues_n; ++i) { 1601 int idx = ind_tbl->queues[i]; 1602 struct mlx5_rxq_ctrl *rxq_ctrl; 1603 1604 if (mlx5_is_external_rxq(dev, idx)) 1605 continue; 1606 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1607 MLX5_ASSERT(rxq_ctrl != NULL); 1608 if (rxq_ctrl == NULL) 1609 continue; 1610 /* 1611 * To support metadata register copy on Tx loopback, 1612 * this must be always enabled (metadata may arive 1613 * from other port - not from local flows only. 1614 */ 1615 if (tunnel) { 1616 unsigned int j; 1617 1618 /* Increase the counter matching the flow. */ 1619 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1620 if ((tunnels_info[j].tunnel & 1621 dev_handle->layers) == 1622 tunnels_info[j].tunnel) { 1623 rxq_ctrl->flow_tunnels_n[j]++; 1624 break; 1625 } 1626 } 1627 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1628 } 1629 } 1630 } 1631 1632 static void 1633 flow_rxq_mark_flag_set(struct rte_eth_dev *dev) 1634 { 1635 struct mlx5_priv *priv = dev->data->dev_private; 1636 struct mlx5_rxq_ctrl *rxq_ctrl; 1637 uint16_t port_id; 1638 1639 if (priv->sh->shared_mark_enabled) 1640 return; 1641 if (priv->master || priv->representor) { 1642 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 1643 struct mlx5_priv *opriv = 1644 rte_eth_devices[port_id].data->dev_private; 1645 1646 if (!opriv || 1647 opriv->sh != priv->sh || 1648 opriv->domain_id != priv->domain_id || 1649 opriv->mark_enabled) 1650 continue; 1651 LIST_FOREACH(rxq_ctrl, &opriv->rxqsctrl, next) { 1652 rxq_ctrl->rxq.mark = 1; 1653 } 1654 opriv->mark_enabled = 1; 1655 } 1656 } else { 1657 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 1658 rxq_ctrl->rxq.mark = 1; 1659 } 1660 priv->mark_enabled = 1; 1661 } 1662 priv->sh->shared_mark_enabled = 1; 1663 } 1664 1665 /** 1666 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1667 * 1668 * @param[in] dev 1669 * Pointer to the Ethernet device structure. 1670 * @param[in] flow 1671 * Pointer to flow structure. 1672 */ 1673 static void 1674 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1675 { 1676 struct mlx5_priv *priv = dev->data->dev_private; 1677 uint32_t handle_idx; 1678 struct mlx5_flow_handle *dev_handle; 1679 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 1680 1681 MLX5_ASSERT(wks); 1682 if (wks->mark) 1683 flow_rxq_mark_flag_set(dev); 1684 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1685 handle_idx, dev_handle, next) 1686 flow_drv_rxq_flags_set(dev, dev_handle); 1687 } 1688 1689 /** 1690 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1691 * device flow if no other flow uses it with the same kind of request. 1692 * 1693 * @param dev 1694 * Pointer to Ethernet device. 1695 * @param[in] dev_handle 1696 * Pointer to the device flow handle structure. 1697 */ 1698 static void 1699 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1700 struct mlx5_flow_handle *dev_handle) 1701 { 1702 struct mlx5_priv *priv = dev->data->dev_private; 1703 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1704 struct mlx5_ind_table_obj *ind_tbl = NULL; 1705 unsigned int i; 1706 1707 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1708 struct mlx5_hrxq *hrxq; 1709 1710 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1711 dev_handle->rix_hrxq); 1712 if (hrxq) 1713 ind_tbl = hrxq->ind_table; 1714 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1715 struct mlx5_shared_action_rss *shared_rss; 1716 1717 shared_rss = mlx5_ipool_get 1718 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1719 dev_handle->rix_srss); 1720 if (shared_rss) 1721 ind_tbl = shared_rss->ind_tbl; 1722 } 1723 if (!ind_tbl) 1724 return; 1725 MLX5_ASSERT(dev->data->dev_started); 1726 for (i = 0; i != ind_tbl->queues_n; ++i) { 1727 int idx = ind_tbl->queues[i]; 1728 struct mlx5_rxq_ctrl *rxq_ctrl; 1729 1730 if (mlx5_is_external_rxq(dev, idx)) 1731 continue; 1732 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1733 MLX5_ASSERT(rxq_ctrl != NULL); 1734 if (rxq_ctrl == NULL) 1735 continue; 1736 if (tunnel) { 1737 unsigned int j; 1738 1739 /* Decrease the counter matching the flow. */ 1740 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1741 if ((tunnels_info[j].tunnel & 1742 dev_handle->layers) == 1743 tunnels_info[j].tunnel) { 1744 rxq_ctrl->flow_tunnels_n[j]--; 1745 break; 1746 } 1747 } 1748 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1749 } 1750 } 1751 } 1752 1753 /** 1754 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1755 * @p flow if no other flow uses it with the same kind of request. 1756 * 1757 * @param dev 1758 * Pointer to Ethernet device. 1759 * @param[in] flow 1760 * Pointer to the flow. 1761 */ 1762 static void 1763 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1764 { 1765 struct mlx5_priv *priv = dev->data->dev_private; 1766 uint32_t handle_idx; 1767 struct mlx5_flow_handle *dev_handle; 1768 1769 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1770 handle_idx, dev_handle, next) 1771 flow_drv_rxq_flags_trim(dev, dev_handle); 1772 } 1773 1774 /** 1775 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1776 * 1777 * @param dev 1778 * Pointer to Ethernet device. 1779 */ 1780 static void 1781 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1782 { 1783 struct mlx5_priv *priv = dev->data->dev_private; 1784 unsigned int i; 1785 1786 for (i = 0; i != priv->rxqs_n; ++i) { 1787 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1788 unsigned int j; 1789 1790 if (rxq == NULL || rxq->ctrl == NULL) 1791 continue; 1792 rxq->ctrl->rxq.mark = 0; 1793 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1794 rxq->ctrl->flow_tunnels_n[j] = 0; 1795 rxq->ctrl->rxq.tunnel = 0; 1796 } 1797 priv->mark_enabled = 0; 1798 priv->sh->shared_mark_enabled = 0; 1799 } 1800 1801 static uint64_t mlx5_restore_info_dynflag; 1802 1803 int 1804 mlx5_flow_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 1805 { 1806 struct mlx5_priv *priv = dev->data->dev_private; 1807 uint64_t supported = 0; 1808 1809 if (!is_tunnel_offload_active(dev)) { 1810 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 1811 supported |= RTE_ETH_RX_METADATA_USER_MARK; 1812 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0) { 1813 DRV_LOG(DEBUG, 1814 "tunnel offload was not activated, consider setting dv_xmeta_en=%d", 1815 MLX5_XMETA_MODE_MISS_INFO); 1816 } 1817 } else { 1818 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 1819 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0 && 1820 mlx5_restore_info_dynflag == 0) 1821 mlx5_restore_info_dynflag = rte_flow_restore_info_dynflag(); 1822 } 1823 1824 if (((*features & supported) & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0) 1825 priv->tunnel_enabled = 1; 1826 else 1827 priv->tunnel_enabled = 0; 1828 1829 *features &= supported; 1830 return 0; 1831 } 1832 1833 /** 1834 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1835 * 1836 * @param[in] dev 1837 * Pointer to the Ethernet device structure. 1838 */ 1839 void 1840 mlx5_flow_rxq_dynf_set(struct rte_eth_dev *dev) 1841 { 1842 struct mlx5_priv *priv = dev->data->dev_private; 1843 uint64_t mark_flag = RTE_MBUF_F_RX_FDIR_ID; 1844 unsigned int i; 1845 1846 if (priv->tunnel_enabled) 1847 mark_flag |= mlx5_restore_info_dynflag; 1848 1849 for (i = 0; i != priv->rxqs_n; ++i) { 1850 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1851 struct mlx5_rxq_data *data; 1852 1853 if (rxq == NULL || rxq->ctrl == NULL) 1854 continue; 1855 data = &rxq->ctrl->rxq; 1856 if (!rte_flow_dynf_metadata_avail()) { 1857 data->dynf_meta = 0; 1858 data->flow_meta_mask = 0; 1859 data->flow_meta_offset = -1; 1860 data->flow_meta_port_mask = 0; 1861 } else { 1862 data->dynf_meta = 1; 1863 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1864 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1865 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1866 } 1867 data->mark_flag = mark_flag; 1868 } 1869 } 1870 1871 /* 1872 * return a pointer to the desired action in the list of actions. 1873 * 1874 * @param[in] actions 1875 * The list of actions to search the action in. 1876 * @param[in] action 1877 * The action to find. 1878 * 1879 * @return 1880 * Pointer to the action in the list, if found. NULL otherwise. 1881 */ 1882 const struct rte_flow_action * 1883 mlx5_flow_find_action(const struct rte_flow_action *actions, 1884 enum rte_flow_action_type action) 1885 { 1886 if (actions == NULL) 1887 return NULL; 1888 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1889 if (actions->type == action) 1890 return actions; 1891 return NULL; 1892 } 1893 1894 /* 1895 * Validate the flag action. 1896 * 1897 * @param[in] action_flags 1898 * Bit-fields that holds the actions detected until now. 1899 * @param[in] attr 1900 * Attributes of flow that includes this action. 1901 * @param[out] error 1902 * Pointer to error structure. 1903 * 1904 * @return 1905 * 0 on success, a negative errno value otherwise and rte_errno is set. 1906 */ 1907 int 1908 mlx5_flow_validate_action_flag(uint64_t action_flags, 1909 const struct rte_flow_attr *attr, 1910 struct rte_flow_error *error) 1911 { 1912 if (action_flags & MLX5_FLOW_ACTION_MARK) 1913 return rte_flow_error_set(error, EINVAL, 1914 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1915 "can't mark and flag in same flow"); 1916 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1917 return rte_flow_error_set(error, EINVAL, 1918 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1919 "can't have 2 flag" 1920 " actions in same flow"); 1921 if (attr->egress) 1922 return rte_flow_error_set(error, ENOTSUP, 1923 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1924 "flag action not supported for " 1925 "egress"); 1926 return 0; 1927 } 1928 1929 /* 1930 * Validate the mark action. 1931 * 1932 * @param[in] action 1933 * Pointer to the queue action. 1934 * @param[in] action_flags 1935 * Bit-fields that holds the actions detected until now. 1936 * @param[in] attr 1937 * Attributes of flow that includes this action. 1938 * @param[out] error 1939 * Pointer to error structure. 1940 * 1941 * @return 1942 * 0 on success, a negative errno value otherwise and rte_errno is set. 1943 */ 1944 int 1945 mlx5_flow_validate_action_mark(struct rte_eth_dev *dev, 1946 const struct rte_flow_action *action, 1947 uint64_t action_flags, 1948 const struct rte_flow_attr *attr, 1949 struct rte_flow_error *error) 1950 { 1951 const struct rte_flow_action_mark *mark = action->conf; 1952 1953 if (!mark) 1954 return rte_flow_error_set(error, EINVAL, 1955 RTE_FLOW_ERROR_TYPE_ACTION, 1956 action, 1957 "configuration cannot be null"); 1958 if (mark->id >= MLX5_FLOW_MARK_MAX) 1959 return rte_flow_error_set(error, EINVAL, 1960 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1961 &mark->id, 1962 "mark id must in 0 <= id < " 1963 RTE_STR(MLX5_FLOW_MARK_MAX)); 1964 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1965 return rte_flow_error_set(error, EINVAL, 1966 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1967 "can't flag and mark in same flow"); 1968 if (action_flags & MLX5_FLOW_ACTION_MARK) 1969 return rte_flow_error_set(error, EINVAL, 1970 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1971 "can't have 2 mark actions in same" 1972 " flow"); 1973 if (attr->egress) 1974 return rte_flow_error_set(error, ENOTSUP, 1975 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1976 "mark action not supported for " 1977 "egress"); 1978 if (attr->transfer && mlx5_hws_active(dev)) 1979 return rte_flow_error_set(error, ENOTSUP, 1980 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1981 "non-template mark action not supported for transfer"); 1982 return 0; 1983 } 1984 1985 /* 1986 * Validate the drop action. 1987 * 1988 * @param[in] dev 1989 * Pointer to the Ethernet device structure. 1990 * @param[in] is_root 1991 * True if flow is validated for root table. False otherwise. 1992 * @param[in] attr 1993 * Attributes of flow that includes this action. 1994 * @param[out] error 1995 * Pointer to error structure. 1996 * 1997 * @return 1998 * 0 on success, a negative errno value otherwise and rte_errno is set. 1999 */ 2000 int 2001 mlx5_flow_validate_action_drop(struct rte_eth_dev *dev, 2002 bool is_root, 2003 const struct rte_flow_attr *attr, 2004 struct rte_flow_error *error) 2005 { 2006 struct mlx5_priv *priv = dev->data->dev_private; 2007 2008 if (priv->sh->config.dv_flow_en == 0 && attr->egress) 2009 return rte_flow_error_set(error, ENOTSUP, 2010 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2011 "drop action not supported for " 2012 "egress"); 2013 if (priv->sh->config.dv_flow_en == 1 && is_root && (attr->egress || attr->transfer) && 2014 !priv->sh->dr_root_drop_action_en) { 2015 return rte_flow_error_set(error, ENOTSUP, 2016 RTE_FLOW_ERROR_TYPE_ATTR, NULL, 2017 "drop action not supported for " 2018 "egress and transfer on group 0"); 2019 } 2020 return 0; 2021 } 2022 2023 /* 2024 * Validate the queue action. 2025 * 2026 * @param[in] action 2027 * Pointer to the queue action. 2028 * @param[in] action_flags 2029 * Bit-fields that holds the actions detected until now. 2030 * @param[in] dev 2031 * Pointer to the Ethernet device structure. 2032 * @param[in] attr 2033 * Attributes of flow that includes this action. 2034 * @param[out] error 2035 * Pointer to error structure. 2036 * 2037 * @return 2038 * 0 on success, a negative errno value otherwise and rte_errno is set. 2039 */ 2040 int 2041 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 2042 uint64_t action_flags, 2043 struct rte_eth_dev *dev, 2044 const struct rte_flow_attr *attr, 2045 struct rte_flow_error *error) 2046 { 2047 struct mlx5_priv *priv = dev->data->dev_private; 2048 const struct rte_flow_action_queue *queue = action->conf; 2049 2050 if (!queue) 2051 return rte_flow_error_set(error, EINVAL, 2052 RTE_FLOW_ERROR_TYPE_ACTION, action, 2053 "no QUEUE action configuration"); 2054 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2055 return rte_flow_error_set(error, EINVAL, 2056 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2057 "can't have 2 fate actions in" 2058 " same flow"); 2059 if (attr->egress) 2060 return rte_flow_error_set(error, ENOTSUP, 2061 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2062 "queue action not supported for egress."); 2063 if (mlx5_is_external_rxq(dev, queue->index)) 2064 return 0; 2065 if (!priv->rxqs_n) 2066 return rte_flow_error_set(error, EINVAL, 2067 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2068 NULL, "No Rx queues configured"); 2069 if (queue->index >= priv->rxqs_n) 2070 return rte_flow_error_set(error, EINVAL, 2071 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2072 &queue->index, 2073 "queue index out of range"); 2074 if (mlx5_rxq_get(dev, queue->index) == NULL) 2075 return rte_flow_error_set(error, EINVAL, 2076 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2077 &queue->index, 2078 "queue is not configured"); 2079 return 0; 2080 } 2081 2082 /** 2083 * Validate queue numbers for device RSS. 2084 * 2085 * @param[in] dev 2086 * Configured device. 2087 * @param[in] queues 2088 * Array of queue numbers. 2089 * @param[in] queues_n 2090 * Size of the @p queues array. 2091 * @param[out] error 2092 * On error, filled with a textual error description. 2093 * @param[out] queue_idx 2094 * On error, filled with an offending queue index in @p queues array. 2095 * 2096 * @return 2097 * 0 on success, a negative errno code on error. 2098 */ 2099 static int 2100 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 2101 const uint16_t *queues, uint32_t queues_n, 2102 const char **error, uint32_t *queue_idx) 2103 { 2104 const struct mlx5_priv *priv = dev->data->dev_private; 2105 bool is_hairpin = false; 2106 bool is_ext_rss = false; 2107 uint32_t i; 2108 2109 for (i = 0; i != queues_n; ++i) { 2110 struct mlx5_rxq_ctrl *rxq_ctrl; 2111 2112 if (mlx5_is_external_rxq(dev, queues[0])) { 2113 is_ext_rss = true; 2114 continue; 2115 } 2116 if (is_ext_rss) { 2117 *error = "Combining external and regular RSS queues is not supported"; 2118 *queue_idx = i; 2119 return -ENOTSUP; 2120 } 2121 if (queues[i] >= priv->rxqs_n) { 2122 *error = "queue index out of range"; 2123 *queue_idx = i; 2124 return -EINVAL; 2125 } 2126 rxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]); 2127 if (rxq_ctrl == NULL) { 2128 *error = "queue is not configured"; 2129 *queue_idx = i; 2130 return -EINVAL; 2131 } 2132 if (i == 0 && rxq_ctrl->is_hairpin) 2133 is_hairpin = true; 2134 if (is_hairpin != rxq_ctrl->is_hairpin) { 2135 *error = "combining hairpin and regular RSS queues is not supported"; 2136 *queue_idx = i; 2137 return -ENOTSUP; 2138 } 2139 } 2140 return 0; 2141 } 2142 2143 /* 2144 * Validate the rss action. 2145 * 2146 * @param[in] dev 2147 * Pointer to the Ethernet device structure. 2148 * @param[in] action 2149 * Pointer to the queue action. 2150 * @param[out] error 2151 * Pointer to error structure. 2152 * 2153 * @return 2154 * 0 on success, a negative errno value otherwise and rte_errno is set. 2155 */ 2156 int 2157 mlx5_validate_action_rss(struct rte_eth_dev *dev, 2158 const struct rte_flow_action *action, 2159 struct rte_flow_error *error) 2160 { 2161 struct mlx5_priv *priv = dev->data->dev_private; 2162 const struct rte_flow_action_rss *rss = action->conf; 2163 int ret; 2164 const char *message; 2165 uint32_t queue_idx; 2166 2167 if (!rss) 2168 return rte_flow_error_set 2169 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 2170 action, "no RSS action configuration"); 2171 if (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) { 2172 DRV_LOG(WARNING, "port %u symmetric RSS supported with SORT", 2173 dev->data->port_id); 2174 } else if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 2175 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 2176 return rte_flow_error_set(error, ENOTSUP, 2177 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2178 &rss->func, 2179 "RSS hash function not supported"); 2180 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2181 if (rss->level > 2) 2182 #else 2183 if (rss->level > 1) 2184 #endif 2185 return rte_flow_error_set(error, ENOTSUP, 2186 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2187 &rss->level, 2188 "tunnel RSS is not supported"); 2189 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 2190 if (rss->key_len == 0 && rss->key != NULL) 2191 return rte_flow_error_set(error, ENOTSUP, 2192 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2193 &rss->key_len, 2194 "RSS hash key length 0"); 2195 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 2196 return rte_flow_error_set(error, ENOTSUP, 2197 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2198 &rss->key_len, 2199 "RSS hash key too small"); 2200 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 2201 return rte_flow_error_set(error, ENOTSUP, 2202 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2203 &rss->key_len, 2204 "RSS hash key too large"); 2205 if (rss->queue_num > priv->sh->dev_cap.ind_table_max_size) 2206 return rte_flow_error_set(error, ENOTSUP, 2207 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2208 &rss->queue_num, 2209 "number of queues too large"); 2210 if (rss->types & MLX5_RSS_HF_MASK) 2211 return rte_flow_error_set(error, ENOTSUP, 2212 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2213 &rss->types, 2214 "some RSS protocols are not" 2215 " supported"); 2216 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 2217 !(rss->types & RTE_ETH_RSS_IP)) 2218 return rte_flow_error_set(error, EINVAL, 2219 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2220 "L3 partial RSS requested but L3 RSS" 2221 " type not specified"); 2222 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 2223 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 2224 return rte_flow_error_set(error, EINVAL, 2225 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2226 "L4 partial RSS requested but L4 RSS" 2227 " type not specified"); 2228 if (!priv->rxqs_n && priv->ext_rxqs == NULL) 2229 return rte_flow_error_set(error, EINVAL, 2230 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2231 NULL, "No Rx queues configured"); 2232 if (!rss->queue_num) 2233 return rte_flow_error_set(error, EINVAL, 2234 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2235 NULL, "No queues configured"); 2236 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 2237 &message, &queue_idx); 2238 if (ret != 0) { 2239 return rte_flow_error_set(error, -ret, 2240 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2241 &rss->queue[queue_idx], message); 2242 } 2243 return 0; 2244 } 2245 2246 /* 2247 * Validate the rss action. 2248 * 2249 * @param[in] action 2250 * Pointer to the queue action. 2251 * @param[in] action_flags 2252 * Bit-fields that holds the actions detected until now. 2253 * @param[in] dev 2254 * Pointer to the Ethernet device structure. 2255 * @param[in] attr 2256 * Attributes of flow that includes this action. 2257 * @param[in] item_flags 2258 * Items that were detected. 2259 * @param[out] error 2260 * Pointer to error structure. 2261 * 2262 * @return 2263 * 0 on success, a negative errno value otherwise and rte_errno is set. 2264 */ 2265 int 2266 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 2267 uint64_t action_flags, 2268 struct rte_eth_dev *dev, 2269 const struct rte_flow_attr *attr, 2270 uint64_t item_flags, 2271 struct rte_flow_error *error) 2272 { 2273 const struct rte_flow_action_rss *rss = action->conf; 2274 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2275 int ret; 2276 2277 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2278 return rte_flow_error_set(error, EINVAL, 2279 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2280 "can't have 2 fate actions" 2281 " in same flow"); 2282 ret = mlx5_validate_action_rss(dev, action, error); 2283 if (ret) 2284 return ret; 2285 if (attr->egress) 2286 return rte_flow_error_set(error, ENOTSUP, 2287 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2288 "rss action not supported for " 2289 "egress"); 2290 if (rss->level > 1 && !tunnel) 2291 return rte_flow_error_set(error, EINVAL, 2292 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2293 "inner RSS is not supported for " 2294 "non-tunnel flows"); 2295 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 2296 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 2297 return rte_flow_error_set(error, EINVAL, 2298 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2299 "RSS on eCPRI is not supported now"); 2300 } 2301 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 2302 !(item_flags & 2303 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 2304 rss->level > 1) 2305 return rte_flow_error_set(error, EINVAL, 2306 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 2307 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 2308 return 0; 2309 } 2310 2311 /* 2312 * Validate the default miss action. 2313 * 2314 * @param[in] action_flags 2315 * Bit-fields that holds the actions detected until now. 2316 * @param[out] error 2317 * Pointer to error structure. 2318 * 2319 * @return 2320 * 0 on success, a negative errno value otherwise and rte_errno is set. 2321 */ 2322 int 2323 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 2324 const struct rte_flow_attr *attr, 2325 struct rte_flow_error *error) 2326 { 2327 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2328 return rte_flow_error_set(error, EINVAL, 2329 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2330 "can't have 2 fate actions in" 2331 " same flow"); 2332 if (attr->egress) 2333 return rte_flow_error_set(error, ENOTSUP, 2334 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2335 "default miss action not supported " 2336 "for egress"); 2337 if (attr->group) 2338 return rte_flow_error_set(error, ENOTSUP, 2339 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 2340 "only group 0 is supported"); 2341 if (attr->transfer) 2342 return rte_flow_error_set(error, ENOTSUP, 2343 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2344 NULL, "transfer is not supported"); 2345 return 0; 2346 } 2347 2348 /* 2349 * Validate the count action. 2350 * 2351 * @param[in] dev 2352 * Pointer to the Ethernet device structure. 2353 * @param[in] attr 2354 * Attributes of flow that includes this action. 2355 * @param[out] error 2356 * Pointer to error structure. 2357 * 2358 * @return 2359 * 0 on success, a negative errno value otherwise and rte_errno is set. 2360 */ 2361 int 2362 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 2363 const struct rte_flow_attr *attr, 2364 struct rte_flow_error *error) 2365 { 2366 if (attr->egress) 2367 return rte_flow_error_set(error, ENOTSUP, 2368 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2369 "count action not supported for " 2370 "egress"); 2371 return 0; 2372 } 2373 2374 /* 2375 * Validate the ASO CT action. 2376 * 2377 * @param[in] dev 2378 * Pointer to the Ethernet device structure. 2379 * @param[in] conntrack 2380 * Pointer to the CT action profile. 2381 * @param[out] error 2382 * Pointer to error structure. 2383 * 2384 * @return 2385 * 0 on success, a negative errno value otherwise and rte_errno is set. 2386 */ 2387 int 2388 mlx5_validate_action_ct(struct rte_eth_dev *dev, 2389 const struct rte_flow_action_conntrack *conntrack, 2390 struct rte_flow_error *error) 2391 { 2392 RTE_SET_USED(dev); 2393 2394 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 2395 return rte_flow_error_set(error, EINVAL, 2396 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2397 "Invalid CT state"); 2398 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 2399 return rte_flow_error_set(error, EINVAL, 2400 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2401 "Invalid last TCP packet flag"); 2402 return 0; 2403 } 2404 2405 /** 2406 * Validate the level value for modify field action. 2407 * 2408 * @param[in] data 2409 * Pointer to the rte_flow_field_data structure either src or dst. 2410 * @param[out] error 2411 * Pointer to error structure. 2412 * 2413 * @return 2414 * 0 on success, a negative errno value otherwise and rte_errno is set. 2415 */ 2416 int 2417 flow_validate_modify_field_level(const struct rte_flow_field_data *data, 2418 struct rte_flow_error *error) 2419 { 2420 if (data->level == 0 || data->field == RTE_FLOW_FIELD_FLEX_ITEM) 2421 return 0; 2422 if (data->field != RTE_FLOW_FIELD_TAG && 2423 data->field != (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) { 2424 if (data->level > 1) 2425 return rte_flow_error_set(error, ENOTSUP, 2426 RTE_FLOW_ERROR_TYPE_ACTION, 2427 NULL, 2428 "inner header fields modification is not supported"); 2429 return 0; 2430 } 2431 if (data->tag_index != 0) 2432 return rte_flow_error_set(error, EINVAL, 2433 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2434 "tag array can be provided using 'level' or 'tag_index' fields, not both"); 2435 /* 2436 * The tag array for RTE_FLOW_FIELD_TAG type is provided using 2437 * 'tag_index' field. In old API, it was provided using 'level' field 2438 * and it is still supported for backwards compatibility. 2439 */ 2440 DRV_LOG(DEBUG, "tag array provided in 'level' field instead of 'tag_index' field."); 2441 return 0; 2442 } 2443 2444 /** 2445 * Validate ICMP6 item. 2446 * 2447 * @param[in] item 2448 * Item specification. 2449 * @param[in] item_flags 2450 * Bit-fields that holds the items detected until now. 2451 * @param[in] ext_vlan_sup 2452 * Whether extended VLAN features are supported or not. 2453 * @param[out] error 2454 * Pointer to error structure. 2455 * 2456 * @return 2457 * 0 on success, a negative errno value otherwise and rte_errno is set. 2458 */ 2459 int 2460 mlx5_flow_validate_item_icmp6(const struct rte_eth_dev *dev, 2461 const struct rte_flow_item *item, 2462 uint64_t item_flags, 2463 uint8_t target_protocol, 2464 struct rte_flow_error *error) 2465 { 2466 const struct rte_flow_item_icmp6 *mask = item->mask; 2467 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2468 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2469 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2470 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2471 MLX5_FLOW_LAYER_OUTER_L4; 2472 int ret; 2473 2474 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2475 return rte_flow_error_set(error, EINVAL, 2476 RTE_FLOW_ERROR_TYPE_ITEM, item, 2477 "protocol filtering not compatible" 2478 " with ICMP6 layer"); 2479 if (!mlx5_hws_active(dev)) { 2480 if (!(item_flags & l3m)) 2481 return rte_flow_error_set(error, EINVAL, 2482 RTE_FLOW_ERROR_TYPE_ITEM, 2483 item, "IPv6 is mandatory to filter on ICMP6"); 2484 } 2485 if (item_flags & l4m) 2486 return rte_flow_error_set(error, EINVAL, 2487 RTE_FLOW_ERROR_TYPE_ITEM, item, 2488 "multiple L4 layers not supported"); 2489 if (!mask) 2490 mask = &rte_flow_item_icmp6_mask; 2491 ret = mlx5_flow_item_acceptable 2492 (dev, item, (const uint8_t *)mask, 2493 (const uint8_t *)&rte_flow_item_icmp6_mask, 2494 sizeof(struct rte_flow_item_icmp6), 2495 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2496 if (ret < 0) 2497 return ret; 2498 return 0; 2499 } 2500 2501 /** 2502 * Validate ICMP6 echo request/reply item. 2503 * 2504 * @param[in] item 2505 * Item specification. 2506 * @param[in] item_flags 2507 * Bit-fields that holds the items detected until now. 2508 * @param[in] ext_vlan_sup 2509 * Whether extended VLAN features are supported or not. 2510 * @param[out] error 2511 * Pointer to error structure. 2512 * 2513 * @return 2514 * 0 on success, a negative errno value otherwise and rte_errno is set. 2515 */ 2516 int 2517 mlx5_flow_validate_item_icmp6_echo(const struct rte_eth_dev *dev, 2518 const struct rte_flow_item *item, 2519 uint64_t item_flags, 2520 uint8_t target_protocol, 2521 struct rte_flow_error *error) 2522 { 2523 const struct rte_flow_item_icmp6_echo *mask = item->mask; 2524 const struct rte_flow_item_icmp6_echo nic_mask = { 2525 .hdr.base.type = 0xff, 2526 .hdr.base.code = 0xff, 2527 .hdr.identifier = RTE_BE16(0xffff), 2528 .hdr.sequence = RTE_BE16(0xffff), 2529 }; 2530 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2531 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2532 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2533 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2534 MLX5_FLOW_LAYER_OUTER_L4; 2535 int ret; 2536 2537 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2538 return rte_flow_error_set(error, EINVAL, 2539 RTE_FLOW_ERROR_TYPE_ITEM, item, 2540 "protocol filtering not compatible" 2541 " with ICMP6 layer"); 2542 if (!mlx5_hws_active(dev)) { 2543 if (!(item_flags & l3m)) 2544 return rte_flow_error_set(error, EINVAL, 2545 RTE_FLOW_ERROR_TYPE_ITEM, 2546 item, "IPv6 is mandatory to filter on ICMP6"); 2547 } 2548 if (item_flags & l4m) 2549 return rte_flow_error_set(error, EINVAL, 2550 RTE_FLOW_ERROR_TYPE_ITEM, item, 2551 "multiple L4 layers not supported"); 2552 if (!mask) 2553 mask = &nic_mask; 2554 ret = mlx5_flow_item_acceptable 2555 (dev, item, (const uint8_t *)mask, 2556 (const uint8_t *)&nic_mask, 2557 sizeof(struct rte_flow_item_icmp6_echo), 2558 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2559 if (ret < 0) 2560 return ret; 2561 return 0; 2562 } 2563 2564 /** 2565 * Validate ICMP item. 2566 * 2567 * @param[in] item 2568 * Item specification. 2569 * @param[in] item_flags 2570 * Bit-fields that holds the items detected until now. 2571 * @param[out] error 2572 * Pointer to error structure. 2573 * 2574 * @return 2575 * 0 on success, a negative errno value otherwise and rte_errno is set. 2576 */ 2577 int 2578 mlx5_flow_validate_item_icmp(const struct rte_eth_dev *dev, 2579 const struct rte_flow_item *item, 2580 uint64_t item_flags, 2581 uint8_t target_protocol, 2582 struct rte_flow_error *error) 2583 { 2584 const struct rte_flow_item_icmp *mask = item->mask; 2585 const struct rte_flow_item_icmp nic_mask = { 2586 .hdr.icmp_type = 0xff, 2587 .hdr.icmp_code = 0xff, 2588 .hdr.icmp_ident = RTE_BE16(0xffff), 2589 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2590 }; 2591 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2592 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2593 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2594 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2595 MLX5_FLOW_LAYER_OUTER_L4; 2596 int ret; 2597 2598 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2599 return rte_flow_error_set(error, EINVAL, 2600 RTE_FLOW_ERROR_TYPE_ITEM, item, 2601 "protocol filtering not compatible" 2602 " with ICMP layer"); 2603 if (!mlx5_hws_active(dev)) { 2604 if (!(item_flags & l3m)) 2605 return rte_flow_error_set(error, EINVAL, 2606 RTE_FLOW_ERROR_TYPE_ITEM, 2607 item, "IPv4 is mandatory to filter on ICMP"); 2608 } 2609 if (item_flags & l4m) 2610 return rte_flow_error_set(error, EINVAL, 2611 RTE_FLOW_ERROR_TYPE_ITEM, item, 2612 "multiple L4 layers not supported"); 2613 if (!mask) 2614 mask = &nic_mask; 2615 ret = mlx5_flow_item_acceptable 2616 (dev, item, (const uint8_t *)mask, 2617 (const uint8_t *)&nic_mask, 2618 sizeof(struct rte_flow_item_icmp), 2619 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2620 if (ret < 0) 2621 return ret; 2622 return 0; 2623 } 2624 2625 /** 2626 * Validate Ethernet item. 2627 * 2628 * @param[in] item 2629 * Item specification. 2630 * @param[in] item_flags 2631 * Bit-fields that holds the items detected until now. 2632 * @param[out] error 2633 * Pointer to error structure. 2634 * 2635 * @return 2636 * 0 on success, a negative errno value otherwise and rte_errno is set. 2637 */ 2638 int 2639 mlx5_flow_validate_item_eth(const struct rte_eth_dev *dev, 2640 const struct rte_flow_item *item, 2641 uint64_t item_flags, bool ext_vlan_sup, 2642 struct rte_flow_error *error) 2643 { 2644 const struct rte_flow_item_eth *mask = item->mask; 2645 const struct rte_flow_item_eth nic_mask = { 2646 .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2647 .hdr.src_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2648 .hdr.ether_type = RTE_BE16(0xffff), 2649 .has_vlan = ext_vlan_sup ? 1 : 0, 2650 }; 2651 int ret; 2652 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2653 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2654 MLX5_FLOW_LAYER_OUTER_L2; 2655 2656 if (item_flags & ethm) 2657 return rte_flow_error_set(error, ENOTSUP, 2658 RTE_FLOW_ERROR_TYPE_ITEM, item, 2659 "multiple L2 layers not supported"); 2660 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2661 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2662 return rte_flow_error_set(error, EINVAL, 2663 RTE_FLOW_ERROR_TYPE_ITEM, item, 2664 "L2 layer should not follow " 2665 "L3 layers"); 2666 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2667 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2668 return rte_flow_error_set(error, EINVAL, 2669 RTE_FLOW_ERROR_TYPE_ITEM, item, 2670 "L2 layer should not follow VLAN"); 2671 if (item_flags & MLX5_FLOW_LAYER_GTP) 2672 return rte_flow_error_set(error, EINVAL, 2673 RTE_FLOW_ERROR_TYPE_ITEM, item, 2674 "L2 layer should not follow GTP"); 2675 if (!mask) 2676 mask = &rte_flow_item_eth_mask; 2677 ret = mlx5_flow_item_acceptable(dev, item, (const uint8_t *)mask, 2678 (const uint8_t *)&nic_mask, 2679 sizeof(struct rte_flow_item_eth), 2680 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2681 return ret; 2682 } 2683 2684 /** 2685 * Validate VLAN item. 2686 * 2687 * @param[in] item 2688 * Item specification. 2689 * @param[in] item_flags 2690 * Bit-fields that holds the items detected until now. 2691 * @param[in] dev 2692 * Ethernet device flow is being created on. 2693 * @param[out] error 2694 * Pointer to error structure. 2695 * 2696 * @return 2697 * 0 on success, a negative errno value otherwise and rte_errno is set. 2698 */ 2699 int 2700 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2701 uint64_t item_flags, 2702 struct rte_eth_dev *dev, 2703 struct rte_flow_error *error) 2704 { 2705 const struct rte_flow_item_vlan *spec = item->spec; 2706 const struct rte_flow_item_vlan *mask = item->mask; 2707 const struct rte_flow_item_vlan nic_mask = { 2708 .hdr.vlan_tci = RTE_BE16(UINT16_MAX), 2709 .hdr.eth_proto = RTE_BE16(UINT16_MAX), 2710 }; 2711 uint16_t vlan_tag = 0; 2712 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2713 int ret; 2714 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2715 MLX5_FLOW_LAYER_INNER_L4) : 2716 (MLX5_FLOW_LAYER_OUTER_L3 | 2717 MLX5_FLOW_LAYER_OUTER_L4); 2718 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2719 MLX5_FLOW_LAYER_OUTER_VLAN; 2720 2721 if (item_flags & vlanm) 2722 return rte_flow_error_set(error, EINVAL, 2723 RTE_FLOW_ERROR_TYPE_ITEM, item, 2724 "multiple VLAN layers not supported"); 2725 else if ((item_flags & l34m) != 0) 2726 return rte_flow_error_set(error, EINVAL, 2727 RTE_FLOW_ERROR_TYPE_ITEM, item, 2728 "VLAN cannot follow L3/L4 layer"); 2729 if (!mask) 2730 mask = &rte_flow_item_vlan_mask; 2731 ret = mlx5_flow_item_acceptable(dev, item, (const uint8_t *)mask, 2732 (const uint8_t *)&nic_mask, 2733 sizeof(struct rte_flow_item_vlan), 2734 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2735 if (ret) 2736 return ret; 2737 if (!tunnel && mask->hdr.vlan_tci != RTE_BE16(0x0fff)) { 2738 struct mlx5_priv *priv = dev->data->dev_private; 2739 2740 if (priv->vmwa_context) { 2741 /* 2742 * Non-NULL context means we have a virtual machine 2743 * and SR-IOV enabled, we have to create VLAN interface 2744 * to make hypervisor to setup E-Switch vport 2745 * context correctly. We avoid creating the multiple 2746 * VLAN interfaces, so we cannot support VLAN tag mask. 2747 */ 2748 return rte_flow_error_set(error, EINVAL, 2749 RTE_FLOW_ERROR_TYPE_ITEM, 2750 item, 2751 "VLAN tag mask is not" 2752 " supported in virtual" 2753 " environment"); 2754 } 2755 } 2756 if (spec) { 2757 vlan_tag = spec->hdr.vlan_tci; 2758 vlan_tag &= mask->hdr.vlan_tci; 2759 } 2760 /* 2761 * From verbs perspective an empty VLAN is equivalent 2762 * to a packet without VLAN layer. 2763 */ 2764 if (!vlan_tag) 2765 return rte_flow_error_set(error, EINVAL, 2766 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2767 item->spec, 2768 "VLAN cannot be empty"); 2769 return 0; 2770 } 2771 2772 /** 2773 * Validate IPV4 item. 2774 * 2775 * @param[in] item 2776 * Item specification. 2777 * @param[in] item_flags 2778 * Bit-fields that holds the items detected until now. 2779 * @param[in] last_item 2780 * Previous validated item in the pattern items. 2781 * @param[in] ether_type 2782 * Type in the ethernet layer header (including dot1q). 2783 * @param[in] acc_mask 2784 * Acceptable mask, if NULL default internal default mask 2785 * will be used to check whether item fields are supported. 2786 * @param[in] range_accepted 2787 * True if range of values is accepted for specific fields, false otherwise. 2788 * @param[out] error 2789 * Pointer to error structure. 2790 * 2791 * @return 2792 * 0 on success, a negative errno value otherwise and rte_errno is set. 2793 */ 2794 int 2795 mlx5_flow_validate_item_ipv4(const struct rte_eth_dev *dev, 2796 const struct rte_flow_item *item, 2797 uint64_t item_flags, 2798 uint64_t last_item, 2799 uint16_t ether_type, 2800 const struct rte_flow_item_ipv4 *acc_mask, 2801 bool range_accepted, 2802 struct rte_flow_error *error) 2803 { 2804 const struct rte_flow_item_ipv4 *mask = item->mask; 2805 const struct rte_flow_item_ipv4 *spec = item->spec; 2806 const struct rte_flow_item_ipv4 nic_mask = { 2807 .hdr = { 2808 .src_addr = RTE_BE32(0xffffffff), 2809 .dst_addr = RTE_BE32(0xffffffff), 2810 .type_of_service = 0xff, 2811 .next_proto_id = 0xff, 2812 }, 2813 }; 2814 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2815 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2816 MLX5_FLOW_LAYER_OUTER_L3; 2817 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2818 MLX5_FLOW_LAYER_OUTER_L4; 2819 int ret; 2820 uint8_t next_proto = 0xFF; 2821 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2822 MLX5_FLOW_LAYER_OUTER_VLAN | 2823 MLX5_FLOW_LAYER_INNER_VLAN); 2824 2825 if ((last_item & l2_vlan) && ether_type && 2826 ether_type != RTE_ETHER_TYPE_IPV4) 2827 return rte_flow_error_set(error, EINVAL, 2828 RTE_FLOW_ERROR_TYPE_ITEM, item, 2829 "IPv4 cannot follow L2/VLAN layer " 2830 "which ether type is not IPv4"); 2831 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2832 if (mask && spec) 2833 next_proto = mask->hdr.next_proto_id & 2834 spec->hdr.next_proto_id; 2835 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2836 return rte_flow_error_set(error, EINVAL, 2837 RTE_FLOW_ERROR_TYPE_ITEM, 2838 item, 2839 "multiple tunnel " 2840 "not supported"); 2841 } 2842 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2843 return rte_flow_error_set(error, EINVAL, 2844 RTE_FLOW_ERROR_TYPE_ITEM, item, 2845 "wrong tunnel type - IPv6 specified " 2846 "but IPv4 item provided"); 2847 if (item_flags & l3m) 2848 return rte_flow_error_set(error, ENOTSUP, 2849 RTE_FLOW_ERROR_TYPE_ITEM, item, 2850 "multiple L3 layers not supported"); 2851 else if (item_flags & l4m) 2852 return rte_flow_error_set(error, EINVAL, 2853 RTE_FLOW_ERROR_TYPE_ITEM, item, 2854 "L3 cannot follow an L4 layer."); 2855 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2856 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2857 return rte_flow_error_set(error, EINVAL, 2858 RTE_FLOW_ERROR_TYPE_ITEM, item, 2859 "L3 cannot follow an NVGRE layer."); 2860 if (!mask) 2861 mask = &rte_flow_item_ipv4_mask; 2862 else if (mask->hdr.next_proto_id != 0 && 2863 mask->hdr.next_proto_id != 0xff) 2864 return rte_flow_error_set(error, EINVAL, 2865 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2866 "partial mask is not supported" 2867 " for protocol"); 2868 ret = mlx5_flow_item_acceptable(dev, item, (const uint8_t *)mask, 2869 acc_mask ? (const uint8_t *)acc_mask 2870 : (const uint8_t *)&nic_mask, 2871 sizeof(struct rte_flow_item_ipv4), 2872 range_accepted, error); 2873 if (ret < 0) 2874 return ret; 2875 return 0; 2876 } 2877 2878 /** 2879 * Validate IPV6 item. 2880 * 2881 * @param[in] item 2882 * Item specification. 2883 * @param[in] item_flags 2884 * Bit-fields that holds the items detected until now. 2885 * @param[in] last_item 2886 * Previous validated item in the pattern items. 2887 * @param[in] ether_type 2888 * Type in the ethernet layer header (including dot1q). 2889 * @param[in] acc_mask 2890 * Acceptable mask, if NULL default internal default mask 2891 * will be used to check whether item fields are supported. 2892 * @param[out] error 2893 * Pointer to error structure. 2894 * 2895 * @return 2896 * 0 on success, a negative errno value otherwise and rte_errno is set. 2897 */ 2898 int 2899 mlx5_flow_validate_item_ipv6(const struct rte_eth_dev *dev, 2900 const struct rte_flow_item *item, 2901 uint64_t item_flags, 2902 uint64_t last_item, 2903 uint16_t ether_type, 2904 const struct rte_flow_item_ipv6 *acc_mask, 2905 struct rte_flow_error *error) 2906 { 2907 const struct rte_flow_item_ipv6 *mask = item->mask; 2908 const struct rte_flow_item_ipv6 *spec = item->spec; 2909 const struct rte_flow_item_ipv6 nic_mask = { 2910 .hdr = { 2911 .src_addr = 2912 "\xff\xff\xff\xff\xff\xff\xff\xff" 2913 "\xff\xff\xff\xff\xff\xff\xff\xff", 2914 .dst_addr = 2915 "\xff\xff\xff\xff\xff\xff\xff\xff" 2916 "\xff\xff\xff\xff\xff\xff\xff\xff", 2917 .vtc_flow = RTE_BE32(0xffffffff), 2918 .proto = 0xff, 2919 }, 2920 }; 2921 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2922 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2923 MLX5_FLOW_LAYER_OUTER_L3; 2924 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2925 MLX5_FLOW_LAYER_OUTER_L4; 2926 int ret; 2927 uint8_t next_proto = 0xFF; 2928 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2929 MLX5_FLOW_LAYER_OUTER_VLAN | 2930 MLX5_FLOW_LAYER_INNER_VLAN); 2931 2932 if ((last_item & l2_vlan) && ether_type && 2933 ether_type != RTE_ETHER_TYPE_IPV6) 2934 return rte_flow_error_set(error, EINVAL, 2935 RTE_FLOW_ERROR_TYPE_ITEM, item, 2936 "IPv6 cannot follow L2/VLAN layer " 2937 "which ether type is not IPv6"); 2938 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2939 next_proto = spec->hdr.proto; 2940 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2941 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2942 return rte_flow_error_set(error, EINVAL, 2943 RTE_FLOW_ERROR_TYPE_ITEM, 2944 item, 2945 "multiple tunnel " 2946 "not supported"); 2947 } 2948 if (next_proto == IPPROTO_HOPOPTS || 2949 next_proto == IPPROTO_ROUTING || 2950 next_proto == IPPROTO_FRAGMENT || 2951 next_proto == IPPROTO_AH || 2952 next_proto == IPPROTO_DSTOPTS || 2953 (!mlx5_hws_active(dev) && next_proto == IPPROTO_ESP)) 2954 return rte_flow_error_set(error, EINVAL, 2955 RTE_FLOW_ERROR_TYPE_ITEM, item, 2956 "IPv6 proto (next header) should " 2957 "not be set as extension header"); 2958 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2959 return rte_flow_error_set(error, EINVAL, 2960 RTE_FLOW_ERROR_TYPE_ITEM, item, 2961 "wrong tunnel type - IPv4 specified " 2962 "but IPv6 item provided"); 2963 if (item_flags & l3m) 2964 return rte_flow_error_set(error, ENOTSUP, 2965 RTE_FLOW_ERROR_TYPE_ITEM, item, 2966 "multiple L3 layers not supported"); 2967 else if (item_flags & l4m) 2968 return rte_flow_error_set(error, EINVAL, 2969 RTE_FLOW_ERROR_TYPE_ITEM, item, 2970 "L3 cannot follow an L4 layer."); 2971 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2972 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2973 return rte_flow_error_set(error, EINVAL, 2974 RTE_FLOW_ERROR_TYPE_ITEM, item, 2975 "L3 cannot follow an NVGRE layer."); 2976 if (!mask) 2977 mask = &rte_flow_item_ipv6_mask; 2978 ret = mlx5_flow_item_acceptable(dev, item, (const uint8_t *)mask, 2979 acc_mask ? (const uint8_t *)acc_mask 2980 : (const uint8_t *)&nic_mask, 2981 sizeof(struct rte_flow_item_ipv6), 2982 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2983 if (ret < 0) 2984 return ret; 2985 return 0; 2986 } 2987 2988 /** 2989 * Validate UDP item. 2990 * 2991 * @param[in] item 2992 * Item specification. 2993 * @param[in] item_flags 2994 * Bit-fields that holds the items detected until now. 2995 * @param[in] target_protocol 2996 * The next protocol in the previous item. 2997 * @param[in] flow_mask 2998 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2999 * @param[out] error 3000 * Pointer to error structure. 3001 * 3002 * @return 3003 * 0 on success, a negative errno value otherwise and rte_errno is set. 3004 */ 3005 int 3006 mlx5_flow_validate_item_udp(const struct rte_eth_dev *dev, 3007 const struct rte_flow_item *item, 3008 uint64_t item_flags, 3009 uint8_t target_protocol, 3010 struct rte_flow_error *error) 3011 { 3012 const struct rte_flow_item_udp *mask = item->mask; 3013 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 3014 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 3015 MLX5_FLOW_LAYER_OUTER_L3; 3016 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 3017 MLX5_FLOW_LAYER_OUTER_L4; 3018 int ret; 3019 3020 if (!mlx5_hws_active(dev)) { 3021 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 3022 return rte_flow_error_set(error, EINVAL, 3023 RTE_FLOW_ERROR_TYPE_ITEM, 3024 item, "protocol filtering not compatible with UDP layer"); 3025 if (!(item_flags & l3m)) 3026 return rte_flow_error_set(error, EINVAL, 3027 RTE_FLOW_ERROR_TYPE_ITEM, 3028 item, 3029 "L3 is mandatory to filter on L4"); 3030 } 3031 if (item_flags & l4m) 3032 return rte_flow_error_set(error, EINVAL, 3033 RTE_FLOW_ERROR_TYPE_ITEM, item, 3034 "multiple L4 layers not supported"); 3035 if (!mask) 3036 mask = &rte_flow_item_udp_mask; 3037 ret = mlx5_flow_item_acceptable 3038 (dev, item, (const uint8_t *)mask, 3039 (const uint8_t *)&rte_flow_item_udp_mask, 3040 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3041 error); 3042 if (ret < 0) 3043 return ret; 3044 return 0; 3045 } 3046 3047 /** 3048 * Validate TCP item. 3049 * 3050 * @param[in] item 3051 * Item specification. 3052 * @param[in] item_flags 3053 * Bit-fields that holds the items detected until now. 3054 * @param[in] target_protocol 3055 * The next protocol in the previous item. 3056 * @param[out] error 3057 * Pointer to error structure. 3058 * 3059 * @return 3060 * 0 on success, a negative errno value otherwise and rte_errno is set. 3061 */ 3062 int 3063 mlx5_flow_validate_item_tcp(const struct rte_eth_dev *dev, 3064 const struct rte_flow_item *item, 3065 uint64_t item_flags, 3066 uint8_t target_protocol, 3067 const struct rte_flow_item_tcp *flow_mask, 3068 struct rte_flow_error *error) 3069 { 3070 const struct rte_flow_item_tcp *mask = item->mask; 3071 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 3072 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 3073 MLX5_FLOW_LAYER_OUTER_L3; 3074 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 3075 MLX5_FLOW_LAYER_OUTER_L4; 3076 int ret; 3077 3078 MLX5_ASSERT(flow_mask); 3079 if (!mlx5_hws_active(dev)) { 3080 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 3081 return rte_flow_error_set(error, EINVAL, 3082 RTE_FLOW_ERROR_TYPE_ITEM, 3083 item, "protocol filtering not compatible with TCP layer"); 3084 if (!(item_flags & l3m)) 3085 return rte_flow_error_set(error, EINVAL, 3086 RTE_FLOW_ERROR_TYPE_ITEM, 3087 item, "L3 is mandatory to filter on L4"); 3088 } 3089 if (item_flags & l4m) 3090 return rte_flow_error_set(error, EINVAL, 3091 RTE_FLOW_ERROR_TYPE_ITEM, item, 3092 "multiple L4 layers not supported"); 3093 if (!mask) 3094 mask = &rte_flow_item_tcp_mask; 3095 ret = mlx5_flow_item_acceptable 3096 (dev, item, (const uint8_t *)mask, 3097 (const uint8_t *)flow_mask, 3098 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3099 error); 3100 if (ret < 0) 3101 return ret; 3102 return 0; 3103 } 3104 3105 /** 3106 * Validate VXLAN item. 3107 * 3108 * @param[in] dev 3109 * Pointer to the Ethernet device structure. 3110 * @param[in] udp_dport 3111 * UDP destination port 3112 * @param[in] item 3113 * Item specification. 3114 * @param[in] item_flags 3115 * Bit-fields that holds the items detected until now. 3116 * @param root 3117 * Whether action is on root table. 3118 * @param[out] error 3119 * Pointer to error structure. 3120 * 3121 * @return 3122 * 0 on success, a negative errno value otherwise and rte_errno is set. 3123 */ 3124 int 3125 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 3126 uint16_t udp_dport, 3127 const struct rte_flow_item *item, 3128 uint64_t item_flags, 3129 bool root, 3130 struct rte_flow_error *error) 3131 { 3132 const struct rte_flow_item_vxlan *spec = item->spec; 3133 const struct rte_flow_item_vxlan *mask = item->mask; 3134 int ret; 3135 struct mlx5_priv *priv = dev->data->dev_private; 3136 union vni { 3137 uint32_t vlan_id; 3138 uint8_t vni[4]; 3139 } id = { .vlan_id = 0, }; 3140 const struct rte_flow_item_vxlan nic_mask = { 3141 .hdr.vni = "\xff\xff\xff", 3142 .hdr.rsvd1 = 0xff, 3143 }; 3144 const struct rte_flow_item_vxlan *valid_mask; 3145 3146 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3147 return rte_flow_error_set(error, ENOTSUP, 3148 RTE_FLOW_ERROR_TYPE_ITEM, item, 3149 "multiple tunnel layers not" 3150 " supported"); 3151 valid_mask = &rte_flow_item_vxlan_mask; 3152 /* 3153 * Verify only UDPv4 is present as defined in 3154 * https://tools.ietf.org/html/rfc7348 3155 */ 3156 if (!mlx5_hws_active(dev)) { 3157 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3158 return rte_flow_error_set(error, EINVAL, 3159 RTE_FLOW_ERROR_TYPE_ITEM, 3160 item, "no outer UDP layer found"); 3161 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3162 return rte_flow_error_set(error, ENOTSUP, 3163 RTE_FLOW_ERROR_TYPE_ITEM, item, 3164 "VXLAN tunnel must be fully defined"); 3165 } 3166 if (!mask) 3167 mask = &rte_flow_item_vxlan_mask; 3168 3169 if (priv->sh->steering_format_version != 3170 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3171 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 3172 /* non-root table */ 3173 if (!root && priv->sh->misc5_cap) 3174 valid_mask = &nic_mask; 3175 /* Group zero in NIC domain */ 3176 if (!root && priv->sh->tunnel_header_0_1) 3177 valid_mask = &nic_mask; 3178 } 3179 ret = mlx5_flow_item_acceptable 3180 (dev, item, (const uint8_t *)mask, 3181 (const uint8_t *)valid_mask, 3182 sizeof(struct rte_flow_item_vxlan), 3183 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3184 if (ret < 0) 3185 return ret; 3186 if (spec) { 3187 memcpy(&id.vni[1], spec->hdr.vni, 3); 3188 memcpy(&id.vni[1], mask->hdr.vni, 3); 3189 } 3190 return 0; 3191 } 3192 3193 /** 3194 * Validate VXLAN_GPE item. 3195 * 3196 * @param[in] item 3197 * Item specification. 3198 * @param[in] item_flags 3199 * Bit-fields that holds the items detected until now. 3200 * @param[in] priv 3201 * Pointer to the private data structure. 3202 * @param[in] target_protocol 3203 * The next protocol in the previous item. 3204 * @param[out] error 3205 * Pointer to error structure. 3206 * 3207 * @return 3208 * 0 on success, a negative errno value otherwise and rte_errno is set. 3209 */ 3210 int 3211 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 3212 uint64_t item_flags, 3213 struct rte_eth_dev *dev, 3214 struct rte_flow_error *error) 3215 { 3216 struct mlx5_priv *priv = dev->data->dev_private; 3217 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 3218 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 3219 int ret; 3220 union vni { 3221 uint32_t vlan_id; 3222 uint8_t vni[4]; 3223 } id = { .vlan_id = 0, }; 3224 3225 struct rte_flow_item_vxlan_gpe nic_mask = { 3226 .vni = "\xff\xff\xff", 3227 .protocol = 0xff, 3228 .flags = 0xff, 3229 }; 3230 3231 if (!priv->sh->config.l3_vxlan_en) 3232 return rte_flow_error_set(error, ENOTSUP, 3233 RTE_FLOW_ERROR_TYPE_ITEM, item, 3234 "L3 VXLAN is not enabled by device" 3235 " parameter and/or not configured in" 3236 " firmware"); 3237 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3238 return rte_flow_error_set(error, ENOTSUP, 3239 RTE_FLOW_ERROR_TYPE_ITEM, item, 3240 "multiple tunnel layers not" 3241 " supported"); 3242 /* 3243 * Verify only UDPv4 is present as defined in 3244 * https://tools.ietf.org/html/rfc7348 3245 */ 3246 if (!mlx5_hws_active(dev)) { 3247 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3248 return rte_flow_error_set(error, EINVAL, 3249 RTE_FLOW_ERROR_TYPE_ITEM, 3250 item, "no outer UDP layer found"); 3251 } 3252 if (!mask) 3253 mask = &rte_flow_item_vxlan_gpe_mask; 3254 if (mlx5_hws_active(dev) || 3255 (priv->sh->misc5_cap && priv->sh->tunnel_header_0_1)) { 3256 nic_mask.rsvd0[0] = 0xff; 3257 nic_mask.rsvd0[1] = 0xff; 3258 nic_mask.rsvd1 = 0xff; 3259 } 3260 ret = mlx5_flow_item_acceptable 3261 (dev, item, (const uint8_t *)mask, 3262 (const uint8_t *)&nic_mask, 3263 sizeof(struct rte_flow_item_vxlan_gpe), 3264 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3265 if (ret < 0) 3266 return ret; 3267 if (spec) { 3268 memcpy(&id.vni[1], spec->hdr.vni, 3); 3269 memcpy(&id.vni[1], mask->hdr.vni, 3); 3270 } 3271 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3272 return rte_flow_error_set(error, ENOTSUP, 3273 RTE_FLOW_ERROR_TYPE_ITEM, item, 3274 "VXLAN-GPE tunnel must be fully" 3275 " defined"); 3276 return 0; 3277 } 3278 /** 3279 * Validate GRE Key item. 3280 * 3281 * @param[in] item 3282 * Item specification. 3283 * @param[in] item_flags 3284 * Bit flags to mark detected items. 3285 * @param[in] gre_item 3286 * Pointer to gre_item 3287 * @param[out] error 3288 * Pointer to error structure. 3289 * 3290 * @return 3291 * 0 on success, a negative errno value otherwise and rte_errno is set. 3292 */ 3293 int 3294 mlx5_flow_validate_item_gre_key(const struct rte_eth_dev *dev, 3295 const struct rte_flow_item *item, 3296 uint64_t item_flags, 3297 const struct rte_flow_item *gre_item, 3298 struct rte_flow_error *error) 3299 { 3300 const rte_be32_t *mask = item->mask; 3301 int ret = 0; 3302 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 3303 const struct rte_flow_item_gre *gre_spec; 3304 const struct rte_flow_item_gre *gre_mask; 3305 3306 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 3307 return rte_flow_error_set(error, ENOTSUP, 3308 RTE_FLOW_ERROR_TYPE_ITEM, item, 3309 "Multiple GRE key not support"); 3310 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3311 return rte_flow_error_set(error, ENOTSUP, 3312 RTE_FLOW_ERROR_TYPE_ITEM, item, 3313 "No preceding GRE header"); 3314 if (item_flags & MLX5_FLOW_LAYER_INNER) 3315 return rte_flow_error_set(error, ENOTSUP, 3316 RTE_FLOW_ERROR_TYPE_ITEM, item, 3317 "GRE key following a wrong item"); 3318 gre_mask = gre_item->mask; 3319 if (!gre_mask) 3320 gre_mask = &rte_flow_item_gre_mask; 3321 gre_spec = gre_item->spec; 3322 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3323 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3324 return rte_flow_error_set(error, EINVAL, 3325 RTE_FLOW_ERROR_TYPE_ITEM, item, 3326 "Key bit must be on"); 3327 3328 if (!mask) 3329 mask = &gre_key_default_mask; 3330 ret = mlx5_flow_item_acceptable 3331 (dev, item, (const uint8_t *)mask, 3332 (const uint8_t *)&gre_key_default_mask, 3333 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3334 return ret; 3335 } 3336 3337 /** 3338 * Validate GRE optional item. 3339 * 3340 * @param[in] dev 3341 * Pointer to the Ethernet device structure. 3342 * @param[in] item 3343 * Item specification. 3344 * @param[in] item_flags 3345 * Bit flags to mark detected items. 3346 * @param[in] attr 3347 * Flow rule attributes. 3348 * @param[in] gre_item 3349 * Pointer to gre_item 3350 * @param[out] error 3351 * Pointer to error structure. 3352 * 3353 * @return 3354 * 0 on success, a negative errno value otherwise and rte_errno is set. 3355 */ 3356 int 3357 mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, 3358 const struct rte_flow_item *item, 3359 uint64_t item_flags, 3360 const struct rte_flow_attr *attr, 3361 const struct rte_flow_item *gre_item, 3362 struct rte_flow_error *error) 3363 { 3364 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 3365 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 3366 const struct rte_flow_item_gre_opt *spec = item->spec; 3367 const struct rte_flow_item_gre_opt *mask = item->mask; 3368 struct mlx5_priv *priv = dev->data->dev_private; 3369 int ret = 0; 3370 struct rte_flow_item_gre_opt nic_mask = { 3371 .checksum_rsvd = { 3372 .checksum = RTE_BE16(UINT16_MAX), 3373 .reserved1 = 0x0, 3374 }, 3375 .key = { 3376 .key = RTE_BE32(UINT32_MAX), 3377 }, 3378 .sequence = { 3379 .sequence = RTE_BE32(UINT32_MAX), 3380 }, 3381 }; 3382 3383 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3384 return rte_flow_error_set(error, ENOTSUP, 3385 RTE_FLOW_ERROR_TYPE_ITEM, item, 3386 "No preceding GRE header"); 3387 if (item_flags & MLX5_FLOW_LAYER_INNER) 3388 return rte_flow_error_set(error, ENOTSUP, 3389 RTE_FLOW_ERROR_TYPE_ITEM, item, 3390 "GRE option following a wrong item"); 3391 if (!spec || !mask) 3392 return rte_flow_error_set(error, EINVAL, 3393 RTE_FLOW_ERROR_TYPE_ITEM, item, 3394 "At least one field gre_option(checksum/key/sequence) must be specified"); 3395 if (!gre_mask) 3396 gre_mask = &rte_flow_item_gre_mask; 3397 if (mask->checksum_rsvd.checksum) 3398 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && 3399 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) 3400 return rte_flow_error_set(error, EINVAL, 3401 RTE_FLOW_ERROR_TYPE_ITEM, 3402 item, 3403 "Checksum bit must be on"); 3404 if (mask->key.key) 3405 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3406 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3407 return rte_flow_error_set(error, EINVAL, 3408 RTE_FLOW_ERROR_TYPE_ITEM, 3409 item, "Key bit must be on"); 3410 if (mask->sequence.sequence) 3411 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && 3412 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) 3413 return rte_flow_error_set(error, EINVAL, 3414 RTE_FLOW_ERROR_TYPE_ITEM, 3415 item, 3416 "Sequence bit must be on"); 3417 if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { 3418 if (priv->sh->steering_format_version == 3419 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3420 ((attr->group || (attr->transfer && priv->fdb_def_rule)) && 3421 !priv->sh->misc5_cap) || 3422 (!(priv->sh->tunnel_header_0_1 && 3423 priv->sh->tunnel_header_2_3) && 3424 !attr->group && (!attr->transfer || !priv->fdb_def_rule))) 3425 return rte_flow_error_set(error, EINVAL, 3426 RTE_FLOW_ERROR_TYPE_ITEM, 3427 item, 3428 "Checksum/Sequence not supported"); 3429 } 3430 ret = mlx5_flow_item_acceptable 3431 (dev, item, (const uint8_t *)mask, 3432 (const uint8_t *)&nic_mask, 3433 sizeof(struct rte_flow_item_gre_opt), 3434 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3435 return ret; 3436 } 3437 3438 /** 3439 * Validate GRE item. 3440 * 3441 * @param[in] item 3442 * Item specification. 3443 * @param[in] item_flags 3444 * Bit flags to mark detected items. 3445 * @param[in] target_protocol 3446 * The next protocol in the previous item. 3447 * @param[out] error 3448 * Pointer to error structure. 3449 * 3450 * @return 3451 * 0 on success, a negative errno value otherwise and rte_errno is set. 3452 */ 3453 int 3454 mlx5_flow_validate_item_gre(const struct rte_eth_dev *dev, 3455 const struct rte_flow_item *item, 3456 uint64_t item_flags, 3457 uint8_t target_protocol, 3458 struct rte_flow_error *error) 3459 { 3460 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 3461 const struct rte_flow_item_gre *mask = item->mask; 3462 int ret; 3463 const struct rte_flow_item_gre nic_mask = { 3464 .c_rsvd0_ver = RTE_BE16(0xB000), 3465 .protocol = RTE_BE16(UINT16_MAX), 3466 }; 3467 3468 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3469 return rte_flow_error_set(error, EINVAL, 3470 RTE_FLOW_ERROR_TYPE_ITEM, item, 3471 "protocol filtering not compatible" 3472 " with this GRE layer"); 3473 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3474 return rte_flow_error_set(error, ENOTSUP, 3475 RTE_FLOW_ERROR_TYPE_ITEM, item, 3476 "multiple tunnel layers not" 3477 " supported"); 3478 if (!mlx5_hws_active(dev)) { 3479 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3480 return rte_flow_error_set(error, ENOTSUP, 3481 RTE_FLOW_ERROR_TYPE_ITEM, 3482 item, "L3 Layer is missing"); 3483 } 3484 if (!mask) 3485 mask = &rte_flow_item_gre_mask; 3486 ret = mlx5_flow_item_acceptable 3487 (dev, item, (const uint8_t *)mask, 3488 (const uint8_t *)&nic_mask, 3489 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3490 error); 3491 if (ret < 0) 3492 return ret; 3493 #ifndef HAVE_MLX5DV_DR 3494 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 3495 if (spec && (spec->protocol & mask->protocol)) 3496 return rte_flow_error_set(error, ENOTSUP, 3497 RTE_FLOW_ERROR_TYPE_ITEM, item, 3498 "without MPLS support the" 3499 " specification cannot be used for" 3500 " filtering"); 3501 #endif 3502 #endif 3503 return 0; 3504 } 3505 3506 /** 3507 * Validate Geneve item. 3508 * 3509 * @param[in] item 3510 * Item specification. 3511 * @param[in] itemFlags 3512 * Bit-fields that holds the items detected until now. 3513 * @param[in] enPriv 3514 * Pointer to the private data structure. 3515 * @param[out] error 3516 * Pointer to error structure. 3517 * 3518 * @return 3519 * 0 on success, a negative errno value otherwise and rte_errno is set. 3520 */ 3521 3522 int 3523 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 3524 uint64_t item_flags, 3525 struct rte_eth_dev *dev, 3526 struct rte_flow_error *error) 3527 { 3528 struct mlx5_priv *priv = dev->data->dev_private; 3529 const struct rte_flow_item_geneve *spec = item->spec; 3530 const struct rte_flow_item_geneve *mask = item->mask; 3531 int ret; 3532 uint16_t gbhdr; 3533 uint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ? 3534 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 3535 const struct rte_flow_item_geneve nic_mask = { 3536 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 3537 .vni = "\xff\xff\xff", 3538 .protocol = RTE_BE16(UINT16_MAX), 3539 }; 3540 3541 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx) 3542 return rte_flow_error_set(error, ENOTSUP, 3543 RTE_FLOW_ERROR_TYPE_ITEM, item, 3544 "L3 Geneve is not enabled by device" 3545 " parameter and/or not configured in" 3546 " firmware"); 3547 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3548 return rte_flow_error_set(error, ENOTSUP, 3549 RTE_FLOW_ERROR_TYPE_ITEM, item, 3550 "multiple tunnel layers not" 3551 " supported"); 3552 /* 3553 * Verify only UDPv4 is present as defined in 3554 * https://tools.ietf.org/html/rfc7348 3555 */ 3556 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3557 return rte_flow_error_set(error, EINVAL, 3558 RTE_FLOW_ERROR_TYPE_ITEM, item, 3559 "no outer UDP layer found"); 3560 if (!mask) 3561 mask = &rte_flow_item_geneve_mask; 3562 ret = mlx5_flow_item_acceptable 3563 (dev, item, (const uint8_t *)mask, 3564 (const uint8_t *)&nic_mask, 3565 sizeof(struct rte_flow_item_geneve), 3566 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3567 if (ret) 3568 return ret; 3569 if (spec) { 3570 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 3571 if (MLX5_GENEVE_VER_VAL(gbhdr) || 3572 MLX5_GENEVE_CRITO_VAL(gbhdr) || 3573 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 3574 return rte_flow_error_set(error, ENOTSUP, 3575 RTE_FLOW_ERROR_TYPE_ITEM, 3576 item, 3577 "Geneve protocol unsupported" 3578 " fields are being used"); 3579 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 3580 return rte_flow_error_set 3581 (error, ENOTSUP, 3582 RTE_FLOW_ERROR_TYPE_ITEM, 3583 item, 3584 "Unsupported Geneve options length"); 3585 } 3586 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3587 return rte_flow_error_set 3588 (error, ENOTSUP, 3589 RTE_FLOW_ERROR_TYPE_ITEM, item, 3590 "Geneve tunnel must be fully defined"); 3591 return 0; 3592 } 3593 3594 /** 3595 * Validate Geneve TLV option item. 3596 * 3597 * @param[in] item 3598 * Item specification. 3599 * @param[in] last_item 3600 * Previous validated item in the pattern items. 3601 * @param[in] geneve_item 3602 * Previous GENEVE item specification. 3603 * @param[in] dev 3604 * Pointer to the rte_eth_dev structure. 3605 * @param[out] error 3606 * Pointer to error structure. 3607 * 3608 * @return 3609 * 0 on success, a negative errno value otherwise and rte_errno is set. 3610 */ 3611 int 3612 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 3613 uint64_t last_item, 3614 const struct rte_flow_item *geneve_item, 3615 struct rte_eth_dev *dev, 3616 struct rte_flow_error *error) 3617 { 3618 struct mlx5_priv *priv = dev->data->dev_private; 3619 struct mlx5_dev_ctx_shared *sh = priv->sh; 3620 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 3621 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 3622 uint8_t data_max_supported = 3623 hca_attr->max_geneve_tlv_option_data_len * 4; 3624 const struct rte_flow_item_geneve *geneve_spec; 3625 const struct rte_flow_item_geneve *geneve_mask; 3626 const struct rte_flow_item_geneve_opt *spec = item->spec; 3627 const struct rte_flow_item_geneve_opt *mask = item->mask; 3628 unsigned int i; 3629 unsigned int data_len; 3630 uint8_t tlv_option_len; 3631 uint16_t optlen_m, optlen_v; 3632 const struct rte_flow_item_geneve_opt full_mask = { 3633 .option_class = RTE_BE16(0xffff), 3634 .option_type = 0xff, 3635 .option_len = 0x1f, 3636 }; 3637 3638 if (!mask) 3639 mask = &rte_flow_item_geneve_opt_mask; 3640 if (!spec) 3641 return rte_flow_error_set 3642 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3643 "Geneve TLV opt class/type/length must be specified"); 3644 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3645 return rte_flow_error_set 3646 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3647 "Geneve TLV opt length exceeds the limit (31)"); 3648 /* Check if class type and length masks are full. */ 3649 if (full_mask.option_class != mask->option_class || 3650 full_mask.option_type != mask->option_type || 3651 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3652 return rte_flow_error_set 3653 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3654 "Geneve TLV opt class/type/length masks must be full"); 3655 /* Check if length is supported */ 3656 if ((uint32_t)spec->option_len > 3657 hca_attr->max_geneve_tlv_option_data_len) 3658 return rte_flow_error_set 3659 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3660 "Geneve TLV opt length not supported"); 3661 if (hca_attr->max_geneve_tlv_options > 1) 3662 DRV_LOG(DEBUG, 3663 "max_geneve_tlv_options supports more than 1 option"); 3664 /* Check GENEVE item preceding. */ 3665 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3666 return rte_flow_error_set 3667 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3668 "Geneve opt item must be preceded with Geneve item"); 3669 geneve_spec = geneve_item->spec; 3670 geneve_mask = geneve_item->mask ? geneve_item->mask : 3671 &rte_flow_item_geneve_mask; 3672 /* Check if GENEVE TLV option size doesn't exceed option length */ 3673 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3674 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3675 tlv_option_len = spec->option_len & mask->option_len; 3676 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3677 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3678 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3679 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3680 if ((optlen_v & optlen_m) <= tlv_option_len) 3681 return rte_flow_error_set 3682 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3683 "GENEVE TLV option length exceeds optlen"); 3684 } 3685 /* Check if length is 0 or data is 0. */ 3686 if (spec->data == NULL || spec->option_len == 0) 3687 return rte_flow_error_set 3688 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3689 "Geneve TLV opt with zero data/length not supported"); 3690 /* Check not all data & mask are 0. */ 3691 data_len = spec->option_len * 4; 3692 if (mask->data == NULL) { 3693 for (i = 0; i < data_len; i++) 3694 if (spec->data[i]) 3695 break; 3696 if (i == data_len) 3697 return rte_flow_error_set(error, ENOTSUP, 3698 RTE_FLOW_ERROR_TYPE_ITEM, item, 3699 "Can't match on Geneve option data 0"); 3700 } else { 3701 for (i = 0; i < data_len; i++) 3702 if (spec->data[i] & mask->data[i]) 3703 break; 3704 if (i == data_len) 3705 return rte_flow_error_set(error, ENOTSUP, 3706 RTE_FLOW_ERROR_TYPE_ITEM, item, 3707 "Can't match on Geneve option data and mask 0"); 3708 /* Check data mask supported. */ 3709 for (i = data_max_supported; i < data_len ; i++) 3710 if (mask->data[i]) 3711 return rte_flow_error_set(error, ENOTSUP, 3712 RTE_FLOW_ERROR_TYPE_ITEM, item, 3713 "Data mask is of unsupported size"); 3714 } 3715 /* Check GENEVE option is supported in NIC. */ 3716 if (!hca_attr->geneve_tlv_opt) 3717 return rte_flow_error_set 3718 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3719 "Geneve TLV opt not supported"); 3720 /* Check if we already have geneve option with different type/class. */ 3721 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3722 geneve_opt_resource = sh->geneve_tlv_option_resource; 3723 if (geneve_opt_resource != NULL) 3724 if (geneve_opt_resource->option_class != spec->option_class || 3725 geneve_opt_resource->option_type != spec->option_type || 3726 geneve_opt_resource->length != spec->option_len) { 3727 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3728 return rte_flow_error_set(error, ENOTSUP, 3729 RTE_FLOW_ERROR_TYPE_ITEM, item, 3730 "Only one Geneve TLV option supported"); 3731 } 3732 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3733 return 0; 3734 } 3735 3736 /** 3737 * Validate MPLS item. 3738 * 3739 * @param[in] dev 3740 * Pointer to the rte_eth_dev structure. 3741 * @param[in] item 3742 * Item specification. 3743 * @param[in] item_flags 3744 * Bit-fields that holds the items detected until now. 3745 * @param[in] prev_layer 3746 * The protocol layer indicated in previous item. 3747 * @param[out] error 3748 * Pointer to error structure. 3749 * 3750 * @return 3751 * 0 on success, a negative errno value otherwise and rte_errno is set. 3752 */ 3753 int 3754 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3755 const struct rte_flow_item *item __rte_unused, 3756 uint64_t item_flags __rte_unused, 3757 uint64_t prev_layer __rte_unused, 3758 struct rte_flow_error *error) 3759 { 3760 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3761 const struct rte_flow_item_mpls hws_nic_mask = { 3762 .label_tc_s = {0xff, 0xff, 0xff}, 3763 .ttl = 0xff 3764 }; 3765 const struct rte_flow_item_mpls *nic_mask = !mlx5_hws_active(dev) ? 3766 &rte_flow_item_mpls_mask : &hws_nic_mask; 3767 const struct rte_flow_item_mpls *mask = item->mask; 3768 struct mlx5_priv *priv = dev->data->dev_private; 3769 int ret; 3770 3771 if (!mlx5_hws_active(dev)) { 3772 /* MPLS has HW support in HWS */ 3773 if (!priv->sh->dev_cap.mpls_en) 3774 return rte_flow_error_set(error, ENOTSUP, 3775 RTE_FLOW_ERROR_TYPE_ITEM, 3776 item, "MPLS not supported or disabled in firmware configuration."); 3777 /* MPLS over UDP, GRE is allowed */ 3778 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3779 MLX5_FLOW_LAYER_GRE | 3780 MLX5_FLOW_LAYER_GRE_KEY))) 3781 return rte_flow_error_set(error, EINVAL, 3782 RTE_FLOW_ERROR_TYPE_ITEM, 3783 item, "protocol filtering not compatible with MPLS layer"); 3784 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3785 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3786 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3787 return rte_flow_error_set(error, ENOTSUP, 3788 RTE_FLOW_ERROR_TYPE_ITEM, item, 3789 "multiple tunnel layers not supported"); 3790 } else { 3791 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3792 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3793 !(item_flags & MLX5_FLOW_LAYER_MPLS)) 3794 return rte_flow_error_set(error, ENOTSUP, 3795 RTE_FLOW_ERROR_TYPE_ITEM, item, 3796 "multiple tunnel layers not supported"); 3797 } 3798 if (!mask) 3799 mask = nic_mask; 3800 ret = mlx5_flow_item_acceptable 3801 (dev, item, (const uint8_t *)mask, 3802 (const uint8_t *)nic_mask, 3803 sizeof(struct rte_flow_item_mpls), 3804 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3805 if (ret < 0) 3806 return ret; 3807 return 0; 3808 #else 3809 return rte_flow_error_set(error, ENOTSUP, 3810 RTE_FLOW_ERROR_TYPE_ITEM, item, 3811 "MPLS is not supported by Verbs, please" 3812 " update."); 3813 #endif 3814 } 3815 3816 /** 3817 * Validate NVGRE item. 3818 * 3819 * @param[in] item 3820 * Item specification. 3821 * @param[in] item_flags 3822 * Bit flags to mark detected items. 3823 * @param[in] target_protocol 3824 * The next protocol in the previous item. 3825 * @param[out] error 3826 * Pointer to error structure. 3827 * 3828 * @return 3829 * 0 on success, a negative errno value otherwise and rte_errno is set. 3830 */ 3831 int 3832 mlx5_flow_validate_item_nvgre(const struct rte_eth_dev *dev, 3833 const struct rte_flow_item *item, 3834 uint64_t item_flags, 3835 uint8_t target_protocol, 3836 struct rte_flow_error *error) 3837 { 3838 const struct rte_flow_item_nvgre *mask = item->mask; 3839 int ret; 3840 3841 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3842 return rte_flow_error_set(error, EINVAL, 3843 RTE_FLOW_ERROR_TYPE_ITEM, item, 3844 "protocol filtering not compatible" 3845 " with this GRE layer"); 3846 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3847 return rte_flow_error_set(error, ENOTSUP, 3848 RTE_FLOW_ERROR_TYPE_ITEM, item, 3849 "multiple tunnel layers not" 3850 " supported"); 3851 if (!mlx5_hws_active(dev)) { 3852 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3853 return rte_flow_error_set(error, ENOTSUP, 3854 RTE_FLOW_ERROR_TYPE_ITEM, 3855 item, "L3 Layer is missing"); 3856 } 3857 if (!mask) 3858 mask = &rte_flow_item_nvgre_mask; 3859 ret = mlx5_flow_item_acceptable 3860 (dev, item, (const uint8_t *)mask, 3861 (const uint8_t *)&rte_flow_item_nvgre_mask, 3862 sizeof(struct rte_flow_item_nvgre), 3863 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3864 if (ret < 0) 3865 return ret; 3866 return 0; 3867 } 3868 3869 /** 3870 * Validate eCPRI item. 3871 * 3872 * @param[in] item 3873 * Item specification. 3874 * @param[in] item_flags 3875 * Bit-fields that holds the items detected until now. 3876 * @param[in] last_item 3877 * Previous validated item in the pattern items. 3878 * @param[in] ether_type 3879 * Type in the ethernet layer header (including dot1q). 3880 * @param[in] acc_mask 3881 * Acceptable mask, if NULL default internal default mask 3882 * will be used to check whether item fields are supported. 3883 * @param[out] error 3884 * Pointer to error structure. 3885 * 3886 * @return 3887 * 0 on success, a negative errno value otherwise and rte_errno is set. 3888 */ 3889 int 3890 mlx5_flow_validate_item_ecpri(const struct rte_eth_dev *dev, 3891 const struct rte_flow_item *item, 3892 uint64_t item_flags, 3893 uint64_t last_item, 3894 uint16_t ether_type, 3895 const struct rte_flow_item_ecpri *acc_mask, 3896 struct rte_flow_error *error) 3897 { 3898 const struct rte_flow_item_ecpri *mask = item->mask; 3899 const struct rte_flow_item_ecpri nic_mask = { 3900 .hdr = { 3901 .common = { 3902 .u32 = 3903 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3904 .type = 0xFF, 3905 }).u32), 3906 }, 3907 .dummy[0] = 0xFFFFFFFF, 3908 }, 3909 }; 3910 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3911 MLX5_FLOW_LAYER_OUTER_VLAN); 3912 struct rte_flow_item_ecpri mask_lo; 3913 3914 if (!(last_item & outer_l2_vlan) && 3915 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3916 return rte_flow_error_set(error, EINVAL, 3917 RTE_FLOW_ERROR_TYPE_ITEM, item, 3918 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3919 if ((last_item & outer_l2_vlan) && ether_type && 3920 ether_type != RTE_ETHER_TYPE_ECPRI) 3921 return rte_flow_error_set(error, EINVAL, 3922 RTE_FLOW_ERROR_TYPE_ITEM, item, 3923 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3924 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3925 return rte_flow_error_set(error, EINVAL, 3926 RTE_FLOW_ERROR_TYPE_ITEM, item, 3927 "eCPRI with tunnel is not supported right now"); 3928 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3929 return rte_flow_error_set(error, ENOTSUP, 3930 RTE_FLOW_ERROR_TYPE_ITEM, item, 3931 "multiple L3 layers not supported"); 3932 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3933 return rte_flow_error_set(error, EINVAL, 3934 RTE_FLOW_ERROR_TYPE_ITEM, item, 3935 "eCPRI cannot coexist with a TCP layer"); 3936 /* In specification, eCPRI could be over UDP layer. */ 3937 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3938 return rte_flow_error_set(error, EINVAL, 3939 RTE_FLOW_ERROR_TYPE_ITEM, item, 3940 "eCPRI over UDP layer is not yet supported right now"); 3941 /* Mask for type field in common header could be zero. */ 3942 if (!mask) 3943 mask = &rte_flow_item_ecpri_mask; 3944 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3945 /* Input mask is in big-endian format. */ 3946 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3947 return rte_flow_error_set(error, EINVAL, 3948 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3949 "partial mask is not supported for protocol"); 3950 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3951 return rte_flow_error_set(error, EINVAL, 3952 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3953 "message header mask must be after a type mask"); 3954 return mlx5_flow_item_acceptable(dev, item, (const uint8_t *)mask, 3955 acc_mask ? (const uint8_t *)acc_mask 3956 : (const uint8_t *)&nic_mask, 3957 sizeof(struct rte_flow_item_ecpri), 3958 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3959 } 3960 3961 /** 3962 * Validate the NSH item. 3963 * 3964 * @param[in] dev 3965 * Pointer to Ethernet device on which flow rule is being created on. 3966 * @param[out] error 3967 * Pointer to error structure. 3968 * 3969 * @return 3970 * 0 on success, a negative errno value otherwise and rte_errno is set. 3971 */ 3972 int 3973 mlx5_flow_validate_item_nsh(struct rte_eth_dev *dev, 3974 const struct rte_flow_item *item, 3975 struct rte_flow_error *error) 3976 { 3977 struct mlx5_priv *priv = dev->data->dev_private; 3978 3979 if (item->mask) { 3980 return rte_flow_error_set(error, ENOTSUP, 3981 RTE_FLOW_ERROR_TYPE_ITEM, item, 3982 "NSH fields matching is not supported"); 3983 } 3984 3985 if (!priv->sh->config.dv_flow_en) { 3986 return rte_flow_error_set(error, ENOTSUP, 3987 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 3988 NULL, "NSH support requires DV flow interface"); 3989 } 3990 3991 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_vxlan_gpe_nsh) { 3992 return rte_flow_error_set(error, ENOTSUP, 3993 RTE_FLOW_ERROR_TYPE_ITEM, item, 3994 "Current FW does not support matching on NSH"); 3995 } 3996 3997 return 0; 3998 } 3999 4000 static int 4001 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 4002 const struct rte_flow_attr *attr __rte_unused, 4003 const struct rte_flow_item items[] __rte_unused, 4004 const struct rte_flow_action actions[] __rte_unused, 4005 bool external __rte_unused, 4006 int hairpin __rte_unused, 4007 struct rte_flow_error *error) 4008 { 4009 return rte_flow_error_set(error, ENOTSUP, 4010 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4011 } 4012 4013 static struct mlx5_flow * 4014 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 4015 const struct rte_flow_attr *attr __rte_unused, 4016 const struct rte_flow_item items[] __rte_unused, 4017 const struct rte_flow_action actions[] __rte_unused, 4018 struct rte_flow_error *error) 4019 { 4020 rte_flow_error_set(error, ENOTSUP, 4021 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4022 return NULL; 4023 } 4024 4025 static int 4026 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 4027 struct mlx5_flow *dev_flow __rte_unused, 4028 const struct rte_flow_attr *attr __rte_unused, 4029 const struct rte_flow_item items[] __rte_unused, 4030 const struct rte_flow_action actions[] __rte_unused, 4031 struct rte_flow_error *error) 4032 { 4033 return rte_flow_error_set(error, ENOTSUP, 4034 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4035 } 4036 4037 static int 4038 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 4039 struct rte_flow *flow __rte_unused, 4040 struct rte_flow_error *error) 4041 { 4042 return rte_flow_error_set(error, ENOTSUP, 4043 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4044 } 4045 4046 static void 4047 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 4048 struct rte_flow *flow __rte_unused) 4049 { 4050 } 4051 4052 static void 4053 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 4054 struct rte_flow *flow __rte_unused) 4055 { 4056 } 4057 4058 static int 4059 flow_null_query(struct rte_eth_dev *dev __rte_unused, 4060 struct rte_flow *flow __rte_unused, 4061 const struct rte_flow_action *actions __rte_unused, 4062 void *data __rte_unused, 4063 struct rte_flow_error *error) 4064 { 4065 return rte_flow_error_set(error, ENOTSUP, 4066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4067 } 4068 4069 static int 4070 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 4071 uint32_t domains __rte_unused, 4072 uint32_t flags __rte_unused) 4073 { 4074 return 0; 4075 } 4076 4077 int 4078 flow_null_get_aged_flows(struct rte_eth_dev *dev, 4079 void **context __rte_unused, 4080 uint32_t nb_contexts __rte_unused, 4081 struct rte_flow_error *error __rte_unused) 4082 { 4083 DRV_LOG(ERR, "port %u get aged flows is not supported.", 4084 dev->data->port_id); 4085 return -ENOTSUP; 4086 } 4087 4088 uint32_t 4089 flow_null_counter_allocate(struct rte_eth_dev *dev) 4090 { 4091 DRV_LOG(ERR, "port %u counter allocate is not supported.", 4092 dev->data->port_id); 4093 return 0; 4094 } 4095 4096 void 4097 flow_null_counter_free(struct rte_eth_dev *dev, 4098 uint32_t counter __rte_unused) 4099 { 4100 DRV_LOG(ERR, "port %u counter free is not supported.", 4101 dev->data->port_id); 4102 } 4103 4104 int 4105 flow_null_counter_query(struct rte_eth_dev *dev, 4106 uint32_t counter __rte_unused, 4107 bool clear __rte_unused, 4108 uint64_t *pkts __rte_unused, 4109 uint64_t *bytes __rte_unused, 4110 void **action __rte_unused) 4111 { 4112 DRV_LOG(ERR, "port %u counter query is not supported.", 4113 dev->data->port_id); 4114 return -ENOTSUP; 4115 } 4116 4117 /* Void driver to protect from null pointer reference. */ 4118 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 4119 .validate = flow_null_validate, 4120 .prepare = flow_null_prepare, 4121 .translate = flow_null_translate, 4122 .apply = flow_null_apply, 4123 .remove = flow_null_remove, 4124 .destroy = flow_null_destroy, 4125 .query = flow_null_query, 4126 .sync_domain = flow_null_sync_domain, 4127 .get_aged_flows = flow_null_get_aged_flows, 4128 .counter_alloc = flow_null_counter_allocate, 4129 .counter_free = flow_null_counter_free, 4130 .counter_query = flow_null_counter_query 4131 }; 4132 4133 /** 4134 * Select flow driver type according to flow attributes and device 4135 * configuration. 4136 * 4137 * @param[in] dev 4138 * Pointer to the dev structure. 4139 * @param[in] attr 4140 * Pointer to the flow attributes. 4141 * 4142 * @return 4143 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 4144 */ 4145 static enum mlx5_flow_drv_type 4146 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 4147 { 4148 struct mlx5_priv *priv = dev->data->dev_private; 4149 /* The OS can determine first a specific flow type (DV, VERBS) */ 4150 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 4151 4152 if (type != MLX5_FLOW_TYPE_MAX) 4153 return type; 4154 /* 4155 * Currently when dv_flow_en == 2, only HW steering engine is 4156 * supported. New engines can also be chosen here if ready. 4157 */ 4158 if (priv->sh->config.dv_flow_en == 2) 4159 return MLX5_FLOW_TYPE_HW; 4160 if (!attr) 4161 return MLX5_FLOW_TYPE_MIN; 4162 /* If no OS specific type - continue with DV/VERBS selection */ 4163 if (attr->transfer && priv->sh->config.dv_esw_en) 4164 type = MLX5_FLOW_TYPE_DV; 4165 if (!attr->transfer) 4166 type = priv->sh->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 4167 MLX5_FLOW_TYPE_VERBS; 4168 return type; 4169 } 4170 4171 #define flow_get_drv_ops(type) flow_drv_ops[type] 4172 4173 /** 4174 * Flow driver validation API. This abstracts calling driver specific functions. 4175 * The type of flow driver is determined according to flow attributes. 4176 * 4177 * @param[in] dev 4178 * Pointer to the dev structure. 4179 * @param[in] attr 4180 * Pointer to the flow attributes. 4181 * @param[in] items 4182 * Pointer to the list of items. 4183 * @param[in] actions 4184 * Pointer to the list of actions. 4185 * @param[in] external 4186 * This flow rule is created by request external to PMD. 4187 * @param[in] hairpin 4188 * Number of hairpin TX actions, 0 means classic flow. 4189 * @param[out] error 4190 * Pointer to the error structure. 4191 * 4192 * @return 4193 * 0 on success, a negative errno value otherwise and rte_errno is set. 4194 */ 4195 static inline int 4196 flow_drv_validate(struct rte_eth_dev *dev, 4197 const struct rte_flow_attr *attr, 4198 const struct rte_flow_item items[], 4199 const struct rte_flow_action actions[], 4200 bool external, int hairpin, struct rte_flow_error *error) 4201 { 4202 const struct mlx5_flow_driver_ops *fops; 4203 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 4204 4205 fops = flow_get_drv_ops(type); 4206 return fops->validate(dev, attr, items, actions, external, 4207 hairpin, error); 4208 } 4209 4210 /** 4211 * Flow driver preparation API. This abstracts calling driver specific 4212 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 4213 * calculates the size of memory required for device flow, allocates the memory, 4214 * initializes the device flow and returns the pointer. 4215 * 4216 * @note 4217 * This function initializes device flow structure such as dv or verbs in 4218 * struct mlx5_flow. However, it is caller's responsibility to initialize the 4219 * rest. For example, adding returning device flow to flow->dev_flow list and 4220 * setting backward reference to the flow should be done out of this function. 4221 * layers field is not filled either. 4222 * 4223 * @param[in] dev 4224 * Pointer to the dev structure. 4225 * @param[in] attr 4226 * Pointer to the flow attributes. 4227 * @param[in] items 4228 * Pointer to the list of items. 4229 * @param[in] actions 4230 * Pointer to the list of actions. 4231 * @param[in] flow_idx 4232 * This memory pool index to the flow. 4233 * @param[out] error 4234 * Pointer to the error structure. 4235 * 4236 * @return 4237 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 4238 */ 4239 static inline struct mlx5_flow * 4240 flow_drv_prepare(struct rte_eth_dev *dev, 4241 const struct rte_flow *flow, 4242 const struct rte_flow_attr *attr, 4243 const struct rte_flow_item items[], 4244 const struct rte_flow_action actions[], 4245 uint32_t flow_idx, 4246 struct rte_flow_error *error) 4247 { 4248 const struct mlx5_flow_driver_ops *fops; 4249 enum mlx5_flow_drv_type type = flow->drv_type; 4250 struct mlx5_flow *mlx5_flow = NULL; 4251 4252 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4253 fops = flow_get_drv_ops(type); 4254 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 4255 if (mlx5_flow) 4256 mlx5_flow->flow_idx = flow_idx; 4257 return mlx5_flow; 4258 } 4259 4260 /** 4261 * Flow driver translation API. This abstracts calling driver specific 4262 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 4263 * translates a generic flow into a driver flow. flow_drv_prepare() must 4264 * precede. 4265 * 4266 * @note 4267 * dev_flow->layers could be filled as a result of parsing during translation 4268 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 4269 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 4270 * flow->actions could be overwritten even though all the expanded dev_flows 4271 * have the same actions. 4272 * 4273 * @param[in] dev 4274 * Pointer to the rte dev structure. 4275 * @param[in, out] dev_flow 4276 * Pointer to the mlx5 flow. 4277 * @param[in] attr 4278 * Pointer to the flow attributes. 4279 * @param[in] items 4280 * Pointer to the list of items. 4281 * @param[in] actions 4282 * Pointer to the list of actions. 4283 * @param[out] error 4284 * Pointer to the error structure. 4285 * 4286 * @return 4287 * 0 on success, a negative errno value otherwise and rte_errno is set. 4288 */ 4289 static inline int 4290 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 4291 const struct rte_flow_attr *attr, 4292 const struct rte_flow_item items[], 4293 const struct rte_flow_action actions[], 4294 struct rte_flow_error *error) 4295 { 4296 const struct mlx5_flow_driver_ops *fops; 4297 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 4298 4299 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4300 fops = flow_get_drv_ops(type); 4301 return fops->translate(dev, dev_flow, attr, items, actions, error); 4302 } 4303 4304 /** 4305 * Flow driver apply API. This abstracts calling driver specific functions. 4306 * Parent flow (rte_flow) should have driver type (drv_type). It applies 4307 * translated driver flows on to device. flow_drv_translate() must precede. 4308 * 4309 * @param[in] dev 4310 * Pointer to Ethernet device structure. 4311 * @param[in, out] flow 4312 * Pointer to flow structure. 4313 * @param[out] error 4314 * Pointer to error structure. 4315 * 4316 * @return 4317 * 0 on success, a negative errno value otherwise and rte_errno is set. 4318 */ 4319 static inline int 4320 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 4321 struct rte_flow_error *error) 4322 { 4323 const struct mlx5_flow_driver_ops *fops; 4324 enum mlx5_flow_drv_type type = flow->drv_type; 4325 4326 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4327 fops = flow_get_drv_ops(type); 4328 return fops->apply(dev, flow, error); 4329 } 4330 4331 /** 4332 * Flow driver destroy API. This abstracts calling driver specific functions. 4333 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 4334 * on device and releases resources of the flow. 4335 * 4336 * @param[in] dev 4337 * Pointer to Ethernet device. 4338 * @param[in, out] flow 4339 * Pointer to flow structure. 4340 */ 4341 static inline void 4342 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 4343 { 4344 const struct mlx5_flow_driver_ops *fops; 4345 enum mlx5_flow_drv_type type = flow->drv_type; 4346 4347 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4348 fops = flow_get_drv_ops(type); 4349 fops->destroy(dev, flow); 4350 } 4351 4352 /** 4353 * Flow driver find RSS policy tbl API. This abstracts calling driver 4354 * specific functions. Parent flow (rte_flow) should have driver 4355 * type (drv_type). It will find the RSS policy table that has the rss_desc. 4356 * 4357 * @param[in] dev 4358 * Pointer to Ethernet device. 4359 * @param[in, out] flow 4360 * Pointer to flow structure. 4361 * @param[in] policy 4362 * Pointer to meter policy table. 4363 * @param[in] rss_desc 4364 * Pointer to rss_desc 4365 */ 4366 static struct mlx5_flow_meter_sub_policy * 4367 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 4368 struct rte_flow *flow, 4369 struct mlx5_flow_meter_policy *policy, 4370 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 4371 { 4372 const struct mlx5_flow_driver_ops *fops; 4373 enum mlx5_flow_drv_type type = flow->drv_type; 4374 4375 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4376 fops = flow_get_drv_ops(type); 4377 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 4378 } 4379 4380 /** 4381 * Flow driver color tag rule API. This abstracts calling driver 4382 * specific functions. Parent flow (rte_flow) should have driver 4383 * type (drv_type). It will create the color tag rules in hierarchy meter. 4384 * 4385 * @param[in] dev 4386 * Pointer to Ethernet device. 4387 * @param[in, out] flow 4388 * Pointer to flow structure. 4389 * @param[in] fm 4390 * Pointer to flow meter structure. 4391 * @param[in] src_port 4392 * The src port this extra rule should use. 4393 * @param[in] item 4394 * The src port id match item. 4395 * @param[out] error 4396 * Pointer to error structure. 4397 */ 4398 static int 4399 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 4400 struct rte_flow *flow, 4401 struct mlx5_flow_meter_info *fm, 4402 int32_t src_port, 4403 const struct rte_flow_item *item, 4404 struct rte_flow_error *error) 4405 { 4406 const struct mlx5_flow_driver_ops *fops; 4407 enum mlx5_flow_drv_type type = flow->drv_type; 4408 4409 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4410 fops = flow_get_drv_ops(type); 4411 return fops->meter_hierarchy_rule_create(dev, fm, 4412 src_port, item, error); 4413 } 4414 4415 /** 4416 * Get RSS action from the action list. 4417 * 4418 * @param[in] dev 4419 * Pointer to Ethernet device. 4420 * @param[in] actions 4421 * Pointer to the list of actions. 4422 * @param[in] flow 4423 * Parent flow structure pointer. 4424 * 4425 * @return 4426 * Pointer to the RSS action if exist, else return NULL. 4427 */ 4428 static const struct rte_flow_action_rss* 4429 flow_get_rss_action(struct rte_eth_dev *dev, 4430 const struct rte_flow_action actions[]) 4431 { 4432 struct mlx5_priv *priv = dev->data->dev_private; 4433 const struct rte_flow_action_rss *rss = NULL; 4434 struct mlx5_meter_policy_action_container *acg; 4435 struct mlx5_meter_policy_action_container *acy; 4436 4437 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4438 switch (actions->type) { 4439 case RTE_FLOW_ACTION_TYPE_RSS: 4440 rss = actions->conf; 4441 break; 4442 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4443 { 4444 const struct rte_flow_action_sample *sample = 4445 actions->conf; 4446 const struct rte_flow_action *act = sample->actions; 4447 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 4448 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 4449 rss = act->conf; 4450 break; 4451 } 4452 case RTE_FLOW_ACTION_TYPE_METER: 4453 { 4454 uint32_t mtr_idx; 4455 struct mlx5_flow_meter_info *fm; 4456 struct mlx5_flow_meter_policy *policy; 4457 const struct rte_flow_action_meter *mtr = actions->conf; 4458 4459 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 4460 if (fm && !fm->def_policy) { 4461 policy = mlx5_flow_meter_policy_find(dev, 4462 fm->policy_id, NULL); 4463 MLX5_ASSERT(policy); 4464 if (policy->is_hierarchy) { 4465 policy = 4466 mlx5_flow_meter_hierarchy_get_final_policy(dev, 4467 policy); 4468 if (!policy) 4469 return NULL; 4470 } 4471 if (policy->is_rss) { 4472 acg = 4473 &policy->act_cnt[RTE_COLOR_GREEN]; 4474 acy = 4475 &policy->act_cnt[RTE_COLOR_YELLOW]; 4476 if (acg->fate_action == 4477 MLX5_FLOW_FATE_SHARED_RSS) 4478 rss = acg->rss->conf; 4479 else if (acy->fate_action == 4480 MLX5_FLOW_FATE_SHARED_RSS) 4481 rss = acy->rss->conf; 4482 } 4483 } 4484 break; 4485 } 4486 default: 4487 break; 4488 } 4489 } 4490 return rss; 4491 } 4492 4493 /** 4494 * Get ASO age action by index. 4495 * 4496 * @param[in] dev 4497 * Pointer to the Ethernet device structure. 4498 * @param[in] age_idx 4499 * Index to the ASO age action. 4500 * 4501 * @return 4502 * The specified ASO age action. 4503 */ 4504 struct mlx5_aso_age_action* 4505 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 4506 { 4507 uint16_t pool_idx = age_idx & UINT16_MAX; 4508 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 4509 struct mlx5_priv *priv = dev->data->dev_private; 4510 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 4511 struct mlx5_aso_age_pool *pool; 4512 4513 rte_rwlock_read_lock(&mng->resize_rwl); 4514 pool = mng->pools[pool_idx]; 4515 rte_rwlock_read_unlock(&mng->resize_rwl); 4516 return &pool->actions[offset - 1]; 4517 } 4518 4519 /* maps indirect action to translated direct in some actions array */ 4520 struct mlx5_translated_action_handle { 4521 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 4522 int index; /**< Index in related array of rte_flow_action. */ 4523 }; 4524 4525 /** 4526 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 4527 * direct action if translation possible. 4528 * This functionality used to run same execution path for both direct and 4529 * indirect actions on flow create. All necessary preparations for indirect 4530 * action handling should be performed on *handle* actions list returned 4531 * from this call. 4532 * 4533 * @param[in] dev 4534 * Pointer to Ethernet device. 4535 * @param[in] actions 4536 * List of actions to translate. 4537 * @param[out] handle 4538 * List to store translated indirect action object handles. 4539 * @param[in, out] indir_n 4540 * Size of *handle* array. On return should be updated with number of 4541 * indirect actions retrieved from the *actions* list. 4542 * @param[out] translated_actions 4543 * List of actions where all indirect actions were translated to direct 4544 * if possible. NULL if no translation took place. 4545 * @param[out] error 4546 * Pointer to the error structure. 4547 * 4548 * @return 4549 * 0 on success, a negative errno value otherwise and rte_errno is set. 4550 */ 4551 static int 4552 flow_action_handles_translate(struct rte_eth_dev *dev, 4553 const struct rte_flow_action actions[], 4554 struct mlx5_translated_action_handle *handle, 4555 int *indir_n, 4556 struct rte_flow_action **translated_actions, 4557 struct rte_flow_error *error) 4558 { 4559 struct mlx5_priv *priv = dev->data->dev_private; 4560 struct rte_flow_action *translated = NULL; 4561 size_t actions_size; 4562 int n; 4563 int copied_n = 0; 4564 struct mlx5_translated_action_handle *handle_end = NULL; 4565 4566 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 4567 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 4568 continue; 4569 if (copied_n == *indir_n) { 4570 return rte_flow_error_set 4571 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4572 NULL, "too many shared actions"); 4573 } 4574 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 4575 sizeof(actions[n].conf)); 4576 handle[copied_n].index = n; 4577 copied_n++; 4578 } 4579 n++; 4580 *indir_n = copied_n; 4581 if (!copied_n) 4582 return 0; 4583 actions_size = sizeof(struct rte_flow_action) * n; 4584 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 4585 if (!translated) { 4586 rte_errno = ENOMEM; 4587 return -ENOMEM; 4588 } 4589 memcpy(translated, actions, actions_size); 4590 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 4591 struct mlx5_shared_action_rss *shared_rss; 4592 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4593 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4594 uint32_t idx = act_idx & 4595 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4596 4597 switch (type) { 4598 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4599 shared_rss = mlx5_ipool_get 4600 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 4601 translated[handle->index].type = 4602 RTE_FLOW_ACTION_TYPE_RSS; 4603 translated[handle->index].conf = 4604 &shared_rss->origin; 4605 break; 4606 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 4607 translated[handle->index].type = 4608 (enum rte_flow_action_type) 4609 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 4610 translated[handle->index].conf = (void *)(uintptr_t)idx; 4611 break; 4612 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 4613 translated[handle->index].type = 4614 (enum rte_flow_action_type) 4615 MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK; 4616 translated[handle->index].conf = (void *)(uintptr_t)idx; 4617 break; 4618 case MLX5_INDIRECT_ACTION_TYPE_AGE: 4619 if (priv->sh->flow_hit_aso_en) { 4620 translated[handle->index].type = 4621 (enum rte_flow_action_type) 4622 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 4623 translated[handle->index].conf = 4624 (void *)(uintptr_t)idx; 4625 break; 4626 } 4627 /* Fall-through */ 4628 case MLX5_INDIRECT_ACTION_TYPE_CT: 4629 if (priv->sh->ct_aso_en) { 4630 translated[handle->index].type = 4631 RTE_FLOW_ACTION_TYPE_CONNTRACK; 4632 translated[handle->index].conf = 4633 (void *)(uintptr_t)idx; 4634 break; 4635 } 4636 /* Fall-through */ 4637 default: 4638 mlx5_free(translated); 4639 return rte_flow_error_set 4640 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 4641 NULL, "invalid indirect action type"); 4642 } 4643 } 4644 *translated_actions = translated; 4645 return 0; 4646 } 4647 4648 /** 4649 * Get Shared RSS action from the action list. 4650 * 4651 * @param[in] dev 4652 * Pointer to Ethernet device. 4653 * @param[in] shared 4654 * Pointer to the list of actions. 4655 * @param[in] shared_n 4656 * Actions list length. 4657 * 4658 * @return 4659 * The MLX5 RSS action ID if exists, otherwise return 0. 4660 */ 4661 static uint32_t 4662 flow_get_shared_rss_action(struct rte_eth_dev *dev, 4663 struct mlx5_translated_action_handle *handle, 4664 int shared_n) 4665 { 4666 struct mlx5_translated_action_handle *handle_end; 4667 struct mlx5_priv *priv = dev->data->dev_private; 4668 struct mlx5_shared_action_rss *shared_rss; 4669 4670 4671 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 4672 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4673 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4674 uint32_t idx = act_idx & 4675 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4676 switch (type) { 4677 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4678 shared_rss = mlx5_ipool_get 4679 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 4680 idx); 4681 rte_atomic_fetch_add_explicit(&shared_rss->refcnt, 1, 4682 rte_memory_order_relaxed); 4683 return idx; 4684 default: 4685 break; 4686 } 4687 } 4688 return 0; 4689 } 4690 4691 static unsigned int 4692 find_graph_root(uint32_t rss_level) 4693 { 4694 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 4695 MLX5_EXPANSION_ROOT_OUTER; 4696 } 4697 4698 /** 4699 * Get layer flags from the prefix flow. 4700 * 4701 * Some flows may be split to several subflows, the prefix subflow gets the 4702 * match items and the suffix sub flow gets the actions. 4703 * Some actions need the user defined match item flags to get the detail for 4704 * the action. 4705 * This function helps the suffix flow to get the item layer flags from prefix 4706 * subflow. 4707 * 4708 * @param[in] dev_flow 4709 * Pointer the created prefix subflow. 4710 * 4711 * @return 4712 * The layers get from prefix subflow. 4713 */ 4714 static inline uint64_t 4715 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 4716 { 4717 uint64_t layers = 0; 4718 4719 /* 4720 * Layers bits could be localization, but usually the compiler will 4721 * help to do the optimization work for source code. 4722 * If no decap actions, use the layers directly. 4723 */ 4724 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 4725 return dev_flow->handle->layers; 4726 /* Convert L3 layers with decap action. */ 4727 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 4728 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 4729 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 4730 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 4731 /* Convert L4 layers with decap action. */ 4732 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 4733 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 4734 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 4735 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 4736 return layers; 4737 } 4738 4739 /** 4740 * Get metadata split action information. 4741 * 4742 * @param[in] actions 4743 * Pointer to the list of actions. 4744 * @param[out] qrss 4745 * Pointer to the return pointer. 4746 * @param[out] qrss_type 4747 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 4748 * if no QUEUE/RSS is found. 4749 * @param[out] encap_idx 4750 * Pointer to the index of the encap action if exists, otherwise the last 4751 * action index. 4752 * 4753 * @return 4754 * Total number of actions. 4755 */ 4756 static int 4757 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4758 const struct rte_flow_action **qrss, 4759 int *encap_idx) 4760 { 4761 const struct rte_flow_action_raw_encap *raw_encap; 4762 int actions_n = 0; 4763 int raw_decap_idx = -1; 4764 4765 *encap_idx = -1; 4766 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4767 switch (actions->type) { 4768 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4769 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4770 *encap_idx = actions_n; 4771 break; 4772 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4773 raw_decap_idx = actions_n; 4774 break; 4775 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4776 raw_encap = actions->conf; 4777 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4778 *encap_idx = raw_decap_idx != -1 ? 4779 raw_decap_idx : actions_n; 4780 break; 4781 case RTE_FLOW_ACTION_TYPE_QUEUE: 4782 case RTE_FLOW_ACTION_TYPE_RSS: 4783 *qrss = actions; 4784 break; 4785 default: 4786 break; 4787 } 4788 actions_n++; 4789 } 4790 if (*encap_idx == -1) 4791 *encap_idx = actions_n; 4792 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4793 return actions_n + 1; 4794 } 4795 4796 /** 4797 * Check if the action will change packet. 4798 * 4799 * @param dev 4800 * Pointer to Ethernet device. 4801 * @param[in] type 4802 * action type. 4803 * 4804 * @return 4805 * true if action will change packet, false otherwise. 4806 */ 4807 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4808 enum rte_flow_action_type type) 4809 { 4810 struct mlx5_priv *priv = dev->data->dev_private; 4811 4812 switch (type) { 4813 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4814 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4815 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4816 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4817 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4818 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4819 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4820 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4821 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4822 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4823 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4824 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4825 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4826 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4827 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4828 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4829 case RTE_FLOW_ACTION_TYPE_SET_META: 4830 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4831 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4832 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4833 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4834 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4835 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4836 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4837 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4838 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4839 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4840 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4841 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4842 return true; 4843 case RTE_FLOW_ACTION_TYPE_FLAG: 4844 case RTE_FLOW_ACTION_TYPE_MARK: 4845 if (priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 4846 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) 4847 return true; 4848 else 4849 return false; 4850 default: 4851 return false; 4852 } 4853 } 4854 4855 /** 4856 * Check meter action from the action list. 4857 * 4858 * @param dev 4859 * Pointer to Ethernet device. 4860 * @param[in] actions 4861 * Pointer to the list of actions. 4862 * @param[out] has_mtr 4863 * Pointer to the meter exist flag. 4864 * @param[out] has_modify 4865 * Pointer to the flag showing there's packet change action. 4866 * @param[out] meter_id 4867 * Pointer to the meter id. 4868 * 4869 * @return 4870 * Total number of actions. 4871 */ 4872 static int 4873 flow_check_meter_action(struct rte_eth_dev *dev, 4874 const struct rte_flow_action actions[], 4875 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4876 { 4877 const struct rte_flow_action_meter *mtr = NULL; 4878 int actions_n = 0; 4879 4880 MLX5_ASSERT(has_mtr); 4881 *has_mtr = false; 4882 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4883 switch (actions->type) { 4884 case RTE_FLOW_ACTION_TYPE_METER: 4885 mtr = actions->conf; 4886 *meter_id = mtr->mtr_id; 4887 *has_mtr = true; 4888 break; 4889 default: 4890 break; 4891 } 4892 if (!*has_mtr) 4893 *has_modify |= flow_check_modify_action_type(dev, 4894 actions->type); 4895 actions_n++; 4896 } 4897 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4898 return actions_n + 1; 4899 } 4900 4901 /** 4902 * Check if the flow should be split due to hairpin. 4903 * The reason for the split is that in current HW we can't 4904 * support encap and push-vlan on Rx, so if a flow contains 4905 * these actions we move it to Tx. 4906 * 4907 * @param dev 4908 * Pointer to Ethernet device. 4909 * @param[in] attr 4910 * Flow rule attributes. 4911 * @param[in] actions 4912 * Associated actions (list terminated by the END action). 4913 * 4914 * @return 4915 * > 0 the number of actions and the flow should be split, 4916 * 0 when no split required. 4917 */ 4918 static int 4919 flow_check_hairpin_split(struct rte_eth_dev *dev, 4920 const struct rte_flow_attr *attr, 4921 const struct rte_flow_action actions[]) 4922 { 4923 int queue_action = 0; 4924 int action_n = 0; 4925 int split = 0; 4926 int push_vlan = 0; 4927 const struct rte_flow_action_queue *queue; 4928 const struct rte_flow_action_rss *rss; 4929 const struct rte_flow_action_raw_encap *raw_encap; 4930 const struct rte_eth_hairpin_conf *conf; 4931 4932 if (!attr->ingress) 4933 return 0; 4934 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4935 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 4936 push_vlan = 1; 4937 switch (actions->type) { 4938 case RTE_FLOW_ACTION_TYPE_QUEUE: 4939 queue = actions->conf; 4940 if (queue == NULL) 4941 return 0; 4942 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4943 if (conf == NULL || conf->tx_explicit != 0) 4944 return 0; 4945 queue_action = 1; 4946 action_n++; 4947 break; 4948 case RTE_FLOW_ACTION_TYPE_RSS: 4949 rss = actions->conf; 4950 if (rss == NULL || rss->queue_num == 0) 4951 return 0; 4952 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4953 if (conf == NULL || conf->tx_explicit != 0) 4954 return 0; 4955 queue_action = 1; 4956 action_n++; 4957 break; 4958 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4959 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4960 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4961 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4962 split++; 4963 action_n++; 4964 break; 4965 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4966 if (push_vlan) 4967 split++; 4968 action_n++; 4969 break; 4970 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4971 raw_encap = actions->conf; 4972 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4973 split++; 4974 action_n++; 4975 break; 4976 default: 4977 action_n++; 4978 break; 4979 } 4980 } 4981 if (split && queue_action) 4982 return action_n; 4983 return 0; 4984 } 4985 4986 /* Declare flow create/destroy prototype in advance. */ 4987 static uint32_t 4988 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4989 const struct rte_flow_attr *attr, 4990 const struct rte_flow_item items[], 4991 const struct rte_flow_action actions[], 4992 bool external, struct rte_flow_error *error); 4993 4994 static void 4995 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4996 uint32_t flow_idx); 4997 4998 int 4999 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 5000 struct mlx5_list_entry *entry, void *cb_ctx) 5001 { 5002 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 5003 struct mlx5_flow_mreg_copy_resource *mcp_res = 5004 container_of(entry, typeof(*mcp_res), hlist_ent); 5005 5006 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 5007 } 5008 5009 struct mlx5_list_entry * 5010 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 5011 { 5012 struct rte_eth_dev *dev = tool_ctx; 5013 struct mlx5_priv *priv = dev->data->dev_private; 5014 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 5015 struct mlx5_flow_mreg_copy_resource *mcp_res; 5016 struct rte_flow_error *error = ctx->error; 5017 uint32_t idx = 0; 5018 int ret; 5019 uint32_t mark_id = *(uint32_t *)(ctx->data); 5020 struct rte_flow_attr attr = { 5021 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5022 .ingress = 1, 5023 }; 5024 struct mlx5_rte_flow_item_tag tag_spec = { 5025 .data = mark_id, 5026 }; 5027 struct rte_flow_item items[] = { 5028 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 5029 }; 5030 struct rte_flow_action_mark ftag = { 5031 .id = mark_id, 5032 }; 5033 struct mlx5_flow_action_copy_mreg cp_mreg = { 5034 .dst = REG_B, 5035 .src = REG_NON, 5036 }; 5037 struct rte_flow_action_jump jump = { 5038 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 5039 }; 5040 struct rte_flow_action actions[] = { 5041 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 5042 }; 5043 5044 /* Fill the register fields in the flow. */ 5045 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 5046 if (ret < 0) 5047 return NULL; 5048 tag_spec.id = ret; 5049 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 5050 if (ret < 0) 5051 return NULL; 5052 cp_mreg.src = ret; 5053 /* Provide the full width of FLAG specific value. */ 5054 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 5055 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 5056 /* Build a new flow. */ 5057 if (mark_id != MLX5_DEFAULT_COPY_ID) { 5058 items[0] = (struct rte_flow_item){ 5059 .type = (enum rte_flow_item_type) 5060 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5061 .spec = &tag_spec, 5062 }; 5063 items[1] = (struct rte_flow_item){ 5064 .type = RTE_FLOW_ITEM_TYPE_END, 5065 }; 5066 actions[0] = (struct rte_flow_action){ 5067 .type = (enum rte_flow_action_type) 5068 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 5069 .conf = &ftag, 5070 }; 5071 actions[1] = (struct rte_flow_action){ 5072 .type = (enum rte_flow_action_type) 5073 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5074 .conf = &cp_mreg, 5075 }; 5076 actions[2] = (struct rte_flow_action){ 5077 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5078 .conf = &jump, 5079 }; 5080 actions[3] = (struct rte_flow_action){ 5081 .type = RTE_FLOW_ACTION_TYPE_END, 5082 }; 5083 } else { 5084 /* Default rule, wildcard match. */ 5085 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 5086 items[0] = (struct rte_flow_item){ 5087 .type = RTE_FLOW_ITEM_TYPE_END, 5088 }; 5089 actions[0] = (struct rte_flow_action){ 5090 .type = (enum rte_flow_action_type) 5091 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5092 .conf = &cp_mreg, 5093 }; 5094 actions[1] = (struct rte_flow_action){ 5095 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5096 .conf = &jump, 5097 }; 5098 actions[2] = (struct rte_flow_action){ 5099 .type = RTE_FLOW_ACTION_TYPE_END, 5100 }; 5101 } 5102 /* Build a new entry. */ 5103 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 5104 if (!mcp_res) { 5105 rte_errno = ENOMEM; 5106 return NULL; 5107 } 5108 mcp_res->idx = idx; 5109 mcp_res->mark_id = mark_id; 5110 /* 5111 * The copy Flows are not included in any list. There 5112 * ones are referenced from other Flows and can not 5113 * be applied, removed, deleted in arbitrary order 5114 * by list traversing. 5115 */ 5116 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 5117 &attr, items, actions, false, error); 5118 if (!mcp_res->rix_flow) { 5119 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 5120 return NULL; 5121 } 5122 return &mcp_res->hlist_ent; 5123 } 5124 5125 struct mlx5_list_entry * 5126 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 5127 void *cb_ctx __rte_unused) 5128 { 5129 struct rte_eth_dev *dev = tool_ctx; 5130 struct mlx5_priv *priv = dev->data->dev_private; 5131 struct mlx5_flow_mreg_copy_resource *mcp_res; 5132 uint32_t idx = 0; 5133 5134 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 5135 if (!mcp_res) { 5136 rte_errno = ENOMEM; 5137 return NULL; 5138 } 5139 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 5140 mcp_res->idx = idx; 5141 return &mcp_res->hlist_ent; 5142 } 5143 5144 void 5145 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 5146 { 5147 struct mlx5_flow_mreg_copy_resource *mcp_res = 5148 container_of(entry, typeof(*mcp_res), hlist_ent); 5149 struct rte_eth_dev *dev = tool_ctx; 5150 struct mlx5_priv *priv = dev->data->dev_private; 5151 5152 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 5153 } 5154 5155 /** 5156 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5157 * 5158 * As mark_id is unique, if there's already a registered flow for the mark_id, 5159 * return by increasing the reference counter of the resource. Otherwise, create 5160 * the resource (mcp_res) and flow. 5161 * 5162 * Flow looks like, 5163 * - If ingress port is ANY and reg_c[1] is mark_id, 5164 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5165 * 5166 * For default flow (zero mark_id), flow is like, 5167 * - If ingress port is ANY, 5168 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 5169 * 5170 * @param dev 5171 * Pointer to Ethernet device. 5172 * @param mark_id 5173 * ID of MARK action, zero means default flow for META. 5174 * @param[out] error 5175 * Perform verbose error reporting if not NULL. 5176 * 5177 * @return 5178 * Associated resource on success, NULL otherwise and rte_errno is set. 5179 */ 5180 static struct mlx5_flow_mreg_copy_resource * 5181 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 5182 struct rte_flow_error *error) 5183 { 5184 struct mlx5_priv *priv = dev->data->dev_private; 5185 struct mlx5_list_entry *entry; 5186 struct mlx5_flow_cb_ctx ctx = { 5187 .dev = dev, 5188 .error = error, 5189 .data = &mark_id, 5190 }; 5191 5192 /* Check if already registered. */ 5193 MLX5_ASSERT(priv->mreg_cp_tbl); 5194 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 5195 if (!entry) 5196 return NULL; 5197 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 5198 hlist_ent); 5199 } 5200 5201 void 5202 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 5203 { 5204 struct mlx5_flow_mreg_copy_resource *mcp_res = 5205 container_of(entry, typeof(*mcp_res), hlist_ent); 5206 struct rte_eth_dev *dev = tool_ctx; 5207 struct mlx5_priv *priv = dev->data->dev_private; 5208 5209 MLX5_ASSERT(mcp_res->rix_flow); 5210 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 5211 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 5212 } 5213 5214 /** 5215 * Release flow in RX_CP_TBL. 5216 * 5217 * @param dev 5218 * Pointer to Ethernet device. 5219 * @flow 5220 * Parent flow for wich copying is provided. 5221 */ 5222 static void 5223 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 5224 struct rte_flow *flow) 5225 { 5226 struct mlx5_flow_mreg_copy_resource *mcp_res; 5227 struct mlx5_priv *priv = dev->data->dev_private; 5228 5229 if (!flow->rix_mreg_copy) 5230 return; 5231 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 5232 flow->rix_mreg_copy); 5233 if (!mcp_res || !priv->mreg_cp_tbl) 5234 return; 5235 MLX5_ASSERT(mcp_res->rix_flow); 5236 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 5237 flow->rix_mreg_copy = 0; 5238 } 5239 5240 /** 5241 * Remove the default copy action from RX_CP_TBL. 5242 * 5243 * This functions is called in the mlx5_dev_start(). No thread safe 5244 * is guaranteed. 5245 * 5246 * @param dev 5247 * Pointer to Ethernet device. 5248 */ 5249 static void 5250 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 5251 { 5252 struct mlx5_list_entry *entry; 5253 struct mlx5_priv *priv = dev->data->dev_private; 5254 struct mlx5_flow_cb_ctx ctx; 5255 uint32_t mark_id; 5256 5257 /* Check if default flow is registered. */ 5258 if (!priv->mreg_cp_tbl) 5259 return; 5260 mark_id = MLX5_DEFAULT_COPY_ID; 5261 ctx.data = &mark_id; 5262 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 5263 if (!entry) 5264 return; 5265 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 5266 } 5267 5268 /** 5269 * Add the default copy action in RX_CP_TBL. 5270 * 5271 * This functions is called in the mlx5_dev_start(). No thread safe 5272 * is guaranteed. 5273 * 5274 * @param dev 5275 * Pointer to Ethernet device. 5276 * @param[out] error 5277 * Perform verbose error reporting if not NULL. 5278 * 5279 * @return 5280 * 0 for success, negative value otherwise and rte_errno is set. 5281 */ 5282 static int 5283 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 5284 struct rte_flow_error *error) 5285 { 5286 struct mlx5_priv *priv = dev->data->dev_private; 5287 struct mlx5_flow_mreg_copy_resource *mcp_res; 5288 struct mlx5_flow_cb_ctx ctx; 5289 uint32_t mark_id; 5290 5291 /* Check whether extensive metadata feature is engaged. */ 5292 if (!priv->sh->config.dv_flow_en || 5293 priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5294 !mlx5_flow_ext_mreg_supported(dev) || 5295 !priv->sh->dv_regc0_mask) 5296 return 0; 5297 /* 5298 * Add default mreg copy flow may be called multiple time, but 5299 * only be called once in stop. Avoid register it twice. 5300 */ 5301 mark_id = MLX5_DEFAULT_COPY_ID; 5302 ctx.data = &mark_id; 5303 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 5304 return 0; 5305 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 5306 if (!mcp_res) 5307 return -rte_errno; 5308 return 0; 5309 } 5310 5311 /** 5312 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5313 * 5314 * All the flow having Q/RSS action should be split by 5315 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 5316 * performs the following, 5317 * - CQE->flow_tag := reg_c[1] (MARK) 5318 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5319 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 5320 * but there should be a flow per each MARK ID set by MARK action. 5321 * 5322 * For the aforementioned reason, if there's a MARK action in flow's action 5323 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 5324 * the MARK ID to CQE's flow_tag like, 5325 * - If reg_c[1] is mark_id, 5326 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5327 * 5328 * For SET_META action which stores value in reg_c[0], as the destination is 5329 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 5330 * MARK ID means the default flow. The default flow looks like, 5331 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5332 * 5333 * @param dev 5334 * Pointer to Ethernet device. 5335 * @param flow 5336 * Pointer to flow structure. 5337 * @param[in] actions 5338 * Pointer to the list of actions. 5339 * @param[out] error 5340 * Perform verbose error reporting if not NULL. 5341 * 5342 * @return 5343 * 0 on success, negative value otherwise and rte_errno is set. 5344 */ 5345 static int 5346 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 5347 struct rte_flow *flow, 5348 const struct rte_flow_action *actions, 5349 struct rte_flow_error *error) 5350 { 5351 struct mlx5_priv *priv = dev->data->dev_private; 5352 struct mlx5_sh_config *config = &priv->sh->config; 5353 struct mlx5_flow_mreg_copy_resource *mcp_res; 5354 const struct rte_flow_action_mark *mark; 5355 5356 /* Check whether extensive metadata feature is engaged. */ 5357 if (!config->dv_flow_en || 5358 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5359 !mlx5_flow_ext_mreg_supported(dev) || 5360 !priv->sh->dv_regc0_mask) 5361 return 0; 5362 /* Find MARK action. */ 5363 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5364 switch (actions->type) { 5365 case RTE_FLOW_ACTION_TYPE_FLAG: 5366 mcp_res = flow_mreg_add_copy_action 5367 (dev, MLX5_FLOW_MARK_DEFAULT, error); 5368 if (!mcp_res) 5369 return -rte_errno; 5370 flow->rix_mreg_copy = mcp_res->idx; 5371 return 0; 5372 case RTE_FLOW_ACTION_TYPE_MARK: 5373 mark = (const struct rte_flow_action_mark *) 5374 actions->conf; 5375 mcp_res = 5376 flow_mreg_add_copy_action(dev, mark->id, error); 5377 if (!mcp_res) 5378 return -rte_errno; 5379 flow->rix_mreg_copy = mcp_res->idx; 5380 return 0; 5381 default: 5382 break; 5383 } 5384 } 5385 return 0; 5386 } 5387 5388 #define MLX5_MAX_SPLIT_ACTIONS 24 5389 #define MLX5_MAX_SPLIT_ITEMS 24 5390 5391 /** 5392 * Split the hairpin flow. 5393 * Since HW can't support encap and push-vlan on Rx, we move these 5394 * actions to Tx. 5395 * If the count action is after the encap then we also 5396 * move the count action. in this case the count will also measure 5397 * the outer bytes. 5398 * 5399 * @param dev 5400 * Pointer to Ethernet device. 5401 * @param[in] actions 5402 * Associated actions (list terminated by the END action). 5403 * @param[out] actions_rx 5404 * Rx flow actions. 5405 * @param[out] actions_tx 5406 * Tx flow actions.. 5407 * @param[out] pattern_tx 5408 * The pattern items for the Tx flow. 5409 * @param[out] flow_id 5410 * The flow ID connected to this flow. 5411 * 5412 * @return 5413 * 0 on success. 5414 */ 5415 static int 5416 flow_hairpin_split(struct rte_eth_dev *dev, 5417 const struct rte_flow_action actions[], 5418 struct rte_flow_action actions_rx[], 5419 struct rte_flow_action actions_tx[], 5420 struct rte_flow_item pattern_tx[], 5421 uint32_t flow_id) 5422 { 5423 const struct rte_flow_action_raw_encap *raw_encap; 5424 const struct rte_flow_action_raw_decap *raw_decap; 5425 struct mlx5_rte_flow_action_set_tag *set_tag; 5426 struct rte_flow_action *tag_action; 5427 struct mlx5_rte_flow_item_tag *tag_item; 5428 struct rte_flow_item *item; 5429 char *addr; 5430 int push_vlan = 0; 5431 int encap = 0; 5432 5433 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5434 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 5435 push_vlan = 1; 5436 switch (actions->type) { 5437 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 5438 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 5439 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5440 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5441 rte_memcpy(actions_tx, actions, 5442 sizeof(struct rte_flow_action)); 5443 actions_tx++; 5444 break; 5445 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5446 if (push_vlan) { 5447 rte_memcpy(actions_tx, actions, 5448 sizeof(struct rte_flow_action)); 5449 actions_tx++; 5450 } else { 5451 rte_memcpy(actions_rx, actions, 5452 sizeof(struct rte_flow_action)); 5453 actions_rx++; 5454 } 5455 break; 5456 case RTE_FLOW_ACTION_TYPE_COUNT: 5457 case RTE_FLOW_ACTION_TYPE_AGE: 5458 if (encap) { 5459 rte_memcpy(actions_tx, actions, 5460 sizeof(struct rte_flow_action)); 5461 actions_tx++; 5462 } else { 5463 rte_memcpy(actions_rx, actions, 5464 sizeof(struct rte_flow_action)); 5465 actions_rx++; 5466 } 5467 break; 5468 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5469 raw_encap = actions->conf; 5470 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 5471 memcpy(actions_tx, actions, 5472 sizeof(struct rte_flow_action)); 5473 actions_tx++; 5474 encap = 1; 5475 } else { 5476 rte_memcpy(actions_rx, actions, 5477 sizeof(struct rte_flow_action)); 5478 actions_rx++; 5479 } 5480 break; 5481 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5482 raw_decap = actions->conf; 5483 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 5484 memcpy(actions_tx, actions, 5485 sizeof(struct rte_flow_action)); 5486 actions_tx++; 5487 } else { 5488 rte_memcpy(actions_rx, actions, 5489 sizeof(struct rte_flow_action)); 5490 actions_rx++; 5491 } 5492 break; 5493 default: 5494 rte_memcpy(actions_rx, actions, 5495 sizeof(struct rte_flow_action)); 5496 actions_rx++; 5497 break; 5498 } 5499 } 5500 /* Add set meta action and end action for the Rx flow. */ 5501 tag_action = actions_rx; 5502 tag_action->type = (enum rte_flow_action_type) 5503 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5504 actions_rx++; 5505 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 5506 actions_rx++; 5507 set_tag = (void *)actions_rx; 5508 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5509 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 5510 .data = flow_id, 5511 }; 5512 MLX5_ASSERT(set_tag->id > REG_NON); 5513 tag_action->conf = set_tag; 5514 /* Create Tx item list. */ 5515 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 5516 addr = (void *)&pattern_tx[2]; 5517 item = pattern_tx; 5518 item->type = (enum rte_flow_item_type) 5519 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5520 tag_item = (void *)addr; 5521 tag_item->data = flow_id; 5522 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 5523 MLX5_ASSERT(set_tag->id > REG_NON); 5524 item->spec = tag_item; 5525 addr += sizeof(struct mlx5_rte_flow_item_tag); 5526 tag_item = (void *)addr; 5527 tag_item->data = UINT32_MAX; 5528 tag_item->id = UINT16_MAX; 5529 item->mask = tag_item; 5530 item->last = NULL; 5531 item++; 5532 item->type = RTE_FLOW_ITEM_TYPE_END; 5533 return 0; 5534 } 5535 5536 /** 5537 * The last stage of splitting chain, just creates the subflow 5538 * without any modification. 5539 * 5540 * @param[in] dev 5541 * Pointer to Ethernet device. 5542 * @param[in] flow 5543 * Parent flow structure pointer. 5544 * @param[in, out] sub_flow 5545 * Pointer to return the created subflow, may be NULL. 5546 * @param[in] attr 5547 * Flow rule attributes. 5548 * @param[in] items 5549 * Pattern specification (list terminated by the END pattern item). 5550 * @param[in] actions 5551 * Associated actions (list terminated by the END action). 5552 * @param[in] flow_split_info 5553 * Pointer to flow split info structure. 5554 * @param[out] error 5555 * Perform verbose error reporting if not NULL. 5556 * @return 5557 * 0 on success, negative value otherwise 5558 */ 5559 static int 5560 flow_create_split_inner(struct rte_eth_dev *dev, 5561 struct rte_flow *flow, 5562 struct mlx5_flow **sub_flow, 5563 const struct rte_flow_attr *attr, 5564 const struct rte_flow_item items[], 5565 const struct rte_flow_action actions[], 5566 struct mlx5_flow_split_info *flow_split_info, 5567 struct rte_flow_error *error) 5568 { 5569 struct mlx5_flow *dev_flow; 5570 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5571 5572 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 5573 flow_split_info->flow_idx, error); 5574 if (!dev_flow) 5575 return -rte_errno; 5576 dev_flow->flow = flow; 5577 dev_flow->external = flow_split_info->external; 5578 dev_flow->skip_scale = flow_split_info->skip_scale; 5579 /* Subflow object was created, we must include one in the list. */ 5580 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5581 dev_flow->handle, next); 5582 /* 5583 * If dev_flow is as one of the suffix flow, some actions in suffix 5584 * flow may need some user defined item layer flags, and pass the 5585 * Metadata rxq mark flag to suffix flow as well. 5586 */ 5587 if (flow_split_info->prefix_layers) 5588 dev_flow->handle->layers = flow_split_info->prefix_layers; 5589 if (flow_split_info->prefix_mark) { 5590 MLX5_ASSERT(wks); 5591 wks->mark = 1; 5592 } 5593 if (sub_flow) 5594 *sub_flow = dev_flow; 5595 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5596 dev_flow->dv.table_id = flow_split_info->table_id; 5597 #endif 5598 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 5599 } 5600 5601 /** 5602 * Get the sub policy of a meter. 5603 * 5604 * @param[in] dev 5605 * Pointer to Ethernet device. 5606 * @param[in] flow 5607 * Parent flow structure pointer. 5608 * @param wks 5609 * Pointer to thread flow work space. 5610 * @param[in] attr 5611 * Flow rule attributes. 5612 * @param[in] items 5613 * Pattern specification (list terminated by the END pattern item). 5614 * @param[out] error 5615 * Perform verbose error reporting if not NULL. 5616 * 5617 * @return 5618 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 5619 */ 5620 static struct mlx5_flow_meter_sub_policy * 5621 get_meter_sub_policy(struct rte_eth_dev *dev, 5622 struct rte_flow *flow, 5623 struct mlx5_flow_workspace *wks, 5624 const struct rte_flow_attr *attr, 5625 const struct rte_flow_item items[], 5626 struct rte_flow_error *error) 5627 { 5628 struct mlx5_flow_meter_policy *policy; 5629 struct mlx5_flow_meter_policy *final_policy; 5630 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 5631 5632 policy = wks->policy; 5633 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 5634 if (final_policy->is_rss || final_policy->is_queue) { 5635 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 5636 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 5637 uint32_t i; 5638 5639 /* 5640 * This is a tmp dev_flow, 5641 * no need to register any matcher for it in translate. 5642 */ 5643 wks->skip_matcher_reg = 1; 5644 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 5645 struct mlx5_flow dev_flow = {0}; 5646 struct mlx5_flow_handle dev_handle = { {0} }; 5647 uint8_t fate = final_policy->act_cnt[i].fate_action; 5648 5649 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 5650 const struct rte_flow_action_rss *rss_act = 5651 final_policy->act_cnt[i].rss->conf; 5652 struct rte_flow_action rss_actions[2] = { 5653 [0] = { 5654 .type = RTE_FLOW_ACTION_TYPE_RSS, 5655 .conf = rss_act, 5656 }, 5657 [1] = { 5658 .type = RTE_FLOW_ACTION_TYPE_END, 5659 .conf = NULL, 5660 } 5661 }; 5662 5663 dev_flow.handle = &dev_handle; 5664 dev_flow.ingress = attr->ingress; 5665 dev_flow.flow = flow; 5666 dev_flow.external = 0; 5667 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5668 dev_flow.dv.transfer = attr->transfer; 5669 #endif 5670 /** 5671 * Translate RSS action to get rss hash fields. 5672 */ 5673 if (flow_drv_translate(dev, &dev_flow, attr, 5674 items, rss_actions, error)) 5675 goto exit; 5676 rss_desc_v[i] = wks->rss_desc; 5677 rss_desc_v[i].symmetric_hash_function = 5678 dev_flow.symmetric_hash_function; 5679 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 5680 rss_desc_v[i].hash_fields = 5681 dev_flow.hash_fields; 5682 rss_desc_v[i].queue_num = 5683 rss_desc_v[i].hash_fields ? 5684 rss_desc_v[i].queue_num : 1; 5685 rss_desc_v[i].tunnel = 5686 !!(dev_flow.handle->layers & 5687 MLX5_FLOW_LAYER_TUNNEL); 5688 /* Use the RSS queues in the containers. */ 5689 rss_desc_v[i].queue = 5690 (uint16_t *)(uintptr_t)rss_act->queue; 5691 rss_desc[i] = &rss_desc_v[i]; 5692 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 5693 /* This is queue action. */ 5694 rss_desc_v[i] = wks->rss_desc; 5695 rss_desc_v[i].key_len = 0; 5696 rss_desc_v[i].hash_fields = 0; 5697 rss_desc_v[i].queue = 5698 &final_policy->act_cnt[i].queue; 5699 rss_desc_v[i].queue_num = 1; 5700 rss_desc[i] = &rss_desc_v[i]; 5701 } else { 5702 rss_desc[i] = NULL; 5703 } 5704 } 5705 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 5706 flow, policy, rss_desc); 5707 } else { 5708 enum mlx5_meter_domain mtr_domain = 5709 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5710 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5711 MLX5_MTR_DOMAIN_INGRESS); 5712 sub_policy = policy->sub_policys[mtr_domain][0]; 5713 } 5714 if (!sub_policy) 5715 rte_flow_error_set(error, EINVAL, 5716 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5717 "Failed to get meter sub-policy."); 5718 exit: 5719 return sub_policy; 5720 } 5721 5722 /** 5723 * Split the meter flow. 5724 * 5725 * As meter flow will split to three sub flow, other than meter 5726 * action, the other actions make sense to only meter accepts 5727 * the packet. If it need to be dropped, no other additional 5728 * actions should be take. 5729 * 5730 * One kind of special action which decapsulates the L3 tunnel 5731 * header will be in the prefix sub flow, as not to take the 5732 * L3 tunnel header into account. 5733 * 5734 * @param[in] dev 5735 * Pointer to Ethernet device. 5736 * @param[in] flow 5737 * Parent flow structure pointer. 5738 * @param wks 5739 * Pointer to thread flow work space. 5740 * @param[in] attr 5741 * Flow rule attributes. 5742 * @param[in] items 5743 * Pattern specification (list terminated by the END pattern item). 5744 * @param[out] sfx_items 5745 * Suffix flow match items (list terminated by the END pattern item). 5746 * @param[in] actions 5747 * Associated actions (list terminated by the END action). 5748 * @param[out] actions_sfx 5749 * Suffix flow actions. 5750 * @param[out] actions_pre 5751 * Prefix flow actions. 5752 * @param[out] mtr_flow_id 5753 * Pointer to meter flow id. 5754 * @param[out] error 5755 * Perform verbose error reporting if not NULL. 5756 * 5757 * @return 5758 * 0 on success, a negative errno value otherwise and rte_errno is set. 5759 */ 5760 static int 5761 flow_meter_split_prep(struct rte_eth_dev *dev, 5762 struct rte_flow *flow, 5763 struct mlx5_flow_workspace *wks, 5764 const struct rte_flow_attr *attr, 5765 const struct rte_flow_item items[], 5766 struct rte_flow_item sfx_items[], 5767 const struct rte_flow_action actions[], 5768 struct rte_flow_action actions_sfx[], 5769 struct rte_flow_action actions_pre[], 5770 uint32_t *mtr_flow_id, 5771 struct rte_flow_error *error) 5772 { 5773 struct mlx5_priv *priv = dev->data->dev_private; 5774 struct mlx5_flow_meter_info *fm = wks->fm; 5775 struct rte_flow_action *tag_action = NULL; 5776 struct rte_flow_item *tag_item; 5777 struct mlx5_rte_flow_action_set_tag *set_tag; 5778 const struct rte_flow_action_raw_encap *raw_encap; 5779 const struct rte_flow_action_raw_decap *raw_decap; 5780 struct mlx5_rte_flow_item_tag *tag_item_spec; 5781 struct mlx5_rte_flow_item_tag *tag_item_mask; 5782 uint32_t tag_id = 0; 5783 bool vlan_actions; 5784 struct rte_flow_item *orig_sfx_items = sfx_items; 5785 const struct rte_flow_item *orig_items = items; 5786 struct rte_flow_action *hw_mtr_action; 5787 struct rte_flow_action *action_pre_head = NULL; 5788 uint16_t flow_src_port = priv->representor_id; 5789 bool mtr_first; 5790 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5791 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5792 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5793 uint32_t flow_id = 0; 5794 uint32_t flow_id_reversed = 0; 5795 uint8_t flow_id_bits = 0; 5796 bool after_meter = false; 5797 int shift; 5798 5799 /* Prepare the suffix subflow items. */ 5800 tag_item = sfx_items++; 5801 tag_item->type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5802 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5803 int item_type = items->type; 5804 5805 switch (item_type) { 5806 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5807 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 5808 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 5809 if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, NULL, error)) 5810 return -rte_errno; 5811 if (!fm->def_policy && wks->policy->hierarchy_match_port && 5812 flow_src_port != priv->representor_id) { 5813 if (flow_drv_mtr_hierarchy_rule_create(dev, 5814 flow, fm, 5815 flow_src_port, 5816 items, 5817 error)) 5818 return -rte_errno; 5819 } 5820 memcpy(sfx_items, items, sizeof(*sfx_items)); 5821 sfx_items++; 5822 break; 5823 case RTE_FLOW_ITEM_TYPE_VLAN: 5824 /* 5825 * Copy VLAN items in case VLAN actions are performed. 5826 * If there are no VLAN actions, these items will be VOID. 5827 */ 5828 memcpy(sfx_items, items, sizeof(*sfx_items)); 5829 sfx_items->type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5830 sfx_items++; 5831 break; 5832 default: 5833 break; 5834 } 5835 } 5836 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5837 sfx_items++; 5838 mtr_first = priv->sh->meter_aso_en && 5839 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5840 /* For ASO meter, meter must be before tag in TX direction. */ 5841 if (mtr_first) { 5842 action_pre_head = actions_pre++; 5843 /* Leave space for tag action. */ 5844 tag_action = actions_pre++; 5845 } 5846 /* Prepare the actions for prefix and suffix flow. */ 5847 vlan_actions = false; 5848 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5849 struct rte_flow_action *action_cur = NULL; 5850 5851 switch (actions->type) { 5852 case RTE_FLOW_ACTION_TYPE_METER: 5853 if (mtr_first) { 5854 action_cur = action_pre_head; 5855 } else { 5856 /* Leave space for tag action. */ 5857 tag_action = actions_pre++; 5858 action_cur = actions_pre++; 5859 } 5860 after_meter = true; 5861 break; 5862 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5863 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5864 action_cur = actions_pre++; 5865 break; 5866 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5867 raw_encap = actions->conf; 5868 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5869 action_cur = actions_pre++; 5870 break; 5871 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5872 raw_decap = actions->conf; 5873 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5874 action_cur = actions_pre++; 5875 break; 5876 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5877 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5878 vlan_actions = true; 5879 break; 5880 case RTE_FLOW_ACTION_TYPE_COUNT: 5881 if (fm->def_policy) 5882 action_cur = after_meter ? 5883 actions_sfx++ : actions_pre++; 5884 break; 5885 default: 5886 break; 5887 } 5888 if (!action_cur) 5889 action_cur = (fm->def_policy) ? 5890 actions_sfx++ : actions_pre++; 5891 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5892 } 5893 /* If there are no VLAN actions, convert VLAN items to VOID in suffix flow items. */ 5894 if (!vlan_actions) { 5895 struct rte_flow_item *it = orig_sfx_items; 5896 5897 for (; it->type != RTE_FLOW_ITEM_TYPE_END; it++) 5898 if (it->type == (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_VLAN) 5899 it->type = RTE_FLOW_ITEM_TYPE_VOID; 5900 } 5901 /* Add end action to the actions. */ 5902 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5903 if (priv->sh->meter_aso_en) { 5904 /** 5905 * For ASO meter, need to add an extra jump action explicitly, 5906 * to jump from meter to policer table. 5907 */ 5908 struct mlx5_flow_meter_sub_policy *sub_policy; 5909 struct mlx5_flow_tbl_data_entry *tbl_data; 5910 5911 if (!fm->def_policy) { 5912 sub_policy = get_meter_sub_policy(dev, flow, wks, 5913 attr, orig_items, 5914 error); 5915 if (!sub_policy) 5916 return -rte_errno; 5917 } else { 5918 enum mlx5_meter_domain mtr_domain = 5919 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5920 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5921 MLX5_MTR_DOMAIN_INGRESS); 5922 5923 sub_policy = 5924 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5925 } 5926 tbl_data = container_of(sub_policy->tbl_rsc, 5927 struct mlx5_flow_tbl_data_entry, tbl); 5928 hw_mtr_action = actions_pre++; 5929 hw_mtr_action->type = (enum rte_flow_action_type) 5930 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5931 hw_mtr_action->conf = tbl_data->jump.action; 5932 } 5933 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5934 actions_pre++; 5935 if (!tag_action) 5936 return rte_flow_error_set(error, ENOMEM, 5937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5938 NULL, "No tag action space."); 5939 if (!mtr_flow_id) { 5940 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5941 goto exit; 5942 } 5943 /* Only default-policy Meter creates mtr flow id. */ 5944 if (fm->def_policy) { 5945 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5946 if (!tag_id) 5947 return rte_flow_error_set(error, ENOMEM, 5948 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5949 "Failed to allocate meter flow id."); 5950 flow_id = tag_id - 1; 5951 flow_id_bits = (!flow_id) ? 1 : 5952 (MLX5_REG_BITS - rte_clz32(flow_id)); 5953 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5954 mtr_reg_bits) { 5955 mlx5_ipool_free(fm->flow_ipool, tag_id); 5956 return rte_flow_error_set(error, EINVAL, 5957 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5958 "Meter flow id exceeds max limit."); 5959 } 5960 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5961 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5962 } 5963 /* Build tag actions and items for meter_id/meter flow_id. */ 5964 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 5965 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 5966 tag_item_mask = tag_item_spec + 1; 5967 /* Both flow_id and meter_id share the same register. */ 5968 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5969 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 5970 0, error), 5971 .offset = mtr_id_offset, 5972 .length = mtr_reg_bits, 5973 .data = flow->meter, 5974 }; 5975 /* 5976 * The color Reg bits used by flow_id are growing from 5977 * msb to lsb, so must do bit reverse for flow_id val in RegC. 5978 */ 5979 for (shift = 0; shift < flow_id_bits; shift++) 5980 flow_id_reversed = (flow_id_reversed << 1) | 5981 ((flow_id >> shift) & 0x1); 5982 set_tag->data |= 5983 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 5984 tag_item_spec->id = set_tag->id; 5985 tag_item_spec->data = set_tag->data << mtr_id_offset; 5986 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 5987 tag_action->type = (enum rte_flow_action_type) 5988 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5989 tag_action->conf = set_tag; 5990 tag_item->spec = tag_item_spec; 5991 tag_item->last = NULL; 5992 tag_item->mask = tag_item_mask; 5993 exit: 5994 if (mtr_flow_id) 5995 *mtr_flow_id = tag_id; 5996 return 0; 5997 } 5998 5999 /** 6000 * Split action list having QUEUE/RSS for metadata register copy. 6001 * 6002 * Once Q/RSS action is detected in user's action list, the flow action 6003 * should be split in order to copy metadata registers, which will happen in 6004 * RX_CP_TBL like, 6005 * - CQE->flow_tag := reg_c[1] (MARK) 6006 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 6007 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 6008 * This is because the last action of each flow must be a terminal action 6009 * (QUEUE, RSS or DROP). 6010 * 6011 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 6012 * stored and kept in the mlx5_flow structure per each sub_flow. 6013 * 6014 * The Q/RSS action is replaced with, 6015 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 6016 * And the following JUMP action is added at the end, 6017 * - JUMP, to RX_CP_TBL. 6018 * 6019 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 6020 * flow_create_split_metadata() routine. The flow will look like, 6021 * - If flow ID matches (reg_c[2]), perform Q/RSS. 6022 * 6023 * @param dev 6024 * Pointer to Ethernet device. 6025 * @param[out] split_actions 6026 * Pointer to store split actions to jump to CP_TBL. 6027 * @param[in] actions 6028 * Pointer to the list of original flow actions. 6029 * @param[in] qrss 6030 * Pointer to the Q/RSS action. 6031 * @param[in] actions_n 6032 * Number of original actions. 6033 * @param[in] mtr_sfx 6034 * Check if it is in meter suffix table. 6035 * @param[out] error 6036 * Perform verbose error reporting if not NULL. 6037 * 6038 * @return 6039 * non-zero unique flow_id on success, otherwise 0 and 6040 * error/rte_error are set. 6041 */ 6042 static uint32_t 6043 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 6044 struct rte_flow_action *split_actions, 6045 const struct rte_flow_action *actions, 6046 const struct rte_flow_action *qrss, 6047 int actions_n, int mtr_sfx, 6048 struct rte_flow_error *error) 6049 { 6050 struct mlx5_priv *priv = dev->data->dev_private; 6051 struct mlx5_rte_flow_action_set_tag *set_tag; 6052 struct rte_flow_action_jump *jump; 6053 const int qrss_idx = qrss - actions; 6054 uint32_t flow_id = 0; 6055 int ret = 0; 6056 6057 /* 6058 * Given actions will be split 6059 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 6060 * - Add jump to mreg CP_TBL. 6061 * As a result, there will be one more action. 6062 */ 6063 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 6064 /* Count MLX5_RTE_FLOW_ACTION_TYPE_TAG. */ 6065 ++actions_n; 6066 set_tag = (void *)(split_actions + actions_n); 6067 /* 6068 * If we are not the meter suffix flow, add the tag action. 6069 * Since meter suffix flow already has the tag added. 6070 */ 6071 if (!mtr_sfx) { 6072 /* 6073 * Allocate the new subflow ID. This one is unique within 6074 * device and not shared with representors. Otherwise, 6075 * we would have to resolve multi-thread access synch 6076 * issue. Each flow on the shared device is appended 6077 * with source vport identifier, so the resulting 6078 * flows will be unique in the shared (by master and 6079 * representors) domain even if they have coinciding 6080 * IDs. 6081 */ 6082 mlx5_ipool_malloc(priv->sh->ipool 6083 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 6084 if (!flow_id) 6085 return rte_flow_error_set(error, ENOMEM, 6086 RTE_FLOW_ERROR_TYPE_ACTION, 6087 NULL, "can't allocate id " 6088 "for split Q/RSS subflow"); 6089 /* Internal SET_TAG action to set flow ID. */ 6090 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 6091 .data = flow_id, 6092 }; 6093 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 6094 if (ret < 0) 6095 return ret; 6096 set_tag->id = ret; 6097 /* Construct new actions array. */ 6098 /* Replace QUEUE/RSS action. */ 6099 split_actions[qrss_idx] = (struct rte_flow_action){ 6100 .type = (enum rte_flow_action_type) 6101 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6102 .conf = set_tag, 6103 }; 6104 } else { 6105 /* 6106 * If we are the suffix flow of meter, tag already exist. 6107 * Set the QUEUE/RSS action to void. 6108 */ 6109 split_actions[qrss_idx].type = RTE_FLOW_ACTION_TYPE_VOID; 6110 } 6111 /* JUMP action to jump to mreg copy table (CP_TBL). */ 6112 jump = (void *)(set_tag + 1); 6113 *jump = (struct rte_flow_action_jump){ 6114 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 6115 }; 6116 split_actions[actions_n - 2] = (struct rte_flow_action){ 6117 .type = RTE_FLOW_ACTION_TYPE_JUMP, 6118 .conf = jump, 6119 }; 6120 split_actions[actions_n - 1] = (struct rte_flow_action){ 6121 .type = RTE_FLOW_ACTION_TYPE_END, 6122 }; 6123 return flow_id; 6124 } 6125 6126 /** 6127 * Extend the given action list for Tx metadata copy. 6128 * 6129 * Copy the given action list to the ext_actions and add flow metadata register 6130 * copy action in order to copy reg_a set by WQE to reg_c[0]. 6131 * 6132 * @param[out] ext_actions 6133 * Pointer to the extended action list. 6134 * @param[in] actions 6135 * Pointer to the list of actions. 6136 * @param[in] actions_n 6137 * Number of actions in the list. 6138 * @param[out] error 6139 * Perform verbose error reporting if not NULL. 6140 * @param[in] encap_idx 6141 * The encap action index. 6142 * 6143 * @return 6144 * 0 on success, negative value otherwise 6145 */ 6146 static int 6147 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 6148 struct rte_flow_action *ext_actions, 6149 const struct rte_flow_action *actions, 6150 int actions_n, struct rte_flow_error *error, 6151 int encap_idx) 6152 { 6153 struct mlx5_flow_action_copy_mreg *cp_mreg = 6154 (struct mlx5_flow_action_copy_mreg *) 6155 (ext_actions + actions_n + 1); 6156 int ret; 6157 6158 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 6159 if (ret < 0) 6160 return ret; 6161 cp_mreg->dst = ret; 6162 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 6163 if (ret < 0) 6164 return ret; 6165 cp_mreg->src = ret; 6166 if (encap_idx != 0) 6167 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 6168 if (encap_idx == actions_n - 1) { 6169 ext_actions[actions_n - 1] = (struct rte_flow_action){ 6170 .type = (enum rte_flow_action_type) 6171 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6172 .conf = cp_mreg, 6173 }; 6174 ext_actions[actions_n] = (struct rte_flow_action){ 6175 .type = RTE_FLOW_ACTION_TYPE_END, 6176 }; 6177 } else { 6178 ext_actions[encap_idx] = (struct rte_flow_action){ 6179 .type = (enum rte_flow_action_type) 6180 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6181 .conf = cp_mreg, 6182 }; 6183 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 6184 sizeof(*ext_actions) * (actions_n - encap_idx)); 6185 } 6186 return 0; 6187 } 6188 6189 /** 6190 * Check the match action from the action list. 6191 * 6192 * @param[in] actions 6193 * Pointer to the list of actions. 6194 * @param[in] attr 6195 * Flow rule attributes. 6196 * @param[in] action 6197 * The action to be check if exist. 6198 * @param[out] match_action_pos 6199 * Pointer to the position of the matched action if exists, otherwise is -1. 6200 * @param[out] qrss_action_pos 6201 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 6202 * @param[out] modify_after_mirror 6203 * Pointer to the flag of modify action after FDB mirroring. 6204 * 6205 * @return 6206 * > 0 the total number of actions. 6207 * 0 if not found match action in action list. 6208 */ 6209 static int 6210 flow_check_match_action(const struct rte_flow_action actions[], 6211 const struct rte_flow_attr *attr, 6212 enum rte_flow_action_type action, 6213 int *match_action_pos, int *qrss_action_pos, 6214 int *modify_after_mirror) 6215 { 6216 const struct rte_flow_action_sample *sample; 6217 const struct rte_flow_action_raw_decap *decap; 6218 const struct rte_flow_action *action_cur = NULL; 6219 int actions_n = 0; 6220 uint32_t ratio = 0; 6221 int sub_type = 0; 6222 int flag = 0; 6223 int fdb_mirror = 0; 6224 6225 *match_action_pos = -1; 6226 *qrss_action_pos = -1; 6227 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 6228 if (actions->type == action) { 6229 flag = 1; 6230 *match_action_pos = actions_n; 6231 } 6232 switch (actions->type) { 6233 case RTE_FLOW_ACTION_TYPE_QUEUE: 6234 case RTE_FLOW_ACTION_TYPE_RSS: 6235 *qrss_action_pos = actions_n; 6236 break; 6237 case RTE_FLOW_ACTION_TYPE_SAMPLE: 6238 sample = actions->conf; 6239 ratio = sample->ratio; 6240 sub_type = ((const struct rte_flow_action *) 6241 (sample->actions))->type; 6242 if (ratio == 1 && attr->transfer && 6243 sub_type != RTE_FLOW_ACTION_TYPE_END) 6244 fdb_mirror = 1; 6245 break; 6246 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 6247 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 6248 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 6249 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 6250 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 6251 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 6252 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 6253 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 6254 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 6255 case RTE_FLOW_ACTION_TYPE_SET_TTL: 6256 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 6257 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 6258 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 6259 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 6260 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 6261 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 6262 case RTE_FLOW_ACTION_TYPE_FLAG: 6263 case RTE_FLOW_ACTION_TYPE_MARK: 6264 case RTE_FLOW_ACTION_TYPE_SET_META: 6265 case RTE_FLOW_ACTION_TYPE_SET_TAG: 6266 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 6267 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6268 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6269 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 6270 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 6271 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 6272 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 6273 case RTE_FLOW_ACTION_TYPE_METER: 6274 if (fdb_mirror) 6275 *modify_after_mirror = 1; 6276 break; 6277 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6278 decap = actions->conf; 6279 action_cur = actions; 6280 while ((++action_cur)->type == RTE_FLOW_ACTION_TYPE_VOID) 6281 ; 6282 if (action_cur->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 6283 const struct rte_flow_action_raw_encap *encap = 6284 action_cur->conf; 6285 if (decap->size <= 6286 MLX5_ENCAPSULATION_DECISION_SIZE && 6287 encap->size > 6288 MLX5_ENCAPSULATION_DECISION_SIZE) 6289 /* L3 encap. */ 6290 break; 6291 } 6292 if (fdb_mirror) 6293 *modify_after_mirror = 1; 6294 break; 6295 default: 6296 break; 6297 } 6298 actions_n++; 6299 } 6300 if (flag && fdb_mirror && !*modify_after_mirror) { 6301 /* FDB mirroring uses the destination array to implement 6302 * instead of FLOW_SAMPLER object. 6303 */ 6304 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 6305 flag = 0; 6306 } 6307 /* Count RTE_FLOW_ACTION_TYPE_END. */ 6308 return flag ? actions_n + 1 : 0; 6309 } 6310 6311 #define SAMPLE_SUFFIX_ITEM 3 6312 6313 /** 6314 * Split the sample flow. 6315 * 6316 * As sample flow will split to two sub flow, sample flow with 6317 * sample action, the other actions will move to new suffix flow. 6318 * 6319 * Also add unique tag id with tag action in the sample flow, 6320 * the same tag id will be as match in the suffix flow. 6321 * 6322 * @param dev 6323 * Pointer to Ethernet device. 6324 * @param[in] add_tag 6325 * Add extra tag action flag. 6326 * @param[out] sfx_items 6327 * Suffix flow match items (list terminated by the END pattern item). 6328 * @param[in] actions 6329 * Associated actions (list terminated by the END action). 6330 * @param[out] actions_sfx 6331 * Suffix flow actions. 6332 * @param[out] actions_pre 6333 * Prefix flow actions. 6334 * @param[in] actions_n 6335 * The total number of actions. 6336 * @param[in] sample_action_pos 6337 * The sample action position. 6338 * @param[in] qrss_action_pos 6339 * The Queue/RSS action position. 6340 * @param[in] jump_table 6341 * Add extra jump action flag. 6342 * @param[out] error 6343 * Perform verbose error reporting if not NULL. 6344 * 6345 * @return 6346 * 0 on success, or unique flow_id, a negative errno value 6347 * otherwise and rte_errno is set. 6348 */ 6349 static int 6350 flow_sample_split_prep(struct rte_eth_dev *dev, 6351 int add_tag, 6352 const struct rte_flow_item items[], 6353 struct rte_flow_item sfx_items[], 6354 const struct rte_flow_action actions[], 6355 struct rte_flow_action actions_sfx[], 6356 struct rte_flow_action actions_pre[], 6357 int actions_n, 6358 int sample_action_pos, 6359 int qrss_action_pos, 6360 int jump_table, 6361 struct rte_flow_error *error) 6362 { 6363 struct mlx5_priv *priv = dev->data->dev_private; 6364 struct mlx5_rte_flow_action_set_tag *set_tag; 6365 struct mlx5_rte_flow_item_tag *tag_spec; 6366 struct mlx5_rte_flow_item_tag *tag_mask; 6367 struct rte_flow_action_jump *jump_action; 6368 uint32_t tag_id = 0; 6369 int append_index = 0; 6370 int set_tag_idx = -1; 6371 int index; 6372 int ret; 6373 6374 if (sample_action_pos < 0) 6375 return rte_flow_error_set(error, EINVAL, 6376 RTE_FLOW_ERROR_TYPE_ACTION, 6377 NULL, "invalid position of sample " 6378 "action in list"); 6379 /* Prepare the actions for prefix and suffix flow. */ 6380 if (add_tag) { 6381 /* Update the new added tag action index preceding 6382 * the PUSH_VLAN or ENCAP action. 6383 */ 6384 const struct rte_flow_action_raw_encap *raw_encap; 6385 const struct rte_flow_action *action = actions; 6386 int encap_idx; 6387 int action_idx = 0; 6388 int raw_decap_idx = -1; 6389 int push_vlan_idx = -1; 6390 for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { 6391 switch (action->type) { 6392 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6393 raw_decap_idx = action_idx; 6394 break; 6395 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 6396 raw_encap = action->conf; 6397 if (raw_encap->size > 6398 MLX5_ENCAPSULATION_DECISION_SIZE) { 6399 encap_idx = raw_decap_idx != -1 ? 6400 raw_decap_idx : action_idx; 6401 if (encap_idx < sample_action_pos && 6402 push_vlan_idx == -1) 6403 set_tag_idx = encap_idx; 6404 } 6405 break; 6406 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 6407 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 6408 encap_idx = action_idx; 6409 if (encap_idx < sample_action_pos && 6410 push_vlan_idx == -1) 6411 set_tag_idx = encap_idx; 6412 break; 6413 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6414 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6415 if (action_idx < sample_action_pos && 6416 push_vlan_idx == -1) { 6417 set_tag_idx = action_idx; 6418 push_vlan_idx = action_idx; 6419 } 6420 break; 6421 default: 6422 break; 6423 } 6424 action_idx++; 6425 } 6426 } 6427 /* Prepare the actions for prefix and suffix flow. */ 6428 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 6429 index = qrss_action_pos; 6430 /* Put the preceding the Queue/RSS action into prefix flow. */ 6431 if (index != 0) 6432 memcpy(actions_pre, actions, 6433 sizeof(struct rte_flow_action) * index); 6434 /* Put others preceding the sample action into prefix flow. */ 6435 if (sample_action_pos > index + 1) 6436 memcpy(actions_pre + index, actions + index + 1, 6437 sizeof(struct rte_flow_action) * 6438 (sample_action_pos - index - 1)); 6439 index = sample_action_pos - 1; 6440 /* Put Queue/RSS action into Suffix flow. */ 6441 memcpy(actions_sfx, actions + qrss_action_pos, 6442 sizeof(struct rte_flow_action)); 6443 actions_sfx++; 6444 } else if (add_tag && set_tag_idx >= 0) { 6445 if (set_tag_idx > 0) 6446 memcpy(actions_pre, actions, 6447 sizeof(struct rte_flow_action) * set_tag_idx); 6448 memcpy(actions_pre + set_tag_idx + 1, actions + set_tag_idx, 6449 sizeof(struct rte_flow_action) * 6450 (sample_action_pos - set_tag_idx)); 6451 index = sample_action_pos; 6452 } else { 6453 index = sample_action_pos; 6454 if (index != 0) 6455 memcpy(actions_pre, actions, 6456 sizeof(struct rte_flow_action) * index); 6457 } 6458 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 6459 * For CX6DX and above, metadata registers Cx preserve their value, 6460 * add an extra tag action for NIC-RX and E-Switch Domain. 6461 */ 6462 if (add_tag) { 6463 /* Prepare the prefix tag action. */ 6464 append_index++; 6465 set_tag = (void *)(actions_pre + actions_n + append_index); 6466 /* Trust VF/SF on CX5 not supported meter so that the reserved 6467 * metadata regC is REG_NON, back to use application tag 6468 * index 0. 6469 */ 6470 if (unlikely(priv->sh->registers.aso_reg == REG_NON)) 6471 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 6472 else 6473 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 6474 if (ret < 0) 6475 return ret; 6476 mlx5_ipool_malloc(priv->sh->ipool 6477 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 6478 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 6479 .id = ret, 6480 .data = tag_id, 6481 }; 6482 /* Prepare the suffix subflow items. */ 6483 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 6484 tag_spec->data = tag_id; 6485 tag_spec->id = set_tag->id; 6486 tag_mask = tag_spec + 1; 6487 tag_mask->data = UINT32_MAX; 6488 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 6489 if (items->type == RTE_FLOW_ITEM_TYPE_PORT_ID || 6490 items->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || 6491 items->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6492 memcpy(sfx_items, items, sizeof(*sfx_items)); 6493 sfx_items++; 6494 break; 6495 } 6496 } 6497 sfx_items[0] = (struct rte_flow_item){ 6498 .type = (enum rte_flow_item_type) 6499 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6500 .spec = tag_spec, 6501 .last = NULL, 6502 .mask = tag_mask, 6503 }; 6504 sfx_items[1] = (struct rte_flow_item){ 6505 .type = (enum rte_flow_item_type) 6506 RTE_FLOW_ITEM_TYPE_END, 6507 }; 6508 /* Prepare the tag action in prefix subflow. */ 6509 set_tag_idx = (set_tag_idx == -1) ? index : set_tag_idx; 6510 actions_pre[set_tag_idx] = 6511 (struct rte_flow_action){ 6512 .type = (enum rte_flow_action_type) 6513 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6514 .conf = set_tag, 6515 }; 6516 /* Update next sample position due to add one tag action */ 6517 index += 1; 6518 } 6519 /* Copy the sample action into prefix flow. */ 6520 memcpy(actions_pre + index, actions + sample_action_pos, 6521 sizeof(struct rte_flow_action)); 6522 index += 1; 6523 /* For the modify action after the sample action in E-Switch mirroring, 6524 * Add the extra jump action in prefix subflow and jump into the next 6525 * table, then do the modify action in the new table. 6526 */ 6527 if (jump_table) { 6528 /* Prepare the prefix jump action. */ 6529 append_index++; 6530 jump_action = (void *)(actions_pre + actions_n + append_index); 6531 jump_action->group = jump_table; 6532 actions_pre[index++] = 6533 (struct rte_flow_action){ 6534 .type = (enum rte_flow_action_type) 6535 RTE_FLOW_ACTION_TYPE_JUMP, 6536 .conf = jump_action, 6537 }; 6538 } 6539 actions_pre[index] = (struct rte_flow_action){ 6540 .type = (enum rte_flow_action_type) 6541 RTE_FLOW_ACTION_TYPE_END, 6542 }; 6543 /* Put the actions after sample into Suffix flow. */ 6544 memcpy(actions_sfx, actions + sample_action_pos + 1, 6545 sizeof(struct rte_flow_action) * 6546 (actions_n - sample_action_pos - 1)); 6547 return tag_id; 6548 } 6549 6550 /** 6551 * The splitting for metadata feature. 6552 * 6553 * - Q/RSS action on NIC Rx should be split in order to pass by 6554 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6555 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6556 * 6557 * - All the actions on NIC Tx should have a mreg copy action to 6558 * copy reg_a from WQE to reg_c[0]. 6559 * 6560 * @param dev 6561 * Pointer to Ethernet device. 6562 * @param[in] flow 6563 * Parent flow structure pointer. 6564 * @param[in] attr 6565 * Flow rule attributes. 6566 * @param[in] items 6567 * Pattern specification (list terminated by the END pattern item). 6568 * @param[in] actions 6569 * Associated actions (list terminated by the END action). 6570 * @param[in] flow_split_info 6571 * Pointer to flow split info structure. 6572 * @param[out] error 6573 * Perform verbose error reporting if not NULL. 6574 * @return 6575 * 0 on success, negative value otherwise 6576 */ 6577 static int 6578 flow_create_split_metadata(struct rte_eth_dev *dev, 6579 struct rte_flow *flow, 6580 const struct rte_flow_attr *attr, 6581 const struct rte_flow_item items[], 6582 const struct rte_flow_action actions[], 6583 struct mlx5_flow_split_info *flow_split_info, 6584 struct rte_flow_error *error) 6585 { 6586 struct mlx5_priv *priv = dev->data->dev_private; 6587 struct mlx5_sh_config *config = &priv->sh->config; 6588 const struct rte_flow_action *qrss = NULL; 6589 struct rte_flow_action *ext_actions = NULL; 6590 struct mlx5_flow *dev_flow = NULL; 6591 uint32_t qrss_id = 0; 6592 int mtr_sfx = 0; 6593 size_t act_size; 6594 int actions_n; 6595 int encap_idx; 6596 int ret; 6597 6598 /* Check whether extensive metadata feature is engaged. */ 6599 if (!config->dv_flow_en || 6600 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 6601 !mlx5_flow_ext_mreg_supported(dev)) 6602 return flow_create_split_inner(dev, flow, NULL, attr, items, 6603 actions, flow_split_info, error); 6604 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 6605 &encap_idx); 6606 if (qrss) { 6607 /* Exclude hairpin flows from splitting. */ 6608 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 6609 const struct rte_flow_action_queue *queue; 6610 6611 queue = qrss->conf; 6612 if (mlx5_rxq_is_hairpin(dev, queue->index)) 6613 qrss = NULL; 6614 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 6615 const struct rte_flow_action_rss *rss; 6616 6617 rss = qrss->conf; 6618 if (mlx5_rxq_is_hairpin(dev, rss->queue[0])) 6619 qrss = NULL; 6620 } 6621 } 6622 if (qrss) { 6623 /* Check if it is in meter suffix table. */ 6624 mtr_sfx = attr->group == 6625 ((attr->transfer && priv->fdb_def_rule) ? 6626 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6627 MLX5_FLOW_TABLE_LEVEL_METER); 6628 /* 6629 * Q/RSS action on NIC Rx should be split in order to pass by 6630 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6631 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6632 */ 6633 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6634 sizeof(struct rte_flow_action_set_tag) + 6635 sizeof(struct rte_flow_action_jump); 6636 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6637 SOCKET_ID_ANY); 6638 if (!ext_actions) 6639 return rte_flow_error_set(error, ENOMEM, 6640 RTE_FLOW_ERROR_TYPE_ACTION, 6641 NULL, "no memory to split " 6642 "metadata flow"); 6643 /* 6644 * Create the new actions list with removed Q/RSS action 6645 * and appended set tag and jump to register copy table 6646 * (RX_CP_TBL). We should preallocate unique tag ID here 6647 * in advance, because it is needed for set tag action. 6648 */ 6649 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 6650 qrss, actions_n, 6651 mtr_sfx, error); 6652 if (!mtr_sfx && !qrss_id) { 6653 ret = -rte_errno; 6654 goto exit; 6655 } 6656 } else if (attr->egress) { 6657 /* 6658 * All the actions on NIC Tx should have a metadata register 6659 * copy action to copy reg_a from WQE to reg_c[meta] 6660 */ 6661 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6662 sizeof(struct mlx5_flow_action_copy_mreg); 6663 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6664 SOCKET_ID_ANY); 6665 if (!ext_actions) 6666 return rte_flow_error_set(error, ENOMEM, 6667 RTE_FLOW_ERROR_TYPE_ACTION, 6668 NULL, "no memory to split " 6669 "metadata flow"); 6670 /* Create the action list appended with copy register. */ 6671 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 6672 actions_n, error, encap_idx); 6673 if (ret < 0) 6674 goto exit; 6675 } 6676 /* Add the unmodified original or prefix subflow. */ 6677 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6678 items, ext_actions ? ext_actions : 6679 actions, flow_split_info, error); 6680 if (ret < 0) 6681 goto exit; 6682 MLX5_ASSERT(dev_flow); 6683 if (qrss) { 6684 const struct rte_flow_attr q_attr = { 6685 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 6686 .ingress = 1, 6687 }; 6688 /* Internal PMD action to set register. */ 6689 struct mlx5_rte_flow_item_tag q_tag_spec = { 6690 .data = qrss_id, 6691 .id = REG_NON, 6692 }; 6693 struct rte_flow_item q_items[] = { 6694 { 6695 .type = (enum rte_flow_item_type) 6696 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6697 .spec = &q_tag_spec, 6698 .last = NULL, 6699 .mask = NULL, 6700 }, 6701 { 6702 .type = RTE_FLOW_ITEM_TYPE_END, 6703 }, 6704 }; 6705 struct rte_flow_action q_actions[] = { 6706 { 6707 .type = qrss->type, 6708 .conf = qrss->conf, 6709 }, 6710 { 6711 .type = RTE_FLOW_ACTION_TYPE_END, 6712 }, 6713 }; 6714 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 6715 6716 /* 6717 * Configure the tag item only if there is no meter subflow. 6718 * Since tag is already marked in the meter suffix subflow 6719 * we can just use the meter suffix items as is. 6720 */ 6721 if (qrss_id) { 6722 /* Not meter subflow. */ 6723 MLX5_ASSERT(!mtr_sfx); 6724 /* 6725 * Put unique id in prefix flow due to it is destroyed 6726 * after suffix flow and id will be freed after there 6727 * is no actual flows with this id and identifier 6728 * reallocation becomes possible (for example, for 6729 * other flows in other threads). 6730 */ 6731 dev_flow->handle->split_flow_id = qrss_id; 6732 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 6733 error); 6734 if (ret < 0) 6735 goto exit; 6736 q_tag_spec.id = ret; 6737 } 6738 dev_flow = NULL; 6739 /* Add suffix subflow to execute Q/RSS. */ 6740 flow_split_info->prefix_layers = layers; 6741 flow_split_info->prefix_mark = 0; 6742 flow_split_info->table_id = 0; 6743 ret = flow_create_split_inner(dev, flow, &dev_flow, 6744 &q_attr, mtr_sfx ? items : 6745 q_items, q_actions, 6746 flow_split_info, error); 6747 if (ret < 0) 6748 goto exit; 6749 /* qrss ID should be freed if failed. */ 6750 qrss_id = 0; 6751 MLX5_ASSERT(dev_flow); 6752 } 6753 6754 exit: 6755 /* 6756 * We do not destroy the partially created sub_flows in case of error. 6757 * These ones are included into parent flow list and will be destroyed 6758 * by flow_drv_destroy. 6759 */ 6760 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 6761 qrss_id); 6762 mlx5_free(ext_actions); 6763 return ret; 6764 } 6765 6766 /** 6767 * Create meter internal drop flow with the original pattern. 6768 * 6769 * @param dev 6770 * Pointer to Ethernet device. 6771 * @param[in] flow 6772 * Parent flow structure pointer. 6773 * @param[in] attr 6774 * Flow rule attributes. 6775 * @param[in] items 6776 * Pattern specification (list terminated by the END pattern item). 6777 * @param[in] flow_split_info 6778 * Pointer to flow split info structure. 6779 * @param[in] fm 6780 * Pointer to flow meter structure. 6781 * @param[out] error 6782 * Perform verbose error reporting if not NULL. 6783 * @return 6784 * 0 on success, negative value otherwise 6785 */ 6786 static uint32_t 6787 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 6788 struct rte_flow *flow, 6789 const struct rte_flow_attr *attr, 6790 const struct rte_flow_item items[], 6791 struct mlx5_flow_split_info *flow_split_info, 6792 struct mlx5_flow_meter_info *fm, 6793 struct rte_flow_error *error) 6794 { 6795 struct mlx5_flow *dev_flow = NULL; 6796 struct rte_flow_attr drop_attr = *attr; 6797 struct rte_flow_action drop_actions[3]; 6798 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 6799 6800 MLX5_ASSERT(fm->drop_cnt); 6801 drop_actions[0].type = 6802 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 6803 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 6804 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 6805 drop_actions[1].conf = NULL; 6806 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 6807 drop_actions[2].conf = NULL; 6808 drop_split_info.external = false; 6809 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6810 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 6811 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 6812 return flow_create_split_inner(dev, flow, &dev_flow, 6813 &drop_attr, items, drop_actions, 6814 &drop_split_info, error); 6815 } 6816 6817 static int 6818 flow_count_vlan_items(const struct rte_flow_item items[]) 6819 { 6820 int items_n = 0; 6821 6822 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 6823 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN || 6824 items->type == (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_VLAN) 6825 items_n++; 6826 } 6827 return items_n; 6828 } 6829 6830 /** 6831 * The splitting for meter feature. 6832 * 6833 * - The meter flow will be split to two flows as prefix and 6834 * suffix flow. The packets make sense only it pass the prefix 6835 * meter action. 6836 * 6837 * - Reg_C_5 is used for the packet to match betweend prefix and 6838 * suffix flow. 6839 * 6840 * @param dev 6841 * Pointer to Ethernet device. 6842 * @param[in] flow 6843 * Parent flow structure pointer. 6844 * @param[in] attr 6845 * Flow rule attributes. 6846 * @param[in] items 6847 * Pattern specification (list terminated by the END pattern item). 6848 * @param[in] actions 6849 * Associated actions (list terminated by the END action). 6850 * @param[in] flow_split_info 6851 * Pointer to flow split info structure. 6852 * @param[out] error 6853 * Perform verbose error reporting if not NULL. 6854 * @return 6855 * 0 on success, negative value otherwise 6856 */ 6857 static int 6858 flow_create_split_meter(struct rte_eth_dev *dev, 6859 struct rte_flow *flow, 6860 const struct rte_flow_attr *attr, 6861 const struct rte_flow_item items[], 6862 const struct rte_flow_action actions[], 6863 struct mlx5_flow_split_info *flow_split_info, 6864 struct rte_flow_error *error) 6865 { 6866 struct mlx5_priv *priv = dev->data->dev_private; 6867 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6868 struct rte_flow_action *sfx_actions = NULL; 6869 struct rte_flow_action *pre_actions = NULL; 6870 struct rte_flow_item *sfx_items = NULL; 6871 struct mlx5_flow *dev_flow = NULL; 6872 struct rte_flow_attr sfx_attr = *attr; 6873 struct mlx5_flow_meter_info *fm = NULL; 6874 uint8_t skip_scale_restore; 6875 bool has_mtr = false; 6876 bool has_modify = false; 6877 bool set_mtr_reg = true; 6878 bool is_mtr_hierarchy = false; 6879 uint32_t meter_id = 0; 6880 uint32_t mtr_idx = 0; 6881 uint32_t mtr_flow_id = 0; 6882 size_t act_size; 6883 size_t item_size; 6884 int actions_n = 0; 6885 int vlan_items_n = 0; 6886 int ret = 0; 6887 6888 if (priv->mtr_en) 6889 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6890 &has_modify, &meter_id); 6891 if (has_mtr) { 6892 if (flow->meter) { 6893 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6894 if (!fm) 6895 return rte_flow_error_set(error, EINVAL, 6896 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6897 NULL, "Meter not found."); 6898 } else { 6899 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6900 if (!fm) 6901 return rte_flow_error_set(error, EINVAL, 6902 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6903 NULL, "Meter not found."); 6904 ret = mlx5_flow_meter_attach(priv, fm, 6905 &sfx_attr, error); 6906 if (ret) 6907 return -rte_errno; 6908 flow->meter = mtr_idx; 6909 } 6910 MLX5_ASSERT(wks); 6911 wks->fm = fm; 6912 if (!fm->def_policy) { 6913 wks->policy = mlx5_flow_meter_policy_find(dev, 6914 fm->policy_id, 6915 NULL); 6916 MLX5_ASSERT(wks->policy); 6917 if (wks->policy->mark) 6918 wks->mark = 1; 6919 if (wks->policy->is_hierarchy) { 6920 wks->final_policy = 6921 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6922 wks->policy); 6923 if (!wks->final_policy) 6924 return rte_flow_error_set(error, 6925 EINVAL, 6926 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6927 "Failed to find terminal policy of hierarchy."); 6928 is_mtr_hierarchy = true; 6929 } 6930 } 6931 /* 6932 * If it isn't default-policy Meter, and 6933 * 1. Not meter hierarchy and there's no action in flow to change 6934 * packet (modify/encap/decap etc.), OR 6935 * 2. No drop count needed for this meter. 6936 * Then no need to use regC to save meter id anymore. 6937 */ 6938 if (!fm->def_policy && ((!has_modify && !is_mtr_hierarchy) || !fm->drop_cnt)) 6939 set_mtr_reg = false; 6940 /* Prefix actions: meter, decap, encap, tag, jump, end, cnt. */ 6941 #define METER_PREFIX_ACTION 7 6942 act_size = (sizeof(struct rte_flow_action) * 6943 (actions_n + METER_PREFIX_ACTION)) + 6944 sizeof(struct mlx5_rte_flow_action_set_tag); 6945 /* Flow can have multiple VLAN items. Account for them in suffix items. */ 6946 vlan_items_n = flow_count_vlan_items(items); 6947 /* Suffix items: tag, [vlans], port id, end. */ 6948 #define METER_SUFFIX_ITEM 3 6949 item_size = sizeof(struct rte_flow_item) * (METER_SUFFIX_ITEM + vlan_items_n) + 6950 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6951 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6952 0, SOCKET_ID_ANY); 6953 if (!sfx_actions) 6954 return rte_flow_error_set(error, ENOMEM, 6955 RTE_FLOW_ERROR_TYPE_ACTION, 6956 NULL, "no memory to split " 6957 "meter flow"); 6958 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6959 act_size); 6960 /* There's no suffix flow for meter of non-default policy. */ 6961 if (!fm->def_policy) 6962 pre_actions = sfx_actions + 1; 6963 else 6964 pre_actions = sfx_actions + actions_n; 6965 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6966 items, sfx_items, actions, 6967 sfx_actions, pre_actions, 6968 (set_mtr_reg ? &mtr_flow_id : NULL), 6969 error); 6970 if (ret) { 6971 ret = -rte_errno; 6972 goto exit; 6973 } 6974 /* Add the prefix subflow. */ 6975 skip_scale_restore = flow_split_info->skip_scale; 6976 flow_split_info->skip_scale |= 6977 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6978 ret = flow_create_split_inner(dev, flow, &dev_flow, 6979 attr, items, pre_actions, 6980 flow_split_info, error); 6981 flow_split_info->skip_scale = skip_scale_restore; 6982 if (ret) { 6983 if (mtr_flow_id) 6984 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 6985 ret = -rte_errno; 6986 goto exit; 6987 } 6988 if (mtr_flow_id) { 6989 dev_flow->handle->split_flow_id = mtr_flow_id; 6990 dev_flow->handle->is_meter_flow_id = 1; 6991 } 6992 if (!fm->def_policy) { 6993 if (!set_mtr_reg && fm->drop_cnt) 6994 ret = 6995 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 6996 &sfx_attr, items, 6997 flow_split_info, 6998 fm, error); 6999 goto exit; 7000 } 7001 /* Setting the sfx group atrr. */ 7002 sfx_attr.group = sfx_attr.transfer ? 7003 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 7004 MLX5_FLOW_TABLE_LEVEL_METER; 7005 flow_split_info->prefix_layers = 7006 flow_get_prefix_layer_flags(dev_flow); 7007 flow_split_info->prefix_mark |= wks->mark; 7008 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 7009 } 7010 /* Add the prefix subflow. */ 7011 ret = flow_create_split_metadata(dev, flow, 7012 &sfx_attr, sfx_items ? 7013 sfx_items : items, 7014 sfx_actions ? sfx_actions : actions, 7015 flow_split_info, error); 7016 exit: 7017 if (sfx_actions) 7018 mlx5_free(sfx_actions); 7019 return ret; 7020 } 7021 7022 /** 7023 * The splitting for sample feature. 7024 * 7025 * Once Sample action is detected in the action list, the flow actions should 7026 * be split into prefix sub flow and suffix sub flow. 7027 * 7028 * The original items remain in the prefix sub flow, all actions preceding the 7029 * sample action and the sample action itself will be copied to the prefix 7030 * sub flow, the actions following the sample action will be copied to the 7031 * suffix sub flow, Queue action always be located in the suffix sub flow. 7032 * 7033 * In order to make the packet from prefix sub flow matches with suffix sub 7034 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 7035 * flow uses tag item with the unique flow id. 7036 * 7037 * @param dev 7038 * Pointer to Ethernet device. 7039 * @param[in] flow 7040 * Parent flow structure pointer. 7041 * @param[in] attr 7042 * Flow rule attributes. 7043 * @param[in] items 7044 * Pattern specification (list terminated by the END pattern item). 7045 * @param[in] actions 7046 * Associated actions (list terminated by the END action). 7047 * @param[in] flow_split_info 7048 * Pointer to flow split info structure. 7049 * @param[out] error 7050 * Perform verbose error reporting if not NULL. 7051 * @return 7052 * 0 on success, negative value otherwise 7053 */ 7054 static int 7055 flow_create_split_sample(struct rte_eth_dev *dev, 7056 struct rte_flow *flow, 7057 const struct rte_flow_attr *attr, 7058 const struct rte_flow_item items[], 7059 const struct rte_flow_action actions[], 7060 struct mlx5_flow_split_info *flow_split_info, 7061 struct rte_flow_error *error) 7062 { 7063 struct mlx5_priv *priv = dev->data->dev_private; 7064 struct rte_flow_action *sfx_actions = NULL; 7065 struct rte_flow_action *pre_actions = NULL; 7066 struct rte_flow_item *sfx_items = NULL; 7067 struct mlx5_flow *dev_flow = NULL; 7068 struct rte_flow_attr sfx_attr = *attr; 7069 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7070 struct mlx5_flow_dv_sample_resource *sample_res; 7071 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 7072 struct mlx5_flow_tbl_resource *sfx_tbl; 7073 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 7074 #endif 7075 size_t act_size; 7076 size_t item_size; 7077 uint32_t fdb_tx = 0; 7078 int32_t tag_id = 0; 7079 int actions_n = 0; 7080 int sample_action_pos; 7081 int qrss_action_pos; 7082 int add_tag = 0; 7083 int modify_after_mirror = 0; 7084 uint16_t jump_table = 0; 7085 const uint32_t next_ft_step = 1; 7086 int ret = 0; 7087 struct mlx5_priv *item_port_priv = NULL; 7088 const struct rte_flow_item *item; 7089 7090 if (priv->sampler_en) 7091 actions_n = flow_check_match_action(actions, attr, 7092 RTE_FLOW_ACTION_TYPE_SAMPLE, 7093 &sample_action_pos, &qrss_action_pos, 7094 &modify_after_mirror); 7095 if (actions_n) { 7096 /* The prefix actions must includes sample, tag, end. */ 7097 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 7098 + sizeof(struct mlx5_rte_flow_action_set_tag); 7099 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 7100 sizeof(struct mlx5_rte_flow_item_tag) * 2; 7101 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 7102 item_size), 0, SOCKET_ID_ANY); 7103 if (!sfx_actions) 7104 return rte_flow_error_set(error, ENOMEM, 7105 RTE_FLOW_ERROR_TYPE_ACTION, 7106 NULL, "no memory to split " 7107 "sample flow"); 7108 for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 7109 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_ID) { 7110 const struct rte_flow_item_port_id *spec; 7111 7112 spec = (const struct rte_flow_item_port_id *)item->spec; 7113 if (spec) 7114 item_port_priv = 7115 mlx5_port_to_eswitch_info(spec->id, true); 7116 break; 7117 } else if (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 7118 const struct rte_flow_item_ethdev *spec; 7119 7120 spec = (const struct rte_flow_item_ethdev *)item->spec; 7121 if (spec) 7122 item_port_priv = 7123 mlx5_port_to_eswitch_info(spec->port_id, true); 7124 break; 7125 } else if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 7126 const struct rte_flow_item_ethdev *spec; 7127 7128 spec = (const struct rte_flow_item_ethdev *)item->spec; 7129 if (spec) 7130 item_port_priv = 7131 mlx5_port_to_eswitch_info(spec->port_id, true); 7132 break; 7133 } 7134 } 7135 /* The representor_id is UINT16_MAX for uplink. */ 7136 fdb_tx = (attr->transfer && 7137 flow_source_vport_representor(priv, item_port_priv)); 7138 /* 7139 * When reg_c_preserve is set, metadata registers Cx preserve 7140 * their value even through packet duplication. 7141 */ 7142 add_tag = (!fdb_tx || 7143 priv->sh->cdev->config.hca_attr.reg_c_preserve); 7144 if (add_tag) 7145 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 7146 + act_size); 7147 if (modify_after_mirror) 7148 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 7149 next_ft_step; 7150 pre_actions = sfx_actions + actions_n; 7151 tag_id = flow_sample_split_prep(dev, add_tag, items, sfx_items, 7152 actions, sfx_actions, 7153 pre_actions, actions_n, 7154 sample_action_pos, 7155 qrss_action_pos, jump_table, 7156 error); 7157 if (tag_id < 0 || (add_tag && !tag_id)) { 7158 ret = -rte_errno; 7159 goto exit; 7160 } 7161 if (modify_after_mirror) 7162 flow_split_info->skip_scale = 7163 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 7164 /* Add the prefix subflow. */ 7165 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 7166 items, pre_actions, 7167 flow_split_info, error); 7168 if (ret) { 7169 ret = -rte_errno; 7170 goto exit; 7171 } 7172 dev_flow->handle->split_flow_id = tag_id; 7173 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7174 if (!modify_after_mirror) { 7175 /* Set the sfx group attr. */ 7176 sample_res = (struct mlx5_flow_dv_sample_resource *) 7177 dev_flow->dv.sample_res; 7178 sfx_tbl = (struct mlx5_flow_tbl_resource *) 7179 sample_res->normal_path_tbl; 7180 sfx_tbl_data = container_of(sfx_tbl, 7181 struct mlx5_flow_tbl_data_entry, 7182 tbl); 7183 sfx_attr.group = sfx_attr.transfer ? 7184 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 7185 } else { 7186 MLX5_ASSERT(attr->transfer); 7187 sfx_attr.group = jump_table; 7188 } 7189 flow_split_info->prefix_layers = 7190 flow_get_prefix_layer_flags(dev_flow); 7191 MLX5_ASSERT(wks); 7192 flow_split_info->prefix_mark |= wks->mark; 7193 /* Suffix group level already be scaled with factor, set 7194 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 7195 * again in translation. 7196 */ 7197 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 7198 #endif 7199 } 7200 /* Add the suffix subflow. */ 7201 ret = flow_create_split_meter(dev, flow, &sfx_attr, 7202 sfx_items ? sfx_items : items, 7203 sfx_actions ? sfx_actions : actions, 7204 flow_split_info, error); 7205 exit: 7206 if (sfx_actions) 7207 mlx5_free(sfx_actions); 7208 return ret; 7209 } 7210 7211 /** 7212 * Split the flow to subflow set. The splitters might be linked 7213 * in the chain, like this: 7214 * flow_create_split_outer() calls: 7215 * flow_create_split_meter() calls: 7216 * flow_create_split_metadata(meter_subflow_0) calls: 7217 * flow_create_split_inner(metadata_subflow_0) 7218 * flow_create_split_inner(metadata_subflow_1) 7219 * flow_create_split_inner(metadata_subflow_2) 7220 * flow_create_split_metadata(meter_subflow_1) calls: 7221 * flow_create_split_inner(metadata_subflow_0) 7222 * flow_create_split_inner(metadata_subflow_1) 7223 * flow_create_split_inner(metadata_subflow_2) 7224 * 7225 * This provide flexible way to add new levels of flow splitting. 7226 * The all of successfully created subflows are included to the 7227 * parent flow dev_flow list. 7228 * 7229 * @param dev 7230 * Pointer to Ethernet device. 7231 * @param[in] flow 7232 * Parent flow structure pointer. 7233 * @param[in] attr 7234 * Flow rule attributes. 7235 * @param[in] items 7236 * Pattern specification (list terminated by the END pattern item). 7237 * @param[in] actions 7238 * Associated actions (list terminated by the END action). 7239 * @param[in] flow_split_info 7240 * Pointer to flow split info structure. 7241 * @param[out] error 7242 * Perform verbose error reporting if not NULL. 7243 * @return 7244 * 0 on success, negative value otherwise 7245 */ 7246 static int 7247 flow_create_split_outer(struct rte_eth_dev *dev, 7248 struct rte_flow *flow, 7249 const struct rte_flow_attr *attr, 7250 const struct rte_flow_item items[], 7251 const struct rte_flow_action actions[], 7252 struct mlx5_flow_split_info *flow_split_info, 7253 struct rte_flow_error *error) 7254 { 7255 int ret; 7256 7257 ret = flow_create_split_sample(dev, flow, attr, items, 7258 actions, flow_split_info, error); 7259 MLX5_ASSERT(ret <= 0); 7260 return ret; 7261 } 7262 7263 static inline struct mlx5_flow_tunnel * 7264 flow_tunnel_from_rule(const struct mlx5_flow *flow) 7265 { 7266 struct mlx5_flow_tunnel *tunnel; 7267 7268 #pragma GCC diagnostic push 7269 #pragma GCC diagnostic ignored "-Wcast-qual" 7270 tunnel = (typeof(tunnel))flow->tunnel; 7271 #pragma GCC diagnostic pop 7272 7273 return tunnel; 7274 } 7275 7276 /** 7277 * Create a flow and add it to @p list. 7278 * 7279 * @param dev 7280 * Pointer to Ethernet device. 7281 * @param list 7282 * Pointer to a TAILQ flow list. If this parameter NULL, 7283 * no list insertion occurred, flow is just created, 7284 * this is caller's responsibility to track the 7285 * created flow. 7286 * @param[in] attr 7287 * Flow rule attributes. 7288 * @param[in] items 7289 * Pattern specification (list terminated by the END pattern item). 7290 * @param[in] actions 7291 * Associated actions (list terminated by the END action). 7292 * @param[in] external 7293 * This flow rule is created by request external to PMD. 7294 * @param[out] error 7295 * Perform verbose error reporting if not NULL. 7296 * 7297 * @return 7298 * A flow index on success, 0 otherwise and rte_errno is set. 7299 */ 7300 static uint32_t 7301 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7302 const struct rte_flow_attr *attr, 7303 const struct rte_flow_item items[], 7304 const struct rte_flow_action original_actions[], 7305 bool external, struct rte_flow_error *error) 7306 { 7307 struct mlx5_priv *priv = dev->data->dev_private; 7308 struct rte_flow *flow = NULL; 7309 struct mlx5_flow *dev_flow; 7310 const struct rte_flow_action_rss *rss = NULL; 7311 struct mlx5_translated_action_handle 7312 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7313 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7314 union { 7315 struct mlx5_flow_expand_rss buf; 7316 uint8_t buffer[8192]; 7317 } expand_buffer; 7318 union { 7319 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7320 uint8_t buffer[2048]; 7321 } actions_rx; 7322 union { 7323 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7324 uint8_t buffer[2048]; 7325 } actions_hairpin_tx; 7326 union { 7327 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 7328 uint8_t buffer[2048]; 7329 } items_tx; 7330 struct mlx5_rte_flow_item_sq sq_specs[RTE_MAX_QUEUES_PER_PORT]; 7331 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 7332 struct mlx5_flow_rss_desc *rss_desc; 7333 const struct rte_flow_action *p_actions_rx; 7334 uint32_t i; 7335 uint32_t idx = 0; 7336 int hairpin_flow; 7337 struct rte_flow_attr attr_tx = { .priority = 0 }; 7338 const struct rte_flow_action *actions; 7339 struct rte_flow_action *translated_actions = NULL; 7340 struct mlx5_flow_tunnel *tunnel; 7341 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 7342 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 7343 struct mlx5_flow_split_info flow_split_info = { 7344 .external = !!external, 7345 .skip_scale = 0, 7346 .flow_idx = 0, 7347 .prefix_mark = 0, 7348 .prefix_layers = 0, 7349 .table_id = 0 7350 }; 7351 int ret; 7352 7353 MLX5_ASSERT(wks); 7354 rss_desc = &wks->rss_desc; 7355 ret = flow_action_handles_translate(dev, original_actions, 7356 indir_actions, 7357 &indir_actions_n, 7358 &translated_actions, error); 7359 if (ret < 0) { 7360 MLX5_ASSERT(translated_actions == NULL); 7361 return 0; 7362 } 7363 actions = translated_actions ? translated_actions : original_actions; 7364 p_actions_rx = actions; 7365 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7366 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 7367 external, hairpin_flow, error); 7368 if (ret < 0) 7369 goto error_before_hairpin_split; 7370 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 7371 if (!flow) { 7372 rte_errno = ENOMEM; 7373 goto error_before_hairpin_split; 7374 } 7375 if (hairpin_flow > 0) { 7376 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 7377 rte_errno = EINVAL; 7378 goto error_before_hairpin_split; 7379 } 7380 flow_hairpin_split(dev, actions, actions_rx.actions, 7381 actions_hairpin_tx.actions, items_tx.items, 7382 idx); 7383 p_actions_rx = actions_rx.actions; 7384 } 7385 flow_split_info.flow_idx = idx; 7386 flow->drv_type = flow_get_drv_type(dev, attr); 7387 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 7388 flow->drv_type < MLX5_FLOW_TYPE_MAX); 7389 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 7390 /* RSS Action only works on NIC RX domain */ 7391 if (attr->ingress) 7392 rss = flow_get_rss_action(dev, p_actions_rx); 7393 if (rss) { 7394 MLX5_ASSERT(rss->queue_num <= RTE_ETH_RSS_RETA_SIZE_512); 7395 rss_desc->symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func); 7396 /* 7397 * The following information is required by 7398 * mlx5_flow_hashfields_adjust() in advance. 7399 */ 7400 rss_desc->level = rss->level; 7401 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 7402 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 7403 } 7404 flow->dev_handles = 0; 7405 if (rss && rss->types) { 7406 unsigned int graph_root; 7407 7408 graph_root = find_graph_root(rss->level); 7409 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 7410 items, rss->types, 7411 mlx5_support_expansion, graph_root); 7412 MLX5_ASSERT(ret > 0 && 7413 (unsigned int)ret < sizeof(expand_buffer.buffer)); 7414 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 7415 for (i = 0; i < buf->entries; ++i) 7416 mlx5_dbg__print_pattern(buf->entry[i].pattern); 7417 } 7418 } else { 7419 ret = mlx5_flow_expand_sqn((struct mlx5_flow_expand_sqn *)buf, 7420 sizeof(expand_buffer.buffer), 7421 items, sq_specs); 7422 if (ret) { 7423 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 7424 NULL, "not enough memory for rte_flow"); 7425 goto error; 7426 } 7427 if (buf->entries == 0) { 7428 buf->entries = 1; 7429 buf->entry[0].pattern = (void *)(uintptr_t)items; 7430 } 7431 } 7432 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 7433 indir_actions_n); 7434 for (i = 0; i < buf->entries; ++i) { 7435 /* Initialize flow split data. */ 7436 flow_split_info.prefix_layers = 0; 7437 flow_split_info.prefix_mark = 0; 7438 flow_split_info.skip_scale = 0; 7439 /* 7440 * The splitter may create multiple dev_flows, 7441 * depending on configuration. In the simplest 7442 * case it just creates unmodified original flow. 7443 */ 7444 ret = flow_create_split_outer(dev, flow, attr, 7445 buf->entry[i].pattern, 7446 p_actions_rx, &flow_split_info, 7447 error); 7448 if (ret < 0) 7449 goto error; 7450 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 7451 ret = flow_tunnel_add_default_miss(dev, flow, attr, 7452 p_actions_rx, 7453 idx, 7454 wks->flows[0].tunnel, 7455 &default_miss_ctx, 7456 error); 7457 if (ret < 0) { 7458 mlx5_free(default_miss_ctx.queue); 7459 goto error; 7460 } 7461 } 7462 } 7463 /* Create the tx flow. */ 7464 if (hairpin_flow) { 7465 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 7466 attr_tx.ingress = 0; 7467 attr_tx.egress = 1; 7468 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 7469 actions_hairpin_tx.actions, 7470 idx, error); 7471 if (!dev_flow) 7472 goto error; 7473 dev_flow->flow = flow; 7474 dev_flow->external = 0; 7475 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7476 dev_flow->handle, next); 7477 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 7478 items_tx.items, 7479 actions_hairpin_tx.actions, error); 7480 if (ret < 0) 7481 goto error; 7482 } 7483 /* 7484 * Update the metadata register copy table. If extensive 7485 * metadata feature is enabled and registers are supported 7486 * we might create the extra rte_flow for each unique 7487 * MARK/FLAG action ID. 7488 * 7489 * The table is updated for ingress and transfer flows only, because 7490 * the egress Flows belong to the different device and 7491 * copy table should be updated in peer NIC Rx domain. 7492 */ 7493 if ((attr->ingress || attr->transfer) && 7494 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 7495 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 7496 if (ret) 7497 goto error; 7498 } 7499 /* 7500 * If the flow is external (from application) OR device is started, 7501 * OR mreg discover, then apply immediately. 7502 */ 7503 if (external || dev->data->dev_started || 7504 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 7505 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 7506 ret = flow_drv_apply(dev, flow, error); 7507 if (ret < 0) 7508 goto error; 7509 } 7510 flow->type = type; 7511 flow_rxq_flags_set(dev, flow); 7512 rte_free(translated_actions); 7513 tunnel = flow_tunnel_from_rule(wks->flows); 7514 if (tunnel) { 7515 flow->tunnel = 1; 7516 flow->tunnel_id = tunnel->tunnel_id; 7517 rte_atomic_fetch_add_explicit(&tunnel->refctn, 1, rte_memory_order_relaxed); 7518 mlx5_free(default_miss_ctx.queue); 7519 } 7520 mlx5_flow_pop_thread_workspace(); 7521 return idx; 7522 error: 7523 MLX5_ASSERT(flow); 7524 ret = rte_errno; /* Save rte_errno before cleanup. */ 7525 flow_mreg_del_copy_action(dev, flow); 7526 flow_drv_destroy(dev, flow); 7527 if (rss_desc->shared_rss) 7528 rte_atomic_fetch_sub_explicit(&((struct mlx5_shared_action_rss *) 7529 mlx5_ipool_get 7530 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7531 rss_desc->shared_rss))->refcnt, 1, rte_memory_order_relaxed); 7532 mlx5_ipool_free(priv->flows[type], idx); 7533 rte_errno = ret; /* Restore rte_errno. */ 7534 ret = rte_errno; 7535 rte_errno = ret; 7536 error_before_hairpin_split: 7537 mlx5_flow_pop_thread_workspace(); 7538 rte_free(translated_actions); 7539 return 0; 7540 } 7541 7542 /** 7543 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 7544 * incoming packets to table 1. 7545 * 7546 * Other flow rules, requested for group n, will be created in 7547 * e-switch table n+1. 7548 * Jump action to e-switch group n will be created to group n+1. 7549 * 7550 * Used when working in switchdev mode, to utilise advantages of table 1 7551 * and above. 7552 * 7553 * @param dev 7554 * Pointer to Ethernet device. 7555 * 7556 * @return 7557 * Pointer to flow on success, NULL otherwise and rte_errno is set. 7558 */ 7559 struct rte_flow * 7560 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 7561 { 7562 const struct rte_flow_attr attr = { 7563 .group = 0, 7564 .priority = 0, 7565 .ingress = 0, 7566 .egress = 0, 7567 .transfer = 1, 7568 }; 7569 const struct rte_flow_item pattern = { 7570 .type = RTE_FLOW_ITEM_TYPE_END, 7571 }; 7572 struct rte_flow_action_jump jump = { 7573 .group = 1, 7574 }; 7575 const struct rte_flow_action actions[] = { 7576 { 7577 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7578 .conf = &jump, 7579 }, 7580 { 7581 .type = RTE_FLOW_ACTION_TYPE_END, 7582 }, 7583 }; 7584 struct rte_flow_error error; 7585 7586 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7587 &attr, &pattern, 7588 actions, false, &error); 7589 } 7590 7591 /** 7592 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 7593 * and sq number, directs all packets to peer vport. 7594 * 7595 * @param dev 7596 * Pointer to Ethernet device. 7597 * @param sq_num 7598 * SQ number. 7599 * 7600 * @return 7601 * Flow ID on success, 0 otherwise and rte_errno is set. 7602 */ 7603 uint32_t 7604 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sq_num) 7605 { 7606 struct rte_flow_attr attr = { 7607 .group = 0, 7608 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7609 .ingress = 0, 7610 .egress = 0, 7611 .transfer = 1, 7612 }; 7613 struct rte_flow_item_port_id port_spec = { 7614 .id = MLX5_PORT_ESW_MGR, 7615 }; 7616 struct mlx5_rte_flow_item_sq sq_spec = { 7617 .queue = sq_num, 7618 }; 7619 struct rte_flow_item pattern[] = { 7620 { 7621 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 7622 .spec = &port_spec, 7623 }, 7624 { 7625 .type = (enum rte_flow_item_type) 7626 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7627 .spec = &sq_spec, 7628 }, 7629 { 7630 .type = RTE_FLOW_ITEM_TYPE_END, 7631 }, 7632 }; 7633 struct rte_flow_action_jump jump = { 7634 .group = 1, 7635 }; 7636 struct rte_flow_action_port_id port = { 7637 .id = dev->data->port_id, 7638 }; 7639 struct rte_flow_action actions[] = { 7640 { 7641 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7642 .conf = &jump, 7643 }, 7644 { 7645 .type = RTE_FLOW_ACTION_TYPE_END, 7646 }, 7647 }; 7648 struct rte_flow_error error; 7649 7650 /* 7651 * Creates group 0, highest priority jump flow. 7652 * Matches txq to bypass kernel packets. 7653 */ 7654 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 7655 false, &error) == 0) 7656 return 0; 7657 /* Create group 1, lowest priority redirect flow for txq. */ 7658 attr.group = 1; 7659 actions[0].conf = &port; 7660 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 7661 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 7662 actions, false, &error); 7663 } 7664 7665 /** 7666 * Validate a flow supported by the NIC. 7667 * 7668 * @see rte_flow_validate() 7669 * @see rte_flow_ops 7670 */ 7671 int 7672 mlx5_flow_validate(struct rte_eth_dev *dev, 7673 const struct rte_flow_attr *attr, 7674 const struct rte_flow_item items[], 7675 const struct rte_flow_action original_actions[], 7676 struct rte_flow_error *error) 7677 { 7678 int hairpin_flow; 7679 struct mlx5_translated_action_handle 7680 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7681 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7682 const struct rte_flow_action *actions; 7683 struct rte_flow_action *translated_actions = NULL; 7684 int ret = flow_action_handles_translate(dev, original_actions, 7685 indir_actions, 7686 &indir_actions_n, 7687 &translated_actions, error); 7688 7689 if (ret) 7690 return ret; 7691 actions = translated_actions ? translated_actions : original_actions; 7692 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7693 ret = flow_drv_validate(dev, attr, items, actions, 7694 true, hairpin_flow, error); 7695 rte_free(translated_actions); 7696 return ret; 7697 } 7698 7699 static int 7700 mlx5_flow_cache_flow_info(struct rte_eth_dev *dev, 7701 const struct rte_flow_attr *attr, 7702 const uint32_t orig_prio, 7703 const struct rte_flow_item *items, 7704 const struct rte_flow_action *actions, 7705 uint32_t flow_idx) 7706 { 7707 struct mlx5_priv *priv = dev->data->dev_private; 7708 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7709 struct mlx5_dv_flow_info *flow_info, *tmp_info; 7710 struct rte_flow_error error; 7711 int len, ret; 7712 7713 flow_info = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_info), 0, SOCKET_ID_ANY); 7714 if (!flow_info) { 7715 DRV_LOG(ERR, "No enough memory for flow_info caching."); 7716 return -1; 7717 } 7718 flow_info->orig_prio = orig_prio; 7719 flow_info->attr = *attr; 7720 /* Standby mode rule awlays saves it in low priority entry. */ 7721 flow_info->flow_idx_low_prio = flow_idx; 7722 7723 /* Store matching items. */ 7724 ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, items, &error); 7725 if (ret <= 0) { 7726 DRV_LOG(ERR, "Can't get items length."); 7727 goto end; 7728 } 7729 len = RTE_ALIGN(ret, 16); 7730 flow_info->items = mlx5_malloc(MLX5_MEM_ZERO, len, 0, SOCKET_ID_ANY); 7731 if (!flow_info->items) { 7732 DRV_LOG(ERR, "No enough memory for items caching."); 7733 goto end; 7734 } 7735 ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, flow_info->items, ret, items, &error); 7736 if (ret <= 0) { 7737 DRV_LOG(ERR, "Can't duplicate items."); 7738 goto end; 7739 } 7740 7741 /* Store flow actions. */ 7742 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, &error); 7743 if (ret <= 0) { 7744 DRV_LOG(ERR, "Can't get actions length."); 7745 goto end; 7746 } 7747 len = RTE_ALIGN(ret, 16); 7748 flow_info->actions = mlx5_malloc(MLX5_MEM_ZERO, len, 0, SOCKET_ID_ANY); 7749 if (!flow_info->actions) { 7750 DRV_LOG(ERR, "No enough memory for actions caching."); 7751 goto end; 7752 } 7753 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, flow_info->actions, ret, actions, &error); 7754 if (ret <= 0) { 7755 DRV_LOG(ERR, "Can't duplicate actions."); 7756 goto end; 7757 } 7758 7759 /* Insert to the list end. */ 7760 if (LIST_EMPTY(&mode_info->hot_upgrade)) { 7761 LIST_INSERT_HEAD(&mode_info->hot_upgrade, flow_info, next); 7762 } else { 7763 tmp_info = LIST_FIRST(&mode_info->hot_upgrade); 7764 while (LIST_NEXT(tmp_info, next)) 7765 tmp_info = LIST_NEXT(tmp_info, next); 7766 LIST_INSERT_AFTER(tmp_info, flow_info, next); 7767 } 7768 return 0; 7769 end: 7770 if (flow_info->items) 7771 mlx5_free(flow_info->items); 7772 if (flow_info->actions) 7773 mlx5_free(flow_info->actions); 7774 mlx5_free(flow_info); 7775 return -1; 7776 } 7777 7778 static int 7779 mlx5_flow_cache_flow_toggle(struct rte_eth_dev *dev, bool orig_prio) 7780 { 7781 struct mlx5_priv *priv = dev->data->dev_private; 7782 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7783 struct mlx5_dv_flow_info *flow_info; 7784 struct rte_flow_attr attr; 7785 struct rte_flow_error error; 7786 struct rte_flow *high, *low; 7787 7788 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7789 while (flow_info) { 7790 /* DUP flow may have the same priority. */ 7791 if (flow_info->orig_prio != flow_info->attr.priority) { 7792 attr = flow_info->attr; 7793 if (orig_prio) 7794 attr.priority = flow_info->orig_prio; 7795 flow_info->flow_idx_high_prio = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 7796 &attr, flow_info->items, flow_info->actions, 7797 true, &error); 7798 if (!flow_info->flow_idx_high_prio) { 7799 DRV_LOG(ERR, "Priority toggle failed internally."); 7800 goto err; 7801 } 7802 } 7803 flow_info = LIST_NEXT(flow_info, next); 7804 } 7805 /* Delete the low priority rules and swap the flow handle. */ 7806 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7807 while (flow_info) { 7808 MLX5_ASSERT(flow_info->flow_idx_low_prio); 7809 if (flow_info->orig_prio != flow_info->attr.priority) { 7810 high = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7811 flow_info->flow_idx_high_prio); 7812 low = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7813 flow_info->flow_idx_low_prio); 7814 if (high && low) { 7815 RTE_SWAP(*low, *high); 7816 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7817 flow_info->flow_idx_low_prio); 7818 flow_info->flow_idx_high_prio = 0; 7819 } 7820 } 7821 flow_info = LIST_NEXT(flow_info, next); 7822 } 7823 return 0; 7824 err: 7825 /* Destroy preceding successful high priority rules. */ 7826 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7827 while (flow_info) { 7828 if (flow_info->orig_prio != flow_info->attr.priority) { 7829 if (flow_info->flow_idx_high_prio) 7830 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7831 flow_info->flow_idx_high_prio); 7832 else 7833 break; 7834 flow_info->flow_idx_high_prio = 0; 7835 } 7836 flow_info = LIST_NEXT(flow_info, next); 7837 } 7838 return -1; 7839 } 7840 7841 /** 7842 * Set the mode of the flow engine of a process to active or standby during live migration. 7843 * 7844 * @param[in] mode 7845 * MLX5 flow engine mode, @see `enum rte_pmd_mlx5_flow_engine_mode`. 7846 * @param[in] flags 7847 * Flow engine mode specific flags. 7848 * 7849 * @return 7850 * Negative value on error, positive on success. 7851 */ 7852 int 7853 rte_pmd_mlx5_flow_engine_set_mode(enum rte_pmd_mlx5_flow_engine_mode mode, uint32_t flags) 7854 { 7855 struct mlx5_priv *priv; 7856 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info; 7857 struct mlx5_dv_flow_info *flow_info, *tmp_info; 7858 uint16_t port, port_id; 7859 uint16_t toggle_num = 0; 7860 struct rte_eth_dev *dev; 7861 enum rte_pmd_mlx5_flow_engine_mode orig_mode; 7862 uint32_t orig_flags; 7863 bool need_toggle = false; 7864 7865 /* Check if flags combinations are supported. */ 7866 if (flags && flags != RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS) { 7867 DRV_LOG(ERR, "Doesn't support such flags %u", flags); 7868 return -1; 7869 } 7870 MLX5_ETH_FOREACH_DEV(port, NULL) { 7871 dev = &rte_eth_devices[port]; 7872 priv = dev->data->dev_private; 7873 mode_info = &priv->mode_info; 7874 /* No mode change. Assume all devices hold the same mode. */ 7875 if (mode_info->mode == mode) { 7876 DRV_LOG(INFO, "Process flow engine has been in mode %u", mode); 7877 if (mode_info->mode_flag != flags && !LIST_EMPTY(&mode_info->hot_upgrade)) { 7878 DRV_LOG(ERR, "Port %u has rule cache with different flag %u\n", 7879 port, mode_info->mode_flag); 7880 orig_mode = mode_info->mode; 7881 orig_flags = mode_info->mode_flag; 7882 goto err; 7883 } 7884 mode_info->mode_flag = flags; 7885 toggle_num++; 7886 continue; 7887 } 7888 /* Active -> standby. */ 7889 if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY) { 7890 if (!LIST_EMPTY(&mode_info->hot_upgrade)) { 7891 DRV_LOG(ERR, "Cached rule existed"); 7892 orig_mode = mode_info->mode; 7893 orig_flags = mode_info->mode_flag; 7894 goto err; 7895 } 7896 mode_info->mode_flag = flags; 7897 mode_info->mode = mode; 7898 toggle_num++; 7899 /* Standby -> active. */ 7900 } else if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE) { 7901 if (LIST_EMPTY(&mode_info->hot_upgrade)) { 7902 DRV_LOG(INFO, "No cached rule existed"); 7903 } else { 7904 if (mlx5_flow_cache_flow_toggle(dev, true)) { 7905 orig_mode = mode_info->mode; 7906 orig_flags = mode_info->mode_flag; 7907 need_toggle = true; 7908 goto err; 7909 } 7910 } 7911 toggle_num++; 7912 } 7913 } 7914 if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE) { 7915 /* Clear cache flow rules. */ 7916 MLX5_ETH_FOREACH_DEV(port, NULL) { 7917 priv = rte_eth_devices[port].data->dev_private; 7918 mode_info = &priv->mode_info; 7919 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7920 while (flow_info) { 7921 tmp_info = LIST_NEXT(flow_info, next); 7922 LIST_REMOVE(flow_info, next); 7923 mlx5_free(flow_info->actions); 7924 mlx5_free(flow_info->items); 7925 mlx5_free(flow_info); 7926 flow_info = tmp_info; 7927 } 7928 MLX5_ASSERT(LIST_EMPTY(&mode_info->hot_upgrade)); 7929 } 7930 } 7931 return toggle_num; 7932 err: 7933 /* Rollback all preceding successful ports. */ 7934 MLX5_ETH_FOREACH_DEV(port_id, NULL) { 7935 if (port_id == port) 7936 break; 7937 priv = rte_eth_devices[port_id].data->dev_private; 7938 mode_info = &priv->mode_info; 7939 if (need_toggle && !LIST_EMPTY(&mode_info->hot_upgrade) && 7940 mlx5_flow_cache_flow_toggle(dev, false)) 7941 return -EPERM; 7942 mode_info->mode = orig_mode; 7943 mode_info->mode_flag = orig_flags; 7944 } 7945 return -EINVAL; 7946 } 7947 /** 7948 * Create a flow. 7949 * 7950 * @see rte_flow_create() 7951 * @see rte_flow_ops 7952 */ 7953 struct rte_flow * 7954 mlx5_flow_create(struct rte_eth_dev *dev, 7955 const struct rte_flow_attr *attr, 7956 const struct rte_flow_item items[], 7957 const struct rte_flow_action actions[], 7958 struct rte_flow_error *error) 7959 { 7960 struct mlx5_priv *priv = dev->data->dev_private; 7961 struct rte_flow_attr *new_attr = (void *)(uintptr_t)attr; 7962 uint32_t prio = attr->priority; 7963 uint32_t flow_idx; 7964 7965 if (priv->sh->config.dv_flow_en == 2) { 7966 rte_flow_error_set(error, ENOTSUP, 7967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7968 NULL, 7969 "Flow non-Q creation not supported"); 7970 return NULL; 7971 } 7972 /* 7973 * If the device is not started yet, it is not allowed to created a 7974 * flow from application. PMD default flows and traffic control flows 7975 * are not affected. 7976 */ 7977 if (unlikely(!dev->data->dev_started)) { 7978 DRV_LOG(DEBUG, "port %u is not started when " 7979 "inserting a flow", dev->data->port_id); 7980 rte_flow_error_set(error, ENODEV, 7981 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7982 NULL, 7983 "port not started"); 7984 return NULL; 7985 } 7986 if (unlikely(mlx5_need_cache_flow(priv, attr))) { 7987 if (attr->transfer || 7988 (attr->ingress && !(priv->mode_info.mode_flag & 7989 RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS))) 7990 new_attr->priority += 1; 7991 } 7992 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, attr, items, actions, true, error); 7993 if (!flow_idx) 7994 return NULL; 7995 if (unlikely(mlx5_need_cache_flow(priv, attr))) { 7996 if (mlx5_flow_cache_flow_info(dev, attr, prio, items, actions, flow_idx)) { 7997 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 7998 flow_idx = 0; 7999 } 8000 } 8001 return (void *)(uintptr_t)flow_idx; 8002 } 8003 8004 /** 8005 * Destroy a flow in a list. 8006 * 8007 * @param dev 8008 * Pointer to Ethernet device. 8009 * @param[in] flow_idx 8010 * Index of flow to destroy. 8011 */ 8012 static void 8013 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 8014 uint32_t flow_idx) 8015 { 8016 struct mlx5_priv *priv = dev->data->dev_private; 8017 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 8018 8019 if (!flow) 8020 return; 8021 MLX5_ASSERT(flow->type == type); 8022 /* 8023 * Update RX queue flags only if port is started, otherwise it is 8024 * already clean. 8025 */ 8026 if (dev->data->dev_started) 8027 flow_rxq_flags_trim(dev, flow); 8028 flow_drv_destroy(dev, flow); 8029 if (flow->tunnel) { 8030 struct mlx5_flow_tunnel *tunnel; 8031 8032 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 8033 RTE_VERIFY(tunnel); 8034 if (!(rte_atomic_fetch_sub_explicit(&tunnel->refctn, 1, 8035 rte_memory_order_relaxed) - 1)) 8036 mlx5_flow_tunnel_free(dev, tunnel); 8037 } 8038 flow_mreg_del_copy_action(dev, flow); 8039 mlx5_ipool_free(priv->flows[type], flow_idx); 8040 } 8041 8042 /** 8043 * Destroy all flows. 8044 * 8045 * @param dev 8046 * Pointer to Ethernet device. 8047 * @param type 8048 * Flow type to be flushed. 8049 * @param active 8050 * If flushing is called actively. 8051 */ 8052 void 8053 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 8054 bool active) 8055 { 8056 struct mlx5_priv *priv = dev->data->dev_private; 8057 uint32_t num_flushed = 0, fidx = 1; 8058 struct rte_flow *flow; 8059 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 8060 struct mlx5_dv_flow_info *flow_info; 8061 8062 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 8063 if (priv->sh->config.dv_flow_en == 2 && 8064 type == MLX5_FLOW_TYPE_GEN) { 8065 flow_hw_q_flow_flush(dev, NULL); 8066 return; 8067 } 8068 #endif 8069 8070 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 8071 flow_list_destroy(dev, type, fidx); 8072 if (unlikely(mlx5_need_cache_flow(priv, NULL) && type == MLX5_FLOW_TYPE_GEN)) { 8073 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 8074 while (flow_info) { 8075 /* Romove the cache flow info. */ 8076 if (flow_info->flow_idx_low_prio == (uint32_t)(uintptr_t)fidx) { 8077 MLX5_ASSERT(!flow_info->flow_idx_high_prio); 8078 LIST_REMOVE(flow_info, next); 8079 mlx5_free(flow_info->items); 8080 mlx5_free(flow_info->actions); 8081 mlx5_free(flow_info); 8082 break; 8083 } 8084 flow_info = LIST_NEXT(flow_info, next); 8085 } 8086 } 8087 num_flushed++; 8088 } 8089 if (active) { 8090 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 8091 dev->data->port_id, num_flushed); 8092 } 8093 } 8094 8095 /** 8096 * Stop all default actions for flows. 8097 * 8098 * @param dev 8099 * Pointer to Ethernet device. 8100 */ 8101 void 8102 mlx5_flow_stop_default(struct rte_eth_dev *dev) 8103 { 8104 flow_mreg_del_default_copy_action(dev); 8105 flow_rxq_flags_clear(dev); 8106 } 8107 8108 /** 8109 * Set rxq flag. 8110 * 8111 * @param[in] dev 8112 * Pointer to the rte_eth_dev structure. 8113 * @param[in] enable 8114 * Flag to enable or not. 8115 */ 8116 void 8117 flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable) 8118 { 8119 struct mlx5_priv *priv = dev->data->dev_private; 8120 unsigned int i; 8121 8122 if ((!priv->mark_enabled && !enable) || 8123 (priv->mark_enabled && enable)) 8124 return; 8125 for (i = 0; i < priv->rxqs_n; ++i) { 8126 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 8127 8128 /* With RXQ start/stop feature, RXQ might be stopped. */ 8129 if (!rxq_ctrl) 8130 continue; 8131 rxq_ctrl->rxq.mark = enable; 8132 } 8133 priv->mark_enabled = enable; 8134 } 8135 8136 /** 8137 * Start all default actions for flows. 8138 * 8139 * @param dev 8140 * Pointer to Ethernet device. 8141 * @return 8142 * 0 on success, a negative errno value otherwise and rte_errno is set. 8143 */ 8144 int 8145 mlx5_flow_start_default(struct rte_eth_dev *dev) 8146 { 8147 struct rte_flow_error error; 8148 8149 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 8150 return flow_mreg_add_default_copy_action(dev, &error); 8151 } 8152 8153 /** 8154 * Release key of thread specific flow workspace data. 8155 */ 8156 void 8157 flow_release_workspace(void *data) 8158 { 8159 struct mlx5_flow_workspace *wks = data; 8160 struct mlx5_flow_workspace *next; 8161 8162 while (wks) { 8163 next = wks->next; 8164 free(wks); 8165 wks = next; 8166 } 8167 } 8168 8169 /** 8170 * Get thread specific current flow workspace. 8171 * 8172 * @return pointer to thread specific flow workspace data, NULL on error. 8173 */ 8174 struct mlx5_flow_workspace* 8175 mlx5_flow_get_thread_workspace(void) 8176 { 8177 struct mlx5_flow_workspace *data; 8178 8179 data = mlx5_flow_os_get_specific_workspace(); 8180 MLX5_ASSERT(data && data->inuse); 8181 if (!data || !data->inuse) 8182 DRV_LOG(ERR, "flow workspace not initialized."); 8183 return data; 8184 } 8185 8186 /** 8187 * Allocate and init new flow workspace. 8188 * 8189 * @return pointer to flow workspace data, NULL on error. 8190 */ 8191 static struct mlx5_flow_workspace* 8192 flow_alloc_thread_workspace(void) 8193 { 8194 size_t data_size = RTE_ALIGN(sizeof(struct mlx5_flow_workspace), sizeof(long)); 8195 size_t rss_queue_array_size = sizeof(uint16_t) * RTE_ETH_RSS_RETA_SIZE_512; 8196 struct mlx5_flow_workspace *data = calloc(1, data_size + 8197 rss_queue_array_size); 8198 8199 if (!data) { 8200 DRV_LOG(ERR, "Failed to allocate flow workspace memory."); 8201 return NULL; 8202 } 8203 data->rss_desc.queue = RTE_PTR_ADD(data, data_size); 8204 return data; 8205 } 8206 8207 /** 8208 * Get new thread specific flow workspace. 8209 * 8210 * If current workspace inuse, create new one and set as current. 8211 * 8212 * @return pointer to thread specific flow workspace data, NULL on error. 8213 */ 8214 struct mlx5_flow_workspace* 8215 mlx5_flow_push_thread_workspace(void) 8216 { 8217 struct mlx5_flow_workspace *curr; 8218 struct mlx5_flow_workspace *data; 8219 8220 curr = mlx5_flow_os_get_specific_workspace(); 8221 if (!curr) { 8222 data = flow_alloc_thread_workspace(); 8223 if (!data) 8224 return NULL; 8225 mlx5_flow_os_workspace_gc_add(data); 8226 } else if (!curr->inuse) { 8227 data = curr; 8228 } else if (curr->next) { 8229 data = curr->next; 8230 } else { 8231 data = flow_alloc_thread_workspace(); 8232 if (!data) 8233 return NULL; 8234 curr->next = data; 8235 data->prev = curr; 8236 } 8237 data->inuse = 1; 8238 data->flow_idx = 0; 8239 /* Set as current workspace */ 8240 if (mlx5_flow_os_set_specific_workspace(data)) 8241 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 8242 return data; 8243 } 8244 8245 /** 8246 * Close current thread specific flow workspace. 8247 * 8248 * If previous workspace available, set it as current. 8249 * 8250 * @return pointer to thread specific flow workspace data, NULL on error. 8251 */ 8252 void 8253 mlx5_flow_pop_thread_workspace(void) 8254 { 8255 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 8256 8257 if (!data) 8258 return; 8259 if (!data->inuse) { 8260 DRV_LOG(ERR, "Failed to close unused flow workspace."); 8261 return; 8262 } 8263 data->inuse = 0; 8264 if (!data->prev) 8265 return; 8266 if (mlx5_flow_os_set_specific_workspace(data->prev)) 8267 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 8268 } 8269 8270 /** 8271 * Verify the flow list is empty 8272 * 8273 * @param dev 8274 * Pointer to Ethernet device. 8275 * 8276 * @return the number of flows not released. 8277 */ 8278 int 8279 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 8280 { 8281 struct mlx5_priv *priv = dev->data->dev_private; 8282 struct rte_flow *flow; 8283 uint32_t idx = 0; 8284 int ret = 0, i; 8285 8286 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 8287 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 8288 DRV_LOG(DEBUG, "port %u flow %p still referenced", 8289 dev->data->port_id, (void *)flow); 8290 ret++; 8291 } 8292 } 8293 return ret; 8294 } 8295 8296 /** 8297 * Enable default hairpin egress flow. 8298 * 8299 * @param dev 8300 * Pointer to Ethernet device. 8301 * @param sq_num 8302 * The SQ hw number. 8303 * 8304 * @return 8305 * 0 on success, a negative errno value otherwise and rte_errno is set. 8306 */ 8307 int 8308 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 8309 uint32_t sq_num) 8310 { 8311 const struct rte_flow_attr attr = { 8312 .egress = 1, 8313 .priority = 0, 8314 }; 8315 struct mlx5_rte_flow_item_sq queue_spec = { 8316 .queue = sq_num, 8317 }; 8318 struct mlx5_rte_flow_item_sq queue_mask = { 8319 .queue = UINT32_MAX, 8320 }; 8321 struct rte_flow_item items[] = { 8322 { 8323 .type = (enum rte_flow_item_type) 8324 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 8325 .spec = &queue_spec, 8326 .last = NULL, 8327 .mask = &queue_mask, 8328 }, 8329 { 8330 .type = RTE_FLOW_ITEM_TYPE_END, 8331 }, 8332 }; 8333 struct rte_flow_action_jump jump = { 8334 .group = MLX5_HAIRPIN_TX_TABLE, 8335 }; 8336 struct rte_flow_action actions[2]; 8337 uint32_t flow_idx; 8338 struct rte_flow_error error; 8339 8340 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 8341 actions[0].conf = &jump; 8342 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 8343 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8344 &attr, items, actions, false, &error); 8345 if (!flow_idx) { 8346 DRV_LOG(DEBUG, 8347 "Failed to create ctrl flow: rte_errno(%d)," 8348 " type(%d), message(%s)", 8349 rte_errno, error.type, 8350 error.message ? error.message : " (no stated reason)"); 8351 return -rte_errno; 8352 } 8353 return 0; 8354 } 8355 8356 /** 8357 * Enable a control flow configured from the control plane. 8358 * 8359 * @param dev 8360 * Pointer to Ethernet device. 8361 * @param eth_spec 8362 * An Ethernet flow spec to apply. 8363 * @param eth_mask 8364 * An Ethernet flow mask to apply. 8365 * @param vlan_spec 8366 * A VLAN flow spec to apply. 8367 * @param vlan_mask 8368 * A VLAN flow mask to apply. 8369 * 8370 * @return 8371 * 0 on success, a negative errno value otherwise and rte_errno is set. 8372 */ 8373 int 8374 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 8375 struct rte_flow_item_eth *eth_spec, 8376 struct rte_flow_item_eth *eth_mask, 8377 struct rte_flow_item_vlan *vlan_spec, 8378 struct rte_flow_item_vlan *vlan_mask) 8379 { 8380 struct mlx5_priv *priv = dev->data->dev_private; 8381 const struct rte_flow_attr attr = { 8382 .ingress = 1, 8383 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 8384 }; 8385 struct rte_flow_item items[] = { 8386 { 8387 .type = RTE_FLOW_ITEM_TYPE_ETH, 8388 .spec = eth_spec, 8389 .last = NULL, 8390 .mask = eth_mask, 8391 }, 8392 { 8393 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 8394 RTE_FLOW_ITEM_TYPE_END, 8395 .spec = vlan_spec, 8396 .last = NULL, 8397 .mask = vlan_mask, 8398 }, 8399 { 8400 .type = RTE_FLOW_ITEM_TYPE_END, 8401 }, 8402 }; 8403 uint16_t queue[priv->reta_idx_n]; 8404 struct rte_flow_action_rss action_rss = { 8405 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 8406 .level = 0, 8407 .types = priv->rss_conf.rss_hf, 8408 .key_len = priv->rss_conf.rss_key_len, 8409 .queue_num = priv->reta_idx_n, 8410 .key = priv->rss_conf.rss_key, 8411 .queue = queue, 8412 }; 8413 struct rte_flow_action actions[] = { 8414 { 8415 .type = RTE_FLOW_ACTION_TYPE_RSS, 8416 .conf = &action_rss, 8417 }, 8418 { 8419 .type = RTE_FLOW_ACTION_TYPE_END, 8420 }, 8421 }; 8422 uint32_t flow_idx; 8423 struct rte_flow_error error; 8424 unsigned int i; 8425 8426 if (!priv->reta_idx_n || !priv->rxqs_n) { 8427 return 0; 8428 } 8429 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 8430 action_rss.types = 0; 8431 for (i = 0; i != priv->reta_idx_n; ++i) 8432 queue[i] = (*priv->reta_idx)[i]; 8433 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8434 &attr, items, actions, false, &error); 8435 if (!flow_idx) 8436 return -rte_errno; 8437 return 0; 8438 } 8439 8440 /** 8441 * Enable a flow control configured from the control plane. 8442 * 8443 * @param dev 8444 * Pointer to Ethernet device. 8445 * @param eth_spec 8446 * An Ethernet flow spec to apply. 8447 * @param eth_mask 8448 * An Ethernet flow mask to apply. 8449 * 8450 * @return 8451 * 0 on success, a negative errno value otherwise and rte_errno is set. 8452 */ 8453 int 8454 mlx5_ctrl_flow(struct rte_eth_dev *dev, 8455 struct rte_flow_item_eth *eth_spec, 8456 struct rte_flow_item_eth *eth_mask) 8457 { 8458 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 8459 } 8460 8461 /** 8462 * Create default miss flow rule matching lacp traffic 8463 * 8464 * @param dev 8465 * Pointer to Ethernet device. 8466 * @param eth_spec 8467 * An Ethernet flow spec to apply. 8468 * 8469 * @return 8470 * 0 on success, a negative errno value otherwise and rte_errno is set. 8471 */ 8472 int 8473 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 8474 { 8475 /* 8476 * The LACP matching is done by only using ether type since using 8477 * a multicast dst mac causes kernel to give low priority to this flow. 8478 */ 8479 static const struct rte_flow_item_eth lacp_spec = { 8480 .hdr.ether_type = RTE_BE16(0x8809), 8481 }; 8482 static const struct rte_flow_item_eth lacp_mask = { 8483 .hdr.ether_type = 0xffff, 8484 }; 8485 const struct rte_flow_attr attr = { 8486 .ingress = 1, 8487 }; 8488 struct rte_flow_item items[] = { 8489 { 8490 .type = RTE_FLOW_ITEM_TYPE_ETH, 8491 .spec = &lacp_spec, 8492 .mask = &lacp_mask, 8493 }, 8494 { 8495 .type = RTE_FLOW_ITEM_TYPE_END, 8496 }, 8497 }; 8498 struct rte_flow_action actions[] = { 8499 { 8500 .type = (enum rte_flow_action_type) 8501 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 8502 }, 8503 { 8504 .type = RTE_FLOW_ACTION_TYPE_END, 8505 }, 8506 }; 8507 struct rte_flow_error error; 8508 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8509 &attr, items, actions, 8510 false, &error); 8511 8512 if (!flow_idx) 8513 return -rte_errno; 8514 return 0; 8515 } 8516 8517 /** 8518 * Destroy a flow. 8519 * 8520 * @see rte_flow_destroy() 8521 * @see rte_flow_ops 8522 */ 8523 int 8524 mlx5_flow_destroy(struct rte_eth_dev *dev, 8525 struct rte_flow *flow, 8526 struct rte_flow_error *error __rte_unused) 8527 { 8528 struct mlx5_priv *priv = dev->data->dev_private; 8529 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 8530 struct mlx5_dv_flow_info *flow_info; 8531 8532 if (priv->sh->config.dv_flow_en == 2) 8533 return rte_flow_error_set(error, ENOTSUP, 8534 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8535 NULL, 8536 "Flow non-Q destruction not supported"); 8537 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 8538 (uintptr_t)(void *)flow); 8539 if (unlikely(mlx5_need_cache_flow(priv, NULL))) { 8540 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 8541 while (flow_info) { 8542 /* Romove the cache flow info. */ 8543 if (flow_info->flow_idx_low_prio == (uint32_t)(uintptr_t)flow) { 8544 MLX5_ASSERT(!flow_info->flow_idx_high_prio); 8545 LIST_REMOVE(flow_info, next); 8546 mlx5_free(flow_info->items); 8547 mlx5_free(flow_info->actions); 8548 mlx5_free(flow_info); 8549 break; 8550 } 8551 flow_info = LIST_NEXT(flow_info, next); 8552 } 8553 } 8554 return 0; 8555 } 8556 8557 /** 8558 * Destroy all flows. 8559 * 8560 * @see rte_flow_flush() 8561 * @see rte_flow_ops 8562 */ 8563 int 8564 mlx5_flow_flush(struct rte_eth_dev *dev, 8565 struct rte_flow_error *error __rte_unused) 8566 { 8567 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 8568 return 0; 8569 } 8570 8571 /** 8572 * Isolated mode. 8573 * 8574 * @see rte_flow_isolate() 8575 * @see rte_flow_ops 8576 */ 8577 int 8578 mlx5_flow_isolate(struct rte_eth_dev *dev, 8579 int enable, 8580 struct rte_flow_error *error) 8581 { 8582 struct mlx5_priv *priv = dev->data->dev_private; 8583 8584 if (dev->data->dev_started) { 8585 rte_flow_error_set(error, EBUSY, 8586 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8587 NULL, 8588 "port must be stopped first"); 8589 return -rte_errno; 8590 } 8591 if (!enable && !priv->sh->config.repr_matching) 8592 return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8593 "isolated mode cannot be disabled when " 8594 "representor matching is disabled"); 8595 priv->isolated = !!enable; 8596 if (enable) 8597 dev->dev_ops = &mlx5_dev_ops_isolate; 8598 else 8599 dev->dev_ops = &mlx5_dev_ops; 8600 8601 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 8602 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 8603 8604 return 0; 8605 } 8606 8607 /** 8608 * Query a flow. 8609 * 8610 * @see rte_flow_query() 8611 * @see rte_flow_ops 8612 */ 8613 static int 8614 flow_drv_query(struct rte_eth_dev *dev, 8615 struct rte_flow *eflow, 8616 const struct rte_flow_action *actions, 8617 void *data, 8618 struct rte_flow_error *error) 8619 { 8620 struct mlx5_priv *priv = dev->data->dev_private; 8621 const struct mlx5_flow_driver_ops *fops; 8622 struct rte_flow *flow = NULL; 8623 enum mlx5_flow_drv_type ftype = MLX5_FLOW_TYPE_MIN; 8624 8625 if (priv->sh->config.dv_flow_en == 2) { 8626 #ifdef HAVE_MLX5_HWS_SUPPORT 8627 flow = eflow; 8628 ftype = MLX5_FLOW_TYPE_HW; 8629 #endif 8630 } else { 8631 flow = (struct rte_flow *)mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 8632 (uintptr_t)(void *)eflow); 8633 } 8634 if (!flow) { 8635 return rte_flow_error_set(error, ENOENT, 8636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8637 NULL, 8638 "invalid flow handle"); 8639 } 8640 if (ftype == MLX5_FLOW_TYPE_MIN) 8641 ftype = flow->drv_type; 8642 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 8643 fops = flow_get_drv_ops(ftype); 8644 8645 return fops->query(dev, flow, actions, data, error); 8646 } 8647 8648 /** 8649 * Query a flow. 8650 * 8651 * @see rte_flow_query() 8652 * @see rte_flow_ops 8653 */ 8654 int 8655 mlx5_flow_query(struct rte_eth_dev *dev, 8656 struct rte_flow *flow, 8657 const struct rte_flow_action *actions, 8658 void *data, 8659 struct rte_flow_error *error) 8660 { 8661 int ret; 8662 8663 ret = flow_drv_query(dev, flow, actions, data, 8664 error); 8665 if (ret < 0) 8666 return ret; 8667 return 0; 8668 } 8669 8670 /** 8671 * Get rte_flow callbacks. 8672 * 8673 * @param dev 8674 * Pointer to Ethernet device structure. 8675 * @param ops 8676 * Pointer to operation-specific structure. 8677 * 8678 * @return 0 8679 */ 8680 int 8681 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 8682 const struct rte_flow_ops **ops) 8683 { 8684 *ops = &mlx5_flow_ops; 8685 return 0; 8686 } 8687 8688 /** 8689 * Validate meter policy actions. 8690 * Dispatcher for action type specific validation. 8691 * 8692 * @param[in] dev 8693 * Pointer to the Ethernet device structure. 8694 * @param[in] action 8695 * The meter policy action object to validate. 8696 * @param[in] attr 8697 * Attributes of flow to determine steering domain. 8698 * @param[out] is_rss 8699 * Is RSS or not. 8700 * @param[out] domain_bitmap 8701 * Domain bitmap. 8702 * @param[out] is_def_policy 8703 * Is default policy or not. 8704 * @param[out] error 8705 * Perform verbose error reporting if not NULL. Initialized in case of 8706 * error only. 8707 * 8708 * @return 8709 * 0 on success, otherwise negative errno value. 8710 */ 8711 int 8712 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 8713 const struct rte_flow_action *actions[RTE_COLORS], 8714 struct rte_flow_attr *attr, 8715 bool *is_rss, 8716 uint8_t *domain_bitmap, 8717 uint8_t *policy_mode, 8718 struct rte_mtr_error *error) 8719 { 8720 const struct mlx5_flow_driver_ops *fops; 8721 8722 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8723 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 8724 domain_bitmap, policy_mode, error); 8725 } 8726 8727 /** 8728 * Destroy the meter table set. 8729 * 8730 * @param[in] dev 8731 * Pointer to Ethernet device. 8732 * @param[in] mtr_policy 8733 * Meter policy struct. 8734 */ 8735 void 8736 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 8737 struct mlx5_flow_meter_policy *mtr_policy) 8738 { 8739 const struct mlx5_flow_driver_ops *fops; 8740 8741 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8742 fops->destroy_mtr_acts(dev, mtr_policy); 8743 } 8744 8745 /** 8746 * Create policy action, lock free, 8747 * (mutex should be acquired by caller). 8748 * Dispatcher for action type specific call. 8749 * 8750 * @param[in] dev 8751 * Pointer to the Ethernet device structure. 8752 * @param[in] mtr_policy 8753 * Meter policy struct. 8754 * @param[in] action 8755 * Action specification used to create meter actions. 8756 * @param[in] attr 8757 * Flow rule attributes. 8758 * @param[out] error 8759 * Perform verbose error reporting if not NULL. Initialized in case of 8760 * error only. 8761 * 8762 * @return 8763 * 0 on success, otherwise negative errno value. 8764 */ 8765 int 8766 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 8767 struct mlx5_flow_meter_policy *mtr_policy, 8768 const struct rte_flow_action *actions[RTE_COLORS], 8769 struct rte_flow_attr *attr, 8770 struct rte_mtr_error *error) 8771 { 8772 const struct mlx5_flow_driver_ops *fops; 8773 8774 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8775 return fops->create_mtr_acts(dev, mtr_policy, actions, attr, error); 8776 } 8777 8778 /** 8779 * Create policy rules, lock free, 8780 * (mutex should be acquired by caller). 8781 * Dispatcher for action type specific call. 8782 * 8783 * @param[in] dev 8784 * Pointer to the Ethernet device structure. 8785 * @param[in] mtr_policy 8786 * Meter policy struct. 8787 * 8788 * @return 8789 * 0 on success, -1 otherwise. 8790 */ 8791 int 8792 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 8793 struct mlx5_flow_meter_policy *mtr_policy) 8794 { 8795 const struct mlx5_flow_driver_ops *fops; 8796 8797 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8798 return fops->create_policy_rules(dev, mtr_policy); 8799 } 8800 8801 /** 8802 * Destroy policy rules, lock free, 8803 * (mutex should be acquired by caller). 8804 * Dispatcher for action type specific call. 8805 * 8806 * @param[in] dev 8807 * Pointer to the Ethernet device structure. 8808 * @param[in] mtr_policy 8809 * Meter policy struct. 8810 */ 8811 void 8812 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 8813 struct mlx5_flow_meter_policy *mtr_policy) 8814 { 8815 const struct mlx5_flow_driver_ops *fops; 8816 8817 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8818 fops->destroy_policy_rules(dev, mtr_policy); 8819 } 8820 8821 /** 8822 * Destroy the default policy table set. 8823 * 8824 * @param[in] dev 8825 * Pointer to Ethernet device. 8826 */ 8827 void 8828 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 8829 { 8830 const struct mlx5_flow_driver_ops *fops; 8831 8832 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8833 fops->destroy_def_policy(dev); 8834 } 8835 8836 /** 8837 * Destroy the default policy table set. 8838 * 8839 * @param[in] dev 8840 * Pointer to Ethernet device. 8841 * 8842 * @return 8843 * 0 on success, -1 otherwise. 8844 */ 8845 int 8846 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 8847 { 8848 const struct mlx5_flow_driver_ops *fops; 8849 8850 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8851 return fops->create_def_policy(dev); 8852 } 8853 8854 /** 8855 * Create the needed meter and suffix tables. 8856 * 8857 * @param[in] dev 8858 * Pointer to Ethernet device. 8859 * 8860 * @return 8861 * 0 on success, -1 otherwise. 8862 */ 8863 int 8864 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 8865 struct mlx5_flow_meter_info *fm, 8866 uint32_t mtr_idx, 8867 uint8_t domain_bitmap) 8868 { 8869 const struct mlx5_flow_driver_ops *fops; 8870 8871 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8872 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 8873 } 8874 8875 /** 8876 * Destroy the meter table set. 8877 * 8878 * @param[in] dev 8879 * Pointer to Ethernet device. 8880 * @param[in] tbl 8881 * Pointer to the meter table set. 8882 */ 8883 void 8884 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 8885 struct mlx5_flow_meter_info *fm) 8886 { 8887 const struct mlx5_flow_driver_ops *fops; 8888 8889 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8890 fops->destroy_mtr_tbls(dev, fm); 8891 } 8892 8893 /** 8894 * Destroy the global meter drop table. 8895 * 8896 * @param[in] dev 8897 * Pointer to Ethernet device. 8898 */ 8899 void 8900 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 8901 { 8902 const struct mlx5_flow_driver_ops *fops; 8903 8904 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8905 fops->destroy_mtr_drop_tbls(dev); 8906 } 8907 8908 /** 8909 * Destroy the sub policy table with RX queue. 8910 * 8911 * @param[in] dev 8912 * Pointer to Ethernet device. 8913 * @param[in] mtr_policy 8914 * Pointer to meter policy table. 8915 */ 8916 void 8917 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 8918 struct mlx5_flow_meter_policy *mtr_policy) 8919 { 8920 const struct mlx5_flow_driver_ops *fops; 8921 8922 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8923 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 8924 } 8925 8926 /** 8927 * Allocate the needed aso flow meter id. 8928 * 8929 * @param[in] dev 8930 * Pointer to Ethernet device. 8931 * 8932 * @return 8933 * Index to aso flow meter on success, NULL otherwise. 8934 */ 8935 uint32_t 8936 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 8937 { 8938 const struct mlx5_flow_driver_ops *fops; 8939 8940 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8941 return fops->create_meter(dev); 8942 } 8943 8944 /** 8945 * Free the aso flow meter id. 8946 * 8947 * @param[in] dev 8948 * Pointer to Ethernet device. 8949 * @param[in] mtr_idx 8950 * Index to aso flow meter to be free. 8951 * 8952 * @return 8953 * 0 on success. 8954 */ 8955 void 8956 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 8957 { 8958 const struct mlx5_flow_driver_ops *fops; 8959 8960 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8961 fops->free_meter(dev, mtr_idx); 8962 } 8963 8964 /** 8965 * Allocate a counter. 8966 * 8967 * @param[in] dev 8968 * Pointer to Ethernet device structure. 8969 * 8970 * @return 8971 * Index to allocated counter on success, 0 otherwise. 8972 */ 8973 uint32_t 8974 mlx5_counter_alloc(struct rte_eth_dev *dev) 8975 { 8976 struct rte_flow_attr attr = { .transfer = 0 }; 8977 8978 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_alloc 8979 (dev); 8980 } 8981 8982 /** 8983 * Free a counter. 8984 * 8985 * @param[in] dev 8986 * Pointer to Ethernet device structure. 8987 * @param[in] cnt 8988 * Index to counter to be free. 8989 */ 8990 void 8991 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 8992 { 8993 struct rte_flow_attr attr = { .transfer = 0 }; 8994 8995 flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_free(dev, cnt); 8996 } 8997 8998 /** 8999 * Query counter statistics. 9000 * 9001 * @param[in] dev 9002 * Pointer to Ethernet device structure. 9003 * @param[in] cnt 9004 * Index to counter to query. 9005 * @param[in] clear 9006 * Set to clear counter statistics. 9007 * @param[out] pkts 9008 * The counter hits packets number to save. 9009 * @param[out] bytes 9010 * The counter hits bytes number to save. 9011 * 9012 * @return 9013 * 0 on success, a negative errno value otherwise. 9014 */ 9015 int 9016 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 9017 bool clear, uint64_t *pkts, uint64_t *bytes, void **action) 9018 { 9019 struct rte_flow_attr attr = { .transfer = 0 }; 9020 9021 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_query 9022 (dev, cnt, clear, pkts, bytes, action); 9023 } 9024 9025 /** 9026 * Get information about HWS pre-configurable resources. 9027 * 9028 * @param[in] dev 9029 * Pointer to the rte_eth_dev structure. 9030 * @param[out] port_info 9031 * Pointer to port information. 9032 * @param[out] queue_info 9033 * Pointer to queue information. 9034 * @param[out] error 9035 * Pointer to error structure. 9036 * 9037 * @return 9038 * 0 on success, a negative errno value otherwise and rte_errno is set. 9039 */ 9040 static int 9041 mlx5_flow_info_get(struct rte_eth_dev *dev, 9042 struct rte_flow_port_info *port_info, 9043 struct rte_flow_queue_info *queue_info, 9044 struct rte_flow_error *error) 9045 { 9046 const struct mlx5_flow_driver_ops *fops; 9047 struct rte_flow_attr attr = {0}; 9048 9049 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9050 return rte_flow_error_set(error, ENOTSUP, 9051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9052 NULL, 9053 "info get with incorrect steering mode"); 9054 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9055 return fops->info_get(dev, port_info, queue_info, error); 9056 } 9057 9058 /** 9059 * Configure port HWS resources. 9060 * 9061 * @param[in] dev 9062 * Pointer to the rte_eth_dev structure. 9063 * @param[in] port_attr 9064 * Port configuration attributes. 9065 * @param[in] nb_queue 9066 * Number of queue. 9067 * @param[in] queue_attr 9068 * Array that holds attributes for each flow queue. 9069 * @param[out] error 9070 * Pointer to error structure. 9071 * 9072 * @return 9073 * 0 on success, a negative errno value otherwise and rte_errno is set. 9074 */ 9075 static int 9076 mlx5_flow_port_configure(struct rte_eth_dev *dev, 9077 const struct rte_flow_port_attr *port_attr, 9078 uint16_t nb_queue, 9079 const struct rte_flow_queue_attr *queue_attr[], 9080 struct rte_flow_error *error) 9081 { 9082 const struct mlx5_flow_driver_ops *fops; 9083 struct rte_flow_attr attr = {0}; 9084 9085 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9086 return rte_flow_error_set(error, ENOTSUP, 9087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9088 NULL, 9089 "port configure with incorrect steering mode"); 9090 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9091 return fops->configure(dev, port_attr, nb_queue, queue_attr, error); 9092 } 9093 9094 /** 9095 * Validate item template. 9096 * 9097 * @param[in] dev 9098 * Pointer to the rte_eth_dev structure. 9099 * @param[in] attr 9100 * Pointer to the item template attributes. 9101 * @param[in] items 9102 * The template item pattern. 9103 * @param[out] error 9104 * Pointer to error structure. 9105 * 9106 * @return 9107 * 0 on success, a negative errno value otherwise and rte_errno is set. 9108 */ 9109 int 9110 mlx5_flow_pattern_validate(struct rte_eth_dev *dev, 9111 const struct rte_flow_pattern_template_attr *attr, 9112 const struct rte_flow_item items[], 9113 struct rte_flow_error *error) 9114 { 9115 const struct mlx5_flow_driver_ops *fops; 9116 struct rte_flow_attr fattr = {0}; 9117 uint64_t item_flags = 0; 9118 9119 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9120 rte_flow_error_set(error, ENOTSUP, 9121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9122 "pattern validate with incorrect steering mode"); 9123 return -ENOTSUP; 9124 } 9125 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9126 return fops->pattern_validate(dev, attr, items, &item_flags, error); 9127 } 9128 9129 /** 9130 * Create flow item template. 9131 * 9132 * @param[in] dev 9133 * Pointer to the rte_eth_dev structure. 9134 * @param[in] attr 9135 * Pointer to the item template attributes. 9136 * @param[in] items 9137 * The template item pattern. 9138 * @param[out] error 9139 * Pointer to error structure. 9140 * 9141 * @return 9142 * 0 on success, a negative errno value otherwise and rte_errno is set. 9143 */ 9144 static struct rte_flow_pattern_template * 9145 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 9146 const struct rte_flow_pattern_template_attr *attr, 9147 const struct rte_flow_item items[], 9148 struct rte_flow_error *error) 9149 { 9150 const struct mlx5_flow_driver_ops *fops; 9151 struct rte_flow_attr fattr = {0}; 9152 9153 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9154 rte_flow_error_set(error, ENOTSUP, 9155 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9156 NULL, 9157 "pattern create with incorrect steering mode"); 9158 return NULL; 9159 } 9160 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9161 return fops->pattern_template_create(dev, attr, items, error); 9162 } 9163 9164 /** 9165 * Destroy flow item template. 9166 * 9167 * @param[in] dev 9168 * Pointer to the rte_eth_dev structure. 9169 * @param[in] template 9170 * Pointer to the item template to be destroyed. 9171 * @param[out] error 9172 * Pointer to error structure. 9173 * 9174 * @return 9175 * 0 on success, a negative errno value otherwise and rte_errno is set. 9176 */ 9177 static int 9178 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 9179 struct rte_flow_pattern_template *template, 9180 struct rte_flow_error *error) 9181 { 9182 const struct mlx5_flow_driver_ops *fops; 9183 struct rte_flow_attr attr = {0}; 9184 9185 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9186 return rte_flow_error_set(error, ENOTSUP, 9187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9188 NULL, 9189 "pattern destroy with incorrect steering mode"); 9190 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9191 return fops->pattern_template_destroy(dev, template, error); 9192 } 9193 9194 /** 9195 * Validate flow actions template. 9196 * 9197 * @param[in] dev 9198 * Pointer to the rte_eth_dev structure. 9199 * @param[in] attr 9200 * Pointer to the action template attributes. 9201 * @param[in] actions 9202 * Associated actions (list terminated by the END action). 9203 * @param[in] masks 9204 * List of actions that marks which of the action's member is constant. 9205 * @param[out] error 9206 * Pointer to error structure. 9207 * 9208 * @return 9209 * 0 on success, a negative errno value otherwise and rte_errno is set. 9210 */ 9211 int 9212 mlx5_flow_actions_validate(struct rte_eth_dev *dev, 9213 const struct rte_flow_actions_template_attr *attr, 9214 const struct rte_flow_action actions[], 9215 const struct rte_flow_action masks[], 9216 struct rte_flow_error *error) 9217 { 9218 const struct mlx5_flow_driver_ops *fops; 9219 struct rte_flow_attr fattr = {0}; 9220 9221 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9222 rte_flow_error_set(error, ENOTSUP, 9223 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9224 "actions validate with incorrect steering mode"); 9225 return -ENOTSUP; 9226 } 9227 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9228 return fops->actions_validate(dev, attr, actions, masks, error); 9229 } 9230 9231 /** 9232 * Create flow item template. 9233 * 9234 * @param[in] dev 9235 * Pointer to the rte_eth_dev structure. 9236 * @param[in] attr 9237 * Pointer to the action template attributes. 9238 * @param[in] actions 9239 * Associated actions (list terminated by the END action). 9240 * @param[in] masks 9241 * List of actions that marks which of the action's member is constant. 9242 * @param[out] error 9243 * Pointer to error structure. 9244 * 9245 * @return 9246 * 0 on success, a negative errno value otherwise and rte_errno is set. 9247 */ 9248 static struct rte_flow_actions_template * 9249 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 9250 const struct rte_flow_actions_template_attr *attr, 9251 const struct rte_flow_action actions[], 9252 const struct rte_flow_action masks[], 9253 struct rte_flow_error *error) 9254 { 9255 const struct mlx5_flow_driver_ops *fops; 9256 struct rte_flow_attr fattr = {0}; 9257 9258 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9259 rte_flow_error_set(error, ENOTSUP, 9260 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9261 NULL, 9262 "action create with incorrect steering mode"); 9263 return NULL; 9264 } 9265 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9266 return fops->actions_template_create(dev, attr, actions, masks, error); 9267 } 9268 9269 /** 9270 * Destroy flow action template. 9271 * 9272 * @param[in] dev 9273 * Pointer to the rte_eth_dev structure. 9274 * @param[in] template 9275 * Pointer to the action template to be destroyed. 9276 * @param[out] error 9277 * Pointer to error structure. 9278 * 9279 * @return 9280 * 0 on success, a negative errno value otherwise and rte_errno is set. 9281 */ 9282 static int 9283 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 9284 struct rte_flow_actions_template *template, 9285 struct rte_flow_error *error) 9286 { 9287 const struct mlx5_flow_driver_ops *fops; 9288 struct rte_flow_attr attr = {0}; 9289 9290 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9291 return rte_flow_error_set(error, ENOTSUP, 9292 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9293 NULL, 9294 "action destroy with incorrect steering mode"); 9295 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9296 return fops->actions_template_destroy(dev, template, error); 9297 } 9298 9299 /** 9300 * Create flow table. 9301 * 9302 * @param[in] dev 9303 * Pointer to the rte_eth_dev structure. 9304 * @param[in] attr 9305 * Pointer to the table attributes. 9306 * @param[in] item_templates 9307 * Item template array to be binded to the table. 9308 * @param[in] nb_item_templates 9309 * Number of item template. 9310 * @param[in] action_templates 9311 * Action template array to be binded to the table. 9312 * @param[in] nb_action_templates 9313 * Number of action template. 9314 * @param[out] error 9315 * Pointer to error structure. 9316 * 9317 * @return 9318 * Table on success, NULL otherwise and rte_errno is set. 9319 */ 9320 static struct rte_flow_template_table * 9321 mlx5_flow_table_create(struct rte_eth_dev *dev, 9322 const struct rte_flow_template_table_attr *attr, 9323 struct rte_flow_pattern_template *item_templates[], 9324 uint8_t nb_item_templates, 9325 struct rte_flow_actions_template *action_templates[], 9326 uint8_t nb_action_templates, 9327 struct rte_flow_error *error) 9328 { 9329 const struct mlx5_flow_driver_ops *fops; 9330 struct rte_flow_attr fattr = {0}; 9331 9332 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9333 rte_flow_error_set(error, ENOTSUP, 9334 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9335 NULL, 9336 "table create with incorrect steering mode"); 9337 return NULL; 9338 } 9339 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9340 return fops->template_table_create(dev, 9341 attr, 9342 item_templates, 9343 nb_item_templates, 9344 action_templates, 9345 nb_action_templates, 9346 error); 9347 } 9348 9349 /** 9350 * PMD destroy flow table. 9351 * 9352 * @param[in] dev 9353 * Pointer to the rte_eth_dev structure. 9354 * @param[in] table 9355 * Pointer to the table to be destroyed. 9356 * @param[out] error 9357 * Pointer to error structure. 9358 * 9359 * @return 9360 * 0 on success, a negative errno value otherwise and rte_errno is set. 9361 */ 9362 static int 9363 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 9364 struct rte_flow_template_table *table, 9365 struct rte_flow_error *error) 9366 { 9367 const struct mlx5_flow_driver_ops *fops; 9368 struct rte_flow_attr attr = {0}; 9369 9370 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9371 return rte_flow_error_set(error, ENOTSUP, 9372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9373 NULL, 9374 "table destroy with incorrect steering mode"); 9375 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9376 return fops->template_table_destroy(dev, table, error); 9377 } 9378 9379 /** 9380 * PMD group set miss actions. 9381 * 9382 * @param[in] dev 9383 * Pointer to the rte_eth_dev structure. 9384 * @param[in] attr 9385 * Pointer to group attributes 9386 * @param[in] actions 9387 * Array of actions 9388 * @param[out] error 9389 * Pointer to error structure. 9390 * 9391 * @return 9392 * 0 on success, a negative errno value otherwise and rte_errno is set. 9393 */ 9394 static int 9395 mlx5_flow_group_set_miss_actions(struct rte_eth_dev *dev, 9396 uint32_t group_id, 9397 const struct rte_flow_group_attr *attr, 9398 const struct rte_flow_action actions[], 9399 struct rte_flow_error *error) 9400 { 9401 const struct mlx5_flow_driver_ops *fops; 9402 struct rte_flow_attr fattr = {0}; 9403 9404 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 9405 return rte_flow_error_set(error, ENOTSUP, 9406 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9407 NULL, 9408 "group set miss actions with incorrect steering mode"); 9409 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9410 return fops->group_set_miss_actions(dev, group_id, attr, actions, error); 9411 } 9412 9413 /** 9414 * Allocate a new memory for the counter values wrapped by all the needed 9415 * management. 9416 * 9417 * @param[in] sh 9418 * Pointer to mlx5_dev_ctx_shared object. 9419 * 9420 * @return 9421 * 0 on success, a negative errno value otherwise. 9422 */ 9423 static int 9424 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 9425 { 9426 struct mlx5_counter_stats_mem_mng *mem_mng; 9427 volatile struct flow_counter_stats *raw_data; 9428 int raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES; 9429 int size = (sizeof(struct flow_counter_stats) * 9430 MLX5_COUNTERS_PER_POOL + 9431 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 9432 sizeof(struct mlx5_counter_stats_mem_mng); 9433 size_t pgsize = rte_mem_page_size(); 9434 uint8_t *mem; 9435 int ret; 9436 int i; 9437 9438 if (pgsize == (size_t)-1) { 9439 DRV_LOG(ERR, "Failed to get mem page size"); 9440 rte_errno = ENOMEM; 9441 return -ENOMEM; 9442 } 9443 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 9444 if (!mem) { 9445 rte_errno = ENOMEM; 9446 return -ENOMEM; 9447 } 9448 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 9449 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 9450 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 9451 sh->cdev->pdn, mem, size, 9452 &mem_mng->wm); 9453 if (ret) { 9454 rte_errno = errno; 9455 mlx5_free(mem); 9456 return -rte_errno; 9457 } 9458 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 9459 raw_data = (volatile struct flow_counter_stats *)mem; 9460 for (i = 0; i < raws_n; ++i) { 9461 mem_mng->raws[i].mem_mng = mem_mng; 9462 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 9463 } 9464 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 9465 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, 9466 mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i, 9467 next); 9468 LIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next); 9469 sh->sws_cmng.mem_mng = mem_mng; 9470 return 0; 9471 } 9472 9473 /** 9474 * Set the statistic memory to the new counter pool. 9475 * 9476 * @param[in] sh 9477 * Pointer to mlx5_dev_ctx_shared object. 9478 * @param[in] pool 9479 * Pointer to the pool to set the statistic memory. 9480 * 9481 * @return 9482 * 0 on success, a negative errno value otherwise. 9483 */ 9484 static int 9485 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 9486 struct mlx5_flow_counter_pool *pool) 9487 { 9488 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9489 /* Resize statistic memory once used out. */ 9490 if (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) && 9491 mlx5_flow_create_counter_stat_mem_mng(sh)) { 9492 DRV_LOG(ERR, "Cannot resize counter stat mem."); 9493 return -1; 9494 } 9495 rte_spinlock_lock(&pool->sl); 9496 pool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK; 9497 rte_spinlock_unlock(&pool->sl); 9498 pool->raw_hw = NULL; 9499 return 0; 9500 } 9501 9502 #define MLX5_POOL_QUERY_FREQ_US 1000000 9503 9504 /** 9505 * Set the periodic procedure for triggering asynchronous batch queries for all 9506 * the counter pools. 9507 * 9508 * @param[in] sh 9509 * Pointer to mlx5_dev_ctx_shared object. 9510 */ 9511 void 9512 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 9513 { 9514 uint32_t pools_n, us; 9515 9516 pools_n = rte_atomic_load_explicit(&sh->sws_cmng.n_valid, rte_memory_order_relaxed); 9517 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 9518 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 9519 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 9520 sh->sws_cmng.query_thread_on = 0; 9521 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 9522 } else { 9523 sh->sws_cmng.query_thread_on = 1; 9524 } 9525 } 9526 9527 /** 9528 * The periodic procedure for triggering asynchronous batch queries for all the 9529 * counter pools. This function is probably called by the host thread. 9530 * 9531 * @param[in] arg 9532 * The parameter for the alarm process. 9533 */ 9534 void 9535 mlx5_flow_query_alarm(void *arg) 9536 { 9537 struct mlx5_dev_ctx_shared *sh = arg; 9538 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9539 uint16_t pool_index = cmng->pool_index; 9540 struct mlx5_flow_counter_pool *pool; 9541 uint16_t n_valid; 9542 int ret; 9543 9544 if (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES) 9545 goto set_alarm; 9546 rte_spinlock_lock(&cmng->pool_update_sl); 9547 pool = cmng->pools[pool_index]; 9548 n_valid = cmng->n_valid; 9549 rte_spinlock_unlock(&cmng->pool_update_sl); 9550 /* Set the statistic memory to the new created pool. */ 9551 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 9552 goto set_alarm; 9553 if (pool->raw_hw) 9554 /* There is a pool query in progress. */ 9555 goto set_alarm; 9556 pool->raw_hw = LIST_FIRST(&cmng->free_stat_raws); 9557 if (!pool->raw_hw) 9558 /* No free counter statistics raw memory. */ 9559 goto set_alarm; 9560 /* 9561 * Identify the counters released between query trigger and query 9562 * handle more efficiently. The counter released in this gap period 9563 * should wait for a new round of query as the new arrived packets 9564 * will not be taken into account. 9565 */ 9566 pool->query_gen++; 9567 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 9568 MLX5_COUNTERS_PER_POOL, 9569 NULL, NULL, 9570 pool->raw_hw->mem_mng->wm.lkey, 9571 (void *)(uintptr_t) 9572 pool->raw_hw->data, 9573 sh->devx_comp, 9574 (uint64_t)(uintptr_t)pool); 9575 if (ret) { 9576 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 9577 " %d", pool->min_dcs->id); 9578 pool->raw_hw = NULL; 9579 goto set_alarm; 9580 } 9581 LIST_REMOVE(pool->raw_hw, next); 9582 cmng->pending_queries++; 9583 pool_index++; 9584 if (pool_index >= n_valid) 9585 pool_index = 0; 9586 set_alarm: 9587 cmng->pool_index = pool_index; 9588 mlx5_set_query_alarm(sh); 9589 } 9590 9591 /** 9592 * Check and callback event for new aged flow in the counter pool 9593 * 9594 * @param[in] sh 9595 * Pointer to mlx5_dev_ctx_shared object. 9596 * @param[in] pool 9597 * Pointer to Current counter pool. 9598 */ 9599 static void 9600 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 9601 struct mlx5_flow_counter_pool *pool) 9602 { 9603 struct mlx5_priv *priv; 9604 struct mlx5_flow_counter *cnt; 9605 struct mlx5_age_info *age_info; 9606 struct mlx5_age_param *age_param; 9607 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 9608 struct mlx5_counter_stats_raw *prev = pool->raw; 9609 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 9610 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 9611 uint16_t expected = AGE_CANDIDATE; 9612 uint32_t i; 9613 9614 pool->time_of_last_age_check = curr_time; 9615 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 9616 cnt = MLX5_POOL_GET_CNT(pool, i); 9617 age_param = MLX5_CNT_TO_AGE(cnt); 9618 if (rte_atomic_load_explicit(&age_param->state, 9619 rte_memory_order_relaxed) != AGE_CANDIDATE) 9620 continue; 9621 if (cur->data[i].hits != prev->data[i].hits) { 9622 rte_atomic_store_explicit(&age_param->sec_since_last_hit, 0, 9623 rte_memory_order_relaxed); 9624 continue; 9625 } 9626 if (rte_atomic_fetch_add_explicit(&age_param->sec_since_last_hit, 9627 time_delta, 9628 rte_memory_order_relaxed) + time_delta <= age_param->timeout) 9629 continue; 9630 /** 9631 * Hold the lock first, or if between the 9632 * state AGE_TMOUT and tailq operation the 9633 * release happened, the release procedure 9634 * may delete a non-existent tailq node. 9635 */ 9636 priv = rte_eth_devices[age_param->port_id].data->dev_private; 9637 age_info = GET_PORT_AGE_INFO(priv); 9638 rte_spinlock_lock(&age_info->aged_sl); 9639 if (rte_atomic_compare_exchange_strong_explicit(&age_param->state, &expected, 9640 AGE_TMOUT, 9641 rte_memory_order_relaxed, 9642 rte_memory_order_relaxed)) { 9643 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 9644 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 9645 } 9646 rte_spinlock_unlock(&age_info->aged_sl); 9647 } 9648 mlx5_age_event_prepare(sh); 9649 } 9650 9651 /** 9652 * Handler for the HW respond about ready values from an asynchronous batch 9653 * query. This function is probably called by the host thread. 9654 * 9655 * @param[in] sh 9656 * The pointer to the shared device context. 9657 * @param[in] async_id 9658 * The Devx async ID. 9659 * @param[in] status 9660 * The status of the completion. 9661 */ 9662 void 9663 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 9664 uint64_t async_id, int status) 9665 { 9666 struct mlx5_flow_counter_pool *pool = 9667 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 9668 struct mlx5_counter_stats_raw *raw_to_free; 9669 uint8_t query_gen = pool->query_gen ^ 1; 9670 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9671 enum mlx5_counter_type cnt_type = 9672 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 9673 MLX5_COUNTER_TYPE_ORIGIN; 9674 9675 if (unlikely(status)) { 9676 raw_to_free = pool->raw_hw; 9677 } else { 9678 raw_to_free = pool->raw; 9679 if (pool->is_aged) 9680 mlx5_flow_aging_check(sh, pool); 9681 rte_spinlock_lock(&pool->sl); 9682 pool->raw = pool->raw_hw; 9683 rte_spinlock_unlock(&pool->sl); 9684 /* Be sure the new raw counters data is updated in memory. */ 9685 rte_io_wmb(); 9686 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 9687 rte_spinlock_lock(&cmng->csl[cnt_type]); 9688 TAILQ_CONCAT(&cmng->counters[cnt_type], 9689 &pool->counters[query_gen], next); 9690 rte_spinlock_unlock(&cmng->csl[cnt_type]); 9691 } 9692 } 9693 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, raw_to_free, next); 9694 pool->raw_hw = NULL; 9695 sh->sws_cmng.pending_queries--; 9696 } 9697 9698 static int 9699 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 9700 const struct flow_grp_info *grp_info, 9701 struct rte_flow_error *error) 9702 { 9703 if (grp_info->transfer && grp_info->external && 9704 grp_info->fdb_def_rule) { 9705 if (group == UINT32_MAX) 9706 return rte_flow_error_set 9707 (error, EINVAL, 9708 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 9709 NULL, 9710 "group index not supported"); 9711 *table = group + 1; 9712 } else { 9713 *table = group; 9714 } 9715 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 9716 return 0; 9717 } 9718 9719 /** 9720 * Translate the rte_flow group index to HW table value. 9721 * 9722 * If tunnel offload is disabled, all group ids converted to flow table 9723 * id using the standard method. 9724 * If tunnel offload is enabled, group id can be converted using the 9725 * standard or tunnel conversion method. Group conversion method 9726 * selection depends on flags in `grp_info` parameter: 9727 * - Internal (grp_info.external == 0) groups conversion uses the 9728 * standard method. 9729 * - Group ids in JUMP action converted with the tunnel conversion. 9730 * - Group id in rule attribute conversion depends on a rule type and 9731 * group id value: 9732 * ** non zero group attributes converted with the tunnel method 9733 * ** zero group attribute in non-tunnel rule is converted using the 9734 * standard method - there's only one root table 9735 * ** zero group attribute in steer tunnel rule is converted with the 9736 * standard method - single root table 9737 * ** zero group attribute in match tunnel rule is a special OvS 9738 * case: that value is used for portability reasons. That group 9739 * id is converted with the tunnel conversion method. 9740 * 9741 * @param[in] dev 9742 * Port device 9743 * @param[in] tunnel 9744 * PMD tunnel offload object 9745 * @param[in] group 9746 * rte_flow group index value. 9747 * @param[out] table 9748 * HW table value. 9749 * @param[in] grp_info 9750 * flags used for conversion 9751 * @param[out] error 9752 * Pointer to error structure. 9753 * 9754 * @return 9755 * 0 on success, a negative errno value otherwise and rte_errno is set. 9756 */ 9757 int 9758 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 9759 const struct mlx5_flow_tunnel *tunnel, 9760 uint32_t group, uint32_t *table, 9761 const struct flow_grp_info *grp_info, 9762 struct rte_flow_error *error) 9763 { 9764 int ret; 9765 bool standard_translation; 9766 9767 if (!grp_info->skip_scale && grp_info->external && 9768 group < MLX5_MAX_TABLES_EXTERNAL) 9769 group *= MLX5_FLOW_TABLE_FACTOR; 9770 if (is_tunnel_offload_active(dev)) { 9771 standard_translation = !grp_info->external || 9772 grp_info->std_tbl_fix; 9773 } else { 9774 standard_translation = true; 9775 } 9776 DRV_LOG(DEBUG, 9777 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 9778 dev->data->port_id, group, grp_info->transfer, 9779 grp_info->external, grp_info->fdb_def_rule, 9780 standard_translation ? "STANDARD" : "TUNNEL"); 9781 if (standard_translation) 9782 ret = flow_group_to_table(dev->data->port_id, group, table, 9783 grp_info, error); 9784 else 9785 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 9786 table, error); 9787 9788 return ret; 9789 } 9790 9791 /** 9792 * Discover availability of metadata reg_c's. 9793 * 9794 * Iteratively use test flows to check availability. 9795 * 9796 * @param[in] dev 9797 * Pointer to the Ethernet device structure. 9798 * 9799 * @return 9800 * 0 on success, a negative errno value otherwise and rte_errno is set. 9801 */ 9802 int 9803 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 9804 { 9805 struct mlx5_priv *priv = dev->data->dev_private; 9806 enum modify_reg idx; 9807 int n = 0; 9808 9809 /* reg_c[0] and reg_c[1] are reserved. */ 9810 priv->sh->flow_mreg_c[n++] = REG_C_0; 9811 priv->sh->flow_mreg_c[n++] = REG_C_1; 9812 /* Discover availability of other reg_c's. */ 9813 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 9814 struct rte_flow_attr attr = { 9815 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 9816 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 9817 .ingress = 1, 9818 }; 9819 struct rte_flow_item items[] = { 9820 [0] = { 9821 .type = RTE_FLOW_ITEM_TYPE_END, 9822 }, 9823 }; 9824 struct rte_flow_action actions[] = { 9825 [0] = { 9826 .type = (enum rte_flow_action_type) 9827 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 9828 .conf = &(struct mlx5_flow_action_copy_mreg){ 9829 .src = REG_C_1, 9830 .dst = idx, 9831 }, 9832 }, 9833 [1] = { 9834 .type = RTE_FLOW_ACTION_TYPE_JUMP, 9835 .conf = &(struct rte_flow_action_jump){ 9836 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 9837 }, 9838 }, 9839 [2] = { 9840 .type = RTE_FLOW_ACTION_TYPE_END, 9841 }, 9842 }; 9843 uint32_t flow_idx; 9844 struct rte_flow *flow; 9845 struct rte_flow_error error; 9846 9847 if (!priv->sh->config.dv_flow_en) 9848 break; 9849 /* Create internal flow, validation skips copy action. */ 9850 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 9851 items, actions, false, &error); 9852 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9853 flow_idx); 9854 if (!flow) 9855 continue; 9856 priv->sh->flow_mreg_c[n++] = idx; 9857 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 9858 } 9859 for (; n < MLX5_MREG_C_NUM; ++n) 9860 priv->sh->flow_mreg_c[n] = REG_NON; 9861 priv->sh->metadata_regc_check_flag = 1; 9862 return 0; 9863 } 9864 9865 int 9866 save_dump_file(const uint8_t *data, uint32_t size, 9867 uint32_t type, uint64_t id, void *arg, FILE *file) 9868 { 9869 char line[BUF_SIZE]; 9870 uint32_t out = 0; 9871 uint32_t k; 9872 uint32_t actions_num; 9873 struct rte_flow_query_count *count; 9874 9875 memset(line, 0, BUF_SIZE); 9876 switch (type) { 9877 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 9878 actions_num = *(uint32_t *)(arg); 9879 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 9880 type, id, actions_num); 9881 break; 9882 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 9883 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 9884 type, id); 9885 break; 9886 case DR_DUMP_REC_TYPE_PMD_COUNTER: 9887 count = (struct rte_flow_query_count *)arg; 9888 fprintf(file, 9889 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 9890 type, id, count->hits, count->bytes); 9891 return 0; 9892 default: 9893 return -1; 9894 } 9895 9896 for (k = 0; k < size; k++) { 9897 /* Make sure we do not overrun the line buffer length. */ 9898 if (out >= BUF_SIZE - 4) { 9899 line[out] = '\0'; 9900 break; 9901 } 9902 out += snprintf(line + out, BUF_SIZE - out, "%02x", 9903 (data[k]) & 0xff); 9904 } 9905 fprintf(file, "%s\n", line); 9906 return 0; 9907 } 9908 9909 int 9910 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 9911 struct rte_flow_query_count *count, struct rte_flow_error *error) 9912 { 9913 struct rte_flow_action action[2]; 9914 enum mlx5_flow_drv_type ftype; 9915 const struct mlx5_flow_driver_ops *fops; 9916 9917 if (!flow) { 9918 return rte_flow_error_set(error, ENOENT, 9919 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9920 NULL, 9921 "invalid flow handle"); 9922 } 9923 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 9924 action[1].type = RTE_FLOW_ACTION_TYPE_END; 9925 if (flow->counter) { 9926 memset(count, 0, sizeof(struct rte_flow_query_count)); 9927 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 9928 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 9929 ftype < MLX5_FLOW_TYPE_MAX); 9930 fops = flow_get_drv_ops(ftype); 9931 return fops->query(dev, flow, action, count, error); 9932 } 9933 return -1; 9934 } 9935 9936 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9937 /** 9938 * Dump flow ipool data to file 9939 * 9940 * @param[in] dev 9941 * The pointer to Ethernet device. 9942 * @param[in] file 9943 * A pointer to a file for output. 9944 * @param[out] error 9945 * Perform verbose error reporting if not NULL. PMDs initialize this 9946 * structure in case of error only. 9947 * @return 9948 * 0 on success, a negative value otherwise. 9949 */ 9950 int 9951 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 9952 struct rte_flow *flow, FILE *file, 9953 struct rte_flow_error *error) 9954 { 9955 struct mlx5_priv *priv = dev->data->dev_private; 9956 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9957 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9958 uint32_t handle_idx; 9959 struct mlx5_flow_handle *dh; 9960 struct rte_flow_query_count count; 9961 uint32_t actions_num; 9962 const uint8_t *data; 9963 size_t size; 9964 uint64_t id; 9965 uint32_t type; 9966 void *action = NULL; 9967 9968 if (!flow) { 9969 return rte_flow_error_set(error, ENOENT, 9970 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9971 NULL, 9972 "invalid flow handle"); 9973 } 9974 handle_idx = flow->dev_handles; 9975 /* query counter */ 9976 if (flow->counter && 9977 (!mlx5_counter_query(dev, flow->counter, false, 9978 &count.hits, &count.bytes, &action)) && action) { 9979 id = (uint64_t)(uintptr_t)action; 9980 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9981 save_dump_file(NULL, 0, type, 9982 id, (void *)&count, file); 9983 } 9984 9985 while (handle_idx) { 9986 dh = mlx5_ipool_get(priv->sh->ipool 9987 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 9988 if (!dh) 9989 continue; 9990 handle_idx = dh->next.next; 9991 9992 /* Get modify_hdr and encap_decap buf from ipools. */ 9993 encap_decap = NULL; 9994 modify_hdr = dh->dvh.modify_hdr; 9995 9996 if (dh->dvh.rix_encap_decap) { 9997 encap_decap = mlx5_ipool_get(priv->sh->ipool 9998 [MLX5_IPOOL_DECAP_ENCAP], 9999 dh->dvh.rix_encap_decap); 10000 } 10001 if (modify_hdr) { 10002 data = (const uint8_t *)modify_hdr->actions; 10003 size = (size_t)(modify_hdr->actions_num) * 8; 10004 id = (uint64_t)(uintptr_t)modify_hdr->action; 10005 actions_num = modify_hdr->actions_num; 10006 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10007 save_dump_file(data, size, type, id, 10008 (void *)(&actions_num), file); 10009 } 10010 if (encap_decap) { 10011 data = encap_decap->buf; 10012 size = encap_decap->size; 10013 id = (uint64_t)(uintptr_t)encap_decap->action; 10014 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 10015 save_dump_file(data, size, type, 10016 id, NULL, file); 10017 } 10018 } 10019 return 0; 10020 } 10021 10022 /** 10023 * Dump all flow's encap_decap/modify_hdr/counter data to file 10024 * 10025 * @param[in] dev 10026 * The pointer to Ethernet device. 10027 * @param[in] file 10028 * A pointer to a file for output. 10029 * @param[out] error 10030 * Perform verbose error reporting if not NULL. PMDs initialize this 10031 * structure in case of error only. 10032 * @return 10033 * 0 on success, a negative value otherwise. 10034 */ 10035 static int 10036 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 10037 FILE *file, struct rte_flow_error *error __rte_unused) 10038 { 10039 struct mlx5_priv *priv = dev->data->dev_private; 10040 struct mlx5_dev_ctx_shared *sh = priv->sh; 10041 struct mlx5_hlist *h; 10042 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 10043 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 10044 struct rte_flow_query_count count; 10045 uint32_t actions_num; 10046 const uint8_t *data; 10047 size_t size; 10048 uint64_t id; 10049 uint32_t type; 10050 uint32_t i; 10051 uint32_t j; 10052 struct mlx5_list_inconst *l_inconst; 10053 struct mlx5_list_entry *e; 10054 int lcore_index; 10055 struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; 10056 uint32_t max; 10057 void *action; 10058 10059 /* encap_decap hlist is lcore_share, get global core cache. */ 10060 i = MLX5_LIST_GLOBAL; 10061 h = sh->encaps_decaps; 10062 if (h) { 10063 for (j = 0; j <= h->mask; j++) { 10064 l_inconst = &h->buckets[j].l; 10065 if (!l_inconst || !l_inconst->cache[i]) 10066 continue; 10067 10068 e = LIST_FIRST(&l_inconst->cache[i]->h); 10069 while (e) { 10070 encap_decap = 10071 (struct mlx5_flow_dv_encap_decap_resource *)e; 10072 data = encap_decap->buf; 10073 size = encap_decap->size; 10074 id = (uint64_t)(uintptr_t)encap_decap->action; 10075 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 10076 save_dump_file(data, size, type, 10077 id, NULL, file); 10078 e = LIST_NEXT(e, next); 10079 } 10080 } 10081 } 10082 10083 /* get modify_hdr */ 10084 h = sh->modify_cmds; 10085 if (h) { 10086 lcore_index = rte_lcore_index(rte_lcore_id()); 10087 if (unlikely(lcore_index == -1)) { 10088 lcore_index = MLX5_LIST_NLCORE; 10089 rte_spinlock_lock(&h->l_const.lcore_lock); 10090 } 10091 i = lcore_index; 10092 10093 if (lcore_index == MLX5_LIST_NLCORE) { 10094 for (i = 0; i <= (uint32_t)lcore_index; i++) { 10095 for (j = 0; j <= h->mask; j++) { 10096 l_inconst = &h->buckets[j].l; 10097 if (!l_inconst || !l_inconst->cache[i]) 10098 continue; 10099 10100 e = LIST_FIRST(&l_inconst->cache[i]->h); 10101 while (e) { 10102 modify_hdr = 10103 (struct mlx5_flow_dv_modify_hdr_resource *)e; 10104 data = (const uint8_t *)modify_hdr->actions; 10105 size = (size_t)(modify_hdr->actions_num) * 8; 10106 actions_num = modify_hdr->actions_num; 10107 id = (uint64_t)(uintptr_t)modify_hdr->action; 10108 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10109 save_dump_file(data, size, type, id, 10110 (void *)(&actions_num), file); 10111 e = LIST_NEXT(e, next); 10112 } 10113 } 10114 } 10115 } else { 10116 for (j = 0; j <= h->mask; j++) { 10117 l_inconst = &h->buckets[j].l; 10118 if (!l_inconst || !l_inconst->cache[i]) 10119 continue; 10120 10121 e = LIST_FIRST(&l_inconst->cache[i]->h); 10122 while (e) { 10123 modify_hdr = 10124 (struct mlx5_flow_dv_modify_hdr_resource *)e; 10125 data = (const uint8_t *)modify_hdr->actions; 10126 size = (size_t)(modify_hdr->actions_num) * 8; 10127 actions_num = modify_hdr->actions_num; 10128 id = (uint64_t)(uintptr_t)modify_hdr->action; 10129 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10130 save_dump_file(data, size, type, id, 10131 (void *)(&actions_num), file); 10132 e = LIST_NEXT(e, next); 10133 } 10134 } 10135 } 10136 10137 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 10138 rte_spinlock_unlock(&h->l_const.lcore_lock); 10139 } 10140 10141 /* get counter */ 10142 MLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM); 10143 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 10144 for (j = 1; j <= max; j++) { 10145 action = NULL; 10146 if ((!mlx5_counter_query(dev, j, false, &count.hits, 10147 &count.bytes, &action)) && action) { 10148 id = (uint64_t)(uintptr_t)action; 10149 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 10150 save_dump_file(NULL, 0, type, 10151 id, (void *)&count, file); 10152 } 10153 } 10154 return 0; 10155 } 10156 #endif 10157 10158 /** 10159 * Dump flow raw hw data to file 10160 * 10161 * @param[in] dev 10162 * The pointer to Ethernet device. 10163 * @param[in] file 10164 * A pointer to a file for output. 10165 * @param[out] error 10166 * Perform verbose error reporting if not NULL. PMDs initialize this 10167 * structure in case of error only. 10168 * @return 10169 * 0 on success, a negative value otherwise. 10170 */ 10171 int 10172 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 10173 FILE *file, 10174 struct rte_flow_error *error __rte_unused) 10175 { 10176 struct mlx5_priv *priv = dev->data->dev_private; 10177 struct mlx5_dev_ctx_shared *sh = priv->sh; 10178 uint32_t handle_idx; 10179 int ret; 10180 struct mlx5_flow_handle *dh; 10181 struct rte_flow *flow; 10182 10183 if (!sh->config.dv_flow_en) { 10184 if (fputs("device dv flow disabled\n", file) <= 0) 10185 return -errno; 10186 return -ENOTSUP; 10187 } 10188 10189 /* dump all */ 10190 if (!flow_idx) { 10191 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10192 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 10193 return -EINVAL; 10194 10195 if (sh->config.dv_flow_en == 2) 10196 return mlx5dr_debug_dump(priv->dr_ctx, file); 10197 #endif 10198 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 10199 sh->rx_domain, 10200 sh->tx_domain, file); 10201 } 10202 /* dump one */ 10203 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 10204 (uintptr_t)(void *)flow_idx); 10205 if (!flow) 10206 return -EINVAL; 10207 10208 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10209 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 10210 #endif 10211 handle_idx = flow->dev_handles; 10212 while (handle_idx) { 10213 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 10214 handle_idx); 10215 if (!dh) 10216 return -ENOENT; 10217 if (dh->drv_flow) { 10218 if (sh->config.dv_flow_en == 2) 10219 return -ENOTSUP; 10220 10221 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 10222 file); 10223 if (ret) 10224 return -ENOENT; 10225 } 10226 handle_idx = dh->next.next; 10227 } 10228 return 0; 10229 } 10230 10231 /** 10232 * Get aged-out flows. 10233 * 10234 * @param[in] dev 10235 * Pointer to the Ethernet device structure. 10236 * @param[in] context 10237 * The address of an array of pointers to the aged-out flows contexts. 10238 * @param[in] nb_countexts 10239 * The length of context array pointers. 10240 * @param[out] error 10241 * Perform verbose error reporting if not NULL. Initialized in case of 10242 * error only. 10243 * 10244 * @return 10245 * how many contexts get in success, otherwise negative errno value. 10246 * if nb_contexts is 0, return the amount of all aged contexts. 10247 * if nb_contexts is not 0 , return the amount of aged flows reported 10248 * in the context array. 10249 */ 10250 int 10251 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 10252 uint32_t nb_contexts, struct rte_flow_error *error) 10253 { 10254 struct rte_flow_attr attr = { .transfer = 0 }; 10255 10256 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->get_aged_flows 10257 (dev, contexts, nb_contexts, error); 10258 } 10259 10260 /** 10261 * Get aged-out flows per HWS queue. 10262 * 10263 * @param[in] dev 10264 * Pointer to the Ethernet device structure. 10265 * @param[in] queue_id 10266 * Flow queue to query. 10267 * @param[in] context 10268 * The address of an array of pointers to the aged-out flows contexts. 10269 * @param[in] nb_countexts 10270 * The length of context array pointers. 10271 * @param[out] error 10272 * Perform verbose error reporting if not NULL. Initialized in case of 10273 * error only. 10274 * 10275 * @return 10276 * how many contexts get in success, otherwise negative errno value. 10277 * if nb_contexts is 0, return the amount of all aged contexts. 10278 * if nb_contexts is not 0 , return the amount of aged flows reported 10279 * in the context array. 10280 */ 10281 int 10282 mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 10283 void **contexts, uint32_t nb_contexts, 10284 struct rte_flow_error *error) 10285 { 10286 const struct mlx5_flow_driver_ops *fops; 10287 struct rte_flow_attr attr = { 0 }; 10288 10289 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_HW) { 10290 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 10291 return fops->get_q_aged_flows(dev, queue_id, contexts, 10292 nb_contexts, error); 10293 } 10294 DRV_LOG(ERR, "port %u queue %u get aged flows is not supported.", 10295 dev->data->port_id, queue_id); 10296 return rte_flow_error_set(error, ENOTSUP, 10297 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10298 "get Q aged flows with incorrect steering mode"); 10299 } 10300 10301 /* Wrapper for driver action_validate op callback */ 10302 static int 10303 flow_drv_action_validate(struct rte_eth_dev *dev, 10304 const struct rte_flow_indir_action_conf *conf, 10305 const struct rte_flow_action *action, 10306 const struct mlx5_flow_driver_ops *fops, 10307 struct rte_flow_error *error) 10308 { 10309 static const char err_msg[] = "indirect action validation unsupported"; 10310 10311 if (!fops->action_validate) { 10312 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10313 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10314 NULL, err_msg); 10315 return -rte_errno; 10316 } 10317 return fops->action_validate(dev, conf, action, error); 10318 } 10319 10320 /** 10321 * Destroys the shared action by handle. 10322 * 10323 * @param dev 10324 * Pointer to Ethernet device structure. 10325 * @param[in] handle 10326 * Handle for the indirect action object to be destroyed. 10327 * @param[out] error 10328 * Perform verbose error reporting if not NULL. PMDs initialize this 10329 * structure in case of error only. 10330 * 10331 * @return 10332 * 0 on success, a negative errno value otherwise and rte_errno is set. 10333 * 10334 * @note: wrapper for driver action_create op callback. 10335 */ 10336 static int 10337 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 10338 struct rte_flow_action_handle *handle, 10339 struct rte_flow_error *error) 10340 { 10341 static const char err_msg[] = "indirect action destruction unsupported"; 10342 struct rte_flow_attr attr = { .transfer = 0 }; 10343 const struct mlx5_flow_driver_ops *fops = 10344 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10345 10346 if (!fops->action_destroy) { 10347 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10348 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10349 NULL, err_msg); 10350 return -rte_errno; 10351 } 10352 return fops->action_destroy(dev, handle, error); 10353 } 10354 10355 /* Wrapper for driver action_destroy op callback */ 10356 static int 10357 flow_drv_action_update(struct rte_eth_dev *dev, 10358 struct rte_flow_action_handle *handle, 10359 const void *update, 10360 const struct mlx5_flow_driver_ops *fops, 10361 struct rte_flow_error *error) 10362 { 10363 static const char err_msg[] = "indirect action update unsupported"; 10364 10365 if (!fops->action_update) { 10366 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10367 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10368 NULL, err_msg); 10369 return -rte_errno; 10370 } 10371 return fops->action_update(dev, handle, update, error); 10372 } 10373 10374 /* Wrapper for driver action_destroy op callback */ 10375 static int 10376 flow_drv_action_query(struct rte_eth_dev *dev, 10377 const struct rte_flow_action_handle *handle, 10378 void *data, 10379 const struct mlx5_flow_driver_ops *fops, 10380 struct rte_flow_error *error) 10381 { 10382 static const char err_msg[] = "indirect action query unsupported"; 10383 10384 if (!fops->action_query) { 10385 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10386 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10387 NULL, err_msg); 10388 return -rte_errno; 10389 } 10390 return fops->action_query(dev, handle, data, error); 10391 } 10392 10393 /** 10394 * Create indirect action for reuse in multiple flow rules. 10395 * 10396 * @param dev 10397 * Pointer to Ethernet device structure. 10398 * @param conf 10399 * Pointer to indirect action object configuration. 10400 * @param[in] action 10401 * Action configuration for indirect action object creation. 10402 * @param[out] error 10403 * Perform verbose error reporting if not NULL. PMDs initialize this 10404 * structure in case of error only. 10405 * @return 10406 * A valid handle in case of success, NULL otherwise and rte_errno is set. 10407 */ 10408 static struct rte_flow_action_handle * 10409 mlx5_action_handle_create(struct rte_eth_dev *dev, 10410 const struct rte_flow_indir_action_conf *conf, 10411 const struct rte_flow_action *action, 10412 struct rte_flow_error *error) 10413 { 10414 static const char err_msg[] = "indirect action creation unsupported"; 10415 struct rte_flow_attr attr = { .transfer = 0 }; 10416 const struct mlx5_flow_driver_ops *fops = 10417 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10418 10419 if (flow_drv_action_validate(dev, conf, action, fops, error)) 10420 return NULL; 10421 if (!fops->action_create) { 10422 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10423 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10424 NULL, err_msg); 10425 return NULL; 10426 } 10427 return fops->action_create(dev, conf, action, error); 10428 } 10429 10430 /** 10431 * Updates inplace the indirect action configuration pointed by *handle* 10432 * with the configuration provided as *update* argument. 10433 * The update of the indirect action configuration effects all flow rules 10434 * reusing the action via handle. 10435 * 10436 * @param dev 10437 * Pointer to Ethernet device structure. 10438 * @param[in] handle 10439 * Handle for the indirect action to be updated. 10440 * @param[in] update 10441 * Action specification used to modify the action pointed by handle. 10442 * *update* could be of same type with the action pointed by the *handle* 10443 * handle argument, or some other structures like a wrapper, depending on 10444 * the indirect action type. 10445 * @param[out] error 10446 * Perform verbose error reporting if not NULL. PMDs initialize this 10447 * structure in case of error only. 10448 * 10449 * @return 10450 * 0 on success, a negative errno value otherwise and rte_errno is set. 10451 */ 10452 static int 10453 mlx5_action_handle_update(struct rte_eth_dev *dev, 10454 struct rte_flow_action_handle *handle, 10455 const void *update, 10456 struct rte_flow_error *error) 10457 { 10458 struct rte_flow_attr attr = { .transfer = 0 }; 10459 const struct mlx5_flow_driver_ops *fops = 10460 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10461 int ret; 10462 uint32_t act_idx = (uint32_t)(uintptr_t)handle; 10463 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 10464 10465 switch (type) { 10466 case MLX5_INDIRECT_ACTION_TYPE_CT: 10467 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 10468 ret = 0; 10469 break; 10470 default: 10471 ret = flow_drv_action_validate(dev, NULL, 10472 (const struct rte_flow_action *)update, 10473 fops, error); 10474 } 10475 if (ret) 10476 return ret; 10477 return flow_drv_action_update(dev, handle, update, fops, 10478 error); 10479 } 10480 10481 /** 10482 * Query the indirect action by handle. 10483 * 10484 * This function allows retrieving action-specific data such as counters. 10485 * Data is gathered by special action which may be present/referenced in 10486 * more than one flow rule definition. 10487 * 10488 * see @RTE_FLOW_ACTION_TYPE_COUNT 10489 * 10490 * @param dev 10491 * Pointer to Ethernet device structure. 10492 * @param[in] handle 10493 * Handle for the indirect action to query. 10494 * @param[in, out] data 10495 * Pointer to storage for the associated query data type. 10496 * @param[out] error 10497 * Perform verbose error reporting if not NULL. PMDs initialize this 10498 * structure in case of error only. 10499 * 10500 * @return 10501 * 0 on success, a negative errno value otherwise and rte_errno is set. 10502 */ 10503 static int 10504 mlx5_action_handle_query(struct rte_eth_dev *dev, 10505 const struct rte_flow_action_handle *handle, 10506 void *data, 10507 struct rte_flow_error *error) 10508 { 10509 struct rte_flow_attr attr = { .transfer = 0 }; 10510 const struct mlx5_flow_driver_ops *fops = 10511 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10512 10513 return flow_drv_action_query(dev, handle, data, fops, error); 10514 } 10515 10516 static int 10517 mlx5_action_handle_query_update(struct rte_eth_dev *dev, 10518 struct rte_flow_action_handle *handle, 10519 const void *update, void *query, 10520 enum rte_flow_query_update_mode qu_mode, 10521 struct rte_flow_error *error) 10522 { 10523 struct rte_flow_attr attr = { .transfer = 0 }; 10524 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, &attr); 10525 const struct mlx5_flow_driver_ops *fops; 10526 10527 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10528 return rte_flow_error_set(error, ENOTSUP, 10529 RTE_FLOW_ERROR_TYPE_ACTION, 10530 NULL, "invalid driver type"); 10531 fops = flow_get_drv_ops(drv_type); 10532 if (!fops || !fops->action_query_update) 10533 return rte_flow_error_set(error, ENOTSUP, 10534 RTE_FLOW_ERROR_TYPE_ACTION, 10535 NULL, "no query_update handler"); 10536 return fops->action_query_update(dev, handle, update, 10537 query, qu_mode, error); 10538 } 10539 10540 10541 #define MLX5_DRV_FOPS_OR_ERR(dev, fops, drv_cb, ret) \ 10542 { \ 10543 struct rte_flow_attr attr = { .transfer = 0 }; \ 10544 enum mlx5_flow_drv_type drv_type = flow_get_drv_type((dev), &attr); \ 10545 if (drv_type == MLX5_FLOW_TYPE_MIN || \ 10546 drv_type == MLX5_FLOW_TYPE_MAX) { \ 10547 rte_flow_error_set(error, ENOTSUP, \ 10548 RTE_FLOW_ERROR_TYPE_ACTION, \ 10549 NULL, "invalid driver type"); \ 10550 return ret; \ 10551 } \ 10552 (fops) = flow_get_drv_ops(drv_type); \ 10553 if (!(fops) || !(fops)->drv_cb) { \ 10554 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, \ 10555 NULL, "no action_list handler"); \ 10556 return ret; \ 10557 } \ 10558 } 10559 10560 static struct rte_flow_action_list_handle * 10561 mlx5_action_list_handle_create(struct rte_eth_dev *dev, 10562 const struct rte_flow_indir_action_conf *conf, 10563 const struct rte_flow_action *actions, 10564 struct rte_flow_error *error) 10565 { 10566 const struct mlx5_flow_driver_ops *fops; 10567 10568 MLX5_DRV_FOPS_OR_ERR(dev, fops, action_list_handle_create, NULL); 10569 return fops->action_list_handle_create(dev, conf, actions, error); 10570 } 10571 10572 static int 10573 mlx5_action_list_handle_destroy(struct rte_eth_dev *dev, 10574 struct rte_flow_action_list_handle *handle, 10575 struct rte_flow_error *error) 10576 { 10577 const struct mlx5_flow_driver_ops *fops; 10578 10579 MLX5_DRV_FOPS_OR_ERR(dev, fops, action_list_handle_destroy, ENOTSUP); 10580 return fops->action_list_handle_destroy(dev, handle, error); 10581 } 10582 10583 static int 10584 mlx5_flow_action_list_handle_query_update(struct rte_eth_dev *dev, 10585 const 10586 struct rte_flow_action_list_handle *handle, 10587 const void **update, void **query, 10588 enum rte_flow_query_update_mode mode, 10589 struct rte_flow_error *error) 10590 { 10591 const struct mlx5_flow_driver_ops *fops; 10592 10593 MLX5_DRV_FOPS_OR_ERR(dev, fops, 10594 action_list_handle_query_update, ENOTSUP); 10595 return fops->action_list_handle_query_update(dev, handle, update, query, 10596 mode, error); 10597 } 10598 static int 10599 mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, 10600 const struct rte_flow_template_table *table, 10601 const struct rte_flow_item pattern[], 10602 uint8_t pattern_template_index, 10603 uint32_t *hash, struct rte_flow_error *error) 10604 { 10605 struct rte_flow_attr attr = { .transfer = 0 }; 10606 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, &attr); 10607 const struct mlx5_flow_driver_ops *fops; 10608 10609 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10610 return rte_flow_error_set(error, ENOTSUP, 10611 RTE_FLOW_ERROR_TYPE_ACTION, 10612 NULL, "invalid driver type"); 10613 fops = flow_get_drv_ops(drv_type); 10614 if (!fops || !fops->action_query_update) 10615 return rte_flow_error_set(error, ENOTSUP, 10616 RTE_FLOW_ERROR_TYPE_ACTION, 10617 NULL, "no query_update handler"); 10618 return fops->flow_calc_table_hash(dev, table, pattern, pattern_template_index, 10619 hash, error); 10620 } 10621 10622 static int 10623 mlx5_flow_calc_encap_hash(struct rte_eth_dev *dev, 10624 const struct rte_flow_item pattern[], 10625 enum rte_flow_encap_hash_field dest_field, 10626 uint8_t *hash, 10627 struct rte_flow_error *error) 10628 { 10629 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, NULL); 10630 const struct mlx5_flow_driver_ops *fops; 10631 10632 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10633 return rte_flow_error_set(error, ENOTSUP, 10634 RTE_FLOW_ERROR_TYPE_ACTION, 10635 NULL, "invalid driver type"); 10636 fops = flow_get_drv_ops(drv_type); 10637 if (!fops || !fops->flow_calc_encap_hash) 10638 return rte_flow_error_set(error, ENOTSUP, 10639 RTE_FLOW_ERROR_TYPE_ACTION, 10640 NULL, "no calc encap hash handler"); 10641 return fops->flow_calc_encap_hash(dev, pattern, dest_field, hash, error); 10642 } 10643 10644 static int 10645 mlx5_template_table_resize(struct rte_eth_dev *dev, 10646 struct rte_flow_template_table *table, 10647 uint32_t nb_rules, struct rte_flow_error *error) 10648 { 10649 const struct mlx5_flow_driver_ops *fops; 10650 10651 MLX5_DRV_FOPS_OR_ERR(dev, fops, table_resize, ENOTSUP); 10652 return fops->table_resize(dev, table, nb_rules, error); 10653 } 10654 10655 static int 10656 mlx5_table_resize_complete(struct rte_eth_dev *dev, 10657 struct rte_flow_template_table *table, 10658 struct rte_flow_error *error) 10659 { 10660 const struct mlx5_flow_driver_ops *fops; 10661 10662 MLX5_DRV_FOPS_OR_ERR(dev, fops, table_resize_complete, ENOTSUP); 10663 return fops->table_resize_complete(dev, table, error); 10664 } 10665 10666 static int 10667 mlx5_flow_async_update_resized(struct rte_eth_dev *dev, uint32_t queue, 10668 const struct rte_flow_op_attr *op_attr, 10669 struct rte_flow *rule, void *user_data, 10670 struct rte_flow_error *error) 10671 { 10672 const struct mlx5_flow_driver_ops *fops; 10673 10674 MLX5_DRV_FOPS_OR_ERR(dev, fops, flow_update_resized, ENOTSUP); 10675 return fops->flow_update_resized(dev, queue, op_attr, rule, user_data, error); 10676 } 10677 10678 /** 10679 * Destroy all indirect actions (shared RSS). 10680 * 10681 * @param dev 10682 * Pointer to Ethernet device. 10683 * 10684 * @return 10685 * 0 on success, a negative errno value otherwise and rte_errno is set. 10686 */ 10687 int 10688 mlx5_action_handle_flush(struct rte_eth_dev *dev) 10689 { 10690 struct rte_flow_error error; 10691 struct mlx5_priv *priv = dev->data->dev_private; 10692 struct mlx5_shared_action_rss *shared_rss; 10693 int ret = 0; 10694 uint32_t idx; 10695 10696 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 10697 priv->rss_shared_actions, idx, shared_rss, next) { 10698 ret |= mlx5_action_handle_destroy(dev, 10699 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 10700 } 10701 return ret; 10702 } 10703 10704 /** 10705 * Validate existing indirect actions against current device configuration 10706 * and attach them to device resources. 10707 * 10708 * @param dev 10709 * Pointer to Ethernet device. 10710 * 10711 * @return 10712 * 0 on success, a negative errno value otherwise and rte_errno is set. 10713 */ 10714 int 10715 mlx5_action_handle_attach(struct rte_eth_dev *dev) 10716 { 10717 struct mlx5_priv *priv = dev->data->dev_private; 10718 int ret = 0; 10719 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10720 10721 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10722 const char *message; 10723 uint32_t queue_idx; 10724 10725 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 10726 ind_tbl->queues_n, 10727 &message, &queue_idx); 10728 if (ret != 0) { 10729 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 10730 dev->data->port_id, ind_tbl->queues[queue_idx], 10731 message); 10732 break; 10733 } 10734 } 10735 if (ret != 0) 10736 return ret; 10737 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10738 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 10739 if (ret != 0) { 10740 DRV_LOG(ERR, "Port %u could not attach " 10741 "indirection table obj %p", 10742 dev->data->port_id, (void *)ind_tbl); 10743 goto error; 10744 } 10745 } 10746 10747 return 0; 10748 error: 10749 ind_tbl_last = ind_tbl; 10750 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10751 if (ind_tbl == ind_tbl_last) 10752 break; 10753 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 10754 DRV_LOG(CRIT, "Port %u could not detach " 10755 "indirection table obj %p on rollback", 10756 dev->data->port_id, (void *)ind_tbl); 10757 } 10758 return ret; 10759 } 10760 10761 /** 10762 * Detach indirect actions of the device from its resources. 10763 * 10764 * @param dev 10765 * Pointer to Ethernet device. 10766 * 10767 * @return 10768 * 0 on success, a negative errno value otherwise and rte_errno is set. 10769 */ 10770 int 10771 mlx5_action_handle_detach(struct rte_eth_dev *dev) 10772 { 10773 struct mlx5_priv *priv = dev->data->dev_private; 10774 int ret = 0; 10775 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10776 10777 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10778 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 10779 if (ret != 0) { 10780 DRV_LOG(ERR, "Port %u could not detach " 10781 "indirection table obj %p", 10782 dev->data->port_id, (void *)ind_tbl); 10783 goto error; 10784 } 10785 } 10786 return 0; 10787 error: 10788 ind_tbl_last = ind_tbl; 10789 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10790 if (ind_tbl == ind_tbl_last) 10791 break; 10792 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 10793 DRV_LOG(CRIT, "Port %u could not attach " 10794 "indirection table obj %p on rollback", 10795 dev->data->port_id, (void *)ind_tbl); 10796 } 10797 return ret; 10798 } 10799 10800 #ifndef HAVE_MLX5DV_DR 10801 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 10802 #else 10803 #define MLX5_DOMAIN_SYNC_FLOW \ 10804 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 10805 #endif 10806 10807 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 10808 { 10809 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 10810 const struct mlx5_flow_driver_ops *fops; 10811 int ret; 10812 struct rte_flow_attr attr = { .transfer = 0 }; 10813 10814 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10815 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 10816 if (ret > 0) 10817 ret = -ret; 10818 return ret; 10819 } 10820 10821 const struct mlx5_flow_tunnel * 10822 mlx5_get_tof(const struct rte_flow_item *item, 10823 const struct rte_flow_action *action, 10824 enum mlx5_tof_rule_type *rule_type) 10825 { 10826 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 10827 if (item->type == (typeof(item->type)) 10828 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 10829 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 10830 return flow_items_to_tunnel(item); 10831 } 10832 } 10833 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 10834 if (action->type == (typeof(action->type)) 10835 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 10836 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 10837 return flow_actions_to_tunnel(action); 10838 } 10839 } 10840 return NULL; 10841 } 10842 10843 /** 10844 * tunnel offload functionality is defined for DV environment only 10845 */ 10846 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10847 __extension__ 10848 union tunnel_offload_mark { 10849 uint32_t val; 10850 struct { 10851 uint32_t app_reserve:8; 10852 uint32_t table_id:15; 10853 uint32_t transfer:1; 10854 uint32_t _unused_:8; 10855 }; 10856 }; 10857 10858 static bool 10859 mlx5_access_tunnel_offload_db 10860 (struct rte_eth_dev *dev, 10861 bool (*match)(struct rte_eth_dev *, 10862 struct mlx5_flow_tunnel *, const void *), 10863 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10864 void (*miss)(struct rte_eth_dev *, void *), 10865 void *ctx, bool lock_op); 10866 10867 static int 10868 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 10869 struct rte_flow *flow, 10870 const struct rte_flow_attr *attr, 10871 const struct rte_flow_action *app_actions, 10872 uint32_t flow_idx, 10873 const struct mlx5_flow_tunnel *tunnel, 10874 struct tunnel_default_miss_ctx *ctx, 10875 struct rte_flow_error *error) 10876 { 10877 struct mlx5_priv *priv = dev->data->dev_private; 10878 struct mlx5_flow *dev_flow; 10879 struct rte_flow_attr miss_attr = *attr; 10880 const struct rte_flow_item miss_items[2] = { 10881 { 10882 .type = RTE_FLOW_ITEM_TYPE_ETH, 10883 .spec = NULL, 10884 .last = NULL, 10885 .mask = NULL 10886 }, 10887 { 10888 .type = RTE_FLOW_ITEM_TYPE_END, 10889 .spec = NULL, 10890 .last = NULL, 10891 .mask = NULL 10892 } 10893 }; 10894 union tunnel_offload_mark mark_id; 10895 struct rte_flow_action_mark miss_mark; 10896 struct rte_flow_action miss_actions[3] = { 10897 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 10898 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 10899 }; 10900 const struct rte_flow_action_jump *jump_data; 10901 uint32_t i, flow_table = 0; /* prevent compilation warning */ 10902 struct flow_grp_info grp_info = { 10903 .external = 1, 10904 .transfer = attr->transfer, 10905 .fdb_def_rule = !!priv->fdb_def_rule, 10906 .std_tbl_fix = 0, 10907 }; 10908 int ret; 10909 10910 if (!attr->transfer) { 10911 uint32_t q_size; 10912 10913 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 10914 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 10915 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 10916 0, SOCKET_ID_ANY); 10917 if (!ctx->queue) 10918 return rte_flow_error_set 10919 (error, ENOMEM, 10920 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10921 NULL, "invalid default miss RSS"); 10922 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 10923 ctx->action_rss.level = 0, 10924 ctx->action_rss.types = priv->rss_conf.rss_hf, 10925 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 10926 ctx->action_rss.queue_num = priv->reta_idx_n, 10927 ctx->action_rss.key = priv->rss_conf.rss_key, 10928 ctx->action_rss.queue = ctx->queue; 10929 if (!priv->reta_idx_n || !priv->rxqs_n) 10930 return rte_flow_error_set 10931 (error, EINVAL, 10932 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10933 NULL, "invalid port configuration"); 10934 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 10935 ctx->action_rss.types = 0; 10936 for (i = 0; i != priv->reta_idx_n; ++i) 10937 ctx->queue[i] = (*priv->reta_idx)[i]; 10938 } else { 10939 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 10940 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 10941 } 10942 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 10943 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 10944 jump_data = app_actions->conf; 10945 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 10946 miss_attr.group = jump_data->group; 10947 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 10948 &flow_table, &grp_info, error); 10949 if (ret) 10950 return rte_flow_error_set(error, EINVAL, 10951 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10952 NULL, "invalid tunnel id"); 10953 mark_id.app_reserve = 0; 10954 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 10955 mark_id.transfer = !!attr->transfer; 10956 mark_id._unused_ = 0; 10957 miss_mark.id = mark_id.val; 10958 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 10959 miss_items, miss_actions, flow_idx, error); 10960 if (!dev_flow) 10961 return -rte_errno; 10962 dev_flow->flow = flow; 10963 dev_flow->external = true; 10964 dev_flow->tunnel = tunnel; 10965 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 10966 /* Subflow object was created, we must include one in the list. */ 10967 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 10968 dev_flow->handle, next); 10969 DRV_LOG(DEBUG, 10970 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 10971 dev->data->port_id, tunnel->app_tunnel.type, 10972 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 10973 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 10974 miss_actions, error); 10975 if (!ret) 10976 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 10977 error); 10978 10979 return ret; 10980 } 10981 10982 static const struct mlx5_flow_tbl_data_entry * 10983 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 10984 { 10985 struct mlx5_priv *priv = dev->data->dev_private; 10986 struct mlx5_dev_ctx_shared *sh = priv->sh; 10987 struct mlx5_list_entry *he; 10988 union tunnel_offload_mark mbits = { .val = mark }; 10989 union mlx5_flow_tbl_key table_key = { 10990 { 10991 .level = tunnel_id_to_flow_tbl(mbits.table_id), 10992 .id = 0, 10993 .reserved = 0, 10994 .dummy = 0, 10995 .is_fdb = !!mbits.transfer, 10996 .is_egress = 0, 10997 } 10998 }; 10999 struct mlx5_flow_cb_ctx ctx = { 11000 .data = &table_key.v64, 11001 }; 11002 11003 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 11004 return he ? 11005 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 11006 } 11007 11008 static void 11009 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 11010 struct mlx5_list_entry *entry) 11011 { 11012 struct mlx5_dev_ctx_shared *sh = tool_ctx; 11013 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 11014 11015 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 11016 tunnel_flow_tbl_to_id(tte->flow_table)); 11017 mlx5_free(tte); 11018 } 11019 11020 static int 11021 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 11022 struct mlx5_list_entry *entry, void *cb_ctx) 11023 { 11024 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 11025 union tunnel_tbl_key tbl = { 11026 .val = *(uint64_t *)(ctx->data), 11027 }; 11028 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 11029 11030 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 11031 } 11032 11033 static struct mlx5_list_entry * 11034 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 11035 { 11036 struct mlx5_dev_ctx_shared *sh = tool_ctx; 11037 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 11038 struct tunnel_tbl_entry *tte; 11039 union tunnel_tbl_key tbl = { 11040 .val = *(uint64_t *)(ctx->data), 11041 }; 11042 11043 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 11044 sizeof(*tte), 0, 11045 SOCKET_ID_ANY); 11046 if (!tte) 11047 goto err; 11048 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 11049 &tte->flow_table); 11050 if (tte->flow_table >= MLX5_MAX_TABLES) { 11051 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 11052 tte->flow_table); 11053 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 11054 tte->flow_table); 11055 goto err; 11056 } else if (!tte->flow_table) { 11057 goto err; 11058 } 11059 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 11060 tte->tunnel_id = tbl.tunnel_id; 11061 tte->group = tbl.group; 11062 return &tte->hash; 11063 err: 11064 if (tte) 11065 mlx5_free(tte); 11066 return NULL; 11067 } 11068 11069 static struct mlx5_list_entry * 11070 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 11071 struct mlx5_list_entry *oentry, 11072 void *cb_ctx __rte_unused) 11073 { 11074 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 11075 0, SOCKET_ID_ANY); 11076 11077 if (!tte) 11078 return NULL; 11079 memcpy(tte, oentry, sizeof(*tte)); 11080 return &tte->hash; 11081 } 11082 11083 static void 11084 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 11085 struct mlx5_list_entry *entry) 11086 { 11087 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 11088 11089 mlx5_free(tte); 11090 } 11091 11092 static uint32_t 11093 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 11094 const struct mlx5_flow_tunnel *tunnel, 11095 uint32_t group, uint32_t *table, 11096 struct rte_flow_error *error) 11097 { 11098 struct mlx5_list_entry *he; 11099 struct tunnel_tbl_entry *tte; 11100 union tunnel_tbl_key key = { 11101 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 11102 .group = group 11103 }; 11104 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11105 struct mlx5_hlist *group_hash; 11106 struct mlx5_flow_cb_ctx ctx = { 11107 .data = &key.val, 11108 }; 11109 11110 group_hash = tunnel ? tunnel->groups : thub->groups; 11111 he = mlx5_hlist_register(group_hash, key.val, &ctx); 11112 if (!he) 11113 return rte_flow_error_set(error, EINVAL, 11114 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 11115 NULL, 11116 "tunnel group index not supported"); 11117 tte = container_of(he, typeof(*tte), hash); 11118 *table = tte->flow_table; 11119 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 11120 dev->data->port_id, key.tunnel_id, group, *table); 11121 return 0; 11122 } 11123 11124 static void 11125 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 11126 struct mlx5_flow_tunnel *tunnel) 11127 { 11128 struct mlx5_priv *priv = dev->data->dev_private; 11129 struct mlx5_indexed_pool *ipool; 11130 11131 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 11132 dev->data->port_id, tunnel->tunnel_id); 11133 LIST_REMOVE(tunnel, chain); 11134 mlx5_hlist_destroy(tunnel->groups); 11135 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 11136 mlx5_ipool_free(ipool, tunnel->tunnel_id); 11137 } 11138 11139 static bool 11140 mlx5_access_tunnel_offload_db 11141 (struct rte_eth_dev *dev, 11142 bool (*match)(struct rte_eth_dev *, 11143 struct mlx5_flow_tunnel *, const void *), 11144 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 11145 void (*miss)(struct rte_eth_dev *, void *), 11146 void *ctx, bool lock_op) 11147 { 11148 bool verdict = false; 11149 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11150 struct mlx5_flow_tunnel *tunnel; 11151 11152 rte_spinlock_lock(&thub->sl); 11153 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 11154 verdict = match(dev, tunnel, (const void *)ctx); 11155 if (verdict) 11156 break; 11157 } 11158 if (!lock_op) 11159 rte_spinlock_unlock(&thub->sl); 11160 if (verdict && hit) 11161 hit(dev, tunnel, ctx); 11162 if (!verdict && miss) 11163 miss(dev, ctx); 11164 if (lock_op) 11165 rte_spinlock_unlock(&thub->sl); 11166 11167 return verdict; 11168 } 11169 11170 struct tunnel_db_find_tunnel_id_ctx { 11171 uint32_t tunnel_id; 11172 struct mlx5_flow_tunnel *tunnel; 11173 }; 11174 11175 static bool 11176 find_tunnel_id_match(struct rte_eth_dev *dev, 11177 struct mlx5_flow_tunnel *tunnel, const void *x) 11178 { 11179 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 11180 11181 RTE_SET_USED(dev); 11182 return tunnel->tunnel_id == ctx->tunnel_id; 11183 } 11184 11185 static void 11186 find_tunnel_id_hit(struct rte_eth_dev *dev, 11187 struct mlx5_flow_tunnel *tunnel, void *x) 11188 { 11189 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 11190 RTE_SET_USED(dev); 11191 ctx->tunnel = tunnel; 11192 } 11193 11194 static struct mlx5_flow_tunnel * 11195 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 11196 { 11197 struct tunnel_db_find_tunnel_id_ctx ctx = { 11198 .tunnel_id = id, 11199 }; 11200 11201 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 11202 find_tunnel_id_hit, NULL, &ctx, true); 11203 11204 return ctx.tunnel; 11205 } 11206 11207 static struct mlx5_flow_tunnel * 11208 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 11209 const struct rte_flow_tunnel *app_tunnel) 11210 { 11211 struct mlx5_priv *priv = dev->data->dev_private; 11212 struct mlx5_indexed_pool *ipool; 11213 struct mlx5_flow_tunnel *tunnel; 11214 uint32_t id; 11215 11216 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 11217 tunnel = mlx5_ipool_zmalloc(ipool, &id); 11218 if (!tunnel) 11219 return NULL; 11220 if (id >= MLX5_MAX_TUNNELS) { 11221 mlx5_ipool_free(ipool, id); 11222 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 11223 return NULL; 11224 } 11225 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 11226 priv->sh, 11227 mlx5_flow_tunnel_grp2tbl_create_cb, 11228 mlx5_flow_tunnel_grp2tbl_match_cb, 11229 mlx5_flow_tunnel_grp2tbl_remove_cb, 11230 mlx5_flow_tunnel_grp2tbl_clone_cb, 11231 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 11232 if (!tunnel->groups) { 11233 mlx5_ipool_free(ipool, id); 11234 return NULL; 11235 } 11236 /* initiate new PMD tunnel */ 11237 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 11238 tunnel->tunnel_id = id; 11239 tunnel->action.type = (typeof(tunnel->action.type)) 11240 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 11241 tunnel->action.conf = tunnel; 11242 tunnel->item.type = (typeof(tunnel->item.type)) 11243 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 11244 tunnel->item.spec = tunnel; 11245 tunnel->item.last = NULL; 11246 tunnel->item.mask = NULL; 11247 11248 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 11249 dev->data->port_id, tunnel->tunnel_id); 11250 11251 return tunnel; 11252 } 11253 11254 struct tunnel_db_get_tunnel_ctx { 11255 const struct rte_flow_tunnel *app_tunnel; 11256 struct mlx5_flow_tunnel *tunnel; 11257 }; 11258 11259 static bool get_tunnel_match(struct rte_eth_dev *dev, 11260 struct mlx5_flow_tunnel *tunnel, const void *x) 11261 { 11262 const struct tunnel_db_get_tunnel_ctx *ctx = x; 11263 11264 RTE_SET_USED(dev); 11265 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 11266 sizeof(*ctx->app_tunnel)); 11267 } 11268 11269 static void get_tunnel_hit(struct rte_eth_dev *dev, 11270 struct mlx5_flow_tunnel *tunnel, void *x) 11271 { 11272 /* called under tunnel spinlock protection */ 11273 struct tunnel_db_get_tunnel_ctx *ctx = x; 11274 11275 RTE_SET_USED(dev); 11276 tunnel->refctn++; 11277 ctx->tunnel = tunnel; 11278 } 11279 11280 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 11281 { 11282 /* called under tunnel spinlock protection */ 11283 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11284 struct tunnel_db_get_tunnel_ctx *ctx = x; 11285 11286 rte_spinlock_unlock(&thub->sl); 11287 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 11288 rte_spinlock_lock(&thub->sl); 11289 if (ctx->tunnel) { 11290 ctx->tunnel->refctn = 1; 11291 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 11292 } 11293 } 11294 11295 11296 static int 11297 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 11298 const struct rte_flow_tunnel *app_tunnel, 11299 struct mlx5_flow_tunnel **tunnel) 11300 { 11301 struct tunnel_db_get_tunnel_ctx ctx = { 11302 .app_tunnel = app_tunnel, 11303 }; 11304 11305 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 11306 get_tunnel_miss, &ctx, true); 11307 *tunnel = ctx.tunnel; 11308 return ctx.tunnel ? 0 : -ENOMEM; 11309 } 11310 11311 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 11312 { 11313 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 11314 11315 if (!thub) 11316 return; 11317 if (!LIST_EMPTY(&thub->tunnels)) 11318 DRV_LOG(WARNING, "port %u tunnels present", port_id); 11319 mlx5_hlist_destroy(thub->groups); 11320 mlx5_free(thub); 11321 } 11322 11323 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 11324 { 11325 int err; 11326 struct mlx5_flow_tunnel_hub *thub; 11327 11328 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 11329 0, SOCKET_ID_ANY); 11330 if (!thub) 11331 return -ENOMEM; 11332 LIST_INIT(&thub->tunnels); 11333 rte_spinlock_init(&thub->sl); 11334 thub->groups = mlx5_hlist_create("flow groups", 64, 11335 false, true, sh, 11336 mlx5_flow_tunnel_grp2tbl_create_cb, 11337 mlx5_flow_tunnel_grp2tbl_match_cb, 11338 mlx5_flow_tunnel_grp2tbl_remove_cb, 11339 mlx5_flow_tunnel_grp2tbl_clone_cb, 11340 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 11341 if (!thub->groups) { 11342 err = -rte_errno; 11343 goto err; 11344 } 11345 sh->tunnel_hub = thub; 11346 11347 return 0; 11348 11349 err: 11350 if (thub->groups) 11351 mlx5_hlist_destroy(thub->groups); 11352 if (thub) 11353 mlx5_free(thub); 11354 return err; 11355 } 11356 11357 static inline int 11358 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 11359 struct rte_flow_tunnel *tunnel, 11360 struct rte_flow_error *error) 11361 { 11362 struct mlx5_priv *priv = dev->data->dev_private; 11363 11364 if (!priv->sh->config.dv_flow_en) 11365 return rte_flow_error_set(error, ENOTSUP, 11366 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11367 "flow DV interface is off"); 11368 if (!is_tunnel_offload_active(dev)) 11369 return rte_flow_error_set(error, ENOTSUP, 11370 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11371 "tunnel offload was not activated, consider setting dv_xmeta_en=3"); 11372 if (!tunnel) 11373 return rte_flow_error_set(error, EINVAL, 11374 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11375 "no application tunnel"); 11376 switch (tunnel->type) { 11377 default: 11378 return rte_flow_error_set(error, EINVAL, 11379 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11380 "unsupported tunnel type"); 11381 case RTE_FLOW_ITEM_TYPE_VXLAN: 11382 case RTE_FLOW_ITEM_TYPE_GRE: 11383 case RTE_FLOW_ITEM_TYPE_NVGRE: 11384 case RTE_FLOW_ITEM_TYPE_GENEVE: 11385 break; 11386 } 11387 return 0; 11388 } 11389 11390 static int 11391 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 11392 struct rte_flow_tunnel *app_tunnel, 11393 struct rte_flow_action **actions, 11394 uint32_t *num_of_actions, 11395 struct rte_flow_error *error) 11396 { 11397 struct mlx5_flow_tunnel *tunnel; 11398 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 11399 11400 if (ret) 11401 return ret; 11402 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 11403 if (ret < 0) { 11404 return rte_flow_error_set(error, ret, 11405 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11406 "failed to initialize pmd tunnel"); 11407 } 11408 *actions = &tunnel->action; 11409 *num_of_actions = 1; 11410 return 0; 11411 } 11412 11413 static int 11414 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 11415 struct rte_flow_tunnel *app_tunnel, 11416 struct rte_flow_item **items, 11417 uint32_t *num_of_items, 11418 struct rte_flow_error *error) 11419 { 11420 struct mlx5_flow_tunnel *tunnel; 11421 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 11422 11423 if (ret) 11424 return ret; 11425 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 11426 if (ret < 0) { 11427 return rte_flow_error_set(error, ret, 11428 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11429 "failed to initialize pmd tunnel"); 11430 } 11431 *items = &tunnel->item; 11432 *num_of_items = 1; 11433 return 0; 11434 } 11435 11436 struct tunnel_db_element_release_ctx { 11437 struct rte_flow_item *items; 11438 struct rte_flow_action *actions; 11439 uint32_t num_elements; 11440 struct rte_flow_error *error; 11441 int ret; 11442 }; 11443 11444 static bool 11445 tunnel_element_release_match(struct rte_eth_dev *dev, 11446 struct mlx5_flow_tunnel *tunnel, const void *x) 11447 { 11448 const struct tunnel_db_element_release_ctx *ctx = x; 11449 11450 RTE_SET_USED(dev); 11451 if (ctx->num_elements != 1) 11452 return false; 11453 else if (ctx->items) 11454 return ctx->items == &tunnel->item; 11455 else if (ctx->actions) 11456 return ctx->actions == &tunnel->action; 11457 11458 return false; 11459 } 11460 11461 static void 11462 tunnel_element_release_hit(struct rte_eth_dev *dev, 11463 struct mlx5_flow_tunnel *tunnel, void *x) 11464 { 11465 struct tunnel_db_element_release_ctx *ctx = x; 11466 ctx->ret = 0; 11467 if (!(rte_atomic_fetch_sub_explicit(&tunnel->refctn, 1, rte_memory_order_relaxed) - 1)) 11468 mlx5_flow_tunnel_free(dev, tunnel); 11469 } 11470 11471 static void 11472 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 11473 { 11474 struct tunnel_db_element_release_ctx *ctx = x; 11475 RTE_SET_USED(dev); 11476 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 11477 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11478 "invalid argument"); 11479 } 11480 11481 static int 11482 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 11483 struct rte_flow_item *pmd_items, 11484 uint32_t num_items, struct rte_flow_error *err) 11485 { 11486 struct tunnel_db_element_release_ctx ctx = { 11487 .items = pmd_items, 11488 .actions = NULL, 11489 .num_elements = num_items, 11490 .error = err, 11491 }; 11492 11493 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11494 tunnel_element_release_hit, 11495 tunnel_element_release_miss, &ctx, false); 11496 11497 return ctx.ret; 11498 } 11499 11500 static int 11501 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 11502 struct rte_flow_action *pmd_actions, 11503 uint32_t num_actions, struct rte_flow_error *err) 11504 { 11505 struct tunnel_db_element_release_ctx ctx = { 11506 .items = NULL, 11507 .actions = pmd_actions, 11508 .num_elements = num_actions, 11509 .error = err, 11510 }; 11511 11512 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11513 tunnel_element_release_hit, 11514 tunnel_element_release_miss, &ctx, false); 11515 11516 return ctx.ret; 11517 } 11518 11519 static int 11520 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 11521 struct rte_mbuf *m, 11522 struct rte_flow_restore_info *info, 11523 struct rte_flow_error *err) 11524 { 11525 uint64_t ol_flags = m->ol_flags; 11526 const struct mlx5_flow_tbl_data_entry *tble; 11527 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 11528 struct mlx5_priv *priv = dev->data->dev_private; 11529 11530 if (priv->tunnel_enabled == 0) 11531 goto err; 11532 if ((ol_flags & mask) != mask) 11533 goto err; 11534 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 11535 if (!tble) { 11536 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 11537 dev->data->port_id, m->hash.fdir.hi); 11538 goto err; 11539 } 11540 MLX5_ASSERT(tble->tunnel); 11541 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 11542 info->group_id = tble->group_id; 11543 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 11544 RTE_FLOW_RESTORE_INFO_GROUP_ID | 11545 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 11546 11547 return 0; 11548 11549 err: 11550 return rte_flow_error_set(err, EINVAL, 11551 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11552 "failed to get restore info"); 11553 } 11554 11555 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 11556 static int 11557 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 11558 __rte_unused struct rte_flow_tunnel *app_tunnel, 11559 __rte_unused struct rte_flow_action **actions, 11560 __rte_unused uint32_t *num_of_actions, 11561 __rte_unused struct rte_flow_error *error) 11562 { 11563 return -ENOTSUP; 11564 } 11565 11566 static int 11567 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 11568 __rte_unused struct rte_flow_tunnel *app_tunnel, 11569 __rte_unused struct rte_flow_item **items, 11570 __rte_unused uint32_t *num_of_items, 11571 __rte_unused struct rte_flow_error *error) 11572 { 11573 return -ENOTSUP; 11574 } 11575 11576 static int 11577 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 11578 __rte_unused struct rte_flow_item *pmd_items, 11579 __rte_unused uint32_t num_items, 11580 __rte_unused struct rte_flow_error *err) 11581 { 11582 return -ENOTSUP; 11583 } 11584 11585 static int 11586 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 11587 __rte_unused struct rte_flow_action *pmd_action, 11588 __rte_unused uint32_t num_actions, 11589 __rte_unused struct rte_flow_error *err) 11590 { 11591 return -ENOTSUP; 11592 } 11593 11594 static int 11595 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 11596 __rte_unused struct rte_mbuf *m, 11597 __rte_unused struct rte_flow_restore_info *i, 11598 __rte_unused struct rte_flow_error *err) 11599 { 11600 return -ENOTSUP; 11601 } 11602 11603 static int 11604 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 11605 __rte_unused struct rte_flow *flow, 11606 __rte_unused const struct rte_flow_attr *attr, 11607 __rte_unused const struct rte_flow_action *actions, 11608 __rte_unused uint32_t flow_idx, 11609 __rte_unused const struct mlx5_flow_tunnel *tunnel, 11610 __rte_unused struct tunnel_default_miss_ctx *ctx, 11611 __rte_unused struct rte_flow_error *error) 11612 { 11613 return -ENOTSUP; 11614 } 11615 11616 static struct mlx5_flow_tunnel * 11617 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 11618 __rte_unused uint32_t id) 11619 { 11620 return NULL; 11621 } 11622 11623 static void 11624 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 11625 __rte_unused struct mlx5_flow_tunnel *tunnel) 11626 { 11627 } 11628 11629 static uint32_t 11630 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 11631 __rte_unused const struct mlx5_flow_tunnel *t, 11632 __rte_unused uint32_t group, 11633 __rte_unused uint32_t *table, 11634 struct rte_flow_error *error) 11635 { 11636 return rte_flow_error_set(error, ENOTSUP, 11637 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11638 "tunnel offload requires DV support"); 11639 } 11640 11641 void 11642 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 11643 __rte_unused uint16_t port_id) 11644 { 11645 } 11646 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 11647 11648 /* Flex flow item API */ 11649 static struct rte_flow_item_flex_handle * 11650 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 11651 const struct rte_flow_item_flex_conf *conf, 11652 struct rte_flow_error *error) 11653 { 11654 static const char err_msg[] = "flex item creation unsupported"; 11655 struct mlx5_priv *priv = dev->data->dev_private; 11656 struct rte_flow_attr attr = { .transfer = 0 }; 11657 const struct mlx5_flow_driver_ops *fops = 11658 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11659 11660 if (!priv->pci_dev) { 11661 rte_flow_error_set(error, ENOTSUP, 11662 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11663 "create flex item on PF only"); 11664 return NULL; 11665 } 11666 switch (priv->pci_dev->id.device_id) { 11667 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD2: 11668 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: 11669 break; 11670 default: 11671 rte_flow_error_set(error, ENOTSUP, 11672 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11673 "flex item available on BlueField ports only"); 11674 return NULL; 11675 } 11676 if (!fops->item_create) { 11677 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11678 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11679 NULL, err_msg); 11680 return NULL; 11681 } 11682 return fops->item_create(dev, conf, error); 11683 } 11684 11685 static int 11686 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 11687 const struct rte_flow_item_flex_handle *handle, 11688 struct rte_flow_error *error) 11689 { 11690 static const char err_msg[] = "flex item release unsupported"; 11691 struct rte_flow_attr attr = { .transfer = 0 }; 11692 const struct mlx5_flow_driver_ops *fops = 11693 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11694 11695 if (!fops->item_release) { 11696 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11697 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11698 NULL, err_msg); 11699 return -rte_errno; 11700 } 11701 return fops->item_release(dev, handle, error); 11702 } 11703 11704 static void 11705 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 11706 { 11707 int ret; 11708 struct rte_flow_error error; 11709 11710 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 11711 char *item_name; 11712 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 11713 sizeof(item_name), 11714 (void *)(uintptr_t)item->type, &error); 11715 if (ret > 0) 11716 printf("%s ", item_name); 11717 else 11718 printf("%d\n", (int)item->type); 11719 } 11720 printf("END\n"); 11721 } 11722 11723 static int 11724 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 11725 { 11726 const struct rte_flow_item_udp *spec = udp_item->spec; 11727 const struct rte_flow_item_udp *mask = udp_item->mask; 11728 uint16_t udp_dport = 0; 11729 11730 if (spec != NULL) { 11731 if (!mask) 11732 mask = &rte_flow_item_udp_mask; 11733 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 11734 mask->hdr.dst_port); 11735 } 11736 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 11737 } 11738 11739 static const struct mlx5_flow_expand_node * 11740 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 11741 unsigned int item_idx, 11742 const struct mlx5_flow_expand_node graph[], 11743 const struct mlx5_flow_expand_node *node) 11744 { 11745 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 11746 11747 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 11748 node != NULL && 11749 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 11750 /* 11751 * The expansion node is VXLAN and it is also the last 11752 * expandable item in the pattern, so need to continue 11753 * expansion of the inner tunnel. 11754 */ 11755 MLX5_ASSERT(item_idx > 0); 11756 prev_item = pattern + item_idx - 1; 11757 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 11758 if (mlx5_flow_is_std_vxlan_port(prev_item)) 11759 return &graph[MLX5_EXPANSION_STD_VXLAN]; 11760 return &graph[MLX5_EXPANSION_L3_VXLAN]; 11761 } 11762 return node; 11763 } 11764 11765 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 11766 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 11767 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 11768 }; 11769 11770 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 11771 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 11772 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 11773 { 9, 10, 11 }, { 12, 13, 14 }, 11774 }; 11775 11776 /** 11777 * Discover the number of available flow priorities. 11778 * 11779 * @param dev 11780 * Ethernet device. 11781 * 11782 * @return 11783 * On success, number of available flow priorities. 11784 * On failure, a negative errno-style code and rte_errno is set. 11785 */ 11786 int 11787 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 11788 { 11789 static const uint16_t vprio[] = {8, 16}; 11790 const struct mlx5_priv *priv = dev->data->dev_private; 11791 const struct mlx5_flow_driver_ops *fops; 11792 enum mlx5_flow_drv_type type; 11793 int ret; 11794 11795 type = mlx5_flow_os_get_type(); 11796 if (type == MLX5_FLOW_TYPE_MAX) { 11797 type = MLX5_FLOW_TYPE_VERBS; 11798 if (priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en) 11799 type = MLX5_FLOW_TYPE_DV; 11800 } 11801 fops = flow_get_drv_ops(type); 11802 if (fops->discover_priorities == NULL) { 11803 DRV_LOG(ERR, "Priority discovery not supported"); 11804 rte_errno = ENOTSUP; 11805 return -rte_errno; 11806 } 11807 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 11808 if (ret < 0) 11809 return ret; 11810 switch (ret) { 11811 case 8: 11812 ret = RTE_DIM(priority_map_3); 11813 break; 11814 case 16: 11815 ret = RTE_DIM(priority_map_5); 11816 break; 11817 default: 11818 rte_errno = ENOTSUP; 11819 DRV_LOG(ERR, 11820 "port %u maximum priority: %d expected 8/16", 11821 dev->data->port_id, ret); 11822 return -rte_errno; 11823 } 11824 DRV_LOG(INFO, "port %u supported flow priorities:" 11825 " 0-%d for ingress or egress root table," 11826 " 0-%d for non-root table or transfer root table.", 11827 dev->data->port_id, ret - 2, 11828 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 11829 return ret; 11830 } 11831 11832 /** 11833 * Adjust flow priority based on the highest layer and the request priority. 11834 * 11835 * @param[in] dev 11836 * Pointer to the Ethernet device structure. 11837 * @param[in] priority 11838 * The rule base priority. 11839 * @param[in] subpriority 11840 * The priority based on the items. 11841 * 11842 * @return 11843 * The new priority. 11844 */ 11845 uint32_t 11846 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 11847 uint32_t subpriority) 11848 { 11849 uint32_t res = 0; 11850 struct mlx5_priv *priv = dev->data->dev_private; 11851 11852 switch (priv->sh->flow_max_priority) { 11853 case RTE_DIM(priority_map_3): 11854 res = priority_map_3[priority][subpriority]; 11855 break; 11856 case RTE_DIM(priority_map_5): 11857 res = priority_map_5[priority][subpriority]; 11858 break; 11859 } 11860 return res; 11861 } 11862 11863 /** 11864 * Get the priority for sending traffic to kernel table. 11865 * 11866 * @param[in] dev 11867 * Pointer to the Ethernet device structure. 11868 * 11869 * @return 11870 * On success: the value of priority for sending traffic to kernel table 11871 * On failure: -1 11872 */ 11873 uint32_t 11874 mlx5_get_send_to_kernel_priority(struct rte_eth_dev *dev) 11875 { 11876 struct mlx5_priv *priv = dev->data->dev_private; 11877 uint32_t res; 11878 11879 switch (priv->sh->flow_max_priority) { 11880 case RTE_DIM(priority_map_5): 11881 res = 15; 11882 break; 11883 case RTE_DIM(priority_map_3): 11884 res = 7; 11885 break; 11886 default: 11887 DRV_LOG(ERR, 11888 "port %u maximum priority: %d expected 8/16", 11889 dev->data->port_id, priv->sh->flow_max_priority); 11890 res = (uint32_t)-1; 11891 } 11892 return res; 11893 } 11894 11895 /** 11896 * Get the E-Switch Manager vport id. 11897 * 11898 * @param[in] dev 11899 * Pointer to the Ethernet device structure. 11900 * 11901 * @return 11902 * The vport id. 11903 */ 11904 int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev) 11905 { 11906 struct mlx5_priv *priv = dev->data->dev_private; 11907 struct mlx5_common_device *cdev = priv->sh->cdev; 11908 11909 /* New FW exposes E-Switch Manager vport ID, can use it directly. */ 11910 if (cdev->config.hca_attr.esw_mgr_vport_id_valid) 11911 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; 11912 11913 if (priv->pci_dev == NULL) 11914 return 0; 11915 switch (priv->pci_dev->id.device_id) { 11916 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD: 11917 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD2: 11918 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: 11919 /* 11920 * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, 11921 * only the BF embedded CPUs control the E-Switch Manager port. Hence, 11922 * ECPF vport ID is selected and not the host port (0) in any BF case. 11923 */ 11924 return (int16_t)MLX5_ECPF_VPORT_ID; 11925 default: 11926 return MLX5_PF_VPORT_ID; 11927 } 11928 } 11929 11930 /** 11931 * Parse item to get the vport id. 11932 * 11933 * @param[in] dev 11934 * Pointer to the Ethernet device structure. 11935 * @param[in] item 11936 * The src port id match item. 11937 * @param[out] vport_id 11938 * Pointer to put the vport id. 11939 * @param[out] all_ports 11940 * Indicate if the item matches all ports. 11941 * @param[out] error 11942 * Pointer to error structure. 11943 * 11944 * @return 11945 * 0 on success, a negative errno value otherwise and rte_errno is set. 11946 */ 11947 int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, 11948 const struct rte_flow_item *item, 11949 uint16_t *vport_id, 11950 bool *all_ports, 11951 struct rte_flow_error *error) 11952 { 11953 struct mlx5_priv *port_priv; 11954 const struct rte_flow_item_port_id *pid_v = NULL; 11955 const struct rte_flow_item_ethdev *dev_v = NULL; 11956 uint32_t esw_mgr_port; 11957 uint32_t src_port; 11958 11959 if (all_ports) 11960 *all_ports = false; 11961 switch (item->type) { 11962 case RTE_FLOW_ITEM_TYPE_PORT_ID: 11963 pid_v = item->spec; 11964 if (!pid_v) 11965 return 0; 11966 src_port = pid_v->id; 11967 esw_mgr_port = MLX5_PORT_ESW_MGR; 11968 break; 11969 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 11970 dev_v = item->spec; 11971 if (!dev_v) { 11972 if (all_ports) 11973 *all_ports = true; 11974 return 0; 11975 } 11976 src_port = dev_v->port_id; 11977 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11978 break; 11979 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 11980 src_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11981 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11982 break; 11983 default: 11984 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11985 NULL, "Incorrect item type."); 11986 } 11987 if (src_port == esw_mgr_port) { 11988 *vport_id = mlx5_flow_get_esw_manager_vport_id(dev); 11989 } else { 11990 port_priv = mlx5_port_to_eswitch_info(src_port, false); 11991 if (!port_priv) 11992 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11993 NULL, "Failed to get port info."); 11994 *vport_id = port_priv->representor_id; 11995 } 11996 11997 return 0; 11998 } 11999 12000 int 12001 mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev, 12002 uint16_t *proxy_port_id, 12003 struct rte_flow_error *error) 12004 { 12005 const struct mlx5_priv *priv = dev->data->dev_private; 12006 uint16_t port_id; 12007 12008 if (!priv->sh->config.dv_esw_en) 12009 return rte_flow_error_set(error, EINVAL, 12010 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 12011 NULL, 12012 "unable to provide a proxy port" 12013 " without E-Switch configured"); 12014 if (!priv->master && !priv->representor) 12015 return rte_flow_error_set(error, EINVAL, 12016 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 12017 NULL, 12018 "unable to provide a proxy port" 12019 " for port which is not a master" 12020 " or a representor port"); 12021 if (priv->master) { 12022 *proxy_port_id = dev->data->port_id; 12023 return 0; 12024 } 12025 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 12026 const struct rte_eth_dev *port_dev = &rte_eth_devices[port_id]; 12027 const struct mlx5_priv *port_priv = port_dev->data->dev_private; 12028 12029 if (port_priv->master && 12030 port_priv->domain_id == priv->domain_id) { 12031 *proxy_port_id = port_id; 12032 return 0; 12033 } 12034 } 12035 return rte_flow_error_set(error, ENODEV, 12036 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 12037 NULL, "unable to find a proxy port"); 12038 } 12039 12040 /** 12041 * Discover IPv6 traffic class ID support in rdma-core and firmware. 12042 * 12043 * @param dev 12044 * Ethernet device. 12045 * 12046 * @return 12047 * 0, rdma-core is good to work with firmware. 12048 * -EOPNOTSUPP, rdma-core could not work with new IPv6 TC ID. 12049 */ 12050 int 12051 mlx5_flow_discover_ipv6_tc_support(struct rte_eth_dev *dev) 12052 { 12053 struct rte_flow_action_set_dscp set_dscp; 12054 struct rte_flow_attr attr; 12055 struct rte_flow_action actions[2]; 12056 struct rte_flow_item items[3]; 12057 struct rte_flow_error error; 12058 uint32_t flow_idx; 12059 12060 memset(&attr, 0, sizeof(attr)); 12061 memset(actions, 0, sizeof(actions)); 12062 memset(items, 0, sizeof(items)); 12063 attr.group = 1; 12064 attr.egress = 1; 12065 items[0].type = RTE_FLOW_ITEM_TYPE_ETH; 12066 items[1].type = RTE_FLOW_ITEM_TYPE_IPV6; 12067 items[2].type = RTE_FLOW_ITEM_TYPE_END; 12068 /* Random value */ 12069 set_dscp.dscp = 9; 12070 actions[0].type = RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP; 12071 actions[0].conf = &set_dscp; 12072 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 12073 12074 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, items, actions, true, &error); 12075 if (!flow_idx) 12076 return -EOPNOTSUPP; 12077 12078 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 12079 return 0; 12080 } 12081 12082 void * 12083 rte_pmd_mlx5_create_geneve_tlv_parser(uint16_t port_id, 12084 const struct rte_pmd_mlx5_geneve_tlv tlv_list[], 12085 uint8_t nb_options) 12086 { 12087 #ifdef HAVE_MLX5_HWS_SUPPORT 12088 return mlx5_geneve_tlv_parser_create(port_id, tlv_list, nb_options); 12089 #else 12090 (void)port_id; 12091 (void)tlv_list; 12092 (void)nb_options; 12093 DRV_LOG(ERR, "%s is not supported.", __func__); 12094 rte_errno = ENOTSUP; 12095 return NULL; 12096 #endif 12097 } 12098 12099 int 12100 rte_pmd_mlx5_destroy_geneve_tlv_parser(void *handle) 12101 { 12102 #ifdef HAVE_MLX5_HWS_SUPPORT 12103 return mlx5_geneve_tlv_parser_destroy(handle); 12104 #else 12105 (void)handle; 12106 DRV_LOG(ERR, "%s is not supported.", __func__); 12107 rte_errno = ENOTSUP; 12108 return -rte_errno; 12109 #endif 12110 } 12111