common/mlx5: get PCI device address from any bus

A function is exported to allow retrieving the PCI address
of the parent PCI device of a Sub-Function in auxiliary bus sysfs.
The function mlx5_dev_t

common/mlx5: get PCI device address from any bus

A function is exported to allow retrieving the PCI address
of the parent PCI device of a Sub-Function in auxiliary bus sysfs.
The function mlx5_dev_to_pci_str() is accepting both PCI and auxiliary
devices. In case of a PCI device, it is simply using the device name.

The function mlx5_dev_to_pci_addr(), which is based on sysfs path
and do not use any device object, is renamed to mlx5_get_pci_addr()
for clarity purpose.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: optimize hash list table allocate on demand

Currently, all the hash list tables are allocated during start up.
Since different applications may only use dedicated limited actions,
optimize

net/mlx5: optimize hash list table allocate on demand

Currently, all the hash list tables are allocated during start up.
Since different applications may only use dedicated limited actions,
optimized the hash list table allocate on demand will save initial
memory.

This commit optimizes hash list table allocate on demand.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: adjust hash bucket size

With the new per core optimization to the list, the hash bucket size
can be tuned to a more accurate number.

This commit adjusts the hash bucket size.

Signed-off-

net/mlx5: adjust hash bucket size

With the new per core optimization to the list, the hash bucket size
can be tuned to a more accurate number.

This commit adjusts the hash bucket size.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: add per-lcore cache to hash list utility

Using the mlx5 list utility object in the hlist buckets.

This patch moves the list utility object to the common utility, creates
all the clone

common/mlx5: add per-lcore cache to hash list utility

Using the mlx5 list utility object in the hlist buckets.

This patch moves the list utility object to the common utility, creates
all the clone operations for all the hlist instances in the driver.

Also adjust all the utility callbacks to be generic for both list and
hlist.

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: add per-lcore sharing flag in object list

Without lcores_share flag, mlx5 PMD was sharing the rdma-core objects
between all lcores.

Having lcores_share flag disabled, means each lcore

common/mlx5: add per-lcore sharing flag in object list

Without lcores_share flag, mlx5 PMD was sharing the rdma-core objects
between all lcores.

Having lcores_share flag disabled, means each lcore will have its own
objects, which will eventually lead to increased insertion/deletion
rates.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: allocate list memory in create function

Currently, the list memory was allocated by the list API caller.

Move it to be allocated by the create API in order to save consistence
with the hl

net/mlx5: allocate list memory in create function

Currently, the list memory was allocated by the list API caller.

Move it to be allocated by the create API in order to save consistence
with the hlist utility.

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: add per-lcore cache to the list utility

When mlx5 list object is accessed by multiple cores, the list lock
counter is all the time written by all the cores what increases cache
misses in t

net/mlx5: add per-lcore cache to the list utility

When mlx5 list object is accessed by multiple cores, the list lock
counter is all the time written by all the cores what increases cache
misses in the memory caches.

In addition, when one thread accesses the list for add\remove\lookup
operation, all the other threads coming to do an operation in the list
are stuck in the lock.

Add per lcore cache to allow thread manipulations to be lockless when
the list objects are mostly reused.

Synchronization with atomic operations should be done in order to
allow threads to unregister an entry from other thread cache.

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: remove cache term from the list utility

The internal mlx5 list tool is used mainly when the list objects need to
be synchronized between multiple threads.

The "cache" term is used in the

net/mlx5: remove cache term from the list utility

The internal mlx5 list tool is used mainly when the list objects need to
be synchronized between multiple threads.

The "cache" term is used in the internal mlx5 list API.

Next enhancements on this tool will use the "cache" term for per thread
cache management.

To prevent confusing, remove the current "cache" term from the API's
names.

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: replace flow list with indexed pool

The flow list is used to save the create flows and to be used only
when port closes all the flows need to be flushed.

This commit takes advantage of th

net/mlx5: replace flow list with indexed pool

The flow list is used to save the create flows and to be used only
when port closes all the flows need to be flushed.

This commit takes advantage of the index pool foreach operation to
flush all the allocated flows.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: support matching on VXLAN reserved field

This adds matching on the reserved field of VXLAN
header (the last 8-bits). The capability from rdma-core
is detected by creating a dummy matcher u

net/mlx5: support matching on VXLAN reserved field

This adds matching on the reserved field of VXLAN
header (the last 8-bits). The capability from rdma-core
is detected by creating a dummy matcher using misc5
when the device is probed.

For non-zero groups and FDB domain, the capability is
detected from rdma-core, meanwhile for NIC domain group
zero it's relying on the HCA_CAP from FW.

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Raslan Darawsheh <rasland@nvidia.com>

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common/mlx5: use new port query API if available

In order to get E-Switch vport identifiers the mlx5 PMD relies
on two approaches:
[a] use port query API if it is provided by rdma-core library
[

common/mlx5: use new port query API if available

In order to get E-Switch vport identifiers the mlx5 PMD relies
on two approaches:
[a] use port query API if it is provided by rdma-core library
[b] otherwise, deduce vport ids from the related VF index
The latter is not reliable and may not work with newer kernel
drivers and in some configurations (LAG), causing E-Switch
malfunction. Hence, engaging the port query API is highly
desirable.

Depending on rdma-core version the port query API is:
- very old OFED versions have no query API (approach [b])
- rdma-core OFED < 5.5 provides mlx5dv_query_devx_port,
HAVE_MLX5DV_DR_DEVX_PORT flag is defined (approach [a])
- rdma-core OFED >= 5.5 has mlx5dv_query_port, flag
HAVE_MLX5DV_DR_DEVX_PORT_V35 is defined (approach [a])
- future OFED versions might remove mlx5dv_query_devx_port
and HAVE_MLX5DV_DR_DEVX_PORT will not be defined
- Upstream rdma-core < v35 has no port query API (approach [b])
- Upstream rdma-core >= v35 has mlx5dv_query_port, flag
HAVE_MLX5DV_DR_DEVX_PORT_V35 is defined (approach [a])

In order to support the new mlx5dv_query_port routine, the
conditional compilation flag HAVE_MLX5DV_DR_DEVX_PORT_V35
is introduced by this patch. The flag HAVE_MLX5DV_DR_DEVX_PORT
is kept for compatibility with previous rdma-core versions.

Despite this patch is not a bugfix (it follows the introduced API
variation in underlying library), it resolves the compatibility
issue and is highly desired to be ported to DPDK LTS.

Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: control flow rules with identical pattern

In order to allow\disallow configuring rules with identical
patterns, the new device argument 'allow_duplicate_pattern'
is introduced.
If allow, t

net/mlx5: control flow rules with identical pattern

In order to allow\disallow configuring rules with identical
patterns, the new device argument 'allow_duplicate_pattern'
is introduced.
If allow, these rules be inserted successfully and only the
first rule take affect.
If disallow, the first rule will be inserted and other rules
be rejected.

The default is to allow.
Set it to 0 if disallow, for example:
-a <PCI_BDF>,allow_duplicate_pattern=0

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: optimize meter profile lookup

Currently a list is used to save all meter profile ids, which is
not efficient when looking up profile from huge amount of profiles.

This changes to use an l

net/mlx5: optimize meter profile lookup

Currently a list is used to save all meter profile ids, which is
not efficient when looking up profile from huge amount of profiles.

This changes to use an l3 table instead to save meter profile ids,
so as to improve the lookup performance.

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: fix switchdev mode recognition

The new kernels might add the switch_id attribute to the
Netlink replies and this caused the wrong recognition
of the E-Switch presence. The single uplink de

net/mlx5: fix switchdev mode recognition

The new kernels might add the switch_id attribute to the
Netlink replies and this caused the wrong recognition
of the E-Switch presence. The single uplink device was
erroneously recognized as master and it caused the
extending match for source vport index on all installed
flows, including the default ones, and adding extra hops
in the steering engine, that affected the maximal
throughput packet rate.

The extra check for the new device name format (it supposes
the new kernel) and the device is only one is added. If this
check succeeds the E-Switch presence is considered as wrongly
detected and overridden.

Fixes: 30a86157f6d5 ("net/mlx5: support PF representor")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: fix loopback for Direct Verbs queue

In the past, all the queues and other hardware objects were created
through Verbs interface. Currently, most of the objects creation are
migrated to Dev

net/mlx5: fix loopback for Direct Verbs queue

In the past, all the queues and other hardware objects were created
through Verbs interface. Currently, most of the objects creation are
migrated to Devx interface by default, including queues. Only when
the DV is disabled by device arg or eswitch is enabled, all or some
of the objects are created through Verbs interface.

When using Devx interface to create queues, the kernel driver
behavior is different from the case using Verbs. The Tx loopback
cannot work properly even if the Tx and Rx queues are configured
with loopback attribute. To fix the support self loopback for Tx, a
Verbs dummy queue pair needs to be created to trigger the kernel to
enable the global loopback capability.

This is only required when TIR is created for Rx and loopback is
needed. Only CQ and QP are needed for this case, no WQ(RQ) needs to
be created.

Bugzilla ID: 645
Fixes: 6deb19e1b2d2 ("net/mlx5: separate Rx queue object creations")
Cc: stable@dpdk.org

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: fix LAG representor probing on PF1 PCI

In case of bonding, orchestrator wants to use same devargs for LAG and
non-LAG scenario to probe representor on PF1 using PF1 PCI address
like "<DBDF

net/mlx5: fix LAG representor probing on PF1 PCI

In case of bonding, orchestrator wants to use same devargs for LAG and
non-LAG scenario to probe representor on PF1 using PF1 PCI address
like "<DBDF_PF1>,representor=pf1vf[0-3]".

This patch changes PCI address check policy to allow PF1 PCI address for
representors on PF1.

Note: detaching PF0 device can't remove representors on PF1. It's
recommended to use primary(PF0) PCI address to probe representors on
both PFs.

Fixes: f926cce3fa94 ("net/mlx5: refactor bonding representor probing")
Cc: stable@dpdk.org

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5/linux: fix firmware version

This patch fixes a bug where firmware version was not
copied from ibv_device_attr structure into mlx5_dev_attr
structure, resulting in inability to read firmware

net/mlx5/linux: fix firmware version

This patch fixes a bug where firmware version was not
copied from ibv_device_attr structure into mlx5_dev_attr
structure, resulting in inability to read firmware
version.

Fixes: e85f623e13ea ("net/mlx5: remove attributes dependency on Verbs")
Cc: stable@dpdk.org

Signed-off-by: Kamil Vojanec <xvojan00@stud.fit.vutbr.cz>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5/linux: fix missed Rx packet stats

There was a typo - the device context was wrongly provided
instead of counter's one for the DevX query operation.

Fixes: e6988afdc75a ("net/mlx5: fix imis

net/mlx5/linux: fix missed Rx packet stats

There was a typo - the device context was wrongly provided
instead of counter's one for the DevX query operation.

Fixes: e6988afdc75a ("net/mlx5: fix imissed statistics")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: initialize connection tracking management

The definitions of ASO connection tracking objects management
structures are added.

Considering performance, the bulk allocation of ASO CT object

net/mlx5: initialize connection tracking management

The definitions of ASO connection tracking objects management
structures are added.

Considering performance, the bulk allocation of ASO CT objects
should be used. The maximal value per bulk and the granularity could
be fetched from HCA capabilities 2. Right now, a fixed number of 64
is used for each bulk for a better management purpose.

The ASO QP for CT is initialized, the SQ will be used for both
modify and query command.

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: fix probing device in legacy bonding mode

If the device was configured as legacy bond one (without
involving E-Switch), the mlx5 PMD erroneously tried to deduce
the vport index raising the

net/mlx5: fix probing device in legacy bonding mode

If the device was configured as legacy bond one (without
involving E-Switch), the mlx5 PMD erroneously tried to deduce
the vport index raising the fatal error and preventing
device from being used.

The patch checks whether there is E-Switch present and we
should use vport index indeed.

Fixes: 2eb4d0107acc ("net/mlx5: refactor PCI probing on Linux")
Fixes: d5c06b1b10ae ("net/mlx5: query vport index match mode and parameters")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: support meter creation with policy

Create a meter with the new pre-defined policy.

The following cases to be considered:
1.Add entry match with meter_id in global drop table.
2.For non-te

net/mlx5: support meter creation with policy

Create a meter with the new pre-defined policy.

The following cases to be considered:
1.Add entry match with meter_id in global drop table.
2.For non-termination policy (policy id 0),
add jump rule to suffix table for green and
jump rule to drop table for red.
3.Allocate counter per meter in drop table.
4.Allocate meter resource per domain per color.
5.It can work with both ASO and legacy meter HW objects.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: support meter policy operations

MLX5 PMD checks the validation of actions in policy while add
a new meter policy, if pass the validation, allocates the new
policy object from the meter pol

net/mlx5: support meter policy operations

MLX5 PMD checks the validation of actions in policy while add
a new meter policy, if pass the validation, allocates the new
policy object from the meter policy indexed memory pool.

It is common to use the same policy for multiple meters.
MLX5 PMD supports two types of policy: termination policy and
no-termination policy.

Implement the next policy operations:
validate:
The driver doesn't support to configure actions in the flow
after the meter action except one case when the meter policy
is configured to do nothing in GREEN\YELLOW and only DROP action
in RED, this special policy is called non-terminated policy
and is handed as a singleton object internally.

For all the terminated policies, the next actions are supported:
GREEN - QUEUE, RSS, PORT_ID, JUMP, DROP, MARK and SET_TAG.
YELLOW - not supported at all -> must be empty.
RED - must include DROP action.

Hence, in ingress case, for example,
QUEUE\RSS\JUMP must be configured as last action for GREEN color.

All the above limitations will be validated.

create:
Validate the policy configuration.
Prepare the related tables and actions.

destroy:
Release the created policy resources.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: support ASO meter action

When ASO action is available, use it as the meter action

Signed-off-by: Shun Hao <shunh@nvidia.com>
Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azra

net/mlx5: support ASO meter action

When ASO action is available, use it as the meter action

Signed-off-by: Shun Hao <shunh@nvidia.com>
Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: initialize flow meter ASO SQ

Initialize the flow meter ASO SQ WQEs with
all the constant data that should not be updated
per enqueue operation.

Signed-off-by: Li Zhang <lizh@nvidia.com>
A

net/mlx5: initialize flow meter ASO SQ

Initialize the flow meter ASO SQ WQEs with
all the constant data that should not be updated
per enqueue operation.

Signed-off-by: Li Zhang <lizh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: separate Tx function declarations to another file

This patch separates Tx function declarations to different header file
in preparation for removing their implementation from the source fi

net/mlx5: separate Tx function declarations to another file

This patch separates Tx function declarations to different header file
in preparation for removing their implementation from the source file
and as an optional preparation for Tx cleanup.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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