1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_rx.h" 44 #include "mlx5_tx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_mr.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 54 55 #ifndef HAVE_IBV_MLX5_MOD_MPW 56 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 57 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 58 #endif 59 60 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 61 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 62 #endif 63 64 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 65 66 /* Spinlock for mlx5_shared_data allocation. */ 67 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 68 69 /* Process local data for secondary processes. */ 70 static struct mlx5_local_data mlx5_local_data; 71 72 /** 73 * Set the completion channel file descriptor interrupt as non-blocking. 74 * 75 * @param[in] rxq_obj 76 * Pointer to RQ channel object, which includes the channel fd 77 * 78 * @param[out] fd 79 * The file descriptor (representing the intetrrupt) used in this channel. 80 * 81 * @return 82 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 83 */ 84 int 85 mlx5_os_set_nonblock_channel_fd(int fd) 86 { 87 int flags; 88 89 flags = fcntl(fd, F_GETFL); 90 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 91 } 92 93 /** 94 * Get mlx5 device attributes. The glue function query_device_ex() is called 95 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 96 * device attributes from the glue out parameter. 97 * 98 * @param dev 99 * Pointer to ibv context. 100 * 101 * @param device_attr 102 * Pointer to mlx5 device attributes. 103 * 104 * @return 105 * 0 on success, non zero error number otherwise 106 */ 107 int 108 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 109 { 110 int err; 111 struct ibv_device_attr_ex attr_ex; 112 memset(device_attr, 0, sizeof(*device_attr)); 113 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 114 if (err) 115 return err; 116 117 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 118 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 119 device_attr->max_sge = attr_ex.orig_attr.max_sge; 120 device_attr->max_cq = attr_ex.orig_attr.max_cq; 121 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 122 device_attr->max_mr = attr_ex.orig_attr.max_mr; 123 device_attr->max_pd = attr_ex.orig_attr.max_pd; 124 device_attr->max_qp = attr_ex.orig_attr.max_qp; 125 device_attr->max_srq = attr_ex.orig_attr.max_srq; 126 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 127 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 128 device_attr->max_rwq_indirection_table_size = 129 attr_ex.rss_caps.max_rwq_indirection_table_size; 130 device_attr->max_tso = attr_ex.tso_caps.max_tso; 131 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 132 133 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 134 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 135 if (err) 136 return err; 137 138 device_attr->flags = dv_attr.flags; 139 device_attr->comp_mask = dv_attr.comp_mask; 140 #ifdef HAVE_IBV_MLX5_MOD_SWP 141 device_attr->sw_parsing_offloads = 142 dv_attr.sw_parsing_caps.sw_parsing_offloads; 143 #endif 144 device_attr->min_single_stride_log_num_of_bytes = 145 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 146 device_attr->max_single_stride_log_num_of_bytes = 147 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 148 device_attr->min_single_wqe_log_num_of_strides = 149 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 150 device_attr->max_single_wqe_log_num_of_strides = 151 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 152 device_attr->stride_supported_qpts = 153 dv_attr.striding_rq_caps.supported_qpts; 154 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 155 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 156 #endif 157 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 158 sizeof(device_attr->fw_ver)); 159 160 return err; 161 } 162 163 /** 164 * Verbs callback to allocate a memory. This function should allocate the space 165 * according to the size provided residing inside a huge page. 166 * Please note that all allocation must respect the alignment from libmlx5 167 * (i.e. currently rte_mem_page_size()). 168 * 169 * @param[in] size 170 * The size in bytes of the memory to allocate. 171 * @param[in] data 172 * A pointer to the callback data. 173 * 174 * @return 175 * Allocated buffer, NULL otherwise and rte_errno is set. 176 */ 177 static void * 178 mlx5_alloc_verbs_buf(size_t size, void *data) 179 { 180 struct mlx5_dev_ctx_shared *sh = data; 181 void *ret; 182 size_t alignment = rte_mem_page_size(); 183 if (alignment == (size_t)-1) { 184 DRV_LOG(ERR, "Failed to get mem page size"); 185 rte_errno = ENOMEM; 186 return NULL; 187 } 188 189 MLX5_ASSERT(data != NULL); 190 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 191 if (!ret && size) 192 rte_errno = ENOMEM; 193 return ret; 194 } 195 196 /** 197 * Verbs callback to free a memory. 198 * 199 * @param[in] ptr 200 * A pointer to the memory to free. 201 * @param[in] data 202 * A pointer to the callback data. 203 */ 204 static void 205 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 206 { 207 MLX5_ASSERT(data != NULL); 208 mlx5_free(ptr); 209 } 210 211 /** 212 * Initialize DR related data within private structure. 213 * Routine checks the reference counter and does actual 214 * resources creation/initialization only if counter is zero. 215 * 216 * @param[in] priv 217 * Pointer to the private device data structure. 218 * 219 * @return 220 * Zero on success, positive error code otherwise. 221 */ 222 static int 223 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 224 { 225 struct mlx5_dev_ctx_shared *sh = priv->sh; 226 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 227 int err; 228 229 MLX5_ASSERT(sh && sh->refcnt); 230 if (sh->refcnt > 1) 231 return 0; 232 err = mlx5_alloc_table_hash_list(priv); 233 if (err) 234 goto error; 235 /* The resources below are only valid with DV support. */ 236 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 237 /* Init port id action cache list. */ 238 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 239 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 240 flow_dv_port_id_create_cb, 241 flow_dv_port_id_match_cb, 242 flow_dv_port_id_remove_cb); 243 /* Init push vlan action cache list. */ 244 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 245 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 246 flow_dv_push_vlan_create_cb, 247 flow_dv_push_vlan_match_cb, 248 flow_dv_push_vlan_remove_cb); 249 /* Init sample action cache list. */ 250 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 251 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 252 flow_dv_sample_create_cb, 253 flow_dv_sample_match_cb, 254 flow_dv_sample_remove_cb); 255 /* Init dest array action cache list. */ 256 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 257 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 258 flow_dv_dest_array_create_cb, 259 flow_dv_dest_array_match_cb, 260 flow_dv_dest_array_remove_cb); 261 /* Create tags hash list table. */ 262 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 263 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 264 MLX5_HLIST_WRITE_MOST, 265 flow_dv_tag_create_cb, 266 flow_dv_tag_match_cb, 267 flow_dv_tag_remove_cb); 268 if (!sh->tag_table) { 269 DRV_LOG(ERR, "tags with hash creation failed."); 270 err = ENOMEM; 271 goto error; 272 } 273 sh->tag_table->ctx = sh; 274 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 275 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 276 0, MLX5_HLIST_WRITE_MOST | 277 MLX5_HLIST_DIRECT_KEY, 278 flow_dv_modify_create_cb, 279 flow_dv_modify_match_cb, 280 flow_dv_modify_remove_cb); 281 if (!sh->modify_cmds) { 282 DRV_LOG(ERR, "hdr modify hash creation failed"); 283 err = ENOMEM; 284 goto error; 285 } 286 sh->modify_cmds->ctx = sh; 287 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 288 sh->encaps_decaps = mlx5_hlist_create(s, 289 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 290 0, MLX5_HLIST_DIRECT_KEY | 291 MLX5_HLIST_WRITE_MOST, 292 flow_dv_encap_decap_create_cb, 293 flow_dv_encap_decap_match_cb, 294 flow_dv_encap_decap_remove_cb); 295 if (!sh->encaps_decaps) { 296 DRV_LOG(ERR, "encap decap hash creation failed"); 297 err = ENOMEM; 298 goto error; 299 } 300 sh->encaps_decaps->ctx = sh; 301 #endif 302 #ifdef HAVE_MLX5DV_DR 303 void *domain; 304 305 /* Reference counter is zero, we should initialize structures. */ 306 domain = mlx5_glue->dr_create_domain(sh->ctx, 307 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 308 if (!domain) { 309 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 310 err = errno; 311 goto error; 312 } 313 sh->rx_domain = domain; 314 domain = mlx5_glue->dr_create_domain(sh->ctx, 315 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 316 if (!domain) { 317 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 318 err = errno; 319 goto error; 320 } 321 sh->tx_domain = domain; 322 #ifdef HAVE_MLX5DV_DR_ESWITCH 323 if (priv->config.dv_esw_en) { 324 domain = mlx5_glue->dr_create_domain 325 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 326 if (!domain) { 327 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 328 err = errno; 329 goto error; 330 } 331 sh->fdb_domain = domain; 332 } 333 /* 334 * The drop action is just some dummy placeholder in rdma-core. It 335 * does not belong to domains and has no any attributes, and, can be 336 * shared by the entire device. 337 */ 338 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 339 if (!sh->dr_drop_action) { 340 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 341 err = errno; 342 goto error; 343 } 344 #endif 345 if (!sh->tunnel_hub) 346 err = mlx5_alloc_tunnel_hub(sh); 347 if (err) { 348 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 349 goto error; 350 } 351 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 352 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 353 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 354 if (sh->fdb_domain) 355 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 356 } 357 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 358 #endif /* HAVE_MLX5DV_DR */ 359 sh->default_miss_action = 360 mlx5_glue->dr_create_flow_action_default_miss(); 361 if (!sh->default_miss_action) 362 DRV_LOG(WARNING, "Default miss action is not supported."); 363 return 0; 364 error: 365 /* Rollback the created objects. */ 366 if (sh->rx_domain) { 367 mlx5_glue->dr_destroy_domain(sh->rx_domain); 368 sh->rx_domain = NULL; 369 } 370 if (sh->tx_domain) { 371 mlx5_glue->dr_destroy_domain(sh->tx_domain); 372 sh->tx_domain = NULL; 373 } 374 if (sh->fdb_domain) { 375 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 376 sh->fdb_domain = NULL; 377 } 378 if (sh->dr_drop_action) { 379 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 380 sh->dr_drop_action = NULL; 381 } 382 if (sh->pop_vlan_action) { 383 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 384 sh->pop_vlan_action = NULL; 385 } 386 if (sh->encaps_decaps) { 387 mlx5_hlist_destroy(sh->encaps_decaps); 388 sh->encaps_decaps = NULL; 389 } 390 if (sh->modify_cmds) { 391 mlx5_hlist_destroy(sh->modify_cmds); 392 sh->modify_cmds = NULL; 393 } 394 if (sh->tag_table) { 395 /* tags should be destroyed with flow before. */ 396 mlx5_hlist_destroy(sh->tag_table); 397 sh->tag_table = NULL; 398 } 399 if (sh->tunnel_hub) { 400 mlx5_release_tunnel_hub(sh, priv->dev_port); 401 sh->tunnel_hub = NULL; 402 } 403 mlx5_free_table_hash_list(priv); 404 return err; 405 } 406 407 /** 408 * Destroy DR related data within private structure. 409 * 410 * @param[in] priv 411 * Pointer to the private device data structure. 412 */ 413 void 414 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 415 { 416 struct mlx5_dev_ctx_shared *sh = priv->sh; 417 418 MLX5_ASSERT(sh && sh->refcnt); 419 if (sh->refcnt > 1) 420 return; 421 #ifdef HAVE_MLX5DV_DR 422 if (sh->rx_domain) { 423 mlx5_glue->dr_destroy_domain(sh->rx_domain); 424 sh->rx_domain = NULL; 425 } 426 if (sh->tx_domain) { 427 mlx5_glue->dr_destroy_domain(sh->tx_domain); 428 sh->tx_domain = NULL; 429 } 430 #ifdef HAVE_MLX5DV_DR_ESWITCH 431 if (sh->fdb_domain) { 432 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 433 sh->fdb_domain = NULL; 434 } 435 if (sh->dr_drop_action) { 436 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 437 sh->dr_drop_action = NULL; 438 } 439 #endif 440 if (sh->pop_vlan_action) { 441 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 442 sh->pop_vlan_action = NULL; 443 } 444 #endif /* HAVE_MLX5DV_DR */ 445 if (sh->default_miss_action) 446 mlx5_glue->destroy_flow_action 447 (sh->default_miss_action); 448 if (sh->encaps_decaps) { 449 mlx5_hlist_destroy(sh->encaps_decaps); 450 sh->encaps_decaps = NULL; 451 } 452 if (sh->modify_cmds) { 453 mlx5_hlist_destroy(sh->modify_cmds); 454 sh->modify_cmds = NULL; 455 } 456 if (sh->tag_table) { 457 /* tags should be destroyed with flow before. */ 458 mlx5_hlist_destroy(sh->tag_table); 459 sh->tag_table = NULL; 460 } 461 if (sh->tunnel_hub) { 462 mlx5_release_tunnel_hub(sh, priv->dev_port); 463 sh->tunnel_hub = NULL; 464 } 465 mlx5_cache_list_destroy(&sh->port_id_action_list); 466 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 467 mlx5_free_table_hash_list(priv); 468 } 469 470 /** 471 * Initialize shared data between primary and secondary process. 472 * 473 * A memzone is reserved by primary process and secondary processes attach to 474 * the memzone. 475 * 476 * @return 477 * 0 on success, a negative errno value otherwise and rte_errno is set. 478 */ 479 static int 480 mlx5_init_shared_data(void) 481 { 482 const struct rte_memzone *mz; 483 int ret = 0; 484 485 rte_spinlock_lock(&mlx5_shared_data_lock); 486 if (mlx5_shared_data == NULL) { 487 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 488 /* Allocate shared memory. */ 489 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 490 sizeof(*mlx5_shared_data), 491 SOCKET_ID_ANY, 0); 492 if (mz == NULL) { 493 DRV_LOG(ERR, 494 "Cannot allocate mlx5 shared data"); 495 ret = -rte_errno; 496 goto error; 497 } 498 mlx5_shared_data = mz->addr; 499 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 500 rte_spinlock_init(&mlx5_shared_data->lock); 501 } else { 502 /* Lookup allocated shared memory. */ 503 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 504 if (mz == NULL) { 505 DRV_LOG(ERR, 506 "Cannot attach mlx5 shared data"); 507 ret = -rte_errno; 508 goto error; 509 } 510 mlx5_shared_data = mz->addr; 511 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 512 } 513 } 514 error: 515 rte_spinlock_unlock(&mlx5_shared_data_lock); 516 return ret; 517 } 518 519 /** 520 * PMD global initialization. 521 * 522 * Independent from individual device, this function initializes global 523 * per-PMD data structures distinguishing primary and secondary processes. 524 * Hence, each initialization is called once per a process. 525 * 526 * @return 527 * 0 on success, a negative errno value otherwise and rte_errno is set. 528 */ 529 static int 530 mlx5_init_once(void) 531 { 532 struct mlx5_shared_data *sd; 533 struct mlx5_local_data *ld = &mlx5_local_data; 534 int ret = 0; 535 536 if (mlx5_init_shared_data()) 537 return -rte_errno; 538 sd = mlx5_shared_data; 539 MLX5_ASSERT(sd); 540 rte_spinlock_lock(&sd->lock); 541 switch (rte_eal_process_type()) { 542 case RTE_PROC_PRIMARY: 543 if (sd->init_done) 544 break; 545 LIST_INIT(&sd->mem_event_cb_list); 546 rte_rwlock_init(&sd->mem_event_rwlock); 547 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 548 mlx5_mr_mem_event_cb, NULL); 549 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 550 mlx5_mp_os_primary_handle); 551 if (ret) 552 goto out; 553 sd->init_done = true; 554 break; 555 case RTE_PROC_SECONDARY: 556 if (ld->init_done) 557 break; 558 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 559 mlx5_mp_os_secondary_handle); 560 if (ret) 561 goto out; 562 ++sd->secondary_cnt; 563 ld->init_done = true; 564 break; 565 default: 566 break; 567 } 568 out: 569 rte_spinlock_unlock(&sd->lock); 570 return ret; 571 } 572 573 /** 574 * Create the Tx queue DevX/Verbs object. 575 * 576 * @param dev 577 * Pointer to Ethernet device. 578 * @param idx 579 * Queue index in DPDK Tx queue array. 580 * 581 * @return 582 * 0 on success, a negative errno value otherwise and rte_errno is set. 583 */ 584 static int 585 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 586 { 587 struct mlx5_priv *priv = dev->data->dev_private; 588 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 589 struct mlx5_txq_ctrl *txq_ctrl = 590 container_of(txq_data, struct mlx5_txq_ctrl, txq); 591 592 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 593 return mlx5_txq_devx_obj_new(dev, idx); 594 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 595 if (!priv->config.dv_esw_en) 596 return mlx5_txq_devx_obj_new(dev, idx); 597 #endif 598 return mlx5_txq_ibv_obj_new(dev, idx); 599 } 600 601 /** 602 * Release an Tx DevX/verbs queue object. 603 * 604 * @param txq_obj 605 * DevX/Verbs Tx queue object. 606 */ 607 static void 608 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 609 { 610 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 611 mlx5_txq_devx_obj_release(txq_obj); 612 return; 613 } 614 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 615 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 616 mlx5_txq_devx_obj_release(txq_obj); 617 return; 618 } 619 #endif 620 mlx5_txq_ibv_obj_release(txq_obj); 621 } 622 623 /** 624 * DV flow counter mode detect and config. 625 * 626 * @param dev 627 * Pointer to rte_eth_dev structure. 628 * 629 */ 630 static void 631 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 632 { 633 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 634 struct mlx5_priv *priv = dev->data->dev_private; 635 struct mlx5_dev_ctx_shared *sh = priv->sh; 636 bool fallback; 637 638 #ifndef HAVE_IBV_DEVX_ASYNC 639 fallback = true; 640 #else 641 fallback = false; 642 if (!priv->config.devx || !priv->config.dv_flow_en || 643 !priv->config.hca_attr.flow_counters_dump || 644 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 645 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 646 fallback = true; 647 #endif 648 if (fallback) 649 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 650 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 651 priv->config.hca_attr.flow_counters_dump, 652 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 653 /* Initialize fallback mode only on the port initializes sh. */ 654 if (sh->refcnt == 1) 655 sh->cmng.counter_fallback = fallback; 656 else if (fallback != sh->cmng.counter_fallback) 657 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 658 "with others:%d.", PORT_ID(priv), fallback); 659 #endif 660 } 661 662 static void 663 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 664 { 665 struct mlx5_priv *priv = dev->data->dev_private; 666 void *ctx = priv->sh->ctx; 667 668 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 669 if (!priv->q_counters) { 670 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 671 struct ibv_wq *wq; 672 673 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 674 "by DevX - fall-back to use the kernel driver global " 675 "queue counter.", dev->data->port_id); 676 /* Create WQ by kernel and query its queue counter ID. */ 677 if (cq) { 678 wq = mlx5_glue->create_wq(ctx, 679 &(struct ibv_wq_init_attr){ 680 .wq_type = IBV_WQT_RQ, 681 .max_wr = 1, 682 .max_sge = 1, 683 .pd = priv->sh->pd, 684 .cq = cq, 685 }); 686 if (wq) { 687 /* Counter is assigned only on RDY state. */ 688 int ret = mlx5_glue->modify_wq(wq, 689 &(struct ibv_wq_attr){ 690 .attr_mask = IBV_WQ_ATTR_STATE, 691 .wq_state = IBV_WQS_RDY, 692 }); 693 694 if (ret == 0) 695 mlx5_devx_cmd_wq_query(wq, 696 &priv->counter_set_id); 697 claim_zero(mlx5_glue->destroy_wq(wq)); 698 } 699 claim_zero(mlx5_glue->destroy_cq(cq)); 700 } 701 } else { 702 priv->counter_set_id = priv->q_counters->id; 703 } 704 if (priv->counter_set_id == 0) 705 DRV_LOG(INFO, "Part of the port %d statistics will not be " 706 "available.", dev->data->port_id); 707 } 708 709 /** 710 * Check if representor spawn info match devargs. 711 * 712 * @param spawn 713 * Verbs device parameters (name, port, switch_info) to spawn. 714 * @param eth_da 715 * Device devargs to probe. 716 * 717 * @return 718 * Match result. 719 */ 720 static bool 721 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 722 struct rte_eth_devargs *eth_da) 723 { 724 struct mlx5_switch_info *switch_info = &spawn->info; 725 unsigned int p, f; 726 uint16_t id; 727 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 728 eth_da->type); 729 730 switch (eth_da->type) { 731 case RTE_ETH_REPRESENTOR_SF: 732 if (!(spawn->info.port_name == -1 && 733 switch_info->name_type == 734 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 735 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 736 rte_errno = EBUSY; 737 return false; 738 } 739 break; 740 case RTE_ETH_REPRESENTOR_VF: 741 /* Allows HPF representor index -1 as exception. */ 742 if (!(spawn->info.port_name == -1 && 743 switch_info->name_type == 744 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 745 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 746 rte_errno = EBUSY; 747 return false; 748 } 749 break; 750 case RTE_ETH_REPRESENTOR_NONE: 751 rte_errno = EBUSY; 752 return false; 753 default: 754 rte_errno = ENOTSUP; 755 DRV_LOG(ERR, "unsupported representor type"); 756 return false; 757 } 758 /* Check representor ID: */ 759 for (p = 0; p < eth_da->nb_ports; ++p) { 760 if (spawn->pf_bond < 0) { 761 /* For non-LAG mode, allow and ignore pf. */ 762 switch_info->pf_num = eth_da->ports[p]; 763 repr_id = mlx5_representor_id_encode(switch_info, 764 eth_da->type); 765 } 766 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 767 id = MLX5_REPRESENTOR_ID 768 (eth_da->ports[p], eth_da->type, 769 eth_da->representor_ports[f]); 770 if (repr_id == id) 771 return true; 772 } 773 } 774 rte_errno = EBUSY; 775 return false; 776 } 777 778 779 /** 780 * Spawn an Ethernet device from Verbs information. 781 * 782 * @param dpdk_dev 783 * Backing DPDK device. 784 * @param spawn 785 * Verbs device parameters (name, port, switch_info) to spawn. 786 * @param config 787 * Device configuration parameters. 788 * @param config 789 * Device arguments. 790 * 791 * @return 792 * A valid Ethernet device object on success, NULL otherwise and rte_errno 793 * is set. The following errors are defined: 794 * 795 * EBUSY: device is not supposed to be spawned. 796 * EEXIST: device is already spawned 797 */ 798 static struct rte_eth_dev * 799 mlx5_dev_spawn(struct rte_device *dpdk_dev, 800 struct mlx5_dev_spawn_data *spawn, 801 struct mlx5_dev_config *config, 802 struct rte_eth_devargs *eth_da) 803 { 804 const struct mlx5_switch_info *switch_info = &spawn->info; 805 struct mlx5_dev_ctx_shared *sh = NULL; 806 struct ibv_port_attr port_attr; 807 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 808 struct rte_eth_dev *eth_dev = NULL; 809 struct mlx5_priv *priv = NULL; 810 int err = 0; 811 unsigned int hw_padding = 0; 812 unsigned int mps; 813 unsigned int tunnel_en = 0; 814 unsigned int mpls_en = 0; 815 unsigned int swp = 0; 816 unsigned int mprq = 0; 817 unsigned int mprq_min_stride_size_n = 0; 818 unsigned int mprq_max_stride_size_n = 0; 819 unsigned int mprq_min_stride_num_n = 0; 820 unsigned int mprq_max_stride_num_n = 0; 821 struct rte_ether_addr mac; 822 char name[RTE_ETH_NAME_MAX_LEN]; 823 int own_domain_id = 0; 824 uint16_t port_id; 825 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 826 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 827 #endif 828 829 /* Determine if this port representor is supposed to be spawned. */ 830 if (switch_info->representor && dpdk_dev->devargs && 831 !mlx5_representor_match(spawn, eth_da)) 832 return NULL; 833 /* Build device name. */ 834 if (spawn->pf_bond < 0) { 835 /* Single device. */ 836 if (!switch_info->representor) 837 strlcpy(name, dpdk_dev->name, sizeof(name)); 838 else 839 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 840 dpdk_dev->name, 841 switch_info->name_type == 842 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 843 switch_info->port_name); 844 } else { 845 /* Bonding device. */ 846 if (!switch_info->representor) { 847 err = snprintf(name, sizeof(name), "%s_%s", 848 dpdk_dev->name, 849 mlx5_os_get_dev_device_name(spawn->phys_dev)); 850 } else { 851 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 852 dpdk_dev->name, 853 mlx5_os_get_dev_device_name(spawn->phys_dev), 854 switch_info->ctrl_num, 855 switch_info->pf_num, 856 switch_info->name_type == 857 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 858 switch_info->port_name); 859 } 860 } 861 if (err >= (int)sizeof(name)) 862 DRV_LOG(WARNING, "device name overflow %s", name); 863 /* check if the device is already spawned */ 864 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 865 rte_errno = EEXIST; 866 return NULL; 867 } 868 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 869 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 870 struct mlx5_mp_id mp_id; 871 872 eth_dev = rte_eth_dev_attach_secondary(name); 873 if (eth_dev == NULL) { 874 DRV_LOG(ERR, "can not attach rte ethdev"); 875 rte_errno = ENOMEM; 876 return NULL; 877 } 878 eth_dev->device = dpdk_dev; 879 eth_dev->dev_ops = &mlx5_dev_sec_ops; 880 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 881 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 882 err = mlx5_proc_priv_init(eth_dev); 883 if (err) 884 return NULL; 885 mp_id.port_id = eth_dev->data->port_id; 886 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 887 /* Receive command fd from primary process */ 888 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 889 if (err < 0) 890 goto err_secondary; 891 /* Remap UAR for Tx queues. */ 892 err = mlx5_tx_uar_init_secondary(eth_dev, err); 893 if (err) 894 goto err_secondary; 895 /* 896 * Ethdev pointer is still required as input since 897 * the primary device is not accessible from the 898 * secondary process. 899 */ 900 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 901 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 902 return eth_dev; 903 err_secondary: 904 mlx5_dev_close(eth_dev); 905 return NULL; 906 } 907 /* 908 * Some parameters ("tx_db_nc" in particularly) are needed in 909 * advance to create dv/verbs device context. We proceed the 910 * devargs here to get ones, and later proceed devargs again 911 * to override some hardware settings. 912 */ 913 err = mlx5_args(config, dpdk_dev->devargs); 914 if (err) { 915 err = rte_errno; 916 DRV_LOG(ERR, "failed to process device arguments: %s", 917 strerror(rte_errno)); 918 goto error; 919 } 920 if (config->dv_miss_info) { 921 if (switch_info->master || switch_info->representor) 922 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 923 } 924 mlx5_malloc_mem_select(config->sys_mem_en); 925 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 926 if (!sh) 927 return NULL; 928 config->devx = sh->devx; 929 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 930 config->dest_tir = 1; 931 #endif 932 #ifdef HAVE_IBV_MLX5_MOD_SWP 933 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 934 #endif 935 /* 936 * Multi-packet send is supported by ConnectX-4 Lx PF as well 937 * as all ConnectX-5 devices. 938 */ 939 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 940 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 941 #endif 942 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 943 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 944 #endif 945 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 946 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 947 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 948 DRV_LOG(DEBUG, "enhanced MPW is supported"); 949 mps = MLX5_MPW_ENHANCED; 950 } else { 951 DRV_LOG(DEBUG, "MPW is supported"); 952 mps = MLX5_MPW; 953 } 954 } else { 955 DRV_LOG(DEBUG, "MPW isn't supported"); 956 mps = MLX5_MPW_DISABLED; 957 } 958 #ifdef HAVE_IBV_MLX5_MOD_SWP 959 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 960 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 961 DRV_LOG(DEBUG, "SWP support: %u", swp); 962 #endif 963 config->swp = !!swp; 964 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 965 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 966 struct mlx5dv_striding_rq_caps mprq_caps = 967 dv_attr.striding_rq_caps; 968 969 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 970 mprq_caps.min_single_stride_log_num_of_bytes); 971 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 972 mprq_caps.max_single_stride_log_num_of_bytes); 973 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 974 mprq_caps.min_single_wqe_log_num_of_strides); 975 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 976 mprq_caps.max_single_wqe_log_num_of_strides); 977 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 978 mprq_caps.supported_qpts); 979 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 980 mprq = 1; 981 mprq_min_stride_size_n = 982 mprq_caps.min_single_stride_log_num_of_bytes; 983 mprq_max_stride_size_n = 984 mprq_caps.max_single_stride_log_num_of_bytes; 985 mprq_min_stride_num_n = 986 mprq_caps.min_single_wqe_log_num_of_strides; 987 mprq_max_stride_num_n = 988 mprq_caps.max_single_wqe_log_num_of_strides; 989 } 990 #endif 991 /* Rx CQE compression is enabled by default. */ 992 config->cqe_comp = 1; 993 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 994 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 995 tunnel_en = ((dv_attr.tunnel_offloads_caps & 996 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 997 (dv_attr.tunnel_offloads_caps & 998 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 999 (dv_attr.tunnel_offloads_caps & 1000 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1001 } 1002 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1003 tunnel_en ? "" : "not "); 1004 #else 1005 DRV_LOG(WARNING, 1006 "tunnel offloading disabled due to old OFED/rdma-core version"); 1007 #endif 1008 config->tunnel_en = tunnel_en; 1009 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1010 mpls_en = ((dv_attr.tunnel_offloads_caps & 1011 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1012 (dv_attr.tunnel_offloads_caps & 1013 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1014 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1015 mpls_en ? "" : "not "); 1016 #else 1017 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1018 " old OFED/rdma-core version or firmware configuration"); 1019 #endif 1020 config->mpls_en = mpls_en; 1021 /* Check port status. */ 1022 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1023 if (err) { 1024 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1025 goto error; 1026 } 1027 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1028 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1029 err = EINVAL; 1030 goto error; 1031 } 1032 if (port_attr.state != IBV_PORT_ACTIVE) 1033 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1034 mlx5_glue->port_state_str(port_attr.state), 1035 port_attr.state); 1036 /* Allocate private eth device data. */ 1037 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1038 sizeof(*priv), 1039 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1040 if (priv == NULL) { 1041 DRV_LOG(ERR, "priv allocation failure"); 1042 err = ENOMEM; 1043 goto error; 1044 } 1045 priv->sh = sh; 1046 priv->dev_port = spawn->phys_port; 1047 priv->pci_dev = spawn->pci_dev; 1048 priv->mtu = RTE_ETHER_MTU; 1049 /* Some internal functions rely on Netlink sockets, open them now. */ 1050 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1051 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1052 priv->representor = !!switch_info->representor; 1053 priv->master = !!switch_info->master; 1054 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1055 priv->vport_meta_tag = 0; 1056 priv->vport_meta_mask = 0; 1057 priv->pf_bond = spawn->pf_bond; 1058 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 1059 /* 1060 * The DevX port query API is implemented. E-Switch may use 1061 * either vport or reg_c[0] metadata register to match on 1062 * vport index. The engaged part of metadata register is 1063 * defined by mask. 1064 */ 1065 if (switch_info->representor || switch_info->master) { 1066 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 1067 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 1068 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 1069 &devx_port); 1070 if (err) { 1071 DRV_LOG(WARNING, 1072 "can't query devx port %d on device %s", 1073 spawn->phys_port, 1074 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1075 devx_port.comp_mask = 0; 1076 } 1077 } 1078 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 1079 priv->vport_meta_tag = devx_port.reg_c_0.value; 1080 priv->vport_meta_mask = devx_port.reg_c_0.mask; 1081 if (!priv->vport_meta_mask) { 1082 DRV_LOG(ERR, "vport zero mask for port %d" 1083 " on bonding device %s", 1084 spawn->phys_port, 1085 mlx5_os_get_dev_device_name 1086 (spawn->phys_dev)); 1087 err = ENOTSUP; 1088 goto error; 1089 } 1090 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1091 DRV_LOG(ERR, "invalid vport tag for port %d" 1092 " on bonding device %s", 1093 spawn->phys_port, 1094 mlx5_os_get_dev_device_name 1095 (spawn->phys_dev)); 1096 err = ENOTSUP; 1097 goto error; 1098 } 1099 } 1100 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 1101 priv->vport_id = devx_port.vport_num; 1102 } else if (spawn->pf_bond >= 0 && 1103 (switch_info->representor || switch_info->master)) { 1104 DRV_LOG(ERR, "can't deduce vport index for port %d" 1105 " on bonding device %s", 1106 spawn->phys_port, 1107 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1108 err = ENOTSUP; 1109 goto error; 1110 } else { 1111 /* Suppose vport index in compatible way. */ 1112 priv->vport_id = switch_info->representor ? 1113 switch_info->port_name + 1 : -1; 1114 } 1115 #else 1116 /* 1117 * Kernel/rdma_core support single E-Switch per PF configurations 1118 * only and vport_id field contains the vport index for 1119 * associated VF, which is deduced from representor port name. 1120 * For example, let's have the IB device port 10, it has 1121 * attached network device eth0, which has port name attribute 1122 * pf0vf2, we can deduce the VF number as 2, and set vport index 1123 * as 3 (2+1). This assigning schema should be changed if the 1124 * multiple E-Switch instances per PF configurations or/and PCI 1125 * subfunctions are added. 1126 */ 1127 priv->vport_id = switch_info->representor ? 1128 switch_info->port_name + 1 : -1; 1129 #endif 1130 priv->representor_id = mlx5_representor_id_encode(switch_info, 1131 eth_da->type); 1132 /* 1133 * Look for sibling devices in order to reuse their switch domain 1134 * if any, otherwise allocate one. 1135 */ 1136 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1137 const struct mlx5_priv *opriv = 1138 rte_eth_devices[port_id].data->dev_private; 1139 1140 if (!opriv || 1141 opriv->sh != priv->sh || 1142 opriv->domain_id == 1143 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1144 continue; 1145 priv->domain_id = opriv->domain_id; 1146 break; 1147 } 1148 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1149 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1150 if (err) { 1151 err = rte_errno; 1152 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1153 strerror(rte_errno)); 1154 goto error; 1155 } 1156 own_domain_id = 1; 1157 } 1158 /* Override some values set by hardware configuration. */ 1159 mlx5_args(config, dpdk_dev->devargs); 1160 err = mlx5_dev_check_sibling_config(priv, config); 1161 if (err) 1162 goto error; 1163 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1164 IBV_DEVICE_RAW_IP_CSUM); 1165 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1166 (config->hw_csum ? "" : "not ")); 1167 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1168 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1169 DRV_LOG(DEBUG, "counters are not supported"); 1170 #endif 1171 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1172 if (config->dv_flow_en) { 1173 DRV_LOG(WARNING, "DV flow is not supported"); 1174 config->dv_flow_en = 0; 1175 } 1176 #endif 1177 config->ind_table_max_size = 1178 sh->device_attr.max_rwq_indirection_table_size; 1179 /* 1180 * Remove this check once DPDK supports larger/variable 1181 * indirection tables. 1182 */ 1183 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1184 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1185 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1186 config->ind_table_max_size); 1187 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1188 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1189 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1190 (config->hw_vlan_strip ? "" : "not ")); 1191 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1192 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1193 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1194 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1195 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1196 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1197 IBV_DEVICE_PCI_WRITE_END_PADDING); 1198 #endif 1199 if (config->hw_padding && !hw_padding) { 1200 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1201 config->hw_padding = 0; 1202 } else if (config->hw_padding) { 1203 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1204 } 1205 config->tso = (sh->device_attr.max_tso > 0 && 1206 (sh->device_attr.tso_supported_qpts & 1207 (1 << IBV_QPT_RAW_PACKET))); 1208 if (config->tso) 1209 config->tso_max_payload_sz = sh->device_attr.max_tso; 1210 /* 1211 * MPW is disabled by default, while the Enhanced MPW is enabled 1212 * by default. 1213 */ 1214 if (config->mps == MLX5_ARG_UNSET) 1215 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1216 MLX5_MPW_DISABLED; 1217 else 1218 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1219 DRV_LOG(INFO, "%sMPS is %s", 1220 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1221 config->mps == MLX5_MPW ? "legacy " : "", 1222 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1223 if (config->devx) { 1224 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1225 if (err) { 1226 err = -err; 1227 goto error; 1228 } 1229 /* Check relax ordering support. */ 1230 if (!haswell_broadwell_cpu) { 1231 sh->cmng.relaxed_ordering_write = 1232 config->hca_attr.relaxed_ordering_write; 1233 sh->cmng.relaxed_ordering_read = 1234 config->hca_attr.relaxed_ordering_read; 1235 } else { 1236 sh->cmng.relaxed_ordering_read = 0; 1237 sh->cmng.relaxed_ordering_write = 0; 1238 } 1239 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1240 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1241 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1242 /* Check for LRO support. */ 1243 if (config->dest_tir && config->hca_attr.lro_cap && 1244 config->dv_flow_en) { 1245 /* TBD check tunnel lro caps. */ 1246 config->lro.supported = config->hca_attr.lro_cap; 1247 DRV_LOG(DEBUG, "Device supports LRO"); 1248 /* 1249 * If LRO timeout is not configured by application, 1250 * use the minimal supported value. 1251 */ 1252 if (!config->lro.timeout) 1253 config->lro.timeout = 1254 config->hca_attr.lro_timer_supported_periods[0]; 1255 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1256 config->lro.timeout); 1257 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1258 "required for coalescing is %d bytes", 1259 config->hca_attr.lro_min_mss_size); 1260 } 1261 #if defined(HAVE_MLX5DV_DR) && \ 1262 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1263 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1264 if (config->hca_attr.qos.sup && 1265 config->hca_attr.qos.flow_meter_old && 1266 config->dv_flow_en) { 1267 uint8_t reg_c_mask = 1268 config->hca_attr.qos.flow_meter_reg_c_ids; 1269 /* 1270 * Meter needs two REG_C's for color match and pre-sfx 1271 * flow match. Here get the REG_C for color match. 1272 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1273 */ 1274 reg_c_mask &= 0xfc; 1275 if (__builtin_popcount(reg_c_mask) < 1) { 1276 priv->mtr_en = 0; 1277 DRV_LOG(WARNING, "No available register for" 1278 " meter."); 1279 } else { 1280 /* 1281 * The meter color register is used by the 1282 * flow-hit feature as well. 1283 * The flow-hit feature must use REG_C_3 1284 * Prefer REG_C_3 if it is available. 1285 */ 1286 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1287 priv->mtr_color_reg = REG_C_3; 1288 else 1289 priv->mtr_color_reg = ffs(reg_c_mask) 1290 - 1 + REG_C_0; 1291 priv->mtr_en = 1; 1292 priv->mtr_reg_share = 1293 config->hca_attr.qos.flow_meter; 1294 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1295 priv->mtr_color_reg); 1296 } 1297 } 1298 if (config->hca_attr.qos.sup && 1299 config->hca_attr.qos.flow_meter_aso_sup) { 1300 uint32_t log_obj_size = 1301 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1302 if (log_obj_size >= 1303 config->hca_attr.qos.log_meter_aso_granularity && 1304 log_obj_size <= 1305 config->hca_attr.qos.log_meter_aso_max_alloc) 1306 sh->meter_aso_en = 1; 1307 } 1308 if (priv->mtr_en) { 1309 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1310 if (err) { 1311 err = -err; 1312 goto error; 1313 } 1314 } 1315 #endif 1316 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1317 if (config->hca_attr.flow_hit_aso && 1318 priv->mtr_color_reg == REG_C_3) { 1319 sh->flow_hit_aso_en = 1; 1320 err = mlx5_flow_aso_age_mng_init(sh); 1321 if (err) { 1322 err = -err; 1323 goto error; 1324 } 1325 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1326 } 1327 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1328 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1329 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1330 if (config->hca_attr.ct_offload && 1331 priv->mtr_color_reg == REG_C_3) { 1332 err = mlx5_flow_aso_ct_mng_init(sh); 1333 if (err) { 1334 err = -err; 1335 goto error; 1336 } 1337 DRV_LOG(DEBUG, "CT ASO is supported."); 1338 sh->ct_aso_en = 1; 1339 } 1340 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1341 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1342 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1343 config->dv_flow_en) { 1344 priv->sampler_en = 1; 1345 DRV_LOG(DEBUG, "Sampler enabled!"); 1346 } else { 1347 priv->sampler_en = 0; 1348 if (!config->hca_attr.log_max_ft_sampler_num) 1349 DRV_LOG(WARNING, 1350 "No available register for sampler."); 1351 else 1352 DRV_LOG(DEBUG, "DV flow is not supported!"); 1353 } 1354 #endif 1355 } 1356 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1357 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1358 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1359 config->cqe_comp = 0; 1360 } 1361 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1362 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1363 DRV_LOG(WARNING, "Flow Tag CQE compression" 1364 " format isn't supported."); 1365 config->cqe_comp = 0; 1366 } 1367 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1368 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1369 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1370 " format isn't supported."); 1371 config->cqe_comp = 0; 1372 } 1373 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1374 config->cqe_comp ? "" : "not "); 1375 if (config->tx_pp) { 1376 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1377 config->hca_attr.dev_freq_khz); 1378 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1379 config->hca_attr.qos.packet_pacing ? "" : "not "); 1380 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1381 config->hca_attr.cross_channel ? "" : "not "); 1382 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1383 config->hca_attr.wqe_index_ignore ? "" : "not "); 1384 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1385 config->hca_attr.non_wire_sq ? "" : "not "); 1386 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1387 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1388 config->hca_attr.log_max_static_sq_wq); 1389 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1390 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1391 if (!config->devx) { 1392 DRV_LOG(ERR, "DevX is required for packet pacing"); 1393 err = ENODEV; 1394 goto error; 1395 } 1396 if (!config->hca_attr.qos.packet_pacing) { 1397 DRV_LOG(ERR, "Packet pacing is not supported"); 1398 err = ENODEV; 1399 goto error; 1400 } 1401 if (!config->hca_attr.cross_channel) { 1402 DRV_LOG(ERR, "Cross channel operations are" 1403 " required for packet pacing"); 1404 err = ENODEV; 1405 goto error; 1406 } 1407 if (!config->hca_attr.wqe_index_ignore) { 1408 DRV_LOG(ERR, "WQE index ignore feature is" 1409 " required for packet pacing"); 1410 err = ENODEV; 1411 goto error; 1412 } 1413 if (!config->hca_attr.non_wire_sq) { 1414 DRV_LOG(ERR, "Non-wire SQ feature is" 1415 " required for packet pacing"); 1416 err = ENODEV; 1417 goto error; 1418 } 1419 if (!config->hca_attr.log_max_static_sq_wq) { 1420 DRV_LOG(ERR, "Static WQE SQ feature is" 1421 " required for packet pacing"); 1422 err = ENODEV; 1423 goto error; 1424 } 1425 if (!config->hca_attr.qos.wqe_rate_pp) { 1426 DRV_LOG(ERR, "WQE rate mode is required" 1427 " for packet pacing"); 1428 err = ENODEV; 1429 goto error; 1430 } 1431 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1432 DRV_LOG(ERR, "DevX does not provide UAR offset," 1433 " can't create queues for packet pacing"); 1434 err = ENODEV; 1435 goto error; 1436 #endif 1437 } 1438 if (config->devx) { 1439 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1440 1441 err = config->hca_attr.access_register_user ? 1442 mlx5_devx_cmd_register_read 1443 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1444 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1445 if (!err) { 1446 uint32_t ts_mode; 1447 1448 /* MTUTC register is read successfully. */ 1449 ts_mode = MLX5_GET(register_mtutc, reg, 1450 time_stamp_mode); 1451 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1452 config->rt_timestamp = 1; 1453 } else { 1454 /* Kernel does not support register reading. */ 1455 if (config->hca_attr.dev_freq_khz == 1456 (NS_PER_S / MS_PER_S)) 1457 config->rt_timestamp = 1; 1458 } 1459 } 1460 /* 1461 * If HW has bug working with tunnel packet decapsulation and 1462 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1463 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1464 */ 1465 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1466 config->hw_fcs_strip = 0; 1467 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1468 (config->hw_fcs_strip ? "" : "not ")); 1469 if (config->mprq.enabled && mprq) { 1470 if (config->mprq.stride_num_n && 1471 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1472 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1473 config->mprq.stride_num_n = 1474 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1475 mprq_min_stride_num_n), 1476 mprq_max_stride_num_n); 1477 DRV_LOG(WARNING, 1478 "the number of strides" 1479 " for Multi-Packet RQ is out of range," 1480 " setting default value (%u)", 1481 1 << config->mprq.stride_num_n); 1482 } 1483 if (config->mprq.stride_size_n && 1484 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1485 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1486 config->mprq.stride_size_n = 1487 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1488 mprq_min_stride_size_n), 1489 mprq_max_stride_size_n); 1490 DRV_LOG(WARNING, 1491 "the size of a stride" 1492 " for Multi-Packet RQ is out of range," 1493 " setting default value (%u)", 1494 1 << config->mprq.stride_size_n); 1495 } 1496 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1497 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1498 } else if (config->mprq.enabled && !mprq) { 1499 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1500 config->mprq.enabled = 0; 1501 } 1502 if (config->max_dump_files_num == 0) 1503 config->max_dump_files_num = 128; 1504 eth_dev = rte_eth_dev_allocate(name); 1505 if (eth_dev == NULL) { 1506 DRV_LOG(ERR, "can not allocate rte ethdev"); 1507 err = ENOMEM; 1508 goto error; 1509 } 1510 if (priv->representor) { 1511 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1512 eth_dev->data->representor_id = priv->representor_id; 1513 } 1514 priv->mp_id.port_id = eth_dev->data->port_id; 1515 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1516 /* 1517 * Store associated network device interface index. This index 1518 * is permanent throughout the lifetime of device. So, we may store 1519 * the ifindex here and use the cached value further. 1520 */ 1521 MLX5_ASSERT(spawn->ifindex); 1522 priv->if_index = spawn->ifindex; 1523 eth_dev->data->dev_private = priv; 1524 priv->dev_data = eth_dev->data; 1525 eth_dev->data->mac_addrs = priv->mac; 1526 eth_dev->device = dpdk_dev; 1527 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1528 /* Configure the first MAC address by default. */ 1529 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1530 DRV_LOG(ERR, 1531 "port %u cannot get MAC address, is mlx5_en" 1532 " loaded? (errno: %s)", 1533 eth_dev->data->port_id, strerror(rte_errno)); 1534 err = ENODEV; 1535 goto error; 1536 } 1537 DRV_LOG(INFO, 1538 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1539 eth_dev->data->port_id, 1540 mac.addr_bytes[0], mac.addr_bytes[1], 1541 mac.addr_bytes[2], mac.addr_bytes[3], 1542 mac.addr_bytes[4], mac.addr_bytes[5]); 1543 #ifdef RTE_LIBRTE_MLX5_DEBUG 1544 { 1545 char ifname[MLX5_NAMESIZE]; 1546 1547 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1548 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1549 eth_dev->data->port_id, ifname); 1550 else 1551 DRV_LOG(DEBUG, "port %u ifname is unknown", 1552 eth_dev->data->port_id); 1553 } 1554 #endif 1555 /* Get actual MTU if possible. */ 1556 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1557 if (err) { 1558 err = rte_errno; 1559 goto error; 1560 } 1561 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1562 priv->mtu); 1563 /* Initialize burst functions to prevent crashes before link-up. */ 1564 eth_dev->rx_pkt_burst = removed_rx_burst; 1565 eth_dev->tx_pkt_burst = removed_tx_burst; 1566 eth_dev->dev_ops = &mlx5_dev_ops; 1567 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1568 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1569 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1570 /* Register MAC address. */ 1571 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1572 if (config->vf && config->vf_nl_en) 1573 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1574 mlx5_ifindex(eth_dev), 1575 eth_dev->data->mac_addrs, 1576 MLX5_MAX_MAC_ADDRESSES); 1577 priv->flows = 0; 1578 priv->ctrl_flows = 0; 1579 rte_spinlock_init(&priv->flow_list_lock); 1580 TAILQ_INIT(&priv->flow_meters); 1581 TAILQ_INIT(&priv->flow_meter_profiles); 1582 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1583 mlx5_glue->dv_set_context_attr(sh->ctx, 1584 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1585 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1586 .alloc = &mlx5_alloc_verbs_buf, 1587 .free = &mlx5_free_verbs_buf, 1588 .data = sh, 1589 })); 1590 /* Bring Ethernet device up. */ 1591 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1592 eth_dev->data->port_id); 1593 mlx5_set_link_up(eth_dev); 1594 /* 1595 * Even though the interrupt handler is not installed yet, 1596 * interrupts will still trigger on the async_fd from 1597 * Verbs context returned by ibv_open_device(). 1598 */ 1599 mlx5_link_update(eth_dev, 0); 1600 #ifdef HAVE_MLX5DV_DR_ESWITCH 1601 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1602 (switch_info->representor || switch_info->master))) 1603 config->dv_esw_en = 0; 1604 #else 1605 config->dv_esw_en = 0; 1606 #endif 1607 /* Detect minimal data bytes to inline. */ 1608 mlx5_set_min_inline(spawn, config); 1609 /* Store device configuration on private structure. */ 1610 priv->config = *config; 1611 /* Create context for virtual machine VLAN workaround. */ 1612 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1613 if (config->dv_flow_en) { 1614 err = mlx5_alloc_shared_dr(priv); 1615 if (err) 1616 goto error; 1617 } 1618 if (config->devx && config->dv_flow_en && config->dest_tir) { 1619 priv->obj_ops = devx_obj_ops; 1620 priv->obj_ops.drop_action_create = 1621 ibv_obj_ops.drop_action_create; 1622 priv->obj_ops.drop_action_destroy = 1623 ibv_obj_ops.drop_action_destroy; 1624 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1625 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1626 #else 1627 if (config->dv_esw_en) 1628 priv->obj_ops.txq_obj_modify = 1629 ibv_obj_ops.txq_obj_modify; 1630 #endif 1631 /* Use specific wrappers for Tx object. */ 1632 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1633 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1634 mlx5_queue_counter_id_prepare(eth_dev); 1635 priv->obj_ops.lb_dummy_queue_create = 1636 mlx5_rxq_ibv_obj_dummy_lb_create; 1637 priv->obj_ops.lb_dummy_queue_release = 1638 mlx5_rxq_ibv_obj_dummy_lb_release; 1639 } else { 1640 priv->obj_ops = ibv_obj_ops; 1641 } 1642 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1643 if (!priv->drop_queue.hrxq) 1644 goto error; 1645 /* Supported Verbs flow priority number detection. */ 1646 err = mlx5_flow_discover_priorities(eth_dev); 1647 if (err < 0) { 1648 err = -err; 1649 goto error; 1650 } 1651 priv->config.flow_prio = err; 1652 if (!priv->config.dv_esw_en && 1653 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1654 DRV_LOG(WARNING, "metadata mode %u is not supported " 1655 "(no E-Switch)", priv->config.dv_xmeta_en); 1656 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1657 } 1658 mlx5_set_metadata_mask(eth_dev); 1659 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1660 !priv->sh->dv_regc0_mask) { 1661 DRV_LOG(ERR, "metadata mode %u is not supported " 1662 "(no metadata reg_c[0] is available)", 1663 priv->config.dv_xmeta_en); 1664 err = ENOTSUP; 1665 goto error; 1666 } 1667 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1668 mlx5_hrxq_create_cb, 1669 mlx5_hrxq_match_cb, 1670 mlx5_hrxq_remove_cb); 1671 /* Query availability of metadata reg_c's. */ 1672 err = mlx5_flow_discover_mreg_c(eth_dev); 1673 if (err < 0) { 1674 err = -err; 1675 goto error; 1676 } 1677 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1678 DRV_LOG(DEBUG, 1679 "port %u extensive metadata register is not supported", 1680 eth_dev->data->port_id); 1681 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1682 DRV_LOG(ERR, "metadata mode %u is not supported " 1683 "(no metadata registers available)", 1684 priv->config.dv_xmeta_en); 1685 err = ENOTSUP; 1686 goto error; 1687 } 1688 } 1689 if (priv->config.dv_flow_en && 1690 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1691 mlx5_flow_ext_mreg_supported(eth_dev) && 1692 priv->sh->dv_regc0_mask) { 1693 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1694 MLX5_FLOW_MREG_HTABLE_SZ, 1695 0, 0, 1696 flow_dv_mreg_create_cb, 1697 flow_dv_mreg_match_cb, 1698 flow_dv_mreg_remove_cb); 1699 if (!priv->mreg_cp_tbl) { 1700 err = ENOMEM; 1701 goto error; 1702 } 1703 priv->mreg_cp_tbl->ctx = eth_dev; 1704 } 1705 rte_spinlock_init(&priv->shared_act_sl); 1706 mlx5_flow_counter_mode_config(eth_dev); 1707 if (priv->config.dv_flow_en) 1708 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1709 return eth_dev; 1710 error: 1711 if (priv) { 1712 if (priv->mreg_cp_tbl) 1713 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1714 if (priv->sh) 1715 mlx5_os_free_shared_dr(priv); 1716 if (priv->nl_socket_route >= 0) 1717 close(priv->nl_socket_route); 1718 if (priv->nl_socket_rdma >= 0) 1719 close(priv->nl_socket_rdma); 1720 if (priv->vmwa_context) 1721 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1722 if (eth_dev && priv->drop_queue.hrxq) 1723 mlx5_drop_action_destroy(eth_dev); 1724 if (own_domain_id) 1725 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1726 mlx5_cache_list_destroy(&priv->hrxqs); 1727 mlx5_free(priv); 1728 if (eth_dev != NULL) 1729 eth_dev->data->dev_private = NULL; 1730 } 1731 if (eth_dev != NULL) { 1732 /* mac_addrs must not be freed alone because part of 1733 * dev_private 1734 **/ 1735 eth_dev->data->mac_addrs = NULL; 1736 rte_eth_dev_release_port(eth_dev); 1737 } 1738 if (sh) 1739 mlx5_free_shared_dev_ctx(sh); 1740 MLX5_ASSERT(err > 0); 1741 rte_errno = err; 1742 return NULL; 1743 } 1744 1745 /** 1746 * Comparison callback to sort device data. 1747 * 1748 * This is meant to be used with qsort(). 1749 * 1750 * @param a[in] 1751 * Pointer to pointer to first data object. 1752 * @param b[in] 1753 * Pointer to pointer to second data object. 1754 * 1755 * @return 1756 * 0 if both objects are equal, less than 0 if the first argument is less 1757 * than the second, greater than 0 otherwise. 1758 */ 1759 static int 1760 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1761 { 1762 const struct mlx5_switch_info *si_a = 1763 &((const struct mlx5_dev_spawn_data *)a)->info; 1764 const struct mlx5_switch_info *si_b = 1765 &((const struct mlx5_dev_spawn_data *)b)->info; 1766 int ret; 1767 1768 /* Master device first. */ 1769 ret = si_b->master - si_a->master; 1770 if (ret) 1771 return ret; 1772 /* Then representor devices. */ 1773 ret = si_b->representor - si_a->representor; 1774 if (ret) 1775 return ret; 1776 /* Unidentified devices come last in no specific order. */ 1777 if (!si_a->representor) 1778 return 0; 1779 /* Order representors by name. */ 1780 return si_a->port_name - si_b->port_name; 1781 } 1782 1783 /** 1784 * Match PCI information for possible slaves of bonding device. 1785 * 1786 * @param[in] ibv_dev 1787 * Pointer to Infiniband device structure. 1788 * @param[in] pci_dev 1789 * Pointer to primary PCI address structure to match. 1790 * @param[in] nl_rdma 1791 * Netlink RDMA group socket handle. 1792 * @param[in] owner 1793 * Rerepsentor owner PF index. 1794 * @param[out] bond_info 1795 * Pointer to bonding information. 1796 * 1797 * @return 1798 * negative value if no bonding device found, otherwise 1799 * positive index of slave PF in bonding. 1800 */ 1801 static int 1802 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1803 const struct rte_pci_addr *pci_dev, 1804 int nl_rdma, uint16_t owner, 1805 struct mlx5_bond_info *bond_info) 1806 { 1807 char ifname[IF_NAMESIZE + 1]; 1808 unsigned int ifindex; 1809 unsigned int np, i; 1810 FILE *bond_file = NULL, *file; 1811 int pf = -1; 1812 int ret; 1813 1814 /* 1815 * Try to get master device name. If something goes 1816 * wrong suppose the lack of kernel support and no 1817 * bonding devices. 1818 */ 1819 memset(bond_info, 0, sizeof(*bond_info)); 1820 if (nl_rdma < 0) 1821 return -1; 1822 if (!strstr(ibv_dev->name, "bond")) 1823 return -1; 1824 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1825 if (!np) 1826 return -1; 1827 /* 1828 * The Master device might not be on the predefined 1829 * port (not on port index 1, it is not garanted), 1830 * we have to scan all Infiniband device port and 1831 * find master. 1832 */ 1833 for (i = 1; i <= np; ++i) { 1834 /* Check whether Infiniband port is populated. */ 1835 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1836 if (!ifindex) 1837 continue; 1838 if (!if_indextoname(ifindex, ifname)) 1839 continue; 1840 /* Try to read bonding slave names from sysfs. */ 1841 MKSTR(slaves, 1842 "/sys/class/net/%s/master/bonding/slaves", ifname); 1843 bond_file = fopen(slaves, "r"); 1844 if (bond_file) 1845 break; 1846 } 1847 if (!bond_file) 1848 return -1; 1849 /* Use safe format to check maximal buffer length. */ 1850 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1851 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1852 char tmp_str[IF_NAMESIZE + 32]; 1853 struct rte_pci_addr pci_addr; 1854 struct mlx5_switch_info info; 1855 1856 /* Process slave interface names in the loop. */ 1857 snprintf(tmp_str, sizeof(tmp_str), 1858 "/sys/class/net/%s", ifname); 1859 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1860 DRV_LOG(WARNING, "can not get PCI address" 1861 " for netdev \"%s\"", ifname); 1862 continue; 1863 } 1864 /* Slave interface PCI address match found. */ 1865 snprintf(tmp_str, sizeof(tmp_str), 1866 "/sys/class/net/%s/phys_port_name", ifname); 1867 file = fopen(tmp_str, "rb"); 1868 if (!file) 1869 break; 1870 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1871 if (fscanf(file, "%32s", tmp_str) == 1) 1872 mlx5_translate_port_name(tmp_str, &info); 1873 fclose(file); 1874 /* Only process PF ports. */ 1875 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1876 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1877 continue; 1878 /* Check max bonding member. */ 1879 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1880 DRV_LOG(WARNING, "bonding index out of range, " 1881 "please increase MLX5_BOND_MAX_PORTS: %s", 1882 tmp_str); 1883 break; 1884 } 1885 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 1886 if (pci_dev->domain == pci_addr.domain && 1887 pci_dev->bus == pci_addr.bus && 1888 pci_dev->devid == pci_addr.devid && 1889 ((pci_dev->function == 0 && 1890 pci_dev->function + owner == pci_addr.function) || 1891 (pci_dev->function == owner && 1892 pci_addr.function == owner))) 1893 pf = info.port_name; 1894 /* Get ifindex. */ 1895 snprintf(tmp_str, sizeof(tmp_str), 1896 "/sys/class/net/%s/ifindex", ifname); 1897 file = fopen(tmp_str, "rb"); 1898 if (!file) 1899 break; 1900 ret = fscanf(file, "%u", &ifindex); 1901 fclose(file); 1902 if (ret != 1) 1903 break; 1904 /* Save bonding info. */ 1905 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1906 sizeof(bond_info->ports[0].ifname)); 1907 bond_info->ports[info.port_name].pci_addr = pci_addr; 1908 bond_info->ports[info.port_name].ifindex = ifindex; 1909 bond_info->n_port++; 1910 } 1911 if (pf >= 0) { 1912 /* Get bond interface info */ 1913 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1914 bond_info->ifname); 1915 if (ret) 1916 DRV_LOG(ERR, "unable to get bond info: %s", 1917 strerror(rte_errno)); 1918 else 1919 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1920 ifindex, bond_info->ifindex, bond_info->ifname); 1921 } 1922 return pf; 1923 } 1924 1925 /** 1926 * Register a PCI device within bonding. 1927 * 1928 * This function spawns Ethernet devices out of a given PCI device and 1929 * bonding owner PF index. 1930 * 1931 * @param[in] pci_dev 1932 * PCI device information. 1933 * @param[in] req_eth_da 1934 * Requested ethdev device argument. 1935 * @param[in] owner_id 1936 * Requested owner PF port ID within bonding device, default to 0. 1937 * 1938 * @return 1939 * 0 on success, a negative errno value otherwise and rte_errno is set. 1940 */ 1941 static int 1942 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 1943 struct rte_eth_devargs *req_eth_da, 1944 uint16_t owner_id) 1945 { 1946 struct ibv_device **ibv_list; 1947 /* 1948 * Number of found IB Devices matching with requested PCI BDF. 1949 * nd != 1 means there are multiple IB devices over the same 1950 * PCI device and we have representors and master. 1951 */ 1952 unsigned int nd = 0; 1953 /* 1954 * Number of found IB device Ports. nd = 1 and np = 1..n means 1955 * we have the single multiport IB device, and there may be 1956 * representors attached to some of found ports. 1957 */ 1958 unsigned int np = 0; 1959 /* 1960 * Number of DPDK ethernet devices to Spawn - either over 1961 * multiple IB devices or multiple ports of single IB device. 1962 * Actually this is the number of iterations to spawn. 1963 */ 1964 unsigned int ns = 0; 1965 /* 1966 * Bonding device 1967 * < 0 - no bonding device (single one) 1968 * >= 0 - bonding device (value is slave PF index) 1969 */ 1970 int bd = -1; 1971 struct mlx5_dev_spawn_data *list = NULL; 1972 struct mlx5_dev_config dev_config; 1973 unsigned int dev_config_vf; 1974 struct rte_eth_devargs eth_da = *req_eth_da; 1975 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1976 struct mlx5_bond_info bond_info; 1977 int ret = -1; 1978 1979 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1980 mlx5_pmd_socket_init(); 1981 ret = mlx5_init_once(); 1982 if (ret) { 1983 DRV_LOG(ERR, "unable to init PMD global data: %s", 1984 strerror(rte_errno)); 1985 return -rte_errno; 1986 } 1987 errno = 0; 1988 ibv_list = mlx5_glue->get_device_list(&ret); 1989 if (!ibv_list) { 1990 rte_errno = errno ? errno : ENOSYS; 1991 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1992 return -rte_errno; 1993 } 1994 /* 1995 * First scan the list of all Infiniband devices to find 1996 * matching ones, gathering into the list. 1997 */ 1998 struct ibv_device *ibv_match[ret + 1]; 1999 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2000 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2001 unsigned int i; 2002 2003 while (ret-- > 0) { 2004 struct rte_pci_addr pci_addr; 2005 2006 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2007 bd = mlx5_device_bond_pci_match 2008 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2009 &bond_info); 2010 if (bd >= 0) { 2011 /* 2012 * Bonding device detected. Only one match is allowed, 2013 * the bonding is supported over multi-port IB device, 2014 * there should be no matches on representor PCI 2015 * functions or non VF LAG bonding devices with 2016 * specified address. 2017 */ 2018 if (nd) { 2019 DRV_LOG(ERR, 2020 "multiple PCI match on bonding device" 2021 "\"%s\" found", ibv_list[ret]->name); 2022 rte_errno = ENOENT; 2023 ret = -rte_errno; 2024 goto exit; 2025 } 2026 /* Amend owner pci address if owner PF ID specified. */ 2027 if (eth_da.nb_representor_ports) 2028 owner_pci.function += owner_id; 2029 DRV_LOG(INFO, "PCI information matches for" 2030 " slave %d bonding device \"%s\"", 2031 bd, ibv_list[ret]->name); 2032 ibv_match[nd++] = ibv_list[ret]; 2033 break; 2034 } else { 2035 /* Bonding device not found. */ 2036 if (mlx5_dev_to_pci_addr 2037 (ibv_list[ret]->ibdev_path, &pci_addr)) 2038 continue; 2039 if (owner_pci.domain != pci_addr.domain || 2040 owner_pci.bus != pci_addr.bus || 2041 owner_pci.devid != pci_addr.devid || 2042 owner_pci.function != pci_addr.function) 2043 continue; 2044 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2045 ibv_list[ret]->name); 2046 ibv_match[nd++] = ibv_list[ret]; 2047 } 2048 } 2049 ibv_match[nd] = NULL; 2050 if (!nd) { 2051 /* No device matches, just complain and bail out. */ 2052 DRV_LOG(WARNING, 2053 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2054 " are kernel drivers loaded?", 2055 owner_pci.domain, owner_pci.bus, 2056 owner_pci.devid, owner_pci.function); 2057 rte_errno = ENOENT; 2058 ret = -rte_errno; 2059 goto exit; 2060 } 2061 if (nd == 1) { 2062 /* 2063 * Found single matching device may have multiple ports. 2064 * Each port may be representor, we have to check the port 2065 * number and check the representors existence. 2066 */ 2067 if (nl_rdma >= 0) 2068 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2069 if (!np) 2070 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2071 " ports number", ibv_match[0]->name); 2072 if (bd >= 0 && !np) { 2073 DRV_LOG(ERR, "can not get ports" 2074 " for bonding device"); 2075 rte_errno = ENOENT; 2076 ret = -rte_errno; 2077 goto exit; 2078 } 2079 } 2080 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 2081 if (bd >= 0) { 2082 /* 2083 * This may happen if there is VF LAG kernel support and 2084 * application is compiled with older rdma_core library. 2085 */ 2086 DRV_LOG(ERR, 2087 "No kernel/verbs support for VF LAG bonding found."); 2088 rte_errno = ENOTSUP; 2089 ret = -rte_errno; 2090 goto exit; 2091 } 2092 #endif 2093 /* 2094 * Now we can determine the maximal 2095 * amount of devices to be spawned. 2096 */ 2097 list = mlx5_malloc(MLX5_MEM_ZERO, 2098 sizeof(struct mlx5_dev_spawn_data) * 2099 (np ? np : nd), 2100 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2101 if (!list) { 2102 DRV_LOG(ERR, "spawn data array allocation failure"); 2103 rte_errno = ENOMEM; 2104 ret = -rte_errno; 2105 goto exit; 2106 } 2107 if (bd >= 0 || np > 1) { 2108 /* 2109 * Single IB device with multiple ports found, 2110 * it may be E-Switch master device and representors. 2111 * We have to perform identification through the ports. 2112 */ 2113 MLX5_ASSERT(nl_rdma >= 0); 2114 MLX5_ASSERT(ns == 0); 2115 MLX5_ASSERT(nd == 1); 2116 MLX5_ASSERT(np); 2117 for (i = 1; i <= np; ++i) { 2118 list[ns].bond_info = &bond_info; 2119 list[ns].max_port = np; 2120 list[ns].phys_port = i; 2121 list[ns].phys_dev = ibv_match[0]; 2122 list[ns].eth_dev = NULL; 2123 list[ns].pci_dev = pci_dev; 2124 list[ns].pf_bond = bd; 2125 list[ns].ifindex = mlx5_nl_ifindex 2126 (nl_rdma, 2127 mlx5_os_get_dev_device_name 2128 (list[ns].phys_dev), i); 2129 if (!list[ns].ifindex) { 2130 /* 2131 * No network interface index found for the 2132 * specified port, it means there is no 2133 * representor on this port. It's OK, 2134 * there can be disabled ports, for example 2135 * if sriov_numvfs < sriov_totalvfs. 2136 */ 2137 continue; 2138 } 2139 ret = -1; 2140 if (nl_route >= 0) 2141 ret = mlx5_nl_switch_info 2142 (nl_route, 2143 list[ns].ifindex, 2144 &list[ns].info); 2145 if (ret || (!list[ns].info.representor && 2146 !list[ns].info.master)) { 2147 /* 2148 * We failed to recognize representors with 2149 * Netlink, let's try to perform the task 2150 * with sysfs. 2151 */ 2152 ret = mlx5_sysfs_switch_info 2153 (list[ns].ifindex, 2154 &list[ns].info); 2155 } 2156 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2157 if (!ret && bd >= 0) { 2158 switch (list[ns].info.name_type) { 2159 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2160 if (list[ns].info.port_name == bd) 2161 ns++; 2162 break; 2163 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2164 /* Fallthrough */ 2165 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2166 /* Fallthrough */ 2167 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2168 if (list[ns].info.pf_num == bd) 2169 ns++; 2170 break; 2171 default: 2172 break; 2173 } 2174 continue; 2175 } 2176 #endif 2177 if (!ret && (list[ns].info.representor ^ 2178 list[ns].info.master)) 2179 ns++; 2180 } 2181 if (!ns) { 2182 DRV_LOG(ERR, 2183 "unable to recognize master/representors" 2184 " on the IB device with multiple ports"); 2185 rte_errno = ENOENT; 2186 ret = -rte_errno; 2187 goto exit; 2188 } 2189 } else { 2190 /* 2191 * The existence of several matching entries (nd > 1) means 2192 * port representors have been instantiated. No existing Verbs 2193 * call nor sysfs entries can tell them apart, this can only 2194 * be done through Netlink calls assuming kernel drivers are 2195 * recent enough to support them. 2196 * 2197 * In the event of identification failure through Netlink, 2198 * try again through sysfs, then: 2199 * 2200 * 1. A single IB device matches (nd == 1) with single 2201 * port (np=0/1) and is not a representor, assume 2202 * no switch support. 2203 * 2204 * 2. Otherwise no safe assumptions can be made; 2205 * complain louder and bail out. 2206 */ 2207 for (i = 0; i != nd; ++i) { 2208 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2209 list[ns].bond_info = NULL; 2210 list[ns].max_port = 1; 2211 list[ns].phys_port = 1; 2212 list[ns].phys_dev = ibv_match[i]; 2213 list[ns].eth_dev = NULL; 2214 list[ns].pci_dev = pci_dev; 2215 list[ns].pf_bond = -1; 2216 list[ns].ifindex = 0; 2217 if (nl_rdma >= 0) 2218 list[ns].ifindex = mlx5_nl_ifindex 2219 (nl_rdma, 2220 mlx5_os_get_dev_device_name 2221 (list[ns].phys_dev), 1); 2222 if (!list[ns].ifindex) { 2223 char ifname[IF_NAMESIZE]; 2224 2225 /* 2226 * Netlink failed, it may happen with old 2227 * ib_core kernel driver (before 4.16). 2228 * We can assume there is old driver because 2229 * here we are processing single ports IB 2230 * devices. Let's try sysfs to retrieve 2231 * the ifindex. The method works for 2232 * master device only. 2233 */ 2234 if (nd > 1) { 2235 /* 2236 * Multiple devices found, assume 2237 * representors, can not distinguish 2238 * master/representor and retrieve 2239 * ifindex via sysfs. 2240 */ 2241 continue; 2242 } 2243 ret = mlx5_get_ifname_sysfs 2244 (ibv_match[i]->ibdev_path, ifname); 2245 if (!ret) 2246 list[ns].ifindex = 2247 if_nametoindex(ifname); 2248 if (!list[ns].ifindex) { 2249 /* 2250 * No network interface index found 2251 * for the specified device, it means 2252 * there it is neither representor 2253 * nor master. 2254 */ 2255 continue; 2256 } 2257 } 2258 ret = -1; 2259 if (nl_route >= 0) 2260 ret = mlx5_nl_switch_info 2261 (nl_route, 2262 list[ns].ifindex, 2263 &list[ns].info); 2264 if (ret || (!list[ns].info.representor && 2265 !list[ns].info.master)) { 2266 /* 2267 * We failed to recognize representors with 2268 * Netlink, let's try to perform the task 2269 * with sysfs. 2270 */ 2271 ret = mlx5_sysfs_switch_info 2272 (list[ns].ifindex, 2273 &list[ns].info); 2274 } 2275 if (!ret && (list[ns].info.representor ^ 2276 list[ns].info.master)) { 2277 ns++; 2278 } else if ((nd == 1) && 2279 !list[ns].info.representor && 2280 !list[ns].info.master) { 2281 /* 2282 * Single IB device with 2283 * one physical port and 2284 * attached network device. 2285 * May be SRIOV is not enabled 2286 * or there is no representors. 2287 */ 2288 DRV_LOG(INFO, "no E-Switch support detected"); 2289 ns++; 2290 break; 2291 } 2292 } 2293 if (!ns) { 2294 DRV_LOG(ERR, 2295 "unable to recognize master/representors" 2296 " on the multiple IB devices"); 2297 rte_errno = ENOENT; 2298 ret = -rte_errno; 2299 goto exit; 2300 } 2301 } 2302 MLX5_ASSERT(ns); 2303 /* 2304 * Sort list to probe devices in natural order for users convenience 2305 * (i.e. master first, then representors from lowest to highest ID). 2306 */ 2307 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2308 /* Device specific configuration. */ 2309 switch (pci_dev->id.device_id) { 2310 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2311 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2312 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2313 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2314 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2315 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2316 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2317 dev_config_vf = 1; 2318 break; 2319 default: 2320 dev_config_vf = 0; 2321 break; 2322 } 2323 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2324 /* Set devargs default values. */ 2325 if (eth_da.nb_mh_controllers == 0) { 2326 eth_da.nb_mh_controllers = 1; 2327 eth_da.mh_controllers[0] = 0; 2328 } 2329 if (eth_da.nb_ports == 0 && ns > 0) { 2330 if (list[0].pf_bond >= 0 && list[0].info.representor) 2331 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2332 pci_dev->device.devargs->args); 2333 eth_da.nb_ports = 1; 2334 eth_da.ports[0] = list[0].info.pf_num; 2335 } 2336 if (eth_da.nb_representor_ports == 0) { 2337 eth_da.nb_representor_ports = 1; 2338 eth_da.representor_ports[0] = 0; 2339 } 2340 } 2341 for (i = 0; i != ns; ++i) { 2342 uint32_t restore; 2343 2344 /* Default configuration. */ 2345 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2346 dev_config.vf = dev_config_vf; 2347 dev_config.mps = MLX5_ARG_UNSET; 2348 dev_config.dbnc = MLX5_ARG_UNSET; 2349 dev_config.rx_vec_en = 1; 2350 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2351 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2352 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2353 dev_config.txqs_inline = MLX5_ARG_UNSET; 2354 dev_config.vf_nl_en = 1; 2355 dev_config.mr_ext_memseg_en = 1; 2356 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2357 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2358 dev_config.dv_esw_en = 1; 2359 dev_config.dv_flow_en = 1; 2360 dev_config.decap_en = 1; 2361 dev_config.log_hp_size = MLX5_ARG_UNSET; 2362 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2363 &list[i], 2364 &dev_config, 2365 ð_da); 2366 if (!list[i].eth_dev) { 2367 if (rte_errno != EBUSY && rte_errno != EEXIST) 2368 break; 2369 /* Device is disabled or already spawned. Ignore it. */ 2370 continue; 2371 } 2372 restore = list[i].eth_dev->data->dev_flags; 2373 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2374 /* Restore non-PCI flags cleared by the above call. */ 2375 list[i].eth_dev->data->dev_flags |= restore; 2376 rte_eth_dev_probing_finish(list[i].eth_dev); 2377 } 2378 if (i != ns) { 2379 DRV_LOG(ERR, 2380 "probe of PCI device " PCI_PRI_FMT " aborted after" 2381 " encountering an error: %s", 2382 owner_pci.domain, owner_pci.bus, 2383 owner_pci.devid, owner_pci.function, 2384 strerror(rte_errno)); 2385 ret = -rte_errno; 2386 /* Roll back. */ 2387 while (i--) { 2388 if (!list[i].eth_dev) 2389 continue; 2390 mlx5_dev_close(list[i].eth_dev); 2391 /* mac_addrs must not be freed because in dev_private */ 2392 list[i].eth_dev->data->mac_addrs = NULL; 2393 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2394 } 2395 /* Restore original error. */ 2396 rte_errno = -ret; 2397 } else { 2398 ret = 0; 2399 } 2400 exit: 2401 /* 2402 * Do the routine cleanup: 2403 * - close opened Netlink sockets 2404 * - free allocated spawn data array 2405 * - free the Infiniband device list 2406 */ 2407 if (nl_rdma >= 0) 2408 close(nl_rdma); 2409 if (nl_route >= 0) 2410 close(nl_route); 2411 if (list) 2412 mlx5_free(list); 2413 MLX5_ASSERT(ibv_list); 2414 mlx5_glue->free_device_list(ibv_list); 2415 return ret; 2416 } 2417 2418 /** 2419 * DPDK callback to register a PCI device. 2420 * 2421 * This function spawns Ethernet devices out of a given PCI device. 2422 * 2423 * @param[in] pci_drv 2424 * PCI driver structure (mlx5_driver). 2425 * @param[in] pci_dev 2426 * PCI device information. 2427 * 2428 * @return 2429 * 0 on success, a negative errno value otherwise and rte_errno is set. 2430 */ 2431 int 2432 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2433 struct rte_pci_device *pci_dev) 2434 { 2435 struct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE }; 2436 int ret = 0; 2437 uint16_t p; 2438 2439 if (pci_dev->device.devargs) { 2440 /* Parse representor information from device argument. */ 2441 if (pci_dev->device.devargs->cls_str) 2442 ret = rte_eth_devargs_parse 2443 (pci_dev->device.devargs->cls_str, ð_da); 2444 if (ret) { 2445 DRV_LOG(ERR, "failed to parse device arguments: %s", 2446 pci_dev->device.devargs->cls_str); 2447 return -rte_errno; 2448 } 2449 if (eth_da.type == RTE_ETH_REPRESENTOR_NONE) { 2450 /* Support legacy device argument */ 2451 ret = rte_eth_devargs_parse 2452 (pci_dev->device.devargs->args, ð_da); 2453 if (ret) { 2454 DRV_LOG(ERR, "failed to parse device arguments: %s", 2455 pci_dev->device.devargs->args); 2456 return -rte_errno; 2457 } 2458 } 2459 } 2460 2461 if (eth_da.nb_ports > 0) { 2462 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2463 for (p = 0; p < eth_da.nb_ports; p++) 2464 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2465 eth_da.ports[p]); 2466 } else { 2467 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2468 } 2469 return ret; 2470 } 2471 2472 static int 2473 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2474 { 2475 char *env; 2476 int value; 2477 2478 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2479 /* Get environment variable to store. */ 2480 env = getenv(MLX5_SHUT_UP_BF); 2481 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2482 if (config->dbnc == MLX5_ARG_UNSET) 2483 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2484 else 2485 setenv(MLX5_SHUT_UP_BF, 2486 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2487 return value; 2488 } 2489 2490 static void 2491 mlx5_restore_doorbell_mapping_env(int value) 2492 { 2493 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2494 /* Restore the original environment variable state. */ 2495 if (value == MLX5_ARG_UNSET) 2496 unsetenv(MLX5_SHUT_UP_BF); 2497 else 2498 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2499 } 2500 2501 /** 2502 * Extract pdn of PD object using DV API. 2503 * 2504 * @param[in] pd 2505 * Pointer to the verbs PD object. 2506 * @param[out] pdn 2507 * Pointer to the PD object number variable. 2508 * 2509 * @return 2510 * 0 on success, error value otherwise. 2511 */ 2512 int 2513 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2514 { 2515 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2516 struct mlx5dv_obj obj; 2517 struct mlx5dv_pd pd_info; 2518 int ret = 0; 2519 2520 obj.pd.in = pd; 2521 obj.pd.out = &pd_info; 2522 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2523 if (ret) { 2524 DRV_LOG(DEBUG, "Fail to get PD object info"); 2525 return ret; 2526 } 2527 *pdn = pd_info.pdn; 2528 return 0; 2529 #else 2530 (void)pd; 2531 (void)pdn; 2532 return -ENOTSUP; 2533 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2534 } 2535 2536 /** 2537 * Function API to open IB device. 2538 * 2539 * This function calls the Linux glue APIs to open a device. 2540 * 2541 * @param[in] spawn 2542 * Pointer to the IB device attributes (name, port, etc). 2543 * @param[out] config 2544 * Pointer to device configuration structure. 2545 * @param[out] sh 2546 * Pointer to shared context structure. 2547 * 2548 * @return 2549 * 0 on success, a positive error value otherwise. 2550 */ 2551 int 2552 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2553 const struct mlx5_dev_config *config, 2554 struct mlx5_dev_ctx_shared *sh) 2555 { 2556 int dbmap_env; 2557 int err = 0; 2558 2559 sh->numa_node = spawn->pci_dev->device.numa_node; 2560 pthread_mutex_init(&sh->txpp.mutex, NULL); 2561 /* 2562 * Configure environment variable "MLX5_BF_SHUT_UP" 2563 * before the device creation. The rdma_core library 2564 * checks the variable at device creation and 2565 * stores the result internally. 2566 */ 2567 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2568 /* Try to open IB device with DV first, then usual Verbs. */ 2569 errno = 0; 2570 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2571 if (sh->ctx) { 2572 sh->devx = 1; 2573 DRV_LOG(DEBUG, "DevX is supported"); 2574 /* The device is created, no need for environment. */ 2575 mlx5_restore_doorbell_mapping_env(dbmap_env); 2576 } else { 2577 /* The environment variable is still configured. */ 2578 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2579 err = errno ? errno : ENODEV; 2580 /* 2581 * The environment variable is not needed anymore, 2582 * all device creation attempts are completed. 2583 */ 2584 mlx5_restore_doorbell_mapping_env(dbmap_env); 2585 if (!sh->ctx) 2586 return err; 2587 DRV_LOG(DEBUG, "DevX is NOT supported"); 2588 err = 0; 2589 } 2590 if (!err && sh->ctx) { 2591 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2592 mlx5_glue->dv_set_context_attr(sh->ctx, 2593 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2594 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2595 .alloc = &mlx5_alloc_verbs_buf, 2596 .free = &mlx5_free_verbs_buf, 2597 .data = sh, 2598 })); 2599 } 2600 return err; 2601 } 2602 2603 /** 2604 * Install shared asynchronous device events handler. 2605 * This function is implemented to support event sharing 2606 * between multiple ports of single IB device. 2607 * 2608 * @param sh 2609 * Pointer to mlx5_dev_ctx_shared object. 2610 */ 2611 void 2612 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2613 { 2614 int ret; 2615 int flags; 2616 2617 sh->intr_handle.fd = -1; 2618 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2619 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2620 F_SETFL, flags | O_NONBLOCK); 2621 if (ret) { 2622 DRV_LOG(INFO, "failed to change file descriptor async event" 2623 " queue"); 2624 } else { 2625 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2626 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2627 if (rte_intr_callback_register(&sh->intr_handle, 2628 mlx5_dev_interrupt_handler, sh)) { 2629 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2630 sh->intr_handle.fd = -1; 2631 } 2632 } 2633 if (sh->devx) { 2634 #ifdef HAVE_IBV_DEVX_ASYNC 2635 sh->intr_handle_devx.fd = -1; 2636 sh->devx_comp = 2637 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2638 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2639 if (!devx_comp) { 2640 DRV_LOG(INFO, "failed to allocate devx_comp."); 2641 return; 2642 } 2643 flags = fcntl(devx_comp->fd, F_GETFL); 2644 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2645 if (ret) { 2646 DRV_LOG(INFO, "failed to change file descriptor" 2647 " devx comp"); 2648 return; 2649 } 2650 sh->intr_handle_devx.fd = devx_comp->fd; 2651 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2652 if (rte_intr_callback_register(&sh->intr_handle_devx, 2653 mlx5_dev_interrupt_handler_devx, sh)) { 2654 DRV_LOG(INFO, "Fail to install the devx shared" 2655 " interrupt."); 2656 sh->intr_handle_devx.fd = -1; 2657 } 2658 #endif /* HAVE_IBV_DEVX_ASYNC */ 2659 } 2660 } 2661 2662 /** 2663 * Uninstall shared asynchronous device events handler. 2664 * This function is implemented to support event sharing 2665 * between multiple ports of single IB device. 2666 * 2667 * @param dev 2668 * Pointer to mlx5_dev_ctx_shared object. 2669 */ 2670 void 2671 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2672 { 2673 if (sh->intr_handle.fd >= 0) 2674 mlx5_intr_callback_unregister(&sh->intr_handle, 2675 mlx5_dev_interrupt_handler, sh); 2676 #ifdef HAVE_IBV_DEVX_ASYNC 2677 if (sh->intr_handle_devx.fd >= 0) 2678 rte_intr_callback_unregister(&sh->intr_handle_devx, 2679 mlx5_dev_interrupt_handler_devx, sh); 2680 if (sh->devx_comp) 2681 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2682 #endif 2683 } 2684 2685 /** 2686 * Read statistics by a named counter. 2687 * 2688 * @param[in] priv 2689 * Pointer to the private device data structure. 2690 * @param[in] ctr_name 2691 * Pointer to the name of the statistic counter to read 2692 * @param[out] stat 2693 * Pointer to read statistic value. 2694 * @return 2695 * 0 on success and stat is valud, 1 if failed to read the value 2696 * rte_errno is set. 2697 * 2698 */ 2699 int 2700 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2701 uint64_t *stat) 2702 { 2703 int fd; 2704 2705 if (priv->sh) { 2706 if (priv->q_counters != NULL && 2707 strcmp(ctr_name, "out_of_buffer") == 0) 2708 return mlx5_devx_cmd_queue_counter_query 2709 (priv->q_counters, 0, (uint32_t *)stat); 2710 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2711 priv->sh->ibdev_path, 2712 priv->dev_port, 2713 ctr_name); 2714 fd = open(path, O_RDONLY); 2715 /* 2716 * in switchdev the file location is not per port 2717 * but rather in <ibdev_path>/hw_counters/<file_name>. 2718 */ 2719 if (fd == -1) { 2720 MKSTR(path1, "%s/hw_counters/%s", 2721 priv->sh->ibdev_path, 2722 ctr_name); 2723 fd = open(path1, O_RDONLY); 2724 } 2725 if (fd != -1) { 2726 char buf[21] = {'\0'}; 2727 ssize_t n = read(fd, buf, sizeof(buf)); 2728 2729 close(fd); 2730 if (n != -1) { 2731 *stat = strtoull(buf, NULL, 10); 2732 return 0; 2733 } 2734 } 2735 } 2736 *stat = 0; 2737 return 1; 2738 } 2739 2740 /** 2741 * Set the reg_mr and dereg_mr call backs 2742 * 2743 * @param reg_mr_cb[out] 2744 * Pointer to reg_mr func 2745 * @param dereg_mr_cb[out] 2746 * Pointer to dereg_mr func 2747 * 2748 */ 2749 void 2750 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2751 mlx5_dereg_mr_t *dereg_mr_cb) 2752 { 2753 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2754 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2755 } 2756 2757 /** 2758 * Remove a MAC address from device 2759 * 2760 * @param dev 2761 * Pointer to Ethernet device structure. 2762 * @param index 2763 * MAC address index. 2764 */ 2765 void 2766 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2767 { 2768 struct mlx5_priv *priv = dev->data->dev_private; 2769 const int vf = priv->config.vf; 2770 2771 if (vf) 2772 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2773 mlx5_ifindex(dev), priv->mac_own, 2774 &dev->data->mac_addrs[index], index); 2775 } 2776 2777 /** 2778 * Adds a MAC address to the device 2779 * 2780 * @param dev 2781 * Pointer to Ethernet device structure. 2782 * @param mac_addr 2783 * MAC address to register. 2784 * @param index 2785 * MAC address index. 2786 * 2787 * @return 2788 * 0 on success, a negative errno value otherwise 2789 */ 2790 int 2791 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2792 uint32_t index) 2793 { 2794 struct mlx5_priv *priv = dev->data->dev_private; 2795 const int vf = priv->config.vf; 2796 int ret = 0; 2797 2798 if (vf) 2799 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2800 mlx5_ifindex(dev), priv->mac_own, 2801 mac, index); 2802 return ret; 2803 } 2804 2805 /** 2806 * Modify a VF MAC address 2807 * 2808 * @param priv 2809 * Pointer to device private data. 2810 * @param mac_addr 2811 * MAC address to modify into. 2812 * @param iface_idx 2813 * Net device interface index 2814 * @param vf_index 2815 * VF index 2816 * 2817 * @return 2818 * 0 on success, a negative errno value otherwise 2819 */ 2820 int 2821 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2822 unsigned int iface_idx, 2823 struct rte_ether_addr *mac_addr, 2824 int vf_index) 2825 { 2826 return mlx5_nl_vf_mac_addr_modify 2827 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2828 } 2829 2830 /** 2831 * Set device promiscuous mode 2832 * 2833 * @param dev 2834 * Pointer to Ethernet device structure. 2835 * @param enable 2836 * 0 - promiscuous is disabled, otherwise - enabled 2837 * 2838 * @return 2839 * 0 on success, a negative error value otherwise 2840 */ 2841 int 2842 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2843 { 2844 struct mlx5_priv *priv = dev->data->dev_private; 2845 2846 return mlx5_nl_promisc(priv->nl_socket_route, 2847 mlx5_ifindex(dev), !!enable); 2848 } 2849 2850 /** 2851 * Set device promiscuous mode 2852 * 2853 * @param dev 2854 * Pointer to Ethernet device structure. 2855 * @param enable 2856 * 0 - all multicase is disabled, otherwise - enabled 2857 * 2858 * @return 2859 * 0 on success, a negative error value otherwise 2860 */ 2861 int 2862 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2863 { 2864 struct mlx5_priv *priv = dev->data->dev_private; 2865 2866 return mlx5_nl_allmulti(priv->nl_socket_route, 2867 mlx5_ifindex(dev), !!enable); 2868 } 2869 2870 /** 2871 * Flush device MAC addresses 2872 * 2873 * @param dev 2874 * Pointer to Ethernet device structure. 2875 * 2876 */ 2877 void 2878 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2879 { 2880 struct mlx5_priv *priv = dev->data->dev_private; 2881 2882 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2883 dev->data->mac_addrs, 2884 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2885 } 2886