1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_rx.h" 44 #include "mlx5_tx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_mr.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 54 55 #ifndef HAVE_IBV_MLX5_MOD_MPW 56 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 57 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 58 #endif 59 60 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 61 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 62 #endif 63 64 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 65 66 /* Spinlock for mlx5_shared_data allocation. */ 67 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 68 69 /* Process local data for secondary processes. */ 70 static struct mlx5_local_data mlx5_local_data; 71 72 /** 73 * Set the completion channel file descriptor interrupt as non-blocking. 74 * 75 * @param[in] rxq_obj 76 * Pointer to RQ channel object, which includes the channel fd 77 * 78 * @param[out] fd 79 * The file descriptor (representing the intetrrupt) used in this channel. 80 * 81 * @return 82 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 83 */ 84 int 85 mlx5_os_set_nonblock_channel_fd(int fd) 86 { 87 int flags; 88 89 flags = fcntl(fd, F_GETFL); 90 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 91 } 92 93 /** 94 * Get mlx5 device attributes. The glue function query_device_ex() is called 95 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 96 * device attributes from the glue out parameter. 97 * 98 * @param dev 99 * Pointer to ibv context. 100 * 101 * @param device_attr 102 * Pointer to mlx5 device attributes. 103 * 104 * @return 105 * 0 on success, non zero error number otherwise 106 */ 107 int 108 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 109 { 110 int err; 111 struct ibv_device_attr_ex attr_ex; 112 memset(device_attr, 0, sizeof(*device_attr)); 113 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 114 if (err) 115 return err; 116 117 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 118 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 119 device_attr->max_sge = attr_ex.orig_attr.max_sge; 120 device_attr->max_cq = attr_ex.orig_attr.max_cq; 121 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 122 device_attr->max_mr = attr_ex.orig_attr.max_mr; 123 device_attr->max_pd = attr_ex.orig_attr.max_pd; 124 device_attr->max_qp = attr_ex.orig_attr.max_qp; 125 device_attr->max_srq = attr_ex.orig_attr.max_srq; 126 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 127 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 128 device_attr->max_rwq_indirection_table_size = 129 attr_ex.rss_caps.max_rwq_indirection_table_size; 130 device_attr->max_tso = attr_ex.tso_caps.max_tso; 131 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 132 133 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 134 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 135 if (err) 136 return err; 137 138 device_attr->flags = dv_attr.flags; 139 device_attr->comp_mask = dv_attr.comp_mask; 140 #ifdef HAVE_IBV_MLX5_MOD_SWP 141 device_attr->sw_parsing_offloads = 142 dv_attr.sw_parsing_caps.sw_parsing_offloads; 143 #endif 144 device_attr->min_single_stride_log_num_of_bytes = 145 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 146 device_attr->max_single_stride_log_num_of_bytes = 147 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 148 device_attr->min_single_wqe_log_num_of_strides = 149 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 150 device_attr->max_single_wqe_log_num_of_strides = 151 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 152 device_attr->stride_supported_qpts = 153 dv_attr.striding_rq_caps.supported_qpts; 154 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 155 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 156 #endif 157 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver, 158 sizeof(device_attr->fw_ver)); 159 160 return err; 161 } 162 163 /** 164 * Verbs callback to allocate a memory. This function should allocate the space 165 * according to the size provided residing inside a huge page. 166 * Please note that all allocation must respect the alignment from libmlx5 167 * (i.e. currently rte_mem_page_size()). 168 * 169 * @param[in] size 170 * The size in bytes of the memory to allocate. 171 * @param[in] data 172 * A pointer to the callback data. 173 * 174 * @return 175 * Allocated buffer, NULL otherwise and rte_errno is set. 176 */ 177 static void * 178 mlx5_alloc_verbs_buf(size_t size, void *data) 179 { 180 struct mlx5_dev_ctx_shared *sh = data; 181 void *ret; 182 size_t alignment = rte_mem_page_size(); 183 if (alignment == (size_t)-1) { 184 DRV_LOG(ERR, "Failed to get mem page size"); 185 rte_errno = ENOMEM; 186 return NULL; 187 } 188 189 MLX5_ASSERT(data != NULL); 190 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 191 if (!ret && size) 192 rte_errno = ENOMEM; 193 return ret; 194 } 195 196 /** 197 * Verbs callback to free a memory. 198 * 199 * @param[in] ptr 200 * A pointer to the memory to free. 201 * @param[in] data 202 * A pointer to the callback data. 203 */ 204 static void 205 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 206 { 207 MLX5_ASSERT(data != NULL); 208 mlx5_free(ptr); 209 } 210 211 /** 212 * Initialize DR related data within private structure. 213 * Routine checks the reference counter and does actual 214 * resources creation/initialization only if counter is zero. 215 * 216 * @param[in] priv 217 * Pointer to the private device data structure. 218 * 219 * @return 220 * Zero on success, positive error code otherwise. 221 */ 222 static int 223 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 224 { 225 struct mlx5_dev_ctx_shared *sh = priv->sh; 226 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 227 int err; 228 229 MLX5_ASSERT(sh && sh->refcnt); 230 if (sh->refcnt > 1) 231 return 0; 232 err = mlx5_alloc_table_hash_list(priv); 233 if (err) 234 goto error; 235 /* The resources below are only valid with DV support. */ 236 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 237 /* Init port id action cache list. */ 238 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 239 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 240 flow_dv_port_id_create_cb, 241 flow_dv_port_id_match_cb, 242 flow_dv_port_id_remove_cb); 243 /* Init push vlan action cache list. */ 244 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 245 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 246 flow_dv_push_vlan_create_cb, 247 flow_dv_push_vlan_match_cb, 248 flow_dv_push_vlan_remove_cb); 249 /* Init sample action cache list. */ 250 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 251 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 252 flow_dv_sample_create_cb, 253 flow_dv_sample_match_cb, 254 flow_dv_sample_remove_cb); 255 /* Init dest array action cache list. */ 256 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 257 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 258 flow_dv_dest_array_create_cb, 259 flow_dv_dest_array_match_cb, 260 flow_dv_dest_array_remove_cb); 261 /* Create tags hash list table. */ 262 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 263 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 264 MLX5_HLIST_WRITE_MOST, 265 flow_dv_tag_create_cb, 266 flow_dv_tag_match_cb, 267 flow_dv_tag_remove_cb); 268 if (!sh->tag_table) { 269 DRV_LOG(ERR, "tags with hash creation failed."); 270 err = ENOMEM; 271 goto error; 272 } 273 sh->tag_table->ctx = sh; 274 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 275 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 276 0, MLX5_HLIST_WRITE_MOST | 277 MLX5_HLIST_DIRECT_KEY, 278 flow_dv_modify_create_cb, 279 flow_dv_modify_match_cb, 280 flow_dv_modify_remove_cb); 281 if (!sh->modify_cmds) { 282 DRV_LOG(ERR, "hdr modify hash creation failed"); 283 err = ENOMEM; 284 goto error; 285 } 286 sh->modify_cmds->ctx = sh; 287 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 288 sh->encaps_decaps = mlx5_hlist_create(s, 289 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 290 0, MLX5_HLIST_DIRECT_KEY | 291 MLX5_HLIST_WRITE_MOST, 292 flow_dv_encap_decap_create_cb, 293 flow_dv_encap_decap_match_cb, 294 flow_dv_encap_decap_remove_cb); 295 if (!sh->encaps_decaps) { 296 DRV_LOG(ERR, "encap decap hash creation failed"); 297 err = ENOMEM; 298 goto error; 299 } 300 sh->encaps_decaps->ctx = sh; 301 #endif 302 #ifdef HAVE_MLX5DV_DR 303 void *domain; 304 305 /* Reference counter is zero, we should initialize structures. */ 306 domain = mlx5_glue->dr_create_domain(sh->ctx, 307 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 308 if (!domain) { 309 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 310 err = errno; 311 goto error; 312 } 313 sh->rx_domain = domain; 314 domain = mlx5_glue->dr_create_domain(sh->ctx, 315 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 316 if (!domain) { 317 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 318 err = errno; 319 goto error; 320 } 321 sh->tx_domain = domain; 322 #ifdef HAVE_MLX5DV_DR_ESWITCH 323 if (priv->config.dv_esw_en) { 324 domain = mlx5_glue->dr_create_domain 325 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 326 if (!domain) { 327 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 328 err = errno; 329 goto error; 330 } 331 sh->fdb_domain = domain; 332 } 333 /* 334 * The drop action is just some dummy placeholder in rdma-core. It 335 * does not belong to domains and has no any attributes, and, can be 336 * shared by the entire device. 337 */ 338 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 339 if (!sh->dr_drop_action) { 340 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 341 err = errno; 342 goto error; 343 } 344 #endif 345 if (!sh->tunnel_hub) 346 err = mlx5_alloc_tunnel_hub(sh); 347 if (err) { 348 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 349 goto error; 350 } 351 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 352 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 353 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 354 if (sh->fdb_domain) 355 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 356 } 357 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 358 if (!priv->config.allow_duplicate_pattern) { 359 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE 360 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?"); 361 #endif 362 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); 363 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); 364 if (sh->fdb_domain) 365 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); 366 } 367 #endif /* HAVE_MLX5DV_DR */ 368 sh->default_miss_action = 369 mlx5_glue->dr_create_flow_action_default_miss(); 370 if (!sh->default_miss_action) 371 DRV_LOG(WARNING, "Default miss action is not supported."); 372 return 0; 373 error: 374 /* Rollback the created objects. */ 375 if (sh->rx_domain) { 376 mlx5_glue->dr_destroy_domain(sh->rx_domain); 377 sh->rx_domain = NULL; 378 } 379 if (sh->tx_domain) { 380 mlx5_glue->dr_destroy_domain(sh->tx_domain); 381 sh->tx_domain = NULL; 382 } 383 if (sh->fdb_domain) { 384 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 385 sh->fdb_domain = NULL; 386 } 387 if (sh->dr_drop_action) { 388 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 389 sh->dr_drop_action = NULL; 390 } 391 if (sh->pop_vlan_action) { 392 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 393 sh->pop_vlan_action = NULL; 394 } 395 if (sh->encaps_decaps) { 396 mlx5_hlist_destroy(sh->encaps_decaps); 397 sh->encaps_decaps = NULL; 398 } 399 if (sh->modify_cmds) { 400 mlx5_hlist_destroy(sh->modify_cmds); 401 sh->modify_cmds = NULL; 402 } 403 if (sh->tag_table) { 404 /* tags should be destroyed with flow before. */ 405 mlx5_hlist_destroy(sh->tag_table); 406 sh->tag_table = NULL; 407 } 408 if (sh->tunnel_hub) { 409 mlx5_release_tunnel_hub(sh, priv->dev_port); 410 sh->tunnel_hub = NULL; 411 } 412 mlx5_free_table_hash_list(priv); 413 return err; 414 } 415 416 /** 417 * Destroy DR related data within private structure. 418 * 419 * @param[in] priv 420 * Pointer to the private device data structure. 421 */ 422 void 423 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 424 { 425 struct mlx5_dev_ctx_shared *sh = priv->sh; 426 427 MLX5_ASSERT(sh && sh->refcnt); 428 if (sh->refcnt > 1) 429 return; 430 #ifdef HAVE_MLX5DV_DR 431 if (sh->rx_domain) { 432 mlx5_glue->dr_destroy_domain(sh->rx_domain); 433 sh->rx_domain = NULL; 434 } 435 if (sh->tx_domain) { 436 mlx5_glue->dr_destroy_domain(sh->tx_domain); 437 sh->tx_domain = NULL; 438 } 439 #ifdef HAVE_MLX5DV_DR_ESWITCH 440 if (sh->fdb_domain) { 441 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 442 sh->fdb_domain = NULL; 443 } 444 if (sh->dr_drop_action) { 445 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 446 sh->dr_drop_action = NULL; 447 } 448 #endif 449 if (sh->pop_vlan_action) { 450 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 451 sh->pop_vlan_action = NULL; 452 } 453 #endif /* HAVE_MLX5DV_DR */ 454 if (sh->default_miss_action) 455 mlx5_glue->destroy_flow_action 456 (sh->default_miss_action); 457 if (sh->encaps_decaps) { 458 mlx5_hlist_destroy(sh->encaps_decaps); 459 sh->encaps_decaps = NULL; 460 } 461 if (sh->modify_cmds) { 462 mlx5_hlist_destroy(sh->modify_cmds); 463 sh->modify_cmds = NULL; 464 } 465 if (sh->tag_table) { 466 /* tags should be destroyed with flow before. */ 467 mlx5_hlist_destroy(sh->tag_table); 468 sh->tag_table = NULL; 469 } 470 if (sh->tunnel_hub) { 471 mlx5_release_tunnel_hub(sh, priv->dev_port); 472 sh->tunnel_hub = NULL; 473 } 474 mlx5_cache_list_destroy(&sh->port_id_action_list); 475 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 476 mlx5_free_table_hash_list(priv); 477 } 478 479 /** 480 * Initialize shared data between primary and secondary process. 481 * 482 * A memzone is reserved by primary process and secondary processes attach to 483 * the memzone. 484 * 485 * @return 486 * 0 on success, a negative errno value otherwise and rte_errno is set. 487 */ 488 static int 489 mlx5_init_shared_data(void) 490 { 491 const struct rte_memzone *mz; 492 int ret = 0; 493 494 rte_spinlock_lock(&mlx5_shared_data_lock); 495 if (mlx5_shared_data == NULL) { 496 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 497 /* Allocate shared memory. */ 498 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 499 sizeof(*mlx5_shared_data), 500 SOCKET_ID_ANY, 0); 501 if (mz == NULL) { 502 DRV_LOG(ERR, 503 "Cannot allocate mlx5 shared data"); 504 ret = -rte_errno; 505 goto error; 506 } 507 mlx5_shared_data = mz->addr; 508 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 509 rte_spinlock_init(&mlx5_shared_data->lock); 510 } else { 511 /* Lookup allocated shared memory. */ 512 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 513 if (mz == NULL) { 514 DRV_LOG(ERR, 515 "Cannot attach mlx5 shared data"); 516 ret = -rte_errno; 517 goto error; 518 } 519 mlx5_shared_data = mz->addr; 520 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 521 } 522 } 523 error: 524 rte_spinlock_unlock(&mlx5_shared_data_lock); 525 return ret; 526 } 527 528 /** 529 * PMD global initialization. 530 * 531 * Independent from individual device, this function initializes global 532 * per-PMD data structures distinguishing primary and secondary processes. 533 * Hence, each initialization is called once per a process. 534 * 535 * @return 536 * 0 on success, a negative errno value otherwise and rte_errno is set. 537 */ 538 static int 539 mlx5_init_once(void) 540 { 541 struct mlx5_shared_data *sd; 542 struct mlx5_local_data *ld = &mlx5_local_data; 543 int ret = 0; 544 545 if (mlx5_init_shared_data()) 546 return -rte_errno; 547 sd = mlx5_shared_data; 548 MLX5_ASSERT(sd); 549 rte_spinlock_lock(&sd->lock); 550 switch (rte_eal_process_type()) { 551 case RTE_PROC_PRIMARY: 552 if (sd->init_done) 553 break; 554 LIST_INIT(&sd->mem_event_cb_list); 555 rte_rwlock_init(&sd->mem_event_rwlock); 556 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 557 mlx5_mr_mem_event_cb, NULL); 558 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 559 mlx5_mp_os_primary_handle); 560 if (ret) 561 goto out; 562 sd->init_done = true; 563 break; 564 case RTE_PROC_SECONDARY: 565 if (ld->init_done) 566 break; 567 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 568 mlx5_mp_os_secondary_handle); 569 if (ret) 570 goto out; 571 ++sd->secondary_cnt; 572 ld->init_done = true; 573 break; 574 default: 575 break; 576 } 577 out: 578 rte_spinlock_unlock(&sd->lock); 579 return ret; 580 } 581 582 /** 583 * Create the Tx queue DevX/Verbs object. 584 * 585 * @param dev 586 * Pointer to Ethernet device. 587 * @param idx 588 * Queue index in DPDK Tx queue array. 589 * 590 * @return 591 * 0 on success, a negative errno value otherwise and rte_errno is set. 592 */ 593 static int 594 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 595 { 596 struct mlx5_priv *priv = dev->data->dev_private; 597 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 598 struct mlx5_txq_ctrl *txq_ctrl = 599 container_of(txq_data, struct mlx5_txq_ctrl, txq); 600 601 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 602 return mlx5_txq_devx_obj_new(dev, idx); 603 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 604 if (!priv->config.dv_esw_en) 605 return mlx5_txq_devx_obj_new(dev, idx); 606 #endif 607 return mlx5_txq_ibv_obj_new(dev, idx); 608 } 609 610 /** 611 * Release an Tx DevX/verbs queue object. 612 * 613 * @param txq_obj 614 * DevX/Verbs Tx queue object. 615 */ 616 static void 617 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 618 { 619 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 620 mlx5_txq_devx_obj_release(txq_obj); 621 return; 622 } 623 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 624 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 625 mlx5_txq_devx_obj_release(txq_obj); 626 return; 627 } 628 #endif 629 mlx5_txq_ibv_obj_release(txq_obj); 630 } 631 632 /** 633 * DV flow counter mode detect and config. 634 * 635 * @param dev 636 * Pointer to rte_eth_dev structure. 637 * 638 */ 639 static void 640 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 641 { 642 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 643 struct mlx5_priv *priv = dev->data->dev_private; 644 struct mlx5_dev_ctx_shared *sh = priv->sh; 645 bool fallback; 646 647 #ifndef HAVE_IBV_DEVX_ASYNC 648 fallback = true; 649 #else 650 fallback = false; 651 if (!priv->config.devx || !priv->config.dv_flow_en || 652 !priv->config.hca_attr.flow_counters_dump || 653 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 654 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 655 fallback = true; 656 #endif 657 if (fallback) 658 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 659 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 660 priv->config.hca_attr.flow_counters_dump, 661 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 662 /* Initialize fallback mode only on the port initializes sh. */ 663 if (sh->refcnt == 1) 664 sh->cmng.counter_fallback = fallback; 665 else if (fallback != sh->cmng.counter_fallback) 666 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 667 "with others:%d.", PORT_ID(priv), fallback); 668 #endif 669 } 670 671 static void 672 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 673 { 674 struct mlx5_priv *priv = dev->data->dev_private; 675 void *ctx = priv->sh->ctx; 676 677 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 678 if (!priv->q_counters) { 679 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 680 struct ibv_wq *wq; 681 682 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 683 "by DevX - fall-back to use the kernel driver global " 684 "queue counter.", dev->data->port_id); 685 /* Create WQ by kernel and query its queue counter ID. */ 686 if (cq) { 687 wq = mlx5_glue->create_wq(ctx, 688 &(struct ibv_wq_init_attr){ 689 .wq_type = IBV_WQT_RQ, 690 .max_wr = 1, 691 .max_sge = 1, 692 .pd = priv->sh->pd, 693 .cq = cq, 694 }); 695 if (wq) { 696 /* Counter is assigned only on RDY state. */ 697 int ret = mlx5_glue->modify_wq(wq, 698 &(struct ibv_wq_attr){ 699 .attr_mask = IBV_WQ_ATTR_STATE, 700 .wq_state = IBV_WQS_RDY, 701 }); 702 703 if (ret == 0) 704 mlx5_devx_cmd_wq_query(wq, 705 &priv->counter_set_id); 706 claim_zero(mlx5_glue->destroy_wq(wq)); 707 } 708 claim_zero(mlx5_glue->destroy_cq(cq)); 709 } 710 } else { 711 priv->counter_set_id = priv->q_counters->id; 712 } 713 if (priv->counter_set_id == 0) 714 DRV_LOG(INFO, "Part of the port %d statistics will not be " 715 "available.", dev->data->port_id); 716 } 717 718 /** 719 * Check if representor spawn info match devargs. 720 * 721 * @param spawn 722 * Verbs device parameters (name, port, switch_info) to spawn. 723 * @param eth_da 724 * Device devargs to probe. 725 * 726 * @return 727 * Match result. 728 */ 729 static bool 730 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 731 struct rte_eth_devargs *eth_da) 732 { 733 struct mlx5_switch_info *switch_info = &spawn->info; 734 unsigned int p, f; 735 uint16_t id; 736 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 737 eth_da->type); 738 739 switch (eth_da->type) { 740 case RTE_ETH_REPRESENTOR_SF: 741 if (!(spawn->info.port_name == -1 && 742 switch_info->name_type == 743 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 744 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 745 rte_errno = EBUSY; 746 return false; 747 } 748 break; 749 case RTE_ETH_REPRESENTOR_VF: 750 /* Allows HPF representor index -1 as exception. */ 751 if (!(spawn->info.port_name == -1 && 752 switch_info->name_type == 753 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 754 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 755 rte_errno = EBUSY; 756 return false; 757 } 758 break; 759 case RTE_ETH_REPRESENTOR_NONE: 760 rte_errno = EBUSY; 761 return false; 762 default: 763 rte_errno = ENOTSUP; 764 DRV_LOG(ERR, "unsupported representor type"); 765 return false; 766 } 767 /* Check representor ID: */ 768 for (p = 0; p < eth_da->nb_ports; ++p) { 769 if (spawn->pf_bond < 0) { 770 /* For non-LAG mode, allow and ignore pf. */ 771 switch_info->pf_num = eth_da->ports[p]; 772 repr_id = mlx5_representor_id_encode(switch_info, 773 eth_da->type); 774 } 775 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 776 id = MLX5_REPRESENTOR_ID 777 (eth_da->ports[p], eth_da->type, 778 eth_da->representor_ports[f]); 779 if (repr_id == id) 780 return true; 781 } 782 } 783 rte_errno = EBUSY; 784 return false; 785 } 786 787 788 /** 789 * Spawn an Ethernet device from Verbs information. 790 * 791 * @param dpdk_dev 792 * Backing DPDK device. 793 * @param spawn 794 * Verbs device parameters (name, port, switch_info) to spawn. 795 * @param config 796 * Device configuration parameters. 797 * @param config 798 * Device arguments. 799 * 800 * @return 801 * A valid Ethernet device object on success, NULL otherwise and rte_errno 802 * is set. The following errors are defined: 803 * 804 * EBUSY: device is not supposed to be spawned. 805 * EEXIST: device is already spawned 806 */ 807 static struct rte_eth_dev * 808 mlx5_dev_spawn(struct rte_device *dpdk_dev, 809 struct mlx5_dev_spawn_data *spawn, 810 struct mlx5_dev_config *config, 811 struct rte_eth_devargs *eth_da) 812 { 813 const struct mlx5_switch_info *switch_info = &spawn->info; 814 struct mlx5_dev_ctx_shared *sh = NULL; 815 struct ibv_port_attr port_attr; 816 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 817 struct rte_eth_dev *eth_dev = NULL; 818 struct mlx5_priv *priv = NULL; 819 int err = 0; 820 unsigned int hw_padding = 0; 821 unsigned int mps; 822 unsigned int tunnel_en = 0; 823 unsigned int mpls_en = 0; 824 unsigned int swp = 0; 825 unsigned int mprq = 0; 826 unsigned int mprq_min_stride_size_n = 0; 827 unsigned int mprq_max_stride_size_n = 0; 828 unsigned int mprq_min_stride_num_n = 0; 829 unsigned int mprq_max_stride_num_n = 0; 830 struct rte_ether_addr mac; 831 char name[RTE_ETH_NAME_MAX_LEN]; 832 int own_domain_id = 0; 833 uint16_t port_id; 834 struct mlx5_port_info vport_info = { .query_flags = 0 }; 835 836 /* Determine if this port representor is supposed to be spawned. */ 837 if (switch_info->representor && dpdk_dev->devargs && 838 !mlx5_representor_match(spawn, eth_da)) 839 return NULL; 840 /* Build device name. */ 841 if (spawn->pf_bond < 0) { 842 /* Single device. */ 843 if (!switch_info->representor) 844 strlcpy(name, dpdk_dev->name, sizeof(name)); 845 else 846 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 847 dpdk_dev->name, 848 switch_info->name_type == 849 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 850 switch_info->port_name); 851 } else { 852 /* Bonding device. */ 853 if (!switch_info->representor) { 854 err = snprintf(name, sizeof(name), "%s_%s", 855 dpdk_dev->name, 856 mlx5_os_get_dev_device_name(spawn->phys_dev)); 857 } else { 858 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 859 dpdk_dev->name, 860 mlx5_os_get_dev_device_name(spawn->phys_dev), 861 switch_info->ctrl_num, 862 switch_info->pf_num, 863 switch_info->name_type == 864 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 865 switch_info->port_name); 866 } 867 } 868 if (err >= (int)sizeof(name)) 869 DRV_LOG(WARNING, "device name overflow %s", name); 870 /* check if the device is already spawned */ 871 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 872 rte_errno = EEXIST; 873 return NULL; 874 } 875 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 876 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 877 struct mlx5_mp_id mp_id; 878 879 eth_dev = rte_eth_dev_attach_secondary(name); 880 if (eth_dev == NULL) { 881 DRV_LOG(ERR, "can not attach rte ethdev"); 882 rte_errno = ENOMEM; 883 return NULL; 884 } 885 eth_dev->device = dpdk_dev; 886 eth_dev->dev_ops = &mlx5_dev_sec_ops; 887 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 888 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 889 err = mlx5_proc_priv_init(eth_dev); 890 if (err) 891 return NULL; 892 mp_id.port_id = eth_dev->data->port_id; 893 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 894 /* Receive command fd from primary process */ 895 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 896 if (err < 0) 897 goto err_secondary; 898 /* Remap UAR for Tx queues. */ 899 err = mlx5_tx_uar_init_secondary(eth_dev, err); 900 if (err) 901 goto err_secondary; 902 /* 903 * Ethdev pointer is still required as input since 904 * the primary device is not accessible from the 905 * secondary process. 906 */ 907 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 908 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 909 return eth_dev; 910 err_secondary: 911 mlx5_dev_close(eth_dev); 912 return NULL; 913 } 914 /* 915 * Some parameters ("tx_db_nc" in particularly) are needed in 916 * advance to create dv/verbs device context. We proceed the 917 * devargs here to get ones, and later proceed devargs again 918 * to override some hardware settings. 919 */ 920 err = mlx5_args(config, dpdk_dev->devargs); 921 if (err) { 922 err = rte_errno; 923 DRV_LOG(ERR, "failed to process device arguments: %s", 924 strerror(rte_errno)); 925 goto error; 926 } 927 if (config->dv_miss_info) { 928 if (switch_info->master || switch_info->representor) 929 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 930 } 931 mlx5_malloc_mem_select(config->sys_mem_en); 932 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 933 if (!sh) 934 return NULL; 935 config->devx = sh->devx; 936 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 937 config->dest_tir = 1; 938 #endif 939 #ifdef HAVE_IBV_MLX5_MOD_SWP 940 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 941 #endif 942 /* 943 * Multi-packet send is supported by ConnectX-4 Lx PF as well 944 * as all ConnectX-5 devices. 945 */ 946 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 947 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 948 #endif 949 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 950 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 951 #endif 952 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 953 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 954 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 955 DRV_LOG(DEBUG, "enhanced MPW is supported"); 956 mps = MLX5_MPW_ENHANCED; 957 } else { 958 DRV_LOG(DEBUG, "MPW is supported"); 959 mps = MLX5_MPW; 960 } 961 } else { 962 DRV_LOG(DEBUG, "MPW isn't supported"); 963 mps = MLX5_MPW_DISABLED; 964 } 965 #ifdef HAVE_IBV_MLX5_MOD_SWP 966 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 967 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 968 DRV_LOG(DEBUG, "SWP support: %u", swp); 969 #endif 970 config->swp = !!swp; 971 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 972 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 973 struct mlx5dv_striding_rq_caps mprq_caps = 974 dv_attr.striding_rq_caps; 975 976 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 977 mprq_caps.min_single_stride_log_num_of_bytes); 978 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 979 mprq_caps.max_single_stride_log_num_of_bytes); 980 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 981 mprq_caps.min_single_wqe_log_num_of_strides); 982 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 983 mprq_caps.max_single_wqe_log_num_of_strides); 984 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 985 mprq_caps.supported_qpts); 986 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 987 mprq = 1; 988 mprq_min_stride_size_n = 989 mprq_caps.min_single_stride_log_num_of_bytes; 990 mprq_max_stride_size_n = 991 mprq_caps.max_single_stride_log_num_of_bytes; 992 mprq_min_stride_num_n = 993 mprq_caps.min_single_wqe_log_num_of_strides; 994 mprq_max_stride_num_n = 995 mprq_caps.max_single_wqe_log_num_of_strides; 996 } 997 #endif 998 /* Rx CQE compression is enabled by default. */ 999 config->cqe_comp = 1; 1000 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1001 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1002 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1003 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1004 (dv_attr.tunnel_offloads_caps & 1005 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 1006 (dv_attr.tunnel_offloads_caps & 1007 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 1008 } 1009 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1010 tunnel_en ? "" : "not "); 1011 #else 1012 DRV_LOG(WARNING, 1013 "tunnel offloading disabled due to old OFED/rdma-core version"); 1014 #endif 1015 config->tunnel_en = tunnel_en; 1016 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1017 mpls_en = ((dv_attr.tunnel_offloads_caps & 1018 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1019 (dv_attr.tunnel_offloads_caps & 1020 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1021 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1022 mpls_en ? "" : "not "); 1023 #else 1024 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1025 " old OFED/rdma-core version or firmware configuration"); 1026 #endif 1027 config->mpls_en = mpls_en; 1028 /* Check port status. */ 1029 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1030 if (err) { 1031 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1032 goto error; 1033 } 1034 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1035 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1036 err = EINVAL; 1037 goto error; 1038 } 1039 if (port_attr.state != IBV_PORT_ACTIVE) 1040 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1041 mlx5_glue->port_state_str(port_attr.state), 1042 port_attr.state); 1043 /* Allocate private eth device data. */ 1044 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1045 sizeof(*priv), 1046 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1047 if (priv == NULL) { 1048 DRV_LOG(ERR, "priv allocation failure"); 1049 err = ENOMEM; 1050 goto error; 1051 } 1052 priv->sh = sh; 1053 priv->dev_port = spawn->phys_port; 1054 priv->pci_dev = spawn->pci_dev; 1055 priv->mtu = RTE_ETHER_MTU; 1056 /* Some internal functions rely on Netlink sockets, open them now. */ 1057 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1058 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1059 priv->representor = !!switch_info->representor; 1060 priv->master = !!switch_info->master; 1061 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1062 priv->vport_meta_tag = 0; 1063 priv->vport_meta_mask = 0; 1064 priv->pf_bond = spawn->pf_bond; 1065 /* 1066 * If we have E-Switch we should determine the vport attributes. 1067 * E-Switch may use either source vport field or reg_c[0] metadata 1068 * register to match on vport index. The engaged part of metadata 1069 * register is defined by mask. 1070 */ 1071 if (switch_info->representor || switch_info->master) { 1072 err = mlx5_glue->devx_port_query(sh->ctx, 1073 spawn->phys_port, 1074 &vport_info); 1075 if (err) { 1076 DRV_LOG(WARNING, 1077 "can't query devx port %d on device %s", 1078 spawn->phys_port, 1079 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1080 vport_info.query_flags = 0; 1081 } 1082 } 1083 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) { 1084 priv->vport_meta_tag = vport_info.vport_meta_tag; 1085 priv->vport_meta_mask = vport_info.vport_meta_mask; 1086 if (!priv->vport_meta_mask) { 1087 DRV_LOG(ERR, "vport zero mask for port %d" 1088 " on bonding device %s", 1089 spawn->phys_port, 1090 mlx5_os_get_dev_device_name 1091 (spawn->phys_dev)); 1092 err = ENOTSUP; 1093 goto error; 1094 } 1095 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1096 DRV_LOG(ERR, "invalid vport tag for port %d" 1097 " on bonding device %s", 1098 spawn->phys_port, 1099 mlx5_os_get_dev_device_name 1100 (spawn->phys_dev)); 1101 err = ENOTSUP; 1102 goto error; 1103 } 1104 } 1105 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { 1106 priv->vport_id = vport_info.vport_id; 1107 } else if (spawn->pf_bond >= 0 && 1108 (switch_info->representor || switch_info->master)) { 1109 DRV_LOG(ERR, "can't deduce vport index for port %d" 1110 " on bonding device %s", 1111 spawn->phys_port, 1112 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1113 err = ENOTSUP; 1114 goto error; 1115 } else { 1116 /* 1117 * Suppose vport index in compatible way. Kernel/rdma_core 1118 * support single E-Switch per PF configurations only and 1119 * vport_id field contains the vport index for associated VF, 1120 * which is deduced from representor port name. 1121 * For example, let's have the IB device port 10, it has 1122 * attached network device eth0, which has port name attribute 1123 * pf0vf2, we can deduce the VF number as 2, and set vport index 1124 * as 3 (2+1). This assigning schema should be changed if the 1125 * multiple E-Switch instances per PF configurations or/and PCI 1126 * subfunctions are added. 1127 */ 1128 priv->vport_id = switch_info->representor ? 1129 switch_info->port_name + 1 : -1; 1130 } 1131 priv->representor_id = mlx5_representor_id_encode(switch_info, 1132 eth_da->type); 1133 /* 1134 * Look for sibling devices in order to reuse their switch domain 1135 * if any, otherwise allocate one. 1136 */ 1137 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1138 const struct mlx5_priv *opriv = 1139 rte_eth_devices[port_id].data->dev_private; 1140 1141 if (!opriv || 1142 opriv->sh != priv->sh || 1143 opriv->domain_id == 1144 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1145 continue; 1146 priv->domain_id = opriv->domain_id; 1147 break; 1148 } 1149 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1150 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1151 if (err) { 1152 err = rte_errno; 1153 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1154 strerror(rte_errno)); 1155 goto error; 1156 } 1157 own_domain_id = 1; 1158 } 1159 /* Override some values set by hardware configuration. */ 1160 mlx5_args(config, dpdk_dev->devargs); 1161 err = mlx5_dev_check_sibling_config(priv, config); 1162 if (err) 1163 goto error; 1164 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1165 IBV_DEVICE_RAW_IP_CSUM); 1166 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1167 (config->hw_csum ? "" : "not ")); 1168 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1169 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1170 DRV_LOG(DEBUG, "counters are not supported"); 1171 #endif 1172 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1173 if (config->dv_flow_en) { 1174 DRV_LOG(WARNING, "DV flow is not supported"); 1175 config->dv_flow_en = 0; 1176 } 1177 #endif 1178 config->ind_table_max_size = 1179 sh->device_attr.max_rwq_indirection_table_size; 1180 /* 1181 * Remove this check once DPDK supports larger/variable 1182 * indirection tables. 1183 */ 1184 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1185 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1186 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1187 config->ind_table_max_size); 1188 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1189 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1190 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1191 (config->hw_vlan_strip ? "" : "not ")); 1192 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1193 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1194 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1195 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1196 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1197 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1198 IBV_DEVICE_PCI_WRITE_END_PADDING); 1199 #endif 1200 if (config->hw_padding && !hw_padding) { 1201 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1202 config->hw_padding = 0; 1203 } else if (config->hw_padding) { 1204 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1205 } 1206 config->tso = (sh->device_attr.max_tso > 0 && 1207 (sh->device_attr.tso_supported_qpts & 1208 (1 << IBV_QPT_RAW_PACKET))); 1209 if (config->tso) 1210 config->tso_max_payload_sz = sh->device_attr.max_tso; 1211 /* 1212 * MPW is disabled by default, while the Enhanced MPW is enabled 1213 * by default. 1214 */ 1215 if (config->mps == MLX5_ARG_UNSET) 1216 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1217 MLX5_MPW_DISABLED; 1218 else 1219 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1220 DRV_LOG(INFO, "%sMPS is %s", 1221 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1222 config->mps == MLX5_MPW ? "legacy " : "", 1223 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1224 if (config->devx) { 1225 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1226 if (err) { 1227 err = -err; 1228 goto error; 1229 } 1230 /* Check relax ordering support. */ 1231 if (!haswell_broadwell_cpu) { 1232 sh->cmng.relaxed_ordering_write = 1233 config->hca_attr.relaxed_ordering_write; 1234 sh->cmng.relaxed_ordering_read = 1235 config->hca_attr.relaxed_ordering_read; 1236 } else { 1237 sh->cmng.relaxed_ordering_read = 0; 1238 sh->cmng.relaxed_ordering_write = 0; 1239 } 1240 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1241 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1242 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1243 /* Check for LRO support. */ 1244 if (config->dest_tir && config->hca_attr.lro_cap && 1245 config->dv_flow_en) { 1246 /* TBD check tunnel lro caps. */ 1247 config->lro.supported = config->hca_attr.lro_cap; 1248 DRV_LOG(DEBUG, "Device supports LRO"); 1249 /* 1250 * If LRO timeout is not configured by application, 1251 * use the minimal supported value. 1252 */ 1253 if (!config->lro.timeout) 1254 config->lro.timeout = 1255 config->hca_attr.lro_timer_supported_periods[0]; 1256 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1257 config->lro.timeout); 1258 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1259 "required for coalescing is %d bytes", 1260 config->hca_attr.lro_min_mss_size); 1261 } 1262 #if defined(HAVE_MLX5DV_DR) && \ 1263 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1264 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1265 if (config->hca_attr.qos.sup && 1266 config->hca_attr.qos.flow_meter_old && 1267 config->dv_flow_en) { 1268 uint8_t reg_c_mask = 1269 config->hca_attr.qos.flow_meter_reg_c_ids; 1270 /* 1271 * Meter needs two REG_C's for color match and pre-sfx 1272 * flow match. Here get the REG_C for color match. 1273 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1274 */ 1275 reg_c_mask &= 0xfc; 1276 if (__builtin_popcount(reg_c_mask) < 1) { 1277 priv->mtr_en = 0; 1278 DRV_LOG(WARNING, "No available register for" 1279 " meter."); 1280 } else { 1281 /* 1282 * The meter color register is used by the 1283 * flow-hit feature as well. 1284 * The flow-hit feature must use REG_C_3 1285 * Prefer REG_C_3 if it is available. 1286 */ 1287 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1288 priv->mtr_color_reg = REG_C_3; 1289 else 1290 priv->mtr_color_reg = ffs(reg_c_mask) 1291 - 1 + REG_C_0; 1292 priv->mtr_en = 1; 1293 priv->mtr_reg_share = 1294 config->hca_attr.qos.flow_meter; 1295 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1296 priv->mtr_color_reg); 1297 } 1298 } 1299 if (config->hca_attr.qos.sup && 1300 config->hca_attr.qos.flow_meter_aso_sup) { 1301 uint32_t log_obj_size = 1302 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1303 if (log_obj_size >= 1304 config->hca_attr.qos.log_meter_aso_granularity && 1305 log_obj_size <= 1306 config->hca_attr.qos.log_meter_aso_max_alloc) 1307 sh->meter_aso_en = 1; 1308 } 1309 if (priv->mtr_en) { 1310 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1311 if (err) { 1312 err = -err; 1313 goto error; 1314 } 1315 } 1316 #endif 1317 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1318 if (config->hca_attr.flow_hit_aso && 1319 priv->mtr_color_reg == REG_C_3) { 1320 sh->flow_hit_aso_en = 1; 1321 err = mlx5_flow_aso_age_mng_init(sh); 1322 if (err) { 1323 err = -err; 1324 goto error; 1325 } 1326 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1327 } 1328 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1329 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1330 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1331 if (config->hca_attr.ct_offload && 1332 priv->mtr_color_reg == REG_C_3) { 1333 err = mlx5_flow_aso_ct_mng_init(sh); 1334 if (err) { 1335 err = -err; 1336 goto error; 1337 } 1338 DRV_LOG(DEBUG, "CT ASO is supported."); 1339 sh->ct_aso_en = 1; 1340 } 1341 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1342 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1343 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1344 config->dv_flow_en) { 1345 priv->sampler_en = 1; 1346 DRV_LOG(DEBUG, "Sampler enabled!"); 1347 } else { 1348 priv->sampler_en = 0; 1349 if (!config->hca_attr.log_max_ft_sampler_num) 1350 DRV_LOG(WARNING, 1351 "No available register for sampler."); 1352 else 1353 DRV_LOG(DEBUG, "DV flow is not supported!"); 1354 } 1355 #endif 1356 } 1357 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1358 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1359 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1360 config->cqe_comp = 0; 1361 } 1362 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1363 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1364 DRV_LOG(WARNING, "Flow Tag CQE compression" 1365 " format isn't supported."); 1366 config->cqe_comp = 0; 1367 } 1368 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1369 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1370 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1371 " format isn't supported."); 1372 config->cqe_comp = 0; 1373 } 1374 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1375 config->cqe_comp ? "" : "not "); 1376 if (config->tx_pp) { 1377 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1378 config->hca_attr.dev_freq_khz); 1379 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1380 config->hca_attr.qos.packet_pacing ? "" : "not "); 1381 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1382 config->hca_attr.cross_channel ? "" : "not "); 1383 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1384 config->hca_attr.wqe_index_ignore ? "" : "not "); 1385 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1386 config->hca_attr.non_wire_sq ? "" : "not "); 1387 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1388 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1389 config->hca_attr.log_max_static_sq_wq); 1390 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1391 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1392 if (!config->devx) { 1393 DRV_LOG(ERR, "DevX is required for packet pacing"); 1394 err = ENODEV; 1395 goto error; 1396 } 1397 if (!config->hca_attr.qos.packet_pacing) { 1398 DRV_LOG(ERR, "Packet pacing is not supported"); 1399 err = ENODEV; 1400 goto error; 1401 } 1402 if (!config->hca_attr.cross_channel) { 1403 DRV_LOG(ERR, "Cross channel operations are" 1404 " required for packet pacing"); 1405 err = ENODEV; 1406 goto error; 1407 } 1408 if (!config->hca_attr.wqe_index_ignore) { 1409 DRV_LOG(ERR, "WQE index ignore feature is" 1410 " required for packet pacing"); 1411 err = ENODEV; 1412 goto error; 1413 } 1414 if (!config->hca_attr.non_wire_sq) { 1415 DRV_LOG(ERR, "Non-wire SQ feature is" 1416 " required for packet pacing"); 1417 err = ENODEV; 1418 goto error; 1419 } 1420 if (!config->hca_attr.log_max_static_sq_wq) { 1421 DRV_LOG(ERR, "Static WQE SQ feature is" 1422 " required for packet pacing"); 1423 err = ENODEV; 1424 goto error; 1425 } 1426 if (!config->hca_attr.qos.wqe_rate_pp) { 1427 DRV_LOG(ERR, "WQE rate mode is required" 1428 " for packet pacing"); 1429 err = ENODEV; 1430 goto error; 1431 } 1432 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1433 DRV_LOG(ERR, "DevX does not provide UAR offset," 1434 " can't create queues for packet pacing"); 1435 err = ENODEV; 1436 goto error; 1437 #endif 1438 } 1439 if (config->devx) { 1440 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1441 1442 err = config->hca_attr.access_register_user ? 1443 mlx5_devx_cmd_register_read 1444 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1445 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1446 if (!err) { 1447 uint32_t ts_mode; 1448 1449 /* MTUTC register is read successfully. */ 1450 ts_mode = MLX5_GET(register_mtutc, reg, 1451 time_stamp_mode); 1452 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1453 config->rt_timestamp = 1; 1454 } else { 1455 /* Kernel does not support register reading. */ 1456 if (config->hca_attr.dev_freq_khz == 1457 (NS_PER_S / MS_PER_S)) 1458 config->rt_timestamp = 1; 1459 } 1460 } 1461 /* 1462 * If HW has bug working with tunnel packet decapsulation and 1463 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1464 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1465 */ 1466 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1467 config->hw_fcs_strip = 0; 1468 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1469 (config->hw_fcs_strip ? "" : "not ")); 1470 if (config->mprq.enabled && mprq) { 1471 if (config->mprq.stride_num_n && 1472 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1473 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1474 config->mprq.stride_num_n = 1475 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1476 mprq_min_stride_num_n), 1477 mprq_max_stride_num_n); 1478 DRV_LOG(WARNING, 1479 "the number of strides" 1480 " for Multi-Packet RQ is out of range," 1481 " setting default value (%u)", 1482 1 << config->mprq.stride_num_n); 1483 } 1484 if (config->mprq.stride_size_n && 1485 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1486 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1487 config->mprq.stride_size_n = 1488 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1489 mprq_min_stride_size_n), 1490 mprq_max_stride_size_n); 1491 DRV_LOG(WARNING, 1492 "the size of a stride" 1493 " for Multi-Packet RQ is out of range," 1494 " setting default value (%u)", 1495 1 << config->mprq.stride_size_n); 1496 } 1497 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1498 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1499 } else if (config->mprq.enabled && !mprq) { 1500 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1501 config->mprq.enabled = 0; 1502 } 1503 if (config->max_dump_files_num == 0) 1504 config->max_dump_files_num = 128; 1505 eth_dev = rte_eth_dev_allocate(name); 1506 if (eth_dev == NULL) { 1507 DRV_LOG(ERR, "can not allocate rte ethdev"); 1508 err = ENOMEM; 1509 goto error; 1510 } 1511 if (priv->representor) { 1512 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1513 eth_dev->data->representor_id = priv->representor_id; 1514 } 1515 priv->mp_id.port_id = eth_dev->data->port_id; 1516 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1517 /* 1518 * Store associated network device interface index. This index 1519 * is permanent throughout the lifetime of device. So, we may store 1520 * the ifindex here and use the cached value further. 1521 */ 1522 MLX5_ASSERT(spawn->ifindex); 1523 priv->if_index = spawn->ifindex; 1524 eth_dev->data->dev_private = priv; 1525 priv->dev_data = eth_dev->data; 1526 eth_dev->data->mac_addrs = priv->mac; 1527 eth_dev->device = dpdk_dev; 1528 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1529 /* Configure the first MAC address by default. */ 1530 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1531 DRV_LOG(ERR, 1532 "port %u cannot get MAC address, is mlx5_en" 1533 " loaded? (errno: %s)", 1534 eth_dev->data->port_id, strerror(rte_errno)); 1535 err = ENODEV; 1536 goto error; 1537 } 1538 DRV_LOG(INFO, 1539 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1540 eth_dev->data->port_id, 1541 mac.addr_bytes[0], mac.addr_bytes[1], 1542 mac.addr_bytes[2], mac.addr_bytes[3], 1543 mac.addr_bytes[4], mac.addr_bytes[5]); 1544 #ifdef RTE_LIBRTE_MLX5_DEBUG 1545 { 1546 char ifname[MLX5_NAMESIZE]; 1547 1548 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1549 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1550 eth_dev->data->port_id, ifname); 1551 else 1552 DRV_LOG(DEBUG, "port %u ifname is unknown", 1553 eth_dev->data->port_id); 1554 } 1555 #endif 1556 /* Get actual MTU if possible. */ 1557 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1558 if (err) { 1559 err = rte_errno; 1560 goto error; 1561 } 1562 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1563 priv->mtu); 1564 /* Initialize burst functions to prevent crashes before link-up. */ 1565 eth_dev->rx_pkt_burst = removed_rx_burst; 1566 eth_dev->tx_pkt_burst = removed_tx_burst; 1567 eth_dev->dev_ops = &mlx5_dev_ops; 1568 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1569 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1570 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1571 /* Register MAC address. */ 1572 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1573 if (config->vf && config->vf_nl_en) 1574 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1575 mlx5_ifindex(eth_dev), 1576 eth_dev->data->mac_addrs, 1577 MLX5_MAX_MAC_ADDRESSES); 1578 priv->flows = 0; 1579 priv->ctrl_flows = 0; 1580 rte_spinlock_init(&priv->flow_list_lock); 1581 TAILQ_INIT(&priv->flow_meters); 1582 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR); 1583 if (!priv->mtr_profile_tbl) 1584 goto error; 1585 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1586 mlx5_glue->dv_set_context_attr(sh->ctx, 1587 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1588 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1589 .alloc = &mlx5_alloc_verbs_buf, 1590 .free = &mlx5_free_verbs_buf, 1591 .data = sh, 1592 })); 1593 /* Bring Ethernet device up. */ 1594 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1595 eth_dev->data->port_id); 1596 mlx5_set_link_up(eth_dev); 1597 /* 1598 * Even though the interrupt handler is not installed yet, 1599 * interrupts will still trigger on the async_fd from 1600 * Verbs context returned by ibv_open_device(). 1601 */ 1602 mlx5_link_update(eth_dev, 0); 1603 #ifdef HAVE_MLX5DV_DR_ESWITCH 1604 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1605 (switch_info->representor || switch_info->master))) 1606 config->dv_esw_en = 0; 1607 #else 1608 config->dv_esw_en = 0; 1609 #endif 1610 /* Detect minimal data bytes to inline. */ 1611 mlx5_set_min_inline(spawn, config); 1612 /* Store device configuration on private structure. */ 1613 priv->config = *config; 1614 /* Create context for virtual machine VLAN workaround. */ 1615 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1616 if (config->dv_flow_en) { 1617 err = mlx5_alloc_shared_dr(priv); 1618 if (err) 1619 goto error; 1620 } 1621 if (config->devx && config->dv_flow_en && config->dest_tir) { 1622 priv->obj_ops = devx_obj_ops; 1623 priv->obj_ops.drop_action_create = 1624 ibv_obj_ops.drop_action_create; 1625 priv->obj_ops.drop_action_destroy = 1626 ibv_obj_ops.drop_action_destroy; 1627 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1628 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1629 #else 1630 if (config->dv_esw_en) 1631 priv->obj_ops.txq_obj_modify = 1632 ibv_obj_ops.txq_obj_modify; 1633 #endif 1634 /* Use specific wrappers for Tx object. */ 1635 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1636 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1637 mlx5_queue_counter_id_prepare(eth_dev); 1638 priv->obj_ops.lb_dummy_queue_create = 1639 mlx5_rxq_ibv_obj_dummy_lb_create; 1640 priv->obj_ops.lb_dummy_queue_release = 1641 mlx5_rxq_ibv_obj_dummy_lb_release; 1642 } else { 1643 priv->obj_ops = ibv_obj_ops; 1644 } 1645 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1646 if (!priv->drop_queue.hrxq) 1647 goto error; 1648 /* Supported Verbs flow priority number detection. */ 1649 err = mlx5_flow_discover_priorities(eth_dev); 1650 if (err < 0) { 1651 err = -err; 1652 goto error; 1653 } 1654 priv->config.flow_prio = err; 1655 if (!priv->config.dv_esw_en && 1656 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1657 DRV_LOG(WARNING, "metadata mode %u is not supported " 1658 "(no E-Switch)", priv->config.dv_xmeta_en); 1659 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1660 } 1661 mlx5_set_metadata_mask(eth_dev); 1662 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1663 !priv->sh->dv_regc0_mask) { 1664 DRV_LOG(ERR, "metadata mode %u is not supported " 1665 "(no metadata reg_c[0] is available)", 1666 priv->config.dv_xmeta_en); 1667 err = ENOTSUP; 1668 goto error; 1669 } 1670 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1671 mlx5_hrxq_create_cb, 1672 mlx5_hrxq_match_cb, 1673 mlx5_hrxq_remove_cb); 1674 /* Query availability of metadata reg_c's. */ 1675 err = mlx5_flow_discover_mreg_c(eth_dev); 1676 if (err < 0) { 1677 err = -err; 1678 goto error; 1679 } 1680 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1681 DRV_LOG(DEBUG, 1682 "port %u extensive metadata register is not supported", 1683 eth_dev->data->port_id); 1684 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1685 DRV_LOG(ERR, "metadata mode %u is not supported " 1686 "(no metadata registers available)", 1687 priv->config.dv_xmeta_en); 1688 err = ENOTSUP; 1689 goto error; 1690 } 1691 } 1692 if (priv->config.dv_flow_en && 1693 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1694 mlx5_flow_ext_mreg_supported(eth_dev) && 1695 priv->sh->dv_regc0_mask) { 1696 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1697 MLX5_FLOW_MREG_HTABLE_SZ, 1698 0, 0, 1699 flow_dv_mreg_create_cb, 1700 flow_dv_mreg_match_cb, 1701 flow_dv_mreg_remove_cb); 1702 if (!priv->mreg_cp_tbl) { 1703 err = ENOMEM; 1704 goto error; 1705 } 1706 priv->mreg_cp_tbl->ctx = eth_dev; 1707 } 1708 rte_spinlock_init(&priv->shared_act_sl); 1709 mlx5_flow_counter_mode_config(eth_dev); 1710 if (priv->config.dv_flow_en) 1711 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1712 return eth_dev; 1713 error: 1714 if (priv) { 1715 if (priv->mreg_cp_tbl) 1716 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1717 if (priv->sh) 1718 mlx5_os_free_shared_dr(priv); 1719 if (priv->nl_socket_route >= 0) 1720 close(priv->nl_socket_route); 1721 if (priv->nl_socket_rdma >= 0) 1722 close(priv->nl_socket_rdma); 1723 if (priv->vmwa_context) 1724 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1725 if (eth_dev && priv->drop_queue.hrxq) 1726 mlx5_drop_action_destroy(eth_dev); 1727 if (priv->mtr_profile_tbl) 1728 mlx5_l3t_destroy(priv->mtr_profile_tbl); 1729 if (own_domain_id) 1730 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1731 mlx5_cache_list_destroy(&priv->hrxqs); 1732 mlx5_free(priv); 1733 if (eth_dev != NULL) 1734 eth_dev->data->dev_private = NULL; 1735 } 1736 if (eth_dev != NULL) { 1737 /* mac_addrs must not be freed alone because part of 1738 * dev_private 1739 **/ 1740 eth_dev->data->mac_addrs = NULL; 1741 rte_eth_dev_release_port(eth_dev); 1742 } 1743 if (sh) 1744 mlx5_free_shared_dev_ctx(sh); 1745 MLX5_ASSERT(err > 0); 1746 rte_errno = err; 1747 return NULL; 1748 } 1749 1750 /** 1751 * Comparison callback to sort device data. 1752 * 1753 * This is meant to be used with qsort(). 1754 * 1755 * @param a[in] 1756 * Pointer to pointer to first data object. 1757 * @param b[in] 1758 * Pointer to pointer to second data object. 1759 * 1760 * @return 1761 * 0 if both objects are equal, less than 0 if the first argument is less 1762 * than the second, greater than 0 otherwise. 1763 */ 1764 static int 1765 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1766 { 1767 const struct mlx5_switch_info *si_a = 1768 &((const struct mlx5_dev_spawn_data *)a)->info; 1769 const struct mlx5_switch_info *si_b = 1770 &((const struct mlx5_dev_spawn_data *)b)->info; 1771 int ret; 1772 1773 /* Master device first. */ 1774 ret = si_b->master - si_a->master; 1775 if (ret) 1776 return ret; 1777 /* Then representor devices. */ 1778 ret = si_b->representor - si_a->representor; 1779 if (ret) 1780 return ret; 1781 /* Unidentified devices come last in no specific order. */ 1782 if (!si_a->representor) 1783 return 0; 1784 /* Order representors by name. */ 1785 return si_a->port_name - si_b->port_name; 1786 } 1787 1788 /** 1789 * Match PCI information for possible slaves of bonding device. 1790 * 1791 * @param[in] ibv_dev 1792 * Pointer to Infiniband device structure. 1793 * @param[in] pci_dev 1794 * Pointer to primary PCI address structure to match. 1795 * @param[in] nl_rdma 1796 * Netlink RDMA group socket handle. 1797 * @param[in] owner 1798 * Rerepsentor owner PF index. 1799 * @param[out] bond_info 1800 * Pointer to bonding information. 1801 * 1802 * @return 1803 * negative value if no bonding device found, otherwise 1804 * positive index of slave PF in bonding. 1805 */ 1806 static int 1807 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1808 const struct rte_pci_addr *pci_dev, 1809 int nl_rdma, uint16_t owner, 1810 struct mlx5_bond_info *bond_info) 1811 { 1812 char ifname[IF_NAMESIZE + 1]; 1813 unsigned int ifindex; 1814 unsigned int np, i; 1815 FILE *bond_file = NULL, *file; 1816 int pf = -1; 1817 int ret; 1818 1819 /* 1820 * Try to get master device name. If something goes 1821 * wrong suppose the lack of kernel support and no 1822 * bonding devices. 1823 */ 1824 memset(bond_info, 0, sizeof(*bond_info)); 1825 if (nl_rdma < 0) 1826 return -1; 1827 if (!strstr(ibv_dev->name, "bond")) 1828 return -1; 1829 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1830 if (!np) 1831 return -1; 1832 /* 1833 * The Master device might not be on the predefined 1834 * port (not on port index 1, it is not garanted), 1835 * we have to scan all Infiniband device port and 1836 * find master. 1837 */ 1838 for (i = 1; i <= np; ++i) { 1839 /* Check whether Infiniband port is populated. */ 1840 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1841 if (!ifindex) 1842 continue; 1843 if (!if_indextoname(ifindex, ifname)) 1844 continue; 1845 /* Try to read bonding slave names from sysfs. */ 1846 MKSTR(slaves, 1847 "/sys/class/net/%s/master/bonding/slaves", ifname); 1848 bond_file = fopen(slaves, "r"); 1849 if (bond_file) 1850 break; 1851 } 1852 if (!bond_file) 1853 return -1; 1854 /* Use safe format to check maximal buffer length. */ 1855 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1856 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1857 char tmp_str[IF_NAMESIZE + 32]; 1858 struct rte_pci_addr pci_addr; 1859 struct mlx5_switch_info info; 1860 1861 /* Process slave interface names in the loop. */ 1862 snprintf(tmp_str, sizeof(tmp_str), 1863 "/sys/class/net/%s", ifname); 1864 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1865 DRV_LOG(WARNING, "can not get PCI address" 1866 " for netdev \"%s\"", ifname); 1867 continue; 1868 } 1869 /* Slave interface PCI address match found. */ 1870 snprintf(tmp_str, sizeof(tmp_str), 1871 "/sys/class/net/%s/phys_port_name", ifname); 1872 file = fopen(tmp_str, "rb"); 1873 if (!file) 1874 break; 1875 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1876 if (fscanf(file, "%32s", tmp_str) == 1) 1877 mlx5_translate_port_name(tmp_str, &info); 1878 fclose(file); 1879 /* Only process PF ports. */ 1880 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1881 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1882 continue; 1883 /* Check max bonding member. */ 1884 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1885 DRV_LOG(WARNING, "bonding index out of range, " 1886 "please increase MLX5_BOND_MAX_PORTS: %s", 1887 tmp_str); 1888 break; 1889 } 1890 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ 1891 if (pci_dev->domain == pci_addr.domain && 1892 pci_dev->bus == pci_addr.bus && 1893 pci_dev->devid == pci_addr.devid && 1894 ((pci_dev->function == 0 && 1895 pci_dev->function + owner == pci_addr.function) || 1896 (pci_dev->function == owner && 1897 pci_addr.function == owner))) 1898 pf = info.port_name; 1899 /* Get ifindex. */ 1900 snprintf(tmp_str, sizeof(tmp_str), 1901 "/sys/class/net/%s/ifindex", ifname); 1902 file = fopen(tmp_str, "rb"); 1903 if (!file) 1904 break; 1905 ret = fscanf(file, "%u", &ifindex); 1906 fclose(file); 1907 if (ret != 1) 1908 break; 1909 /* Save bonding info. */ 1910 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1911 sizeof(bond_info->ports[0].ifname)); 1912 bond_info->ports[info.port_name].pci_addr = pci_addr; 1913 bond_info->ports[info.port_name].ifindex = ifindex; 1914 bond_info->n_port++; 1915 } 1916 if (pf >= 0) { 1917 /* Get bond interface info */ 1918 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1919 bond_info->ifname); 1920 if (ret) 1921 DRV_LOG(ERR, "unable to get bond info: %s", 1922 strerror(rte_errno)); 1923 else 1924 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1925 ifindex, bond_info->ifindex, bond_info->ifname); 1926 } 1927 return pf; 1928 } 1929 1930 /** 1931 * Register a PCI device within bonding. 1932 * 1933 * This function spawns Ethernet devices out of a given PCI device and 1934 * bonding owner PF index. 1935 * 1936 * @param[in] pci_dev 1937 * PCI device information. 1938 * @param[in] req_eth_da 1939 * Requested ethdev device argument. 1940 * @param[in] owner_id 1941 * Requested owner PF port ID within bonding device, default to 0. 1942 * 1943 * @return 1944 * 0 on success, a negative errno value otherwise and rte_errno is set. 1945 */ 1946 static int 1947 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 1948 struct rte_eth_devargs *req_eth_da, 1949 uint16_t owner_id) 1950 { 1951 struct ibv_device **ibv_list; 1952 /* 1953 * Number of found IB Devices matching with requested PCI BDF. 1954 * nd != 1 means there are multiple IB devices over the same 1955 * PCI device and we have representors and master. 1956 */ 1957 unsigned int nd = 0; 1958 /* 1959 * Number of found IB device Ports. nd = 1 and np = 1..n means 1960 * we have the single multiport IB device, and there may be 1961 * representors attached to some of found ports. 1962 */ 1963 unsigned int np = 0; 1964 /* 1965 * Number of DPDK ethernet devices to Spawn - either over 1966 * multiple IB devices or multiple ports of single IB device. 1967 * Actually this is the number of iterations to spawn. 1968 */ 1969 unsigned int ns = 0; 1970 /* 1971 * Bonding device 1972 * < 0 - no bonding device (single one) 1973 * >= 0 - bonding device (value is slave PF index) 1974 */ 1975 int bd = -1; 1976 struct mlx5_dev_spawn_data *list = NULL; 1977 struct mlx5_dev_config dev_config; 1978 unsigned int dev_config_vf; 1979 struct rte_eth_devargs eth_da = *req_eth_da; 1980 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1981 struct mlx5_bond_info bond_info; 1982 int ret = -1; 1983 1984 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1985 mlx5_pmd_socket_init(); 1986 ret = mlx5_init_once(); 1987 if (ret) { 1988 DRV_LOG(ERR, "unable to init PMD global data: %s", 1989 strerror(rte_errno)); 1990 return -rte_errno; 1991 } 1992 errno = 0; 1993 ibv_list = mlx5_glue->get_device_list(&ret); 1994 if (!ibv_list) { 1995 rte_errno = errno ? errno : ENOSYS; 1996 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1997 return -rte_errno; 1998 } 1999 /* 2000 * First scan the list of all Infiniband devices to find 2001 * matching ones, gathering into the list. 2002 */ 2003 struct ibv_device *ibv_match[ret + 1]; 2004 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 2005 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2006 unsigned int i; 2007 2008 while (ret-- > 0) { 2009 struct rte_pci_addr pci_addr; 2010 2011 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2012 bd = mlx5_device_bond_pci_match 2013 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2014 &bond_info); 2015 if (bd >= 0) { 2016 /* 2017 * Bonding device detected. Only one match is allowed, 2018 * the bonding is supported over multi-port IB device, 2019 * there should be no matches on representor PCI 2020 * functions or non VF LAG bonding devices with 2021 * specified address. 2022 */ 2023 if (nd) { 2024 DRV_LOG(ERR, 2025 "multiple PCI match on bonding device" 2026 "\"%s\" found", ibv_list[ret]->name); 2027 rte_errno = ENOENT; 2028 ret = -rte_errno; 2029 goto exit; 2030 } 2031 /* Amend owner pci address if owner PF ID specified. */ 2032 if (eth_da.nb_representor_ports) 2033 owner_pci.function += owner_id; 2034 DRV_LOG(INFO, "PCI information matches for" 2035 " slave %d bonding device \"%s\"", 2036 bd, ibv_list[ret]->name); 2037 ibv_match[nd++] = ibv_list[ret]; 2038 break; 2039 } else { 2040 /* Bonding device not found. */ 2041 if (mlx5_dev_to_pci_addr 2042 (ibv_list[ret]->ibdev_path, &pci_addr)) 2043 continue; 2044 if (owner_pci.domain != pci_addr.domain || 2045 owner_pci.bus != pci_addr.bus || 2046 owner_pci.devid != pci_addr.devid || 2047 owner_pci.function != pci_addr.function) 2048 continue; 2049 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2050 ibv_list[ret]->name); 2051 ibv_match[nd++] = ibv_list[ret]; 2052 } 2053 } 2054 ibv_match[nd] = NULL; 2055 if (!nd) { 2056 /* No device matches, just complain and bail out. */ 2057 DRV_LOG(WARNING, 2058 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2059 " are kernel drivers loaded?", 2060 owner_pci.domain, owner_pci.bus, 2061 owner_pci.devid, owner_pci.function); 2062 rte_errno = ENOENT; 2063 ret = -rte_errno; 2064 goto exit; 2065 } 2066 if (nd == 1) { 2067 /* 2068 * Found single matching device may have multiple ports. 2069 * Each port may be representor, we have to check the port 2070 * number and check the representors existence. 2071 */ 2072 if (nl_rdma >= 0) 2073 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2074 if (!np) 2075 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2076 " ports number", ibv_match[0]->name); 2077 if (bd >= 0 && !np) { 2078 DRV_LOG(ERR, "can not get ports" 2079 " for bonding device"); 2080 rte_errno = ENOENT; 2081 ret = -rte_errno; 2082 goto exit; 2083 } 2084 } 2085 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 2086 if (bd >= 0) { 2087 /* 2088 * This may happen if there is VF LAG kernel support and 2089 * application is compiled with older rdma_core library. 2090 */ 2091 DRV_LOG(ERR, 2092 "No kernel/verbs support for VF LAG bonding found."); 2093 rte_errno = ENOTSUP; 2094 ret = -rte_errno; 2095 goto exit; 2096 } 2097 #endif 2098 /* 2099 * Now we can determine the maximal 2100 * amount of devices to be spawned. 2101 */ 2102 list = mlx5_malloc(MLX5_MEM_ZERO, 2103 sizeof(struct mlx5_dev_spawn_data) * 2104 (np ? np : nd), 2105 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2106 if (!list) { 2107 DRV_LOG(ERR, "spawn data array allocation failure"); 2108 rte_errno = ENOMEM; 2109 ret = -rte_errno; 2110 goto exit; 2111 } 2112 if (bd >= 0 || np > 1) { 2113 /* 2114 * Single IB device with multiple ports found, 2115 * it may be E-Switch master device and representors. 2116 * We have to perform identification through the ports. 2117 */ 2118 MLX5_ASSERT(nl_rdma >= 0); 2119 MLX5_ASSERT(ns == 0); 2120 MLX5_ASSERT(nd == 1); 2121 MLX5_ASSERT(np); 2122 for (i = 1; i <= np; ++i) { 2123 list[ns].bond_info = &bond_info; 2124 list[ns].max_port = np; 2125 list[ns].phys_port = i; 2126 list[ns].phys_dev = ibv_match[0]; 2127 list[ns].eth_dev = NULL; 2128 list[ns].pci_dev = pci_dev; 2129 list[ns].pf_bond = bd; 2130 list[ns].ifindex = mlx5_nl_ifindex 2131 (nl_rdma, 2132 mlx5_os_get_dev_device_name 2133 (list[ns].phys_dev), i); 2134 if (!list[ns].ifindex) { 2135 /* 2136 * No network interface index found for the 2137 * specified port, it means there is no 2138 * representor on this port. It's OK, 2139 * there can be disabled ports, for example 2140 * if sriov_numvfs < sriov_totalvfs. 2141 */ 2142 continue; 2143 } 2144 ret = -1; 2145 if (nl_route >= 0) 2146 ret = mlx5_nl_switch_info 2147 (nl_route, 2148 list[ns].ifindex, 2149 &list[ns].info); 2150 if (ret || (!list[ns].info.representor && 2151 !list[ns].info.master)) { 2152 /* 2153 * We failed to recognize representors with 2154 * Netlink, let's try to perform the task 2155 * with sysfs. 2156 */ 2157 ret = mlx5_sysfs_switch_info 2158 (list[ns].ifindex, 2159 &list[ns].info); 2160 } 2161 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2162 if (!ret && bd >= 0) { 2163 switch (list[ns].info.name_type) { 2164 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2165 if (list[ns].info.port_name == bd) 2166 ns++; 2167 break; 2168 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2169 /* Fallthrough */ 2170 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2171 /* Fallthrough */ 2172 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2173 if (list[ns].info.pf_num == bd) 2174 ns++; 2175 break; 2176 default: 2177 break; 2178 } 2179 continue; 2180 } 2181 #endif 2182 if (!ret && (list[ns].info.representor ^ 2183 list[ns].info.master)) 2184 ns++; 2185 } 2186 if (!ns) { 2187 DRV_LOG(ERR, 2188 "unable to recognize master/representors" 2189 " on the IB device with multiple ports"); 2190 rte_errno = ENOENT; 2191 ret = -rte_errno; 2192 goto exit; 2193 } 2194 } else { 2195 /* 2196 * The existence of several matching entries (nd > 1) means 2197 * port representors have been instantiated. No existing Verbs 2198 * call nor sysfs entries can tell them apart, this can only 2199 * be done through Netlink calls assuming kernel drivers are 2200 * recent enough to support them. 2201 * 2202 * In the event of identification failure through Netlink, 2203 * try again through sysfs, then: 2204 * 2205 * 1. A single IB device matches (nd == 1) with single 2206 * port (np=0/1) and is not a representor, assume 2207 * no switch support. 2208 * 2209 * 2. Otherwise no safe assumptions can be made; 2210 * complain louder and bail out. 2211 */ 2212 for (i = 0; i != nd; ++i) { 2213 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2214 list[ns].bond_info = NULL; 2215 list[ns].max_port = 1; 2216 list[ns].phys_port = 1; 2217 list[ns].phys_dev = ibv_match[i]; 2218 list[ns].eth_dev = NULL; 2219 list[ns].pci_dev = pci_dev; 2220 list[ns].pf_bond = -1; 2221 list[ns].ifindex = 0; 2222 if (nl_rdma >= 0) 2223 list[ns].ifindex = mlx5_nl_ifindex 2224 (nl_rdma, 2225 mlx5_os_get_dev_device_name 2226 (list[ns].phys_dev), 1); 2227 if (!list[ns].ifindex) { 2228 char ifname[IF_NAMESIZE]; 2229 2230 /* 2231 * Netlink failed, it may happen with old 2232 * ib_core kernel driver (before 4.16). 2233 * We can assume there is old driver because 2234 * here we are processing single ports IB 2235 * devices. Let's try sysfs to retrieve 2236 * the ifindex. The method works for 2237 * master device only. 2238 */ 2239 if (nd > 1) { 2240 /* 2241 * Multiple devices found, assume 2242 * representors, can not distinguish 2243 * master/representor and retrieve 2244 * ifindex via sysfs. 2245 */ 2246 continue; 2247 } 2248 ret = mlx5_get_ifname_sysfs 2249 (ibv_match[i]->ibdev_path, ifname); 2250 if (!ret) 2251 list[ns].ifindex = 2252 if_nametoindex(ifname); 2253 if (!list[ns].ifindex) { 2254 /* 2255 * No network interface index found 2256 * for the specified device, it means 2257 * there it is neither representor 2258 * nor master. 2259 */ 2260 continue; 2261 } 2262 } 2263 ret = -1; 2264 if (nl_route >= 0) 2265 ret = mlx5_nl_switch_info 2266 (nl_route, 2267 list[ns].ifindex, 2268 &list[ns].info); 2269 if (ret || (!list[ns].info.representor && 2270 !list[ns].info.master)) { 2271 /* 2272 * We failed to recognize representors with 2273 * Netlink, let's try to perform the task 2274 * with sysfs. 2275 */ 2276 ret = mlx5_sysfs_switch_info 2277 (list[ns].ifindex, 2278 &list[ns].info); 2279 } 2280 if (!ret && (list[ns].info.representor ^ 2281 list[ns].info.master)) { 2282 ns++; 2283 } else if ((nd == 1) && 2284 !list[ns].info.representor && 2285 !list[ns].info.master) { 2286 /* 2287 * Single IB device with 2288 * one physical port and 2289 * attached network device. 2290 * May be SRIOV is not enabled 2291 * or there is no representors. 2292 */ 2293 DRV_LOG(INFO, "no E-Switch support detected"); 2294 ns++; 2295 break; 2296 } 2297 } 2298 if (!ns) { 2299 DRV_LOG(ERR, 2300 "unable to recognize master/representors" 2301 " on the multiple IB devices"); 2302 rte_errno = ENOENT; 2303 ret = -rte_errno; 2304 goto exit; 2305 } 2306 /* 2307 * New kernels may add the switch_id attribute for the case 2308 * there is no E-Switch and we wrongly recognized the 2309 * only device as master. Override this if there is the 2310 * single device with single port and new device name 2311 * format present. 2312 */ 2313 if (nd == 1 && 2314 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) { 2315 list[0].info.master = 0; 2316 list[0].info.representor = 0; 2317 } 2318 } 2319 MLX5_ASSERT(ns); 2320 /* 2321 * Sort list to probe devices in natural order for users convenience 2322 * (i.e. master first, then representors from lowest to highest ID). 2323 */ 2324 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2325 /* Device specific configuration. */ 2326 switch (pci_dev->id.device_id) { 2327 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2328 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2329 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2330 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2331 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2332 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2333 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2334 dev_config_vf = 1; 2335 break; 2336 default: 2337 dev_config_vf = 0; 2338 break; 2339 } 2340 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2341 /* Set devargs default values. */ 2342 if (eth_da.nb_mh_controllers == 0) { 2343 eth_da.nb_mh_controllers = 1; 2344 eth_da.mh_controllers[0] = 0; 2345 } 2346 if (eth_da.nb_ports == 0 && ns > 0) { 2347 if (list[0].pf_bond >= 0 && list[0].info.representor) 2348 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2349 pci_dev->device.devargs->args); 2350 eth_da.nb_ports = 1; 2351 eth_da.ports[0] = list[0].info.pf_num; 2352 } 2353 if (eth_da.nb_representor_ports == 0) { 2354 eth_da.nb_representor_ports = 1; 2355 eth_da.representor_ports[0] = 0; 2356 } 2357 } 2358 for (i = 0; i != ns; ++i) { 2359 uint32_t restore; 2360 2361 /* Default configuration. */ 2362 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2363 dev_config.vf = dev_config_vf; 2364 dev_config.mps = MLX5_ARG_UNSET; 2365 dev_config.dbnc = MLX5_ARG_UNSET; 2366 dev_config.rx_vec_en = 1; 2367 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2368 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2369 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2370 dev_config.txqs_inline = MLX5_ARG_UNSET; 2371 dev_config.vf_nl_en = 1; 2372 dev_config.mr_ext_memseg_en = 1; 2373 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2374 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2375 dev_config.dv_esw_en = 1; 2376 dev_config.dv_flow_en = 1; 2377 dev_config.decap_en = 1; 2378 dev_config.log_hp_size = MLX5_ARG_UNSET; 2379 dev_config.allow_duplicate_pattern = 1; 2380 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2381 &list[i], 2382 &dev_config, 2383 ð_da); 2384 if (!list[i].eth_dev) { 2385 if (rte_errno != EBUSY && rte_errno != EEXIST) 2386 break; 2387 /* Device is disabled or already spawned. Ignore it. */ 2388 continue; 2389 } 2390 restore = list[i].eth_dev->data->dev_flags; 2391 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2392 /* Restore non-PCI flags cleared by the above call. */ 2393 list[i].eth_dev->data->dev_flags |= restore; 2394 rte_eth_dev_probing_finish(list[i].eth_dev); 2395 } 2396 if (i != ns) { 2397 DRV_LOG(ERR, 2398 "probe of PCI device " PCI_PRI_FMT " aborted after" 2399 " encountering an error: %s", 2400 owner_pci.domain, owner_pci.bus, 2401 owner_pci.devid, owner_pci.function, 2402 strerror(rte_errno)); 2403 ret = -rte_errno; 2404 /* Roll back. */ 2405 while (i--) { 2406 if (!list[i].eth_dev) 2407 continue; 2408 mlx5_dev_close(list[i].eth_dev); 2409 /* mac_addrs must not be freed because in dev_private */ 2410 list[i].eth_dev->data->mac_addrs = NULL; 2411 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2412 } 2413 /* Restore original error. */ 2414 rte_errno = -ret; 2415 } else { 2416 ret = 0; 2417 } 2418 exit: 2419 /* 2420 * Do the routine cleanup: 2421 * - close opened Netlink sockets 2422 * - free allocated spawn data array 2423 * - free the Infiniband device list 2424 */ 2425 if (nl_rdma >= 0) 2426 close(nl_rdma); 2427 if (nl_route >= 0) 2428 close(nl_route); 2429 if (list) 2430 mlx5_free(list); 2431 MLX5_ASSERT(ibv_list); 2432 mlx5_glue->free_device_list(ibv_list); 2433 return ret; 2434 } 2435 2436 /** 2437 * DPDK callback to register a PCI device. 2438 * 2439 * This function spawns Ethernet devices out of a given PCI device. 2440 * 2441 * @param[in] pci_drv 2442 * PCI driver structure (mlx5_driver). 2443 * @param[in] pci_dev 2444 * PCI device information. 2445 * 2446 * @return 2447 * 0 on success, a negative errno value otherwise and rte_errno is set. 2448 */ 2449 int 2450 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2451 struct rte_pci_device *pci_dev) 2452 { 2453 struct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE }; 2454 int ret = 0; 2455 uint16_t p; 2456 2457 if (pci_dev->device.devargs) { 2458 /* Parse representor information from device argument. */ 2459 if (pci_dev->device.devargs->cls_str) 2460 ret = rte_eth_devargs_parse 2461 (pci_dev->device.devargs->cls_str, ð_da); 2462 if (ret) { 2463 DRV_LOG(ERR, "failed to parse device arguments: %s", 2464 pci_dev->device.devargs->cls_str); 2465 return -rte_errno; 2466 } 2467 if (eth_da.type == RTE_ETH_REPRESENTOR_NONE) { 2468 /* Support legacy device argument */ 2469 ret = rte_eth_devargs_parse 2470 (pci_dev->device.devargs->args, ð_da); 2471 if (ret) { 2472 DRV_LOG(ERR, "failed to parse device arguments: %s", 2473 pci_dev->device.devargs->args); 2474 return -rte_errno; 2475 } 2476 } 2477 } 2478 2479 if (eth_da.nb_ports > 0) { 2480 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2481 for (p = 0; p < eth_da.nb_ports; p++) 2482 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2483 eth_da.ports[p]); 2484 } else { 2485 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2486 } 2487 return ret; 2488 } 2489 2490 static int 2491 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2492 { 2493 char *env; 2494 int value; 2495 2496 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2497 /* Get environment variable to store. */ 2498 env = getenv(MLX5_SHUT_UP_BF); 2499 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2500 if (config->dbnc == MLX5_ARG_UNSET) 2501 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2502 else 2503 setenv(MLX5_SHUT_UP_BF, 2504 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2505 return value; 2506 } 2507 2508 static void 2509 mlx5_restore_doorbell_mapping_env(int value) 2510 { 2511 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2512 /* Restore the original environment variable state. */ 2513 if (value == MLX5_ARG_UNSET) 2514 unsetenv(MLX5_SHUT_UP_BF); 2515 else 2516 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2517 } 2518 2519 /** 2520 * Extract pdn of PD object using DV API. 2521 * 2522 * @param[in] pd 2523 * Pointer to the verbs PD object. 2524 * @param[out] pdn 2525 * Pointer to the PD object number variable. 2526 * 2527 * @return 2528 * 0 on success, error value otherwise. 2529 */ 2530 int 2531 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2532 { 2533 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2534 struct mlx5dv_obj obj; 2535 struct mlx5dv_pd pd_info; 2536 int ret = 0; 2537 2538 obj.pd.in = pd; 2539 obj.pd.out = &pd_info; 2540 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2541 if (ret) { 2542 DRV_LOG(DEBUG, "Fail to get PD object info"); 2543 return ret; 2544 } 2545 *pdn = pd_info.pdn; 2546 return 0; 2547 #else 2548 (void)pd; 2549 (void)pdn; 2550 return -ENOTSUP; 2551 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2552 } 2553 2554 /** 2555 * Function API to open IB device. 2556 * 2557 * This function calls the Linux glue APIs to open a device. 2558 * 2559 * @param[in] spawn 2560 * Pointer to the IB device attributes (name, port, etc). 2561 * @param[out] config 2562 * Pointer to device configuration structure. 2563 * @param[out] sh 2564 * Pointer to shared context structure. 2565 * 2566 * @return 2567 * 0 on success, a positive error value otherwise. 2568 */ 2569 int 2570 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2571 const struct mlx5_dev_config *config, 2572 struct mlx5_dev_ctx_shared *sh) 2573 { 2574 int dbmap_env; 2575 int err = 0; 2576 2577 sh->numa_node = spawn->pci_dev->device.numa_node; 2578 pthread_mutex_init(&sh->txpp.mutex, NULL); 2579 /* 2580 * Configure environment variable "MLX5_BF_SHUT_UP" 2581 * before the device creation. The rdma_core library 2582 * checks the variable at device creation and 2583 * stores the result internally. 2584 */ 2585 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2586 /* Try to open IB device with DV first, then usual Verbs. */ 2587 errno = 0; 2588 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2589 if (sh->ctx) { 2590 sh->devx = 1; 2591 DRV_LOG(DEBUG, "DevX is supported"); 2592 /* The device is created, no need for environment. */ 2593 mlx5_restore_doorbell_mapping_env(dbmap_env); 2594 } else { 2595 /* The environment variable is still configured. */ 2596 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2597 err = errno ? errno : ENODEV; 2598 /* 2599 * The environment variable is not needed anymore, 2600 * all device creation attempts are completed. 2601 */ 2602 mlx5_restore_doorbell_mapping_env(dbmap_env); 2603 if (!sh->ctx) 2604 return err; 2605 DRV_LOG(DEBUG, "DevX is NOT supported"); 2606 err = 0; 2607 } 2608 if (!err && sh->ctx) { 2609 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2610 mlx5_glue->dv_set_context_attr(sh->ctx, 2611 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2612 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2613 .alloc = &mlx5_alloc_verbs_buf, 2614 .free = &mlx5_free_verbs_buf, 2615 .data = sh, 2616 })); 2617 } 2618 return err; 2619 } 2620 2621 /** 2622 * Install shared asynchronous device events handler. 2623 * This function is implemented to support event sharing 2624 * between multiple ports of single IB device. 2625 * 2626 * @param sh 2627 * Pointer to mlx5_dev_ctx_shared object. 2628 */ 2629 void 2630 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2631 { 2632 int ret; 2633 int flags; 2634 2635 sh->intr_handle.fd = -1; 2636 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2637 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2638 F_SETFL, flags | O_NONBLOCK); 2639 if (ret) { 2640 DRV_LOG(INFO, "failed to change file descriptor async event" 2641 " queue"); 2642 } else { 2643 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2644 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2645 if (rte_intr_callback_register(&sh->intr_handle, 2646 mlx5_dev_interrupt_handler, sh)) { 2647 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2648 sh->intr_handle.fd = -1; 2649 } 2650 } 2651 if (sh->devx) { 2652 #ifdef HAVE_IBV_DEVX_ASYNC 2653 sh->intr_handle_devx.fd = -1; 2654 sh->devx_comp = 2655 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2656 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2657 if (!devx_comp) { 2658 DRV_LOG(INFO, "failed to allocate devx_comp."); 2659 return; 2660 } 2661 flags = fcntl(devx_comp->fd, F_GETFL); 2662 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2663 if (ret) { 2664 DRV_LOG(INFO, "failed to change file descriptor" 2665 " devx comp"); 2666 return; 2667 } 2668 sh->intr_handle_devx.fd = devx_comp->fd; 2669 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2670 if (rte_intr_callback_register(&sh->intr_handle_devx, 2671 mlx5_dev_interrupt_handler_devx, sh)) { 2672 DRV_LOG(INFO, "Fail to install the devx shared" 2673 " interrupt."); 2674 sh->intr_handle_devx.fd = -1; 2675 } 2676 #endif /* HAVE_IBV_DEVX_ASYNC */ 2677 } 2678 } 2679 2680 /** 2681 * Uninstall shared asynchronous device events handler. 2682 * This function is implemented to support event sharing 2683 * between multiple ports of single IB device. 2684 * 2685 * @param dev 2686 * Pointer to mlx5_dev_ctx_shared object. 2687 */ 2688 void 2689 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2690 { 2691 if (sh->intr_handle.fd >= 0) 2692 mlx5_intr_callback_unregister(&sh->intr_handle, 2693 mlx5_dev_interrupt_handler, sh); 2694 #ifdef HAVE_IBV_DEVX_ASYNC 2695 if (sh->intr_handle_devx.fd >= 0) 2696 rte_intr_callback_unregister(&sh->intr_handle_devx, 2697 mlx5_dev_interrupt_handler_devx, sh); 2698 if (sh->devx_comp) 2699 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2700 #endif 2701 } 2702 2703 /** 2704 * Read statistics by a named counter. 2705 * 2706 * @param[in] priv 2707 * Pointer to the private device data structure. 2708 * @param[in] ctr_name 2709 * Pointer to the name of the statistic counter to read 2710 * @param[out] stat 2711 * Pointer to read statistic value. 2712 * @return 2713 * 0 on success and stat is valud, 1 if failed to read the value 2714 * rte_errno is set. 2715 * 2716 */ 2717 int 2718 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2719 uint64_t *stat) 2720 { 2721 int fd; 2722 2723 if (priv->sh) { 2724 if (priv->q_counters != NULL && 2725 strcmp(ctr_name, "out_of_buffer") == 0) 2726 return mlx5_devx_cmd_queue_counter_query 2727 (priv->q_counters, 0, (uint32_t *)stat); 2728 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2729 priv->sh->ibdev_path, 2730 priv->dev_port, 2731 ctr_name); 2732 fd = open(path, O_RDONLY); 2733 /* 2734 * in switchdev the file location is not per port 2735 * but rather in <ibdev_path>/hw_counters/<file_name>. 2736 */ 2737 if (fd == -1) { 2738 MKSTR(path1, "%s/hw_counters/%s", 2739 priv->sh->ibdev_path, 2740 ctr_name); 2741 fd = open(path1, O_RDONLY); 2742 } 2743 if (fd != -1) { 2744 char buf[21] = {'\0'}; 2745 ssize_t n = read(fd, buf, sizeof(buf)); 2746 2747 close(fd); 2748 if (n != -1) { 2749 *stat = strtoull(buf, NULL, 10); 2750 return 0; 2751 } 2752 } 2753 } 2754 *stat = 0; 2755 return 1; 2756 } 2757 2758 /** 2759 * Set the reg_mr and dereg_mr call backs 2760 * 2761 * @param reg_mr_cb[out] 2762 * Pointer to reg_mr func 2763 * @param dereg_mr_cb[out] 2764 * Pointer to dereg_mr func 2765 * 2766 */ 2767 void 2768 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2769 mlx5_dereg_mr_t *dereg_mr_cb) 2770 { 2771 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2772 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2773 } 2774 2775 /** 2776 * Remove a MAC address from device 2777 * 2778 * @param dev 2779 * Pointer to Ethernet device structure. 2780 * @param index 2781 * MAC address index. 2782 */ 2783 void 2784 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2785 { 2786 struct mlx5_priv *priv = dev->data->dev_private; 2787 const int vf = priv->config.vf; 2788 2789 if (vf) 2790 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2791 mlx5_ifindex(dev), priv->mac_own, 2792 &dev->data->mac_addrs[index], index); 2793 } 2794 2795 /** 2796 * Adds a MAC address to the device 2797 * 2798 * @param dev 2799 * Pointer to Ethernet device structure. 2800 * @param mac_addr 2801 * MAC address to register. 2802 * @param index 2803 * MAC address index. 2804 * 2805 * @return 2806 * 0 on success, a negative errno value otherwise 2807 */ 2808 int 2809 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2810 uint32_t index) 2811 { 2812 struct mlx5_priv *priv = dev->data->dev_private; 2813 const int vf = priv->config.vf; 2814 int ret = 0; 2815 2816 if (vf) 2817 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2818 mlx5_ifindex(dev), priv->mac_own, 2819 mac, index); 2820 return ret; 2821 } 2822 2823 /** 2824 * Modify a VF MAC address 2825 * 2826 * @param priv 2827 * Pointer to device private data. 2828 * @param mac_addr 2829 * MAC address to modify into. 2830 * @param iface_idx 2831 * Net device interface index 2832 * @param vf_index 2833 * VF index 2834 * 2835 * @return 2836 * 0 on success, a negative errno value otherwise 2837 */ 2838 int 2839 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2840 unsigned int iface_idx, 2841 struct rte_ether_addr *mac_addr, 2842 int vf_index) 2843 { 2844 return mlx5_nl_vf_mac_addr_modify 2845 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2846 } 2847 2848 /** 2849 * Set device promiscuous mode 2850 * 2851 * @param dev 2852 * Pointer to Ethernet device structure. 2853 * @param enable 2854 * 0 - promiscuous is disabled, otherwise - enabled 2855 * 2856 * @return 2857 * 0 on success, a negative error value otherwise 2858 */ 2859 int 2860 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2861 { 2862 struct mlx5_priv *priv = dev->data->dev_private; 2863 2864 return mlx5_nl_promisc(priv->nl_socket_route, 2865 mlx5_ifindex(dev), !!enable); 2866 } 2867 2868 /** 2869 * Set device promiscuous mode 2870 * 2871 * @param dev 2872 * Pointer to Ethernet device structure. 2873 * @param enable 2874 * 0 - all multicase is disabled, otherwise - enabled 2875 * 2876 * @return 2877 * 0 on success, a negative error value otherwise 2878 */ 2879 int 2880 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2881 { 2882 struct mlx5_priv *priv = dev->data->dev_private; 2883 2884 return mlx5_nl_allmulti(priv->nl_socket_route, 2885 mlx5_ifindex(dev), !!enable); 2886 } 2887 2888 /** 2889 * Flush device MAC addresses 2890 * 2891 * @param dev 2892 * Pointer to Ethernet device structure. 2893 * 2894 */ 2895 void 2896 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2897 { 2898 struct mlx5_priv *priv = dev->data->dev_private; 2899 2900 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2901 dev->data->mac_addrs, 2902 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2903 } 2904