1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2020 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <linux/rtnetlink.h> 14 #include <linux/sockios.h> 15 #include <linux/ethtool.h> 16 #include <fcntl.h> 17 18 #include <rte_malloc.h> 19 #include <ethdev_driver.h> 20 #include <ethdev_pci.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_common.h> 24 #include <rte_kvargs.h> 25 #include <rte_rwlock.h> 26 #include <rte_spinlock.h> 27 #include <rte_string_fns.h> 28 #include <rte_alarm.h> 29 #include <rte_eal_paging.h> 30 31 #include <mlx5_glue.h> 32 #include <mlx5_devx_cmds.h> 33 #include <mlx5_common.h> 34 #include <mlx5_common_mp.h> 35 #include <mlx5_common_mr.h> 36 #include <mlx5_malloc.h> 37 38 #include "mlx5_defs.h" 39 #include "mlx5.h" 40 #include "mlx5_common_os.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_rxtx.h" 43 #include "mlx5_rx.h" 44 #include "mlx5_tx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_mr.h" 47 #include "mlx5_flow.h" 48 #include "rte_pmd_mlx5.h" 49 #include "mlx5_verbs.h" 50 #include "mlx5_nl.h" 51 #include "mlx5_devx.h" 52 53 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 54 55 #ifndef HAVE_IBV_MLX5_MOD_MPW 56 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 57 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 58 #endif 59 60 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 61 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 62 #endif 63 64 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 65 66 /* Spinlock for mlx5_shared_data allocation. */ 67 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 68 69 /* Process local data for secondary processes. */ 70 static struct mlx5_local_data mlx5_local_data; 71 72 /** 73 * Set the completion channel file descriptor interrupt as non-blocking. 74 * 75 * @param[in] rxq_obj 76 * Pointer to RQ channel object, which includes the channel fd 77 * 78 * @param[out] fd 79 * The file descriptor (representing the intetrrupt) used in this channel. 80 * 81 * @return 82 * 0 on successfully setting the fd to non-blocking, non-zero otherwise. 83 */ 84 int 85 mlx5_os_set_nonblock_channel_fd(int fd) 86 { 87 int flags; 88 89 flags = fcntl(fd, F_GETFL); 90 return fcntl(fd, F_SETFL, flags | O_NONBLOCK); 91 } 92 93 /** 94 * Get mlx5 device attributes. The glue function query_device_ex() is called 95 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5 96 * device attributes from the glue out parameter. 97 * 98 * @param dev 99 * Pointer to ibv context. 100 * 101 * @param device_attr 102 * Pointer to mlx5 device attributes. 103 * 104 * @return 105 * 0 on success, non zero error number otherwise 106 */ 107 int 108 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) 109 { 110 int err; 111 struct ibv_device_attr_ex attr_ex; 112 memset(device_attr, 0, sizeof(*device_attr)); 113 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex); 114 if (err) 115 return err; 116 117 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex; 118 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr; 119 device_attr->max_sge = attr_ex.orig_attr.max_sge; 120 device_attr->max_cq = attr_ex.orig_attr.max_cq; 121 device_attr->max_cqe = attr_ex.orig_attr.max_cqe; 122 device_attr->max_mr = attr_ex.orig_attr.max_mr; 123 device_attr->max_pd = attr_ex.orig_attr.max_pd; 124 device_attr->max_qp = attr_ex.orig_attr.max_qp; 125 device_attr->max_srq = attr_ex.orig_attr.max_srq; 126 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr; 127 device_attr->raw_packet_caps = attr_ex.raw_packet_caps; 128 device_attr->max_rwq_indirection_table_size = 129 attr_ex.rss_caps.max_rwq_indirection_table_size; 130 device_attr->max_tso = attr_ex.tso_caps.max_tso; 131 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts; 132 133 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 134 err = mlx5_glue->dv_query_device(ctx, &dv_attr); 135 if (err) 136 return err; 137 138 device_attr->flags = dv_attr.flags; 139 device_attr->comp_mask = dv_attr.comp_mask; 140 #ifdef HAVE_IBV_MLX5_MOD_SWP 141 device_attr->sw_parsing_offloads = 142 dv_attr.sw_parsing_caps.sw_parsing_offloads; 143 #endif 144 device_attr->min_single_stride_log_num_of_bytes = 145 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes; 146 device_attr->max_single_stride_log_num_of_bytes = 147 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes; 148 device_attr->min_single_wqe_log_num_of_strides = 149 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides; 150 device_attr->max_single_wqe_log_num_of_strides = 151 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides; 152 device_attr->stride_supported_qpts = 153 dv_attr.striding_rq_caps.supported_qpts; 154 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 155 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps; 156 #endif 157 158 return err; 159 } 160 161 /** 162 * Verbs callback to allocate a memory. This function should allocate the space 163 * according to the size provided residing inside a huge page. 164 * Please note that all allocation must respect the alignment from libmlx5 165 * (i.e. currently rte_mem_page_size()). 166 * 167 * @param[in] size 168 * The size in bytes of the memory to allocate. 169 * @param[in] data 170 * A pointer to the callback data. 171 * 172 * @return 173 * Allocated buffer, NULL otherwise and rte_errno is set. 174 */ 175 static void * 176 mlx5_alloc_verbs_buf(size_t size, void *data) 177 { 178 struct mlx5_dev_ctx_shared *sh = data; 179 void *ret; 180 size_t alignment = rte_mem_page_size(); 181 if (alignment == (size_t)-1) { 182 DRV_LOG(ERR, "Failed to get mem page size"); 183 rte_errno = ENOMEM; 184 return NULL; 185 } 186 187 MLX5_ASSERT(data != NULL); 188 ret = mlx5_malloc(0, size, alignment, sh->numa_node); 189 if (!ret && size) 190 rte_errno = ENOMEM; 191 return ret; 192 } 193 194 /** 195 * Verbs callback to free a memory. 196 * 197 * @param[in] ptr 198 * A pointer to the memory to free. 199 * @param[in] data 200 * A pointer to the callback data. 201 */ 202 static void 203 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 204 { 205 MLX5_ASSERT(data != NULL); 206 mlx5_free(ptr); 207 } 208 209 /** 210 * Initialize DR related data within private structure. 211 * Routine checks the reference counter and does actual 212 * resources creation/initialization only if counter is zero. 213 * 214 * @param[in] priv 215 * Pointer to the private device data structure. 216 * 217 * @return 218 * Zero on success, positive error code otherwise. 219 */ 220 static int 221 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 222 { 223 struct mlx5_dev_ctx_shared *sh = priv->sh; 224 char s[MLX5_HLIST_NAMESIZE] __rte_unused; 225 int err; 226 227 MLX5_ASSERT(sh && sh->refcnt); 228 if (sh->refcnt > 1) 229 return 0; 230 err = mlx5_alloc_table_hash_list(priv); 231 if (err) 232 goto error; 233 /* The resources below are only valid with DV support. */ 234 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 235 /* Init port id action cache list. */ 236 snprintf(s, sizeof(s), "%s_port_id_action_cache", sh->ibdev_name); 237 mlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh, 238 flow_dv_port_id_create_cb, 239 flow_dv_port_id_match_cb, 240 flow_dv_port_id_remove_cb); 241 /* Init push vlan action cache list. */ 242 snprintf(s, sizeof(s), "%s_push_vlan_action_cache", sh->ibdev_name); 243 mlx5_cache_list_init(&sh->push_vlan_action_list, s, 0, sh, 244 flow_dv_push_vlan_create_cb, 245 flow_dv_push_vlan_match_cb, 246 flow_dv_push_vlan_remove_cb); 247 /* Init sample action cache list. */ 248 snprintf(s, sizeof(s), "%s_sample_action_cache", sh->ibdev_name); 249 mlx5_cache_list_init(&sh->sample_action_list, s, 0, sh, 250 flow_dv_sample_create_cb, 251 flow_dv_sample_match_cb, 252 flow_dv_sample_remove_cb); 253 /* Init dest array action cache list. */ 254 snprintf(s, sizeof(s), "%s_dest_array_cache", sh->ibdev_name); 255 mlx5_cache_list_init(&sh->dest_array_list, s, 0, sh, 256 flow_dv_dest_array_create_cb, 257 flow_dv_dest_array_match_cb, 258 flow_dv_dest_array_remove_cb); 259 /* Create tags hash list table. */ 260 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 261 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0, 262 MLX5_HLIST_WRITE_MOST, 263 flow_dv_tag_create_cb, 264 flow_dv_tag_match_cb, 265 flow_dv_tag_remove_cb); 266 if (!sh->tag_table) { 267 DRV_LOG(ERR, "tags with hash creation failed."); 268 err = ENOMEM; 269 goto error; 270 } 271 sh->tag_table->ctx = sh; 272 snprintf(s, sizeof(s), "%s_hdr_modify", sh->ibdev_name); 273 sh->modify_cmds = mlx5_hlist_create(s, MLX5_FLOW_HDR_MODIFY_HTABLE_SZ, 274 0, MLX5_HLIST_WRITE_MOST | 275 MLX5_HLIST_DIRECT_KEY, 276 flow_dv_modify_create_cb, 277 flow_dv_modify_match_cb, 278 flow_dv_modify_remove_cb); 279 if (!sh->modify_cmds) { 280 DRV_LOG(ERR, "hdr modify hash creation failed"); 281 err = ENOMEM; 282 goto error; 283 } 284 sh->modify_cmds->ctx = sh; 285 snprintf(s, sizeof(s), "%s_encaps_decaps", sh->ibdev_name); 286 sh->encaps_decaps = mlx5_hlist_create(s, 287 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ, 288 0, MLX5_HLIST_DIRECT_KEY | 289 MLX5_HLIST_WRITE_MOST, 290 flow_dv_encap_decap_create_cb, 291 flow_dv_encap_decap_match_cb, 292 flow_dv_encap_decap_remove_cb); 293 if (!sh->encaps_decaps) { 294 DRV_LOG(ERR, "encap decap hash creation failed"); 295 err = ENOMEM; 296 goto error; 297 } 298 sh->encaps_decaps->ctx = sh; 299 #endif 300 #ifdef HAVE_MLX5DV_DR 301 void *domain; 302 303 /* Reference counter is zero, we should initialize structures. */ 304 domain = mlx5_glue->dr_create_domain(sh->ctx, 305 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 306 if (!domain) { 307 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 308 err = errno; 309 goto error; 310 } 311 sh->rx_domain = domain; 312 domain = mlx5_glue->dr_create_domain(sh->ctx, 313 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 314 if (!domain) { 315 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 316 err = errno; 317 goto error; 318 } 319 sh->tx_domain = domain; 320 #ifdef HAVE_MLX5DV_DR_ESWITCH 321 if (priv->config.dv_esw_en) { 322 domain = mlx5_glue->dr_create_domain 323 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 324 if (!domain) { 325 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 326 err = errno; 327 goto error; 328 } 329 sh->fdb_domain = domain; 330 } 331 /* 332 * The drop action is just some dummy placeholder in rdma-core. It 333 * does not belong to domains and has no any attributes, and, can be 334 * shared by the entire device. 335 */ 336 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop(); 337 if (!sh->dr_drop_action) { 338 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop"); 339 err = errno; 340 goto error; 341 } 342 #endif 343 if (!sh->tunnel_hub) 344 err = mlx5_alloc_tunnel_hub(sh); 345 if (err) { 346 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err); 347 goto error; 348 } 349 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) { 350 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1); 351 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1); 352 if (sh->fdb_domain) 353 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); 354 } 355 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 356 #endif /* HAVE_MLX5DV_DR */ 357 sh->default_miss_action = 358 mlx5_glue->dr_create_flow_action_default_miss(); 359 if (!sh->default_miss_action) 360 DRV_LOG(WARNING, "Default miss action is not supported."); 361 return 0; 362 error: 363 /* Rollback the created objects. */ 364 if (sh->rx_domain) { 365 mlx5_glue->dr_destroy_domain(sh->rx_domain); 366 sh->rx_domain = NULL; 367 } 368 if (sh->tx_domain) { 369 mlx5_glue->dr_destroy_domain(sh->tx_domain); 370 sh->tx_domain = NULL; 371 } 372 if (sh->fdb_domain) { 373 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 374 sh->fdb_domain = NULL; 375 } 376 if (sh->dr_drop_action) { 377 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 378 sh->dr_drop_action = NULL; 379 } 380 if (sh->pop_vlan_action) { 381 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 382 sh->pop_vlan_action = NULL; 383 } 384 if (sh->encaps_decaps) { 385 mlx5_hlist_destroy(sh->encaps_decaps); 386 sh->encaps_decaps = NULL; 387 } 388 if (sh->modify_cmds) { 389 mlx5_hlist_destroy(sh->modify_cmds); 390 sh->modify_cmds = NULL; 391 } 392 if (sh->tag_table) { 393 /* tags should be destroyed with flow before. */ 394 mlx5_hlist_destroy(sh->tag_table); 395 sh->tag_table = NULL; 396 } 397 if (sh->tunnel_hub) { 398 mlx5_release_tunnel_hub(sh, priv->dev_port); 399 sh->tunnel_hub = NULL; 400 } 401 mlx5_free_table_hash_list(priv); 402 return err; 403 } 404 405 /** 406 * Destroy DR related data within private structure. 407 * 408 * @param[in] priv 409 * Pointer to the private device data structure. 410 */ 411 void 412 mlx5_os_free_shared_dr(struct mlx5_priv *priv) 413 { 414 struct mlx5_dev_ctx_shared *sh = priv->sh; 415 416 MLX5_ASSERT(sh && sh->refcnt); 417 if (sh->refcnt > 1) 418 return; 419 #ifdef HAVE_MLX5DV_DR 420 if (sh->rx_domain) { 421 mlx5_glue->dr_destroy_domain(sh->rx_domain); 422 sh->rx_domain = NULL; 423 } 424 if (sh->tx_domain) { 425 mlx5_glue->dr_destroy_domain(sh->tx_domain); 426 sh->tx_domain = NULL; 427 } 428 #ifdef HAVE_MLX5DV_DR_ESWITCH 429 if (sh->fdb_domain) { 430 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 431 sh->fdb_domain = NULL; 432 } 433 if (sh->dr_drop_action) { 434 mlx5_glue->destroy_flow_action(sh->dr_drop_action); 435 sh->dr_drop_action = NULL; 436 } 437 #endif 438 if (sh->pop_vlan_action) { 439 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 440 sh->pop_vlan_action = NULL; 441 } 442 #endif /* HAVE_MLX5DV_DR */ 443 if (sh->default_miss_action) 444 mlx5_glue->destroy_flow_action 445 (sh->default_miss_action); 446 if (sh->encaps_decaps) { 447 mlx5_hlist_destroy(sh->encaps_decaps); 448 sh->encaps_decaps = NULL; 449 } 450 if (sh->modify_cmds) { 451 mlx5_hlist_destroy(sh->modify_cmds); 452 sh->modify_cmds = NULL; 453 } 454 if (sh->tag_table) { 455 /* tags should be destroyed with flow before. */ 456 mlx5_hlist_destroy(sh->tag_table); 457 sh->tag_table = NULL; 458 } 459 if (sh->tunnel_hub) { 460 mlx5_release_tunnel_hub(sh, priv->dev_port); 461 sh->tunnel_hub = NULL; 462 } 463 mlx5_cache_list_destroy(&sh->port_id_action_list); 464 mlx5_cache_list_destroy(&sh->push_vlan_action_list); 465 mlx5_free_table_hash_list(priv); 466 } 467 468 /** 469 * Initialize shared data between primary and secondary process. 470 * 471 * A memzone is reserved by primary process and secondary processes attach to 472 * the memzone. 473 * 474 * @return 475 * 0 on success, a negative errno value otherwise and rte_errno is set. 476 */ 477 static int 478 mlx5_init_shared_data(void) 479 { 480 const struct rte_memzone *mz; 481 int ret = 0; 482 483 rte_spinlock_lock(&mlx5_shared_data_lock); 484 if (mlx5_shared_data == NULL) { 485 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 486 /* Allocate shared memory. */ 487 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 488 sizeof(*mlx5_shared_data), 489 SOCKET_ID_ANY, 0); 490 if (mz == NULL) { 491 DRV_LOG(ERR, 492 "Cannot allocate mlx5 shared data"); 493 ret = -rte_errno; 494 goto error; 495 } 496 mlx5_shared_data = mz->addr; 497 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 498 rte_spinlock_init(&mlx5_shared_data->lock); 499 } else { 500 /* Lookup allocated shared memory. */ 501 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 502 if (mz == NULL) { 503 DRV_LOG(ERR, 504 "Cannot attach mlx5 shared data"); 505 ret = -rte_errno; 506 goto error; 507 } 508 mlx5_shared_data = mz->addr; 509 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 510 } 511 } 512 error: 513 rte_spinlock_unlock(&mlx5_shared_data_lock); 514 return ret; 515 } 516 517 /** 518 * PMD global initialization. 519 * 520 * Independent from individual device, this function initializes global 521 * per-PMD data structures distinguishing primary and secondary processes. 522 * Hence, each initialization is called once per a process. 523 * 524 * @return 525 * 0 on success, a negative errno value otherwise and rte_errno is set. 526 */ 527 static int 528 mlx5_init_once(void) 529 { 530 struct mlx5_shared_data *sd; 531 struct mlx5_local_data *ld = &mlx5_local_data; 532 int ret = 0; 533 534 if (mlx5_init_shared_data()) 535 return -rte_errno; 536 sd = mlx5_shared_data; 537 MLX5_ASSERT(sd); 538 rte_spinlock_lock(&sd->lock); 539 switch (rte_eal_process_type()) { 540 case RTE_PROC_PRIMARY: 541 if (sd->init_done) 542 break; 543 LIST_INIT(&sd->mem_event_cb_list); 544 rte_rwlock_init(&sd->mem_event_rwlock); 545 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 546 mlx5_mr_mem_event_cb, NULL); 547 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 548 mlx5_mp_os_primary_handle); 549 if (ret) 550 goto out; 551 sd->init_done = true; 552 break; 553 case RTE_PROC_SECONDARY: 554 if (ld->init_done) 555 break; 556 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 557 mlx5_mp_os_secondary_handle); 558 if (ret) 559 goto out; 560 ++sd->secondary_cnt; 561 ld->init_done = true; 562 break; 563 default: 564 break; 565 } 566 out: 567 rte_spinlock_unlock(&sd->lock); 568 return ret; 569 } 570 571 /** 572 * Create the Tx queue DevX/Verbs object. 573 * 574 * @param dev 575 * Pointer to Ethernet device. 576 * @param idx 577 * Queue index in DPDK Tx queue array. 578 * 579 * @return 580 * 0 on success, a negative errno value otherwise and rte_errno is set. 581 */ 582 static int 583 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx) 584 { 585 struct mlx5_priv *priv = dev->data->dev_private; 586 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; 587 struct mlx5_txq_ctrl *txq_ctrl = 588 container_of(txq_data, struct mlx5_txq_ctrl, txq); 589 590 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) 591 return mlx5_txq_devx_obj_new(dev, idx); 592 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 593 if (!priv->config.dv_esw_en) 594 return mlx5_txq_devx_obj_new(dev, idx); 595 #endif 596 return mlx5_txq_ibv_obj_new(dev, idx); 597 } 598 599 /** 600 * Release an Tx DevX/verbs queue object. 601 * 602 * @param txq_obj 603 * DevX/Verbs Tx queue object. 604 */ 605 static void 606 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj) 607 { 608 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { 609 mlx5_txq_devx_obj_release(txq_obj); 610 return; 611 } 612 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET 613 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) { 614 mlx5_txq_devx_obj_release(txq_obj); 615 return; 616 } 617 #endif 618 mlx5_txq_ibv_obj_release(txq_obj); 619 } 620 621 /** 622 * DV flow counter mode detect and config. 623 * 624 * @param dev 625 * Pointer to rte_eth_dev structure. 626 * 627 */ 628 static void 629 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 630 { 631 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 632 struct mlx5_priv *priv = dev->data->dev_private; 633 struct mlx5_dev_ctx_shared *sh = priv->sh; 634 bool fallback; 635 636 #ifndef HAVE_IBV_DEVX_ASYNC 637 fallback = true; 638 #else 639 fallback = false; 640 if (!priv->config.devx || !priv->config.dv_flow_en || 641 !priv->config.hca_attr.flow_counters_dump || 642 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || 643 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 644 fallback = true; 645 #endif 646 if (fallback) 647 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 648 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 649 priv->config.hca_attr.flow_counters_dump, 650 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); 651 /* Initialize fallback mode only on the port initializes sh. */ 652 if (sh->refcnt == 1) 653 sh->cmng.counter_fallback = fallback; 654 else if (fallback != sh->cmng.counter_fallback) 655 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 656 "with others:%d.", PORT_ID(priv), fallback); 657 #endif 658 } 659 660 static void 661 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev) 662 { 663 struct mlx5_priv *priv = dev->data->dev_private; 664 void *ctx = priv->sh->ctx; 665 666 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx); 667 if (!priv->q_counters) { 668 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0); 669 struct ibv_wq *wq; 670 671 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created " 672 "by DevX - fall-back to use the kernel driver global " 673 "queue counter.", dev->data->port_id); 674 /* Create WQ by kernel and query its queue counter ID. */ 675 if (cq) { 676 wq = mlx5_glue->create_wq(ctx, 677 &(struct ibv_wq_init_attr){ 678 .wq_type = IBV_WQT_RQ, 679 .max_wr = 1, 680 .max_sge = 1, 681 .pd = priv->sh->pd, 682 .cq = cq, 683 }); 684 if (wq) { 685 /* Counter is assigned only on RDY state. */ 686 int ret = mlx5_glue->modify_wq(wq, 687 &(struct ibv_wq_attr){ 688 .attr_mask = IBV_WQ_ATTR_STATE, 689 .wq_state = IBV_WQS_RDY, 690 }); 691 692 if (ret == 0) 693 mlx5_devx_cmd_wq_query(wq, 694 &priv->counter_set_id); 695 claim_zero(mlx5_glue->destroy_wq(wq)); 696 } 697 claim_zero(mlx5_glue->destroy_cq(cq)); 698 } 699 } else { 700 priv->counter_set_id = priv->q_counters->id; 701 } 702 if (priv->counter_set_id == 0) 703 DRV_LOG(INFO, "Part of the port %d statistics will not be " 704 "available.", dev->data->port_id); 705 } 706 707 /** 708 * Check if representor spawn info match devargs. 709 * 710 * @param spawn 711 * Verbs device parameters (name, port, switch_info) to spawn. 712 * @param eth_da 713 * Device devargs to probe. 714 * 715 * @return 716 * Match result. 717 */ 718 static bool 719 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn, 720 struct rte_eth_devargs *eth_da) 721 { 722 struct mlx5_switch_info *switch_info = &spawn->info; 723 unsigned int p, f; 724 uint16_t id; 725 uint16_t repr_id = mlx5_representor_id_encode(switch_info, 726 eth_da->type); 727 728 switch (eth_da->type) { 729 case RTE_ETH_REPRESENTOR_SF: 730 if (!(spawn->info.port_name == -1 && 731 switch_info->name_type == 732 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 733 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) { 734 rte_errno = EBUSY; 735 return false; 736 } 737 break; 738 case RTE_ETH_REPRESENTOR_VF: 739 /* Allows HPF representor index -1 as exception. */ 740 if (!(spawn->info.port_name == -1 && 741 switch_info->name_type == 742 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) && 743 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) { 744 rte_errno = EBUSY; 745 return false; 746 } 747 break; 748 case RTE_ETH_REPRESENTOR_NONE: 749 rte_errno = EBUSY; 750 return false; 751 default: 752 rte_errno = ENOTSUP; 753 DRV_LOG(ERR, "unsupported representor type"); 754 return false; 755 } 756 /* Check representor ID: */ 757 for (p = 0; p < eth_da->nb_ports; ++p) { 758 if (spawn->pf_bond < 0) { 759 /* For non-LAG mode, allow and ignore pf. */ 760 switch_info->pf_num = eth_da->ports[p]; 761 repr_id = mlx5_representor_id_encode(switch_info, 762 eth_da->type); 763 } 764 for (f = 0; f < eth_da->nb_representor_ports; ++f) { 765 id = MLX5_REPRESENTOR_ID 766 (eth_da->ports[p], eth_da->type, 767 eth_da->representor_ports[f]); 768 if (repr_id == id) 769 return true; 770 } 771 } 772 rte_errno = EBUSY; 773 return false; 774 } 775 776 777 /** 778 * Spawn an Ethernet device from Verbs information. 779 * 780 * @param dpdk_dev 781 * Backing DPDK device. 782 * @param spawn 783 * Verbs device parameters (name, port, switch_info) to spawn. 784 * @param config 785 * Device configuration parameters. 786 * @param config 787 * Device arguments. 788 * 789 * @return 790 * A valid Ethernet device object on success, NULL otherwise and rte_errno 791 * is set. The following errors are defined: 792 * 793 * EBUSY: device is not supposed to be spawned. 794 * EEXIST: device is already spawned 795 */ 796 static struct rte_eth_dev * 797 mlx5_dev_spawn(struct rte_device *dpdk_dev, 798 struct mlx5_dev_spawn_data *spawn, 799 struct mlx5_dev_config *config, 800 struct rte_eth_devargs *eth_da) 801 { 802 const struct mlx5_switch_info *switch_info = &spawn->info; 803 struct mlx5_dev_ctx_shared *sh = NULL; 804 struct ibv_port_attr port_attr; 805 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 806 struct rte_eth_dev *eth_dev = NULL; 807 struct mlx5_priv *priv = NULL; 808 int err = 0; 809 unsigned int hw_padding = 0; 810 unsigned int mps; 811 unsigned int tunnel_en = 0; 812 unsigned int mpls_en = 0; 813 unsigned int swp = 0; 814 unsigned int mprq = 0; 815 unsigned int mprq_min_stride_size_n = 0; 816 unsigned int mprq_max_stride_size_n = 0; 817 unsigned int mprq_min_stride_num_n = 0; 818 unsigned int mprq_max_stride_num_n = 0; 819 struct rte_ether_addr mac; 820 char name[RTE_ETH_NAME_MAX_LEN]; 821 int own_domain_id = 0; 822 uint16_t port_id; 823 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 824 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 825 #endif 826 827 /* Determine if this port representor is supposed to be spawned. */ 828 if (switch_info->representor && dpdk_dev->devargs && 829 !mlx5_representor_match(spawn, eth_da)) 830 return NULL; 831 /* Build device name. */ 832 if (spawn->pf_bond < 0) { 833 /* Single device. */ 834 if (!switch_info->representor) 835 strlcpy(name, dpdk_dev->name, sizeof(name)); 836 else 837 err = snprintf(name, sizeof(name), "%s_representor_%s%u", 838 dpdk_dev->name, 839 switch_info->name_type == 840 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 841 switch_info->port_name); 842 } else { 843 /* Bonding device. */ 844 if (!switch_info->representor) { 845 err = snprintf(name, sizeof(name), "%s_%s", 846 dpdk_dev->name, 847 mlx5_os_get_dev_device_name(spawn->phys_dev)); 848 } else { 849 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u", 850 dpdk_dev->name, 851 mlx5_os_get_dev_device_name(spawn->phys_dev), 852 switch_info->ctrl_num, 853 switch_info->pf_num, 854 switch_info->name_type == 855 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf", 856 switch_info->port_name); 857 } 858 } 859 if (err >= (int)sizeof(name)) 860 DRV_LOG(WARNING, "device name overflow %s", name); 861 /* check if the device is already spawned */ 862 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 863 rte_errno = EEXIST; 864 return NULL; 865 } 866 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 867 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 868 struct mlx5_mp_id mp_id; 869 870 eth_dev = rte_eth_dev_attach_secondary(name); 871 if (eth_dev == NULL) { 872 DRV_LOG(ERR, "can not attach rte ethdev"); 873 rte_errno = ENOMEM; 874 return NULL; 875 } 876 eth_dev->device = dpdk_dev; 877 eth_dev->dev_ops = &mlx5_dev_sec_ops; 878 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 879 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 880 err = mlx5_proc_priv_init(eth_dev); 881 if (err) 882 return NULL; 883 mp_id.port_id = eth_dev->data->port_id; 884 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 885 /* Receive command fd from primary process */ 886 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 887 if (err < 0) 888 goto err_secondary; 889 /* Remap UAR for Tx queues. */ 890 err = mlx5_tx_uar_init_secondary(eth_dev, err); 891 if (err) 892 goto err_secondary; 893 /* 894 * Ethdev pointer is still required as input since 895 * the primary device is not accessible from the 896 * secondary process. 897 */ 898 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 899 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 900 return eth_dev; 901 err_secondary: 902 mlx5_dev_close(eth_dev); 903 return NULL; 904 } 905 /* 906 * Some parameters ("tx_db_nc" in particularly) are needed in 907 * advance to create dv/verbs device context. We proceed the 908 * devargs here to get ones, and later proceed devargs again 909 * to override some hardware settings. 910 */ 911 err = mlx5_args(config, dpdk_dev->devargs); 912 if (err) { 913 err = rte_errno; 914 DRV_LOG(ERR, "failed to process device arguments: %s", 915 strerror(rte_errno)); 916 goto error; 917 } 918 if (config->dv_miss_info) { 919 if (switch_info->master || switch_info->representor) 920 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 921 } 922 mlx5_malloc_mem_select(config->sys_mem_en); 923 sh = mlx5_alloc_shared_dev_ctx(spawn, config); 924 if (!sh) 925 return NULL; 926 config->devx = sh->devx; 927 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 928 config->dest_tir = 1; 929 #endif 930 #ifdef HAVE_IBV_MLX5_MOD_SWP 931 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 932 #endif 933 /* 934 * Multi-packet send is supported by ConnectX-4 Lx PF as well 935 * as all ConnectX-5 devices. 936 */ 937 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 938 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 939 #endif 940 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 941 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 942 #endif 943 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 944 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 945 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 946 DRV_LOG(DEBUG, "enhanced MPW is supported"); 947 mps = MLX5_MPW_ENHANCED; 948 } else { 949 DRV_LOG(DEBUG, "MPW is supported"); 950 mps = MLX5_MPW; 951 } 952 } else { 953 DRV_LOG(DEBUG, "MPW isn't supported"); 954 mps = MLX5_MPW_DISABLED; 955 } 956 #ifdef HAVE_IBV_MLX5_MOD_SWP 957 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 958 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 959 DRV_LOG(DEBUG, "SWP support: %u", swp); 960 #endif 961 config->swp = !!swp; 962 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 963 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 964 struct mlx5dv_striding_rq_caps mprq_caps = 965 dv_attr.striding_rq_caps; 966 967 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 968 mprq_caps.min_single_stride_log_num_of_bytes); 969 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 970 mprq_caps.max_single_stride_log_num_of_bytes); 971 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 972 mprq_caps.min_single_wqe_log_num_of_strides); 973 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 974 mprq_caps.max_single_wqe_log_num_of_strides); 975 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 976 mprq_caps.supported_qpts); 977 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 978 mprq = 1; 979 mprq_min_stride_size_n = 980 mprq_caps.min_single_stride_log_num_of_bytes; 981 mprq_max_stride_size_n = 982 mprq_caps.max_single_stride_log_num_of_bytes; 983 mprq_min_stride_num_n = 984 mprq_caps.min_single_wqe_log_num_of_strides; 985 mprq_max_stride_num_n = 986 mprq_caps.max_single_wqe_log_num_of_strides; 987 } 988 #endif 989 /* Rx CQE compression is enabled by default. */ 990 config->cqe_comp = 1; 991 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 992 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 993 tunnel_en = ((dv_attr.tunnel_offloads_caps & 994 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 995 (dv_attr.tunnel_offloads_caps & 996 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 997 (dv_attr.tunnel_offloads_caps & 998 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 999 } 1000 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1001 tunnel_en ? "" : "not "); 1002 #else 1003 DRV_LOG(WARNING, 1004 "tunnel offloading disabled due to old OFED/rdma-core version"); 1005 #endif 1006 config->tunnel_en = tunnel_en; 1007 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1008 mpls_en = ((dv_attr.tunnel_offloads_caps & 1009 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1010 (dv_attr.tunnel_offloads_caps & 1011 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1012 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1013 mpls_en ? "" : "not "); 1014 #else 1015 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1016 " old OFED/rdma-core version or firmware configuration"); 1017 #endif 1018 config->mpls_en = mpls_en; 1019 /* Check port status. */ 1020 err = mlx5_glue->query_port(sh->ctx, spawn->phys_port, &port_attr); 1021 if (err) { 1022 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1023 goto error; 1024 } 1025 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1026 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1027 err = EINVAL; 1028 goto error; 1029 } 1030 if (port_attr.state != IBV_PORT_ACTIVE) 1031 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1032 mlx5_glue->port_state_str(port_attr.state), 1033 port_attr.state); 1034 /* Allocate private eth device data. */ 1035 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1036 sizeof(*priv), 1037 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1038 if (priv == NULL) { 1039 DRV_LOG(ERR, "priv allocation failure"); 1040 err = ENOMEM; 1041 goto error; 1042 } 1043 priv->sh = sh; 1044 priv->dev_port = spawn->phys_port; 1045 priv->pci_dev = spawn->pci_dev; 1046 priv->mtu = RTE_ETHER_MTU; 1047 /* Some internal functions rely on Netlink sockets, open them now. */ 1048 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1049 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1050 priv->representor = !!switch_info->representor; 1051 priv->master = !!switch_info->master; 1052 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1053 priv->vport_meta_tag = 0; 1054 priv->vport_meta_mask = 0; 1055 priv->pf_bond = spawn->pf_bond; 1056 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 1057 /* 1058 * The DevX port query API is implemented. E-Switch may use 1059 * either vport or reg_c[0] metadata register to match on 1060 * vport index. The engaged part of metadata register is 1061 * defined by mask. 1062 */ 1063 if (switch_info->representor || switch_info->master) { 1064 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 1065 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 1066 err = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port, 1067 &devx_port); 1068 if (err) { 1069 DRV_LOG(WARNING, 1070 "can't query devx port %d on device %s", 1071 spawn->phys_port, 1072 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1073 devx_port.comp_mask = 0; 1074 } 1075 } 1076 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 1077 priv->vport_meta_tag = devx_port.reg_c_0.value; 1078 priv->vport_meta_mask = devx_port.reg_c_0.mask; 1079 if (!priv->vport_meta_mask) { 1080 DRV_LOG(ERR, "vport zero mask for port %d" 1081 " on bonding device %s", 1082 spawn->phys_port, 1083 mlx5_os_get_dev_device_name 1084 (spawn->phys_dev)); 1085 err = ENOTSUP; 1086 goto error; 1087 } 1088 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 1089 DRV_LOG(ERR, "invalid vport tag for port %d" 1090 " on bonding device %s", 1091 spawn->phys_port, 1092 mlx5_os_get_dev_device_name 1093 (spawn->phys_dev)); 1094 err = ENOTSUP; 1095 goto error; 1096 } 1097 } 1098 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 1099 priv->vport_id = devx_port.vport_num; 1100 } else if (spawn->pf_bond >= 0 && 1101 (switch_info->representor || switch_info->master)) { 1102 DRV_LOG(ERR, "can't deduce vport index for port %d" 1103 " on bonding device %s", 1104 spawn->phys_port, 1105 mlx5_os_get_dev_device_name(spawn->phys_dev)); 1106 err = ENOTSUP; 1107 goto error; 1108 } else { 1109 /* Suppose vport index in compatible way. */ 1110 priv->vport_id = switch_info->representor ? 1111 switch_info->port_name + 1 : -1; 1112 } 1113 #else 1114 /* 1115 * Kernel/rdma_core support single E-Switch per PF configurations 1116 * only and vport_id field contains the vport index for 1117 * associated VF, which is deduced from representor port name. 1118 * For example, let's have the IB device port 10, it has 1119 * attached network device eth0, which has port name attribute 1120 * pf0vf2, we can deduce the VF number as 2, and set vport index 1121 * as 3 (2+1). This assigning schema should be changed if the 1122 * multiple E-Switch instances per PF configurations or/and PCI 1123 * subfunctions are added. 1124 */ 1125 priv->vport_id = switch_info->representor ? 1126 switch_info->port_name + 1 : -1; 1127 #endif 1128 priv->representor_id = mlx5_representor_id_encode(switch_info, 1129 eth_da->type); 1130 /* 1131 * Look for sibling devices in order to reuse their switch domain 1132 * if any, otherwise allocate one. 1133 */ 1134 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1135 const struct mlx5_priv *opriv = 1136 rte_eth_devices[port_id].data->dev_private; 1137 1138 if (!opriv || 1139 opriv->sh != priv->sh || 1140 opriv->domain_id == 1141 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1142 continue; 1143 priv->domain_id = opriv->domain_id; 1144 break; 1145 } 1146 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1147 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1148 if (err) { 1149 err = rte_errno; 1150 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1151 strerror(rte_errno)); 1152 goto error; 1153 } 1154 own_domain_id = 1; 1155 } 1156 /* Override some values set by hardware configuration. */ 1157 mlx5_args(config, dpdk_dev->devargs); 1158 err = mlx5_dev_check_sibling_config(priv, config); 1159 if (err) 1160 goto error; 1161 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1162 IBV_DEVICE_RAW_IP_CSUM); 1163 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1164 (config->hw_csum ? "" : "not ")); 1165 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1166 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1167 DRV_LOG(DEBUG, "counters are not supported"); 1168 #endif 1169 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 1170 if (config->dv_flow_en) { 1171 DRV_LOG(WARNING, "DV flow is not supported"); 1172 config->dv_flow_en = 0; 1173 } 1174 #endif 1175 config->ind_table_max_size = 1176 sh->device_attr.max_rwq_indirection_table_size; 1177 /* 1178 * Remove this check once DPDK supports larger/variable 1179 * indirection tables. 1180 */ 1181 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1182 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1183 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1184 config->ind_table_max_size); 1185 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1186 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1187 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1188 (config->hw_vlan_strip ? "" : "not ")); 1189 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1190 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1191 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1192 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1193 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1194 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1195 IBV_DEVICE_PCI_WRITE_END_PADDING); 1196 #endif 1197 if (config->hw_padding && !hw_padding) { 1198 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1199 config->hw_padding = 0; 1200 } else if (config->hw_padding) { 1201 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1202 } 1203 config->tso = (sh->device_attr.max_tso > 0 && 1204 (sh->device_attr.tso_supported_qpts & 1205 (1 << IBV_QPT_RAW_PACKET))); 1206 if (config->tso) 1207 config->tso_max_payload_sz = sh->device_attr.max_tso; 1208 /* 1209 * MPW is disabled by default, while the Enhanced MPW is enabled 1210 * by default. 1211 */ 1212 if (config->mps == MLX5_ARG_UNSET) 1213 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1214 MLX5_MPW_DISABLED; 1215 else 1216 config->mps = config->mps ? mps : MLX5_MPW_DISABLED; 1217 DRV_LOG(INFO, "%sMPS is %s", 1218 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 1219 config->mps == MLX5_MPW ? "legacy " : "", 1220 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1221 if (config->devx) { 1222 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); 1223 if (err) { 1224 err = -err; 1225 goto error; 1226 } 1227 /* Check relax ordering support. */ 1228 if (!haswell_broadwell_cpu) { 1229 sh->cmng.relaxed_ordering_write = 1230 config->hca_attr.relaxed_ordering_write; 1231 sh->cmng.relaxed_ordering_read = 1232 config->hca_attr.relaxed_ordering_read; 1233 } else { 1234 sh->cmng.relaxed_ordering_read = 0; 1235 sh->cmng.relaxed_ordering_write = 0; 1236 } 1237 sh->rq_ts_format = config->hca_attr.rq_ts_format; 1238 sh->sq_ts_format = config->hca_attr.sq_ts_format; 1239 sh->qp_ts_format = config->hca_attr.qp_ts_format; 1240 /* Check for LRO support. */ 1241 if (config->dest_tir && config->hca_attr.lro_cap && 1242 config->dv_flow_en) { 1243 /* TBD check tunnel lro caps. */ 1244 config->lro.supported = config->hca_attr.lro_cap; 1245 DRV_LOG(DEBUG, "Device supports LRO"); 1246 /* 1247 * If LRO timeout is not configured by application, 1248 * use the minimal supported value. 1249 */ 1250 if (!config->lro.timeout) 1251 config->lro.timeout = 1252 config->hca_attr.lro_timer_supported_periods[0]; 1253 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1254 config->lro.timeout); 1255 DRV_LOG(DEBUG, "LRO minimal size of TCP segment " 1256 "required for coalescing is %d bytes", 1257 config->hca_attr.lro_min_mss_size); 1258 } 1259 #if defined(HAVE_MLX5DV_DR) && \ 1260 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1261 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1262 if (config->hca_attr.qos.sup && 1263 config->hca_attr.qos.flow_meter_old && 1264 config->dv_flow_en) { 1265 uint8_t reg_c_mask = 1266 config->hca_attr.qos.flow_meter_reg_c_ids; 1267 /* 1268 * Meter needs two REG_C's for color match and pre-sfx 1269 * flow match. Here get the REG_C for color match. 1270 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1271 */ 1272 reg_c_mask &= 0xfc; 1273 if (__builtin_popcount(reg_c_mask) < 1) { 1274 priv->mtr_en = 0; 1275 DRV_LOG(WARNING, "No available register for" 1276 " meter."); 1277 } else { 1278 /* 1279 * The meter color register is used by the 1280 * flow-hit feature as well. 1281 * The flow-hit feature must use REG_C_3 1282 * Prefer REG_C_3 if it is available. 1283 */ 1284 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) 1285 priv->mtr_color_reg = REG_C_3; 1286 else 1287 priv->mtr_color_reg = ffs(reg_c_mask) 1288 - 1 + REG_C_0; 1289 priv->mtr_en = 1; 1290 priv->mtr_reg_share = 1291 config->hca_attr.qos.flow_meter; 1292 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 1293 priv->mtr_color_reg); 1294 } 1295 } 1296 if (config->hca_attr.qos.sup && 1297 config->hca_attr.qos.flow_meter_aso_sup) { 1298 uint32_t log_obj_size = 1299 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1); 1300 if (log_obj_size >= 1301 config->hca_attr.qos.log_meter_aso_granularity && 1302 log_obj_size <= 1303 config->hca_attr.qos.log_meter_aso_max_alloc) 1304 sh->meter_aso_en = 1; 1305 } 1306 if (priv->mtr_en) { 1307 err = mlx5_aso_flow_mtrs_mng_init(priv->sh); 1308 if (err) { 1309 err = -err; 1310 goto error; 1311 } 1312 } 1313 #endif 1314 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 1315 if (config->hca_attr.flow_hit_aso && 1316 priv->mtr_color_reg == REG_C_3) { 1317 sh->flow_hit_aso_en = 1; 1318 err = mlx5_flow_aso_age_mng_init(sh); 1319 if (err) { 1320 err = -err; 1321 goto error; 1322 } 1323 DRV_LOG(DEBUG, "Flow Hit ASO is supported."); 1324 } 1325 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 1326 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \ 1327 defined(HAVE_MLX5_DR_ACTION_ASO_CT) 1328 if (config->hca_attr.ct_offload && 1329 priv->mtr_color_reg == REG_C_3) { 1330 err = mlx5_flow_aso_ct_mng_init(sh); 1331 if (err) { 1332 err = -err; 1333 goto error; 1334 } 1335 DRV_LOG(DEBUG, "CT ASO is supported."); 1336 sh->ct_aso_en = 1; 1337 } 1338 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */ 1339 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE) 1340 if (config->hca_attr.log_max_ft_sampler_num > 0 && 1341 config->dv_flow_en) { 1342 priv->sampler_en = 1; 1343 DRV_LOG(DEBUG, "Sampler enabled!"); 1344 } else { 1345 priv->sampler_en = 0; 1346 if (!config->hca_attr.log_max_ft_sampler_num) 1347 DRV_LOG(WARNING, 1348 "No available register for sampler."); 1349 else 1350 DRV_LOG(DEBUG, "DV flow is not supported!"); 1351 } 1352 #endif 1353 } 1354 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && 1355 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { 1356 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); 1357 config->cqe_comp = 0; 1358 } 1359 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 1360 (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { 1361 DRV_LOG(WARNING, "Flow Tag CQE compression" 1362 " format isn't supported."); 1363 config->cqe_comp = 0; 1364 } 1365 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 1366 (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { 1367 DRV_LOG(WARNING, "L3/L4 Header CQE compression" 1368 " format isn't supported."); 1369 config->cqe_comp = 0; 1370 } 1371 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", 1372 config->cqe_comp ? "" : "not "); 1373 if (config->tx_pp) { 1374 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", 1375 config->hca_attr.dev_freq_khz); 1376 DRV_LOG(DEBUG, "Packet pacing is %ssupported", 1377 config->hca_attr.qos.packet_pacing ? "" : "not "); 1378 DRV_LOG(DEBUG, "Cross channel ops are %ssupported", 1379 config->hca_attr.cross_channel ? "" : "not "); 1380 DRV_LOG(DEBUG, "WQE index ignore is %ssupported", 1381 config->hca_attr.wqe_index_ignore ? "" : "not "); 1382 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported", 1383 config->hca_attr.non_wire_sq ? "" : "not "); 1384 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)", 1385 config->hca_attr.log_max_static_sq_wq ? "" : "not ", 1386 config->hca_attr.log_max_static_sq_wq); 1387 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported", 1388 config->hca_attr.qos.wqe_rate_pp ? "" : "not "); 1389 if (!config->devx) { 1390 DRV_LOG(ERR, "DevX is required for packet pacing"); 1391 err = ENODEV; 1392 goto error; 1393 } 1394 if (!config->hca_attr.qos.packet_pacing) { 1395 DRV_LOG(ERR, "Packet pacing is not supported"); 1396 err = ENODEV; 1397 goto error; 1398 } 1399 if (!config->hca_attr.cross_channel) { 1400 DRV_LOG(ERR, "Cross channel operations are" 1401 " required for packet pacing"); 1402 err = ENODEV; 1403 goto error; 1404 } 1405 if (!config->hca_attr.wqe_index_ignore) { 1406 DRV_LOG(ERR, "WQE index ignore feature is" 1407 " required for packet pacing"); 1408 err = ENODEV; 1409 goto error; 1410 } 1411 if (!config->hca_attr.non_wire_sq) { 1412 DRV_LOG(ERR, "Non-wire SQ feature is" 1413 " required for packet pacing"); 1414 err = ENODEV; 1415 goto error; 1416 } 1417 if (!config->hca_attr.log_max_static_sq_wq) { 1418 DRV_LOG(ERR, "Static WQE SQ feature is" 1419 " required for packet pacing"); 1420 err = ENODEV; 1421 goto error; 1422 } 1423 if (!config->hca_attr.qos.wqe_rate_pp) { 1424 DRV_LOG(ERR, "WQE rate mode is required" 1425 " for packet pacing"); 1426 err = ENODEV; 1427 goto error; 1428 } 1429 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1430 DRV_LOG(ERR, "DevX does not provide UAR offset," 1431 " can't create queues for packet pacing"); 1432 err = ENODEV; 1433 goto error; 1434 #endif 1435 } 1436 if (config->devx) { 1437 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; 1438 1439 err = config->hca_attr.access_register_user ? 1440 mlx5_devx_cmd_register_read 1441 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, 1442 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; 1443 if (!err) { 1444 uint32_t ts_mode; 1445 1446 /* MTUTC register is read successfully. */ 1447 ts_mode = MLX5_GET(register_mtutc, reg, 1448 time_stamp_mode); 1449 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1450 config->rt_timestamp = 1; 1451 } else { 1452 /* Kernel does not support register reading. */ 1453 if (config->hca_attr.dev_freq_khz == 1454 (NS_PER_S / MS_PER_S)) 1455 config->rt_timestamp = 1; 1456 } 1457 } 1458 /* 1459 * If HW has bug working with tunnel packet decapsulation and 1460 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip 1461 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1462 */ 1463 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en) 1464 config->hw_fcs_strip = 0; 1465 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1466 (config->hw_fcs_strip ? "" : "not ")); 1467 if (config->mprq.enabled && mprq) { 1468 if (config->mprq.stride_num_n && 1469 (config->mprq.stride_num_n > mprq_max_stride_num_n || 1470 config->mprq.stride_num_n < mprq_min_stride_num_n)) { 1471 config->mprq.stride_num_n = 1472 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1473 mprq_min_stride_num_n), 1474 mprq_max_stride_num_n); 1475 DRV_LOG(WARNING, 1476 "the number of strides" 1477 " for Multi-Packet RQ is out of range," 1478 " setting default value (%u)", 1479 1 << config->mprq.stride_num_n); 1480 } 1481 if (config->mprq.stride_size_n && 1482 (config->mprq.stride_size_n > mprq_max_stride_size_n || 1483 config->mprq.stride_size_n < mprq_min_stride_size_n)) { 1484 config->mprq.stride_size_n = 1485 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 1486 mprq_min_stride_size_n), 1487 mprq_max_stride_size_n); 1488 DRV_LOG(WARNING, 1489 "the size of a stride" 1490 " for Multi-Packet RQ is out of range," 1491 " setting default value (%u)", 1492 1 << config->mprq.stride_size_n); 1493 } 1494 config->mprq.min_stride_size_n = mprq_min_stride_size_n; 1495 config->mprq.max_stride_size_n = mprq_max_stride_size_n; 1496 } else if (config->mprq.enabled && !mprq) { 1497 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1498 config->mprq.enabled = 0; 1499 } 1500 if (config->max_dump_files_num == 0) 1501 config->max_dump_files_num = 128; 1502 eth_dev = rte_eth_dev_allocate(name); 1503 if (eth_dev == NULL) { 1504 DRV_LOG(ERR, "can not allocate rte ethdev"); 1505 err = ENOMEM; 1506 goto error; 1507 } 1508 if (priv->representor) { 1509 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1510 eth_dev->data->representor_id = priv->representor_id; 1511 } 1512 priv->mp_id.port_id = eth_dev->data->port_id; 1513 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 1514 /* 1515 * Store associated network device interface index. This index 1516 * is permanent throughout the lifetime of device. So, we may store 1517 * the ifindex here and use the cached value further. 1518 */ 1519 MLX5_ASSERT(spawn->ifindex); 1520 priv->if_index = spawn->ifindex; 1521 eth_dev->data->dev_private = priv; 1522 priv->dev_data = eth_dev->data; 1523 eth_dev->data->mac_addrs = priv->mac; 1524 eth_dev->device = dpdk_dev; 1525 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1526 /* Configure the first MAC address by default. */ 1527 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1528 DRV_LOG(ERR, 1529 "port %u cannot get MAC address, is mlx5_en" 1530 " loaded? (errno: %s)", 1531 eth_dev->data->port_id, strerror(rte_errno)); 1532 err = ENODEV; 1533 goto error; 1534 } 1535 DRV_LOG(INFO, 1536 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1537 eth_dev->data->port_id, 1538 mac.addr_bytes[0], mac.addr_bytes[1], 1539 mac.addr_bytes[2], mac.addr_bytes[3], 1540 mac.addr_bytes[4], mac.addr_bytes[5]); 1541 #ifdef RTE_LIBRTE_MLX5_DEBUG 1542 { 1543 char ifname[MLX5_NAMESIZE]; 1544 1545 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1546 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1547 eth_dev->data->port_id, ifname); 1548 else 1549 DRV_LOG(DEBUG, "port %u ifname is unknown", 1550 eth_dev->data->port_id); 1551 } 1552 #endif 1553 /* Get actual MTU if possible. */ 1554 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1555 if (err) { 1556 err = rte_errno; 1557 goto error; 1558 } 1559 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1560 priv->mtu); 1561 /* Initialize burst functions to prevent crashes before link-up. */ 1562 eth_dev->rx_pkt_burst = removed_rx_burst; 1563 eth_dev->tx_pkt_burst = removed_tx_burst; 1564 eth_dev->dev_ops = &mlx5_dev_ops; 1565 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; 1566 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; 1567 eth_dev->rx_queue_count = mlx5_rx_queue_count; 1568 /* Register MAC address. */ 1569 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1570 if (config->vf && config->vf_nl_en) 1571 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 1572 mlx5_ifindex(eth_dev), 1573 eth_dev->data->mac_addrs, 1574 MLX5_MAX_MAC_ADDRESSES); 1575 priv->flows = 0; 1576 priv->ctrl_flows = 0; 1577 rte_spinlock_init(&priv->flow_list_lock); 1578 TAILQ_INIT(&priv->flow_meters); 1579 TAILQ_INIT(&priv->flow_meter_profiles); 1580 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1581 mlx5_glue->dv_set_context_attr(sh->ctx, 1582 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1583 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 1584 .alloc = &mlx5_alloc_verbs_buf, 1585 .free = &mlx5_free_verbs_buf, 1586 .data = sh, 1587 })); 1588 /* Bring Ethernet device up. */ 1589 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1590 eth_dev->data->port_id); 1591 mlx5_set_link_up(eth_dev); 1592 /* 1593 * Even though the interrupt handler is not installed yet, 1594 * interrupts will still trigger on the async_fd from 1595 * Verbs context returned by ibv_open_device(). 1596 */ 1597 mlx5_link_update(eth_dev, 0); 1598 #ifdef HAVE_MLX5DV_DR_ESWITCH 1599 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en && 1600 (switch_info->representor || switch_info->master))) 1601 config->dv_esw_en = 0; 1602 #else 1603 config->dv_esw_en = 0; 1604 #endif 1605 /* Detect minimal data bytes to inline. */ 1606 mlx5_set_min_inline(spawn, config); 1607 /* Store device configuration on private structure. */ 1608 priv->config = *config; 1609 /* Create context for virtual machine VLAN workaround. */ 1610 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 1611 if (config->dv_flow_en) { 1612 err = mlx5_alloc_shared_dr(priv); 1613 if (err) 1614 goto error; 1615 } 1616 if (config->devx && config->dv_flow_en && config->dest_tir) { 1617 priv->obj_ops = devx_obj_ops; 1618 priv->obj_ops.drop_action_create = 1619 ibv_obj_ops.drop_action_create; 1620 priv->obj_ops.drop_action_destroy = 1621 ibv_obj_ops.drop_action_destroy; 1622 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET 1623 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; 1624 #else 1625 if (config->dv_esw_en) 1626 priv->obj_ops.txq_obj_modify = 1627 ibv_obj_ops.txq_obj_modify; 1628 #endif 1629 /* Use specific wrappers for Tx object. */ 1630 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; 1631 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; 1632 mlx5_queue_counter_id_prepare(eth_dev); 1633 1634 } else { 1635 priv->obj_ops = ibv_obj_ops; 1636 } 1637 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); 1638 if (!priv->drop_queue.hrxq) 1639 goto error; 1640 /* Supported Verbs flow priority number detection. */ 1641 err = mlx5_flow_discover_priorities(eth_dev); 1642 if (err < 0) { 1643 err = -err; 1644 goto error; 1645 } 1646 priv->config.flow_prio = err; 1647 if (!priv->config.dv_esw_en && 1648 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1649 DRV_LOG(WARNING, "metadata mode %u is not supported " 1650 "(no E-Switch)", priv->config.dv_xmeta_en); 1651 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1652 } 1653 mlx5_set_metadata_mask(eth_dev); 1654 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1655 !priv->sh->dv_regc0_mask) { 1656 DRV_LOG(ERR, "metadata mode %u is not supported " 1657 "(no metadata reg_c[0] is available)", 1658 priv->config.dv_xmeta_en); 1659 err = ENOTSUP; 1660 goto error; 1661 } 1662 mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, 1663 mlx5_hrxq_create_cb, 1664 mlx5_hrxq_match_cb, 1665 mlx5_hrxq_remove_cb); 1666 /* Query availability of metadata reg_c's. */ 1667 err = mlx5_flow_discover_mreg_c(eth_dev); 1668 if (err < 0) { 1669 err = -err; 1670 goto error; 1671 } 1672 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 1673 DRV_LOG(DEBUG, 1674 "port %u extensive metadata register is not supported", 1675 eth_dev->data->port_id); 1676 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1677 DRV_LOG(ERR, "metadata mode %u is not supported " 1678 "(no metadata registers available)", 1679 priv->config.dv_xmeta_en); 1680 err = ENOTSUP; 1681 goto error; 1682 } 1683 } 1684 if (priv->config.dv_flow_en && 1685 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1686 mlx5_flow_ext_mreg_supported(eth_dev) && 1687 priv->sh->dv_regc0_mask) { 1688 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 1689 MLX5_FLOW_MREG_HTABLE_SZ, 1690 0, 0, 1691 flow_dv_mreg_create_cb, 1692 flow_dv_mreg_match_cb, 1693 flow_dv_mreg_remove_cb); 1694 if (!priv->mreg_cp_tbl) { 1695 err = ENOMEM; 1696 goto error; 1697 } 1698 priv->mreg_cp_tbl->ctx = eth_dev; 1699 } 1700 rte_spinlock_init(&priv->shared_act_sl); 1701 mlx5_flow_counter_mode_config(eth_dev); 1702 if (priv->config.dv_flow_en) 1703 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 1704 return eth_dev; 1705 error: 1706 if (priv) { 1707 if (priv->mreg_cp_tbl) 1708 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1709 if (priv->sh) 1710 mlx5_os_free_shared_dr(priv); 1711 if (priv->nl_socket_route >= 0) 1712 close(priv->nl_socket_route); 1713 if (priv->nl_socket_rdma >= 0) 1714 close(priv->nl_socket_rdma); 1715 if (priv->vmwa_context) 1716 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1717 if (eth_dev && priv->drop_queue.hrxq) 1718 mlx5_drop_action_destroy(eth_dev); 1719 if (own_domain_id) 1720 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1721 mlx5_cache_list_destroy(&priv->hrxqs); 1722 mlx5_free(priv); 1723 if (eth_dev != NULL) 1724 eth_dev->data->dev_private = NULL; 1725 } 1726 if (eth_dev != NULL) { 1727 /* mac_addrs must not be freed alone because part of 1728 * dev_private 1729 **/ 1730 eth_dev->data->mac_addrs = NULL; 1731 rte_eth_dev_release_port(eth_dev); 1732 } 1733 if (sh) 1734 mlx5_free_shared_dev_ctx(sh); 1735 MLX5_ASSERT(err > 0); 1736 rte_errno = err; 1737 return NULL; 1738 } 1739 1740 /** 1741 * Comparison callback to sort device data. 1742 * 1743 * This is meant to be used with qsort(). 1744 * 1745 * @param a[in] 1746 * Pointer to pointer to first data object. 1747 * @param b[in] 1748 * Pointer to pointer to second data object. 1749 * 1750 * @return 1751 * 0 if both objects are equal, less than 0 if the first argument is less 1752 * than the second, greater than 0 otherwise. 1753 */ 1754 static int 1755 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1756 { 1757 const struct mlx5_switch_info *si_a = 1758 &((const struct mlx5_dev_spawn_data *)a)->info; 1759 const struct mlx5_switch_info *si_b = 1760 &((const struct mlx5_dev_spawn_data *)b)->info; 1761 int ret; 1762 1763 /* Master device first. */ 1764 ret = si_b->master - si_a->master; 1765 if (ret) 1766 return ret; 1767 /* Then representor devices. */ 1768 ret = si_b->representor - si_a->representor; 1769 if (ret) 1770 return ret; 1771 /* Unidentified devices come last in no specific order. */ 1772 if (!si_a->representor) 1773 return 0; 1774 /* Order representors by name. */ 1775 return si_a->port_name - si_b->port_name; 1776 } 1777 1778 /** 1779 * Match PCI information for possible slaves of bonding device. 1780 * 1781 * @param[in] ibv_dev 1782 * Pointer to Infiniband device structure. 1783 * @param[in] pci_dev 1784 * Pointer to primary PCI address structure to match. 1785 * @param[in] nl_rdma 1786 * Netlink RDMA group socket handle. 1787 * @param[in] owner 1788 * Rerepsentor owner PF index. 1789 * @param[out] bond_info 1790 * Pointer to bonding information. 1791 * 1792 * @return 1793 * negative value if no bonding device found, otherwise 1794 * positive index of slave PF in bonding. 1795 */ 1796 static int 1797 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 1798 const struct rte_pci_addr *pci_dev, 1799 int nl_rdma, uint16_t owner, 1800 struct mlx5_bond_info *bond_info) 1801 { 1802 char ifname[IF_NAMESIZE + 1]; 1803 unsigned int ifindex; 1804 unsigned int np, i; 1805 FILE *bond_file = NULL, *file; 1806 int pf = -1; 1807 int ret; 1808 1809 /* 1810 * Try to get master device name. If something goes 1811 * wrong suppose the lack of kernel support and no 1812 * bonding devices. 1813 */ 1814 memset(bond_info, 0, sizeof(*bond_info)); 1815 if (nl_rdma < 0) 1816 return -1; 1817 if (!strstr(ibv_dev->name, "bond")) 1818 return -1; 1819 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 1820 if (!np) 1821 return -1; 1822 /* 1823 * The Master device might not be on the predefined 1824 * port (not on port index 1, it is not garanted), 1825 * we have to scan all Infiniband device port and 1826 * find master. 1827 */ 1828 for (i = 1; i <= np; ++i) { 1829 /* Check whether Infiniband port is populated. */ 1830 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 1831 if (!ifindex) 1832 continue; 1833 if (!if_indextoname(ifindex, ifname)) 1834 continue; 1835 /* Try to read bonding slave names from sysfs. */ 1836 MKSTR(slaves, 1837 "/sys/class/net/%s/master/bonding/slaves", ifname); 1838 bond_file = fopen(slaves, "r"); 1839 if (bond_file) 1840 break; 1841 } 1842 if (!bond_file) 1843 return -1; 1844 /* Use safe format to check maximal buffer length. */ 1845 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 1846 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 1847 char tmp_str[IF_NAMESIZE + 32]; 1848 struct rte_pci_addr pci_addr; 1849 struct mlx5_switch_info info; 1850 1851 /* Process slave interface names in the loop. */ 1852 snprintf(tmp_str, sizeof(tmp_str), 1853 "/sys/class/net/%s", ifname); 1854 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 1855 DRV_LOG(WARNING, "can not get PCI address" 1856 " for netdev \"%s\"", ifname); 1857 continue; 1858 } 1859 /* Slave interface PCI address match found. */ 1860 snprintf(tmp_str, sizeof(tmp_str), 1861 "/sys/class/net/%s/phys_port_name", ifname); 1862 file = fopen(tmp_str, "rb"); 1863 if (!file) 1864 break; 1865 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 1866 if (fscanf(file, "%32s", tmp_str) == 1) 1867 mlx5_translate_port_name(tmp_str, &info); 1868 fclose(file); 1869 /* Only process PF ports. */ 1870 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY && 1871 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 1872 continue; 1873 /* Check max bonding member. */ 1874 if (info.port_name >= MLX5_BOND_MAX_PORTS) { 1875 DRV_LOG(WARNING, "bonding index out of range, " 1876 "please increase MLX5_BOND_MAX_PORTS: %s", 1877 tmp_str); 1878 break; 1879 } 1880 /* Match PCI address. */ 1881 if (pci_dev->domain == pci_addr.domain && 1882 pci_dev->bus == pci_addr.bus && 1883 pci_dev->devid == pci_addr.devid && 1884 pci_dev->function + owner == pci_addr.function) 1885 pf = info.port_name; 1886 /* Get ifindex. */ 1887 snprintf(tmp_str, sizeof(tmp_str), 1888 "/sys/class/net/%s/ifindex", ifname); 1889 file = fopen(tmp_str, "rb"); 1890 if (!file) 1891 break; 1892 ret = fscanf(file, "%u", &ifindex); 1893 fclose(file); 1894 if (ret != 1) 1895 break; 1896 /* Save bonding info. */ 1897 strncpy(bond_info->ports[info.port_name].ifname, ifname, 1898 sizeof(bond_info->ports[0].ifname)); 1899 bond_info->ports[info.port_name].pci_addr = pci_addr; 1900 bond_info->ports[info.port_name].ifindex = ifindex; 1901 bond_info->n_port++; 1902 } 1903 if (pf >= 0) { 1904 /* Get bond interface info */ 1905 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex, 1906 bond_info->ifname); 1907 if (ret) 1908 DRV_LOG(ERR, "unable to get bond info: %s", 1909 strerror(rte_errno)); 1910 else 1911 DRV_LOG(INFO, "PF device %u, bond device %u(%s)", 1912 ifindex, bond_info->ifindex, bond_info->ifname); 1913 } 1914 return pf; 1915 } 1916 1917 /** 1918 * Register a PCI device within bonding. 1919 * 1920 * This function spawns Ethernet devices out of a given PCI device and 1921 * bonding owner PF index. 1922 * 1923 * @param[in] pci_dev 1924 * PCI device information. 1925 * @param[in] req_eth_da 1926 * Requested ethdev device argument. 1927 * @param[in] owner_id 1928 * Requested owner PF port ID within bonding device, default to 0. 1929 * 1930 * @return 1931 * 0 on success, a negative errno value otherwise and rte_errno is set. 1932 */ 1933 static int 1934 mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, 1935 struct rte_eth_devargs *req_eth_da, 1936 uint16_t owner_id) 1937 { 1938 struct ibv_device **ibv_list; 1939 /* 1940 * Number of found IB Devices matching with requested PCI BDF. 1941 * nd != 1 means there are multiple IB devices over the same 1942 * PCI device and we have representors and master. 1943 */ 1944 unsigned int nd = 0; 1945 /* 1946 * Number of found IB device Ports. nd = 1 and np = 1..n means 1947 * we have the single multiport IB device, and there may be 1948 * representors attached to some of found ports. 1949 */ 1950 unsigned int np = 0; 1951 /* 1952 * Number of DPDK ethernet devices to Spawn - either over 1953 * multiple IB devices or multiple ports of single IB device. 1954 * Actually this is the number of iterations to spawn. 1955 */ 1956 unsigned int ns = 0; 1957 /* 1958 * Bonding device 1959 * < 0 - no bonding device (single one) 1960 * >= 0 - bonding device (value is slave PF index) 1961 */ 1962 int bd = -1; 1963 struct mlx5_dev_spawn_data *list = NULL; 1964 struct mlx5_dev_config dev_config; 1965 unsigned int dev_config_vf; 1966 struct rte_eth_devargs eth_da = *req_eth_da; 1967 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */ 1968 struct mlx5_bond_info bond_info; 1969 int ret = -1; 1970 1971 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1972 mlx5_pmd_socket_init(); 1973 ret = mlx5_init_once(); 1974 if (ret) { 1975 DRV_LOG(ERR, "unable to init PMD global data: %s", 1976 strerror(rte_errno)); 1977 return -rte_errno; 1978 } 1979 errno = 0; 1980 ibv_list = mlx5_glue->get_device_list(&ret); 1981 if (!ibv_list) { 1982 rte_errno = errno ? errno : ENOSYS; 1983 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1984 return -rte_errno; 1985 } 1986 /* 1987 * First scan the list of all Infiniband devices to find 1988 * matching ones, gathering into the list. 1989 */ 1990 struct ibv_device *ibv_match[ret + 1]; 1991 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 1992 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1993 unsigned int i; 1994 1995 while (ret-- > 0) { 1996 struct rte_pci_addr pci_addr; 1997 1998 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1999 bd = mlx5_device_bond_pci_match 2000 (ibv_list[ret], &owner_pci, nl_rdma, owner_id, 2001 &bond_info); 2002 if (bd >= 0) { 2003 /* 2004 * Bonding device detected. Only one match is allowed, 2005 * the bonding is supported over multi-port IB device, 2006 * there should be no matches on representor PCI 2007 * functions or non VF LAG bonding devices with 2008 * specified address. 2009 */ 2010 if (nd) { 2011 DRV_LOG(ERR, 2012 "multiple PCI match on bonding device" 2013 "\"%s\" found", ibv_list[ret]->name); 2014 rte_errno = ENOENT; 2015 ret = -rte_errno; 2016 goto exit; 2017 } 2018 /* Amend owner pci address if owner PF ID specified. */ 2019 if (eth_da.nb_representor_ports) 2020 owner_pci.function += owner_id; 2021 DRV_LOG(INFO, "PCI information matches for" 2022 " slave %d bonding device \"%s\"", 2023 bd, ibv_list[ret]->name); 2024 ibv_match[nd++] = ibv_list[ret]; 2025 break; 2026 } else { 2027 /* Bonding device not found. */ 2028 if (mlx5_dev_to_pci_addr 2029 (ibv_list[ret]->ibdev_path, &pci_addr)) 2030 continue; 2031 if (owner_pci.domain != pci_addr.domain || 2032 owner_pci.bus != pci_addr.bus || 2033 owner_pci.devid != pci_addr.devid || 2034 owner_pci.function != pci_addr.function) 2035 continue; 2036 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2037 ibv_list[ret]->name); 2038 ibv_match[nd++] = ibv_list[ret]; 2039 } 2040 } 2041 ibv_match[nd] = NULL; 2042 if (!nd) { 2043 /* No device matches, just complain and bail out. */ 2044 DRV_LOG(WARNING, 2045 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2046 " are kernel drivers loaded?", 2047 owner_pci.domain, owner_pci.bus, 2048 owner_pci.devid, owner_pci.function); 2049 rte_errno = ENOENT; 2050 ret = -rte_errno; 2051 goto exit; 2052 } 2053 if (nd == 1) { 2054 /* 2055 * Found single matching device may have multiple ports. 2056 * Each port may be representor, we have to check the port 2057 * number and check the representors existence. 2058 */ 2059 if (nl_rdma >= 0) 2060 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2061 if (!np) 2062 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2063 " ports number", ibv_match[0]->name); 2064 if (bd >= 0 && !np) { 2065 DRV_LOG(ERR, "can not get ports" 2066 " for bonding device"); 2067 rte_errno = ENOENT; 2068 ret = -rte_errno; 2069 goto exit; 2070 } 2071 } 2072 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 2073 if (bd >= 0) { 2074 /* 2075 * This may happen if there is VF LAG kernel support and 2076 * application is compiled with older rdma_core library. 2077 */ 2078 DRV_LOG(ERR, 2079 "No kernel/verbs support for VF LAG bonding found."); 2080 rte_errno = ENOTSUP; 2081 ret = -rte_errno; 2082 goto exit; 2083 } 2084 #endif 2085 /* 2086 * Now we can determine the maximal 2087 * amount of devices to be spawned. 2088 */ 2089 list = mlx5_malloc(MLX5_MEM_ZERO, 2090 sizeof(struct mlx5_dev_spawn_data) * 2091 (np ? np : nd), 2092 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2093 if (!list) { 2094 DRV_LOG(ERR, "spawn data array allocation failure"); 2095 rte_errno = ENOMEM; 2096 ret = -rte_errno; 2097 goto exit; 2098 } 2099 if (bd >= 0 || np > 1) { 2100 /* 2101 * Single IB device with multiple ports found, 2102 * it may be E-Switch master device and representors. 2103 * We have to perform identification through the ports. 2104 */ 2105 MLX5_ASSERT(nl_rdma >= 0); 2106 MLX5_ASSERT(ns == 0); 2107 MLX5_ASSERT(nd == 1); 2108 MLX5_ASSERT(np); 2109 for (i = 1; i <= np; ++i) { 2110 list[ns].bond_info = &bond_info; 2111 list[ns].max_port = np; 2112 list[ns].phys_port = i; 2113 list[ns].phys_dev = ibv_match[0]; 2114 list[ns].eth_dev = NULL; 2115 list[ns].pci_dev = pci_dev; 2116 list[ns].pf_bond = bd; 2117 list[ns].ifindex = mlx5_nl_ifindex 2118 (nl_rdma, 2119 mlx5_os_get_dev_device_name 2120 (list[ns].phys_dev), i); 2121 if (!list[ns].ifindex) { 2122 /* 2123 * No network interface index found for the 2124 * specified port, it means there is no 2125 * representor on this port. It's OK, 2126 * there can be disabled ports, for example 2127 * if sriov_numvfs < sriov_totalvfs. 2128 */ 2129 continue; 2130 } 2131 ret = -1; 2132 if (nl_route >= 0) 2133 ret = mlx5_nl_switch_info 2134 (nl_route, 2135 list[ns].ifindex, 2136 &list[ns].info); 2137 if (ret || (!list[ns].info.representor && 2138 !list[ns].info.master)) { 2139 /* 2140 * We failed to recognize representors with 2141 * Netlink, let's try to perform the task 2142 * with sysfs. 2143 */ 2144 ret = mlx5_sysfs_switch_info 2145 (list[ns].ifindex, 2146 &list[ns].info); 2147 } 2148 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2149 if (!ret && bd >= 0) { 2150 switch (list[ns].info.name_type) { 2151 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 2152 if (list[ns].info.port_name == bd) 2153 ns++; 2154 break; 2155 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 2156 /* Fallthrough */ 2157 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 2158 /* Fallthrough */ 2159 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 2160 if (list[ns].info.pf_num == bd) 2161 ns++; 2162 break; 2163 default: 2164 break; 2165 } 2166 continue; 2167 } 2168 #endif 2169 if (!ret && (list[ns].info.representor ^ 2170 list[ns].info.master)) 2171 ns++; 2172 } 2173 if (!ns) { 2174 DRV_LOG(ERR, 2175 "unable to recognize master/representors" 2176 " on the IB device with multiple ports"); 2177 rte_errno = ENOENT; 2178 ret = -rte_errno; 2179 goto exit; 2180 } 2181 } else { 2182 /* 2183 * The existence of several matching entries (nd > 1) means 2184 * port representors have been instantiated. No existing Verbs 2185 * call nor sysfs entries can tell them apart, this can only 2186 * be done through Netlink calls assuming kernel drivers are 2187 * recent enough to support them. 2188 * 2189 * In the event of identification failure through Netlink, 2190 * try again through sysfs, then: 2191 * 2192 * 1. A single IB device matches (nd == 1) with single 2193 * port (np=0/1) and is not a representor, assume 2194 * no switch support. 2195 * 2196 * 2. Otherwise no safe assumptions can be made; 2197 * complain louder and bail out. 2198 */ 2199 for (i = 0; i != nd; ++i) { 2200 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2201 list[ns].bond_info = NULL; 2202 list[ns].max_port = 1; 2203 list[ns].phys_port = 1; 2204 list[ns].phys_dev = ibv_match[i]; 2205 list[ns].eth_dev = NULL; 2206 list[ns].pci_dev = pci_dev; 2207 list[ns].pf_bond = -1; 2208 list[ns].ifindex = 0; 2209 if (nl_rdma >= 0) 2210 list[ns].ifindex = mlx5_nl_ifindex 2211 (nl_rdma, 2212 mlx5_os_get_dev_device_name 2213 (list[ns].phys_dev), 1); 2214 if (!list[ns].ifindex) { 2215 char ifname[IF_NAMESIZE]; 2216 2217 /* 2218 * Netlink failed, it may happen with old 2219 * ib_core kernel driver (before 4.16). 2220 * We can assume there is old driver because 2221 * here we are processing single ports IB 2222 * devices. Let's try sysfs to retrieve 2223 * the ifindex. The method works for 2224 * master device only. 2225 */ 2226 if (nd > 1) { 2227 /* 2228 * Multiple devices found, assume 2229 * representors, can not distinguish 2230 * master/representor and retrieve 2231 * ifindex via sysfs. 2232 */ 2233 continue; 2234 } 2235 ret = mlx5_get_ifname_sysfs 2236 (ibv_match[i]->ibdev_path, ifname); 2237 if (!ret) 2238 list[ns].ifindex = 2239 if_nametoindex(ifname); 2240 if (!list[ns].ifindex) { 2241 /* 2242 * No network interface index found 2243 * for the specified device, it means 2244 * there it is neither representor 2245 * nor master. 2246 */ 2247 continue; 2248 } 2249 } 2250 ret = -1; 2251 if (nl_route >= 0) 2252 ret = mlx5_nl_switch_info 2253 (nl_route, 2254 list[ns].ifindex, 2255 &list[ns].info); 2256 if (ret || (!list[ns].info.representor && 2257 !list[ns].info.master)) { 2258 /* 2259 * We failed to recognize representors with 2260 * Netlink, let's try to perform the task 2261 * with sysfs. 2262 */ 2263 ret = mlx5_sysfs_switch_info 2264 (list[ns].ifindex, 2265 &list[ns].info); 2266 } 2267 if (!ret && (list[ns].info.representor ^ 2268 list[ns].info.master)) { 2269 ns++; 2270 } else if ((nd == 1) && 2271 !list[ns].info.representor && 2272 !list[ns].info.master) { 2273 /* 2274 * Single IB device with 2275 * one physical port and 2276 * attached network device. 2277 * May be SRIOV is not enabled 2278 * or there is no representors. 2279 */ 2280 DRV_LOG(INFO, "no E-Switch support detected"); 2281 ns++; 2282 break; 2283 } 2284 } 2285 if (!ns) { 2286 DRV_LOG(ERR, 2287 "unable to recognize master/representors" 2288 " on the multiple IB devices"); 2289 rte_errno = ENOENT; 2290 ret = -rte_errno; 2291 goto exit; 2292 } 2293 } 2294 MLX5_ASSERT(ns); 2295 /* 2296 * Sort list to probe devices in natural order for users convenience 2297 * (i.e. master first, then representors from lowest to highest ID). 2298 */ 2299 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2300 /* Device specific configuration. */ 2301 switch (pci_dev->id.device_id) { 2302 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2303 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2304 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2305 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2306 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 2307 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 2308 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: 2309 dev_config_vf = 1; 2310 break; 2311 default: 2312 dev_config_vf = 0; 2313 break; 2314 } 2315 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) { 2316 /* Set devargs default values. */ 2317 if (eth_da.nb_mh_controllers == 0) { 2318 eth_da.nb_mh_controllers = 1; 2319 eth_da.mh_controllers[0] = 0; 2320 } 2321 if (eth_da.nb_ports == 0 && ns > 0) { 2322 if (list[0].pf_bond >= 0 && list[0].info.representor) 2323 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s", 2324 pci_dev->device.devargs->args); 2325 eth_da.nb_ports = 1; 2326 eth_da.ports[0] = list[0].info.pf_num; 2327 } 2328 if (eth_da.nb_representor_ports == 0) { 2329 eth_da.nb_representor_ports = 1; 2330 eth_da.representor_ports[0] = 0; 2331 } 2332 } 2333 for (i = 0; i != ns; ++i) { 2334 uint32_t restore; 2335 2336 /* Default configuration. */ 2337 memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); 2338 dev_config.vf = dev_config_vf; 2339 dev_config.mps = MLX5_ARG_UNSET; 2340 dev_config.dbnc = MLX5_ARG_UNSET; 2341 dev_config.rx_vec_en = 1; 2342 dev_config.txq_inline_max = MLX5_ARG_UNSET; 2343 dev_config.txq_inline_min = MLX5_ARG_UNSET; 2344 dev_config.txq_inline_mpw = MLX5_ARG_UNSET; 2345 dev_config.txqs_inline = MLX5_ARG_UNSET; 2346 dev_config.vf_nl_en = 1; 2347 dev_config.mr_ext_memseg_en = 1; 2348 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2349 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2350 dev_config.dv_esw_en = 1; 2351 dev_config.dv_flow_en = 1; 2352 dev_config.decap_en = 1; 2353 dev_config.log_hp_size = MLX5_ARG_UNSET; 2354 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2355 &list[i], 2356 &dev_config, 2357 ð_da); 2358 if (!list[i].eth_dev) { 2359 if (rte_errno != EBUSY && rte_errno != EEXIST) 2360 break; 2361 /* Device is disabled or already spawned. Ignore it. */ 2362 continue; 2363 } 2364 restore = list[i].eth_dev->data->dev_flags; 2365 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2366 /* Restore non-PCI flags cleared by the above call. */ 2367 list[i].eth_dev->data->dev_flags |= restore; 2368 rte_eth_dev_probing_finish(list[i].eth_dev); 2369 } 2370 if (i != ns) { 2371 DRV_LOG(ERR, 2372 "probe of PCI device " PCI_PRI_FMT " aborted after" 2373 " encountering an error: %s", 2374 owner_pci.domain, owner_pci.bus, 2375 owner_pci.devid, owner_pci.function, 2376 strerror(rte_errno)); 2377 ret = -rte_errno; 2378 /* Roll back. */ 2379 while (i--) { 2380 if (!list[i].eth_dev) 2381 continue; 2382 mlx5_dev_close(list[i].eth_dev); 2383 /* mac_addrs must not be freed because in dev_private */ 2384 list[i].eth_dev->data->mac_addrs = NULL; 2385 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2386 } 2387 /* Restore original error. */ 2388 rte_errno = -ret; 2389 } else { 2390 ret = 0; 2391 } 2392 exit: 2393 /* 2394 * Do the routine cleanup: 2395 * - close opened Netlink sockets 2396 * - free allocated spawn data array 2397 * - free the Infiniband device list 2398 */ 2399 if (nl_rdma >= 0) 2400 close(nl_rdma); 2401 if (nl_route >= 0) 2402 close(nl_route); 2403 if (list) 2404 mlx5_free(list); 2405 MLX5_ASSERT(ibv_list); 2406 mlx5_glue->free_device_list(ibv_list); 2407 return ret; 2408 } 2409 2410 /** 2411 * DPDK callback to register a PCI device. 2412 * 2413 * This function spawns Ethernet devices out of a given PCI device. 2414 * 2415 * @param[in] pci_drv 2416 * PCI driver structure (mlx5_driver). 2417 * @param[in] pci_dev 2418 * PCI device information. 2419 * 2420 * @return 2421 * 0 on success, a negative errno value otherwise and rte_errno is set. 2422 */ 2423 int 2424 mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2425 struct rte_pci_device *pci_dev) 2426 { 2427 struct rte_eth_devargs eth_da = { .type = RTE_ETH_REPRESENTOR_NONE }; 2428 int ret = 0; 2429 uint16_t p; 2430 2431 if (pci_dev->device.devargs) { 2432 /* Parse representor information from device argument. */ 2433 if (pci_dev->device.devargs->cls_str) 2434 ret = rte_eth_devargs_parse 2435 (pci_dev->device.devargs->cls_str, ð_da); 2436 if (ret) { 2437 DRV_LOG(ERR, "failed to parse device arguments: %s", 2438 pci_dev->device.devargs->cls_str); 2439 return -rte_errno; 2440 } 2441 if (eth_da.type == RTE_ETH_REPRESENTOR_NONE) { 2442 /* Support legacy device argument */ 2443 ret = rte_eth_devargs_parse 2444 (pci_dev->device.devargs->args, ð_da); 2445 if (ret) { 2446 DRV_LOG(ERR, "failed to parse device arguments: %s", 2447 pci_dev->device.devargs->args); 2448 return -rte_errno; 2449 } 2450 } 2451 } 2452 2453 if (eth_da.nb_ports > 0) { 2454 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */ 2455 for (p = 0; p < eth_da.nb_ports; p++) 2456 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 2457 eth_da.ports[p]); 2458 } else { 2459 ret = mlx5_os_pci_probe_pf(pci_dev, ð_da, 0); 2460 } 2461 return ret; 2462 } 2463 2464 static int 2465 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 2466 { 2467 char *env; 2468 int value; 2469 2470 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2471 /* Get environment variable to store. */ 2472 env = getenv(MLX5_SHUT_UP_BF); 2473 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 2474 if (config->dbnc == MLX5_ARG_UNSET) 2475 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 2476 else 2477 setenv(MLX5_SHUT_UP_BF, 2478 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 2479 return value; 2480 } 2481 2482 static void 2483 mlx5_restore_doorbell_mapping_env(int value) 2484 { 2485 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2486 /* Restore the original environment variable state. */ 2487 if (value == MLX5_ARG_UNSET) 2488 unsetenv(MLX5_SHUT_UP_BF); 2489 else 2490 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 2491 } 2492 2493 /** 2494 * Extract pdn of PD object using DV API. 2495 * 2496 * @param[in] pd 2497 * Pointer to the verbs PD object. 2498 * @param[out] pdn 2499 * Pointer to the PD object number variable. 2500 * 2501 * @return 2502 * 0 on success, error value otherwise. 2503 */ 2504 int 2505 mlx5_os_get_pdn(void *pd, uint32_t *pdn) 2506 { 2507 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2508 struct mlx5dv_obj obj; 2509 struct mlx5dv_pd pd_info; 2510 int ret = 0; 2511 2512 obj.pd.in = pd; 2513 obj.pd.out = &pd_info; 2514 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 2515 if (ret) { 2516 DRV_LOG(DEBUG, "Fail to get PD object info"); 2517 return ret; 2518 } 2519 *pdn = pd_info.pdn; 2520 return 0; 2521 #else 2522 (void)pd; 2523 (void)pdn; 2524 return -ENOTSUP; 2525 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 2526 } 2527 2528 /** 2529 * Function API to open IB device. 2530 * 2531 * This function calls the Linux glue APIs to open a device. 2532 * 2533 * @param[in] spawn 2534 * Pointer to the IB device attributes (name, port, etc). 2535 * @param[out] config 2536 * Pointer to device configuration structure. 2537 * @param[out] sh 2538 * Pointer to shared context structure. 2539 * 2540 * @return 2541 * 0 on success, a positive error value otherwise. 2542 */ 2543 int 2544 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 2545 const struct mlx5_dev_config *config, 2546 struct mlx5_dev_ctx_shared *sh) 2547 { 2548 int dbmap_env; 2549 int err = 0; 2550 2551 sh->numa_node = spawn->pci_dev->device.numa_node; 2552 pthread_mutex_init(&sh->txpp.mutex, NULL); 2553 /* 2554 * Configure environment variable "MLX5_BF_SHUT_UP" 2555 * before the device creation. The rdma_core library 2556 * checks the variable at device creation and 2557 * stores the result internally. 2558 */ 2559 dbmap_env = mlx5_config_doorbell_mapping_env(config); 2560 /* Try to open IB device with DV first, then usual Verbs. */ 2561 errno = 0; 2562 sh->ctx = mlx5_glue->dv_open_device(spawn->phys_dev); 2563 if (sh->ctx) { 2564 sh->devx = 1; 2565 DRV_LOG(DEBUG, "DevX is supported"); 2566 /* The device is created, no need for environment. */ 2567 mlx5_restore_doorbell_mapping_env(dbmap_env); 2568 } else { 2569 /* The environment variable is still configured. */ 2570 sh->ctx = mlx5_glue->open_device(spawn->phys_dev); 2571 err = errno ? errno : ENODEV; 2572 /* 2573 * The environment variable is not needed anymore, 2574 * all device creation attempts are completed. 2575 */ 2576 mlx5_restore_doorbell_mapping_env(dbmap_env); 2577 if (!sh->ctx) 2578 return err; 2579 DRV_LOG(DEBUG, "DevX is NOT supported"); 2580 err = 0; 2581 } 2582 if (!err && sh->ctx) { 2583 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2584 mlx5_glue->dv_set_context_attr(sh->ctx, 2585 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2586 (void *)((uintptr_t)&(struct mlx5dv_ctx_allocators){ 2587 .alloc = &mlx5_alloc_verbs_buf, 2588 .free = &mlx5_free_verbs_buf, 2589 .data = sh, 2590 })); 2591 } 2592 return err; 2593 } 2594 2595 /** 2596 * Install shared asynchronous device events handler. 2597 * This function is implemented to support event sharing 2598 * between multiple ports of single IB device. 2599 * 2600 * @param sh 2601 * Pointer to mlx5_dev_ctx_shared object. 2602 */ 2603 void 2604 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) 2605 { 2606 int ret; 2607 int flags; 2608 2609 sh->intr_handle.fd = -1; 2610 flags = fcntl(((struct ibv_context *)sh->ctx)->async_fd, F_GETFL); 2611 ret = fcntl(((struct ibv_context *)sh->ctx)->async_fd, 2612 F_SETFL, flags | O_NONBLOCK); 2613 if (ret) { 2614 DRV_LOG(INFO, "failed to change file descriptor async event" 2615 " queue"); 2616 } else { 2617 sh->intr_handle.fd = ((struct ibv_context *)sh->ctx)->async_fd; 2618 sh->intr_handle.type = RTE_INTR_HANDLE_EXT; 2619 if (rte_intr_callback_register(&sh->intr_handle, 2620 mlx5_dev_interrupt_handler, sh)) { 2621 DRV_LOG(INFO, "Fail to install the shared interrupt."); 2622 sh->intr_handle.fd = -1; 2623 } 2624 } 2625 if (sh->devx) { 2626 #ifdef HAVE_IBV_DEVX_ASYNC 2627 sh->intr_handle_devx.fd = -1; 2628 sh->devx_comp = 2629 (void *)mlx5_glue->devx_create_cmd_comp(sh->ctx); 2630 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp; 2631 if (!devx_comp) { 2632 DRV_LOG(INFO, "failed to allocate devx_comp."); 2633 return; 2634 } 2635 flags = fcntl(devx_comp->fd, F_GETFL); 2636 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK); 2637 if (ret) { 2638 DRV_LOG(INFO, "failed to change file descriptor" 2639 " devx comp"); 2640 return; 2641 } 2642 sh->intr_handle_devx.fd = devx_comp->fd; 2643 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT; 2644 if (rte_intr_callback_register(&sh->intr_handle_devx, 2645 mlx5_dev_interrupt_handler_devx, sh)) { 2646 DRV_LOG(INFO, "Fail to install the devx shared" 2647 " interrupt."); 2648 sh->intr_handle_devx.fd = -1; 2649 } 2650 #endif /* HAVE_IBV_DEVX_ASYNC */ 2651 } 2652 } 2653 2654 /** 2655 * Uninstall shared asynchronous device events handler. 2656 * This function is implemented to support event sharing 2657 * between multiple ports of single IB device. 2658 * 2659 * @param dev 2660 * Pointer to mlx5_dev_ctx_shared object. 2661 */ 2662 void 2663 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh) 2664 { 2665 if (sh->intr_handle.fd >= 0) 2666 mlx5_intr_callback_unregister(&sh->intr_handle, 2667 mlx5_dev_interrupt_handler, sh); 2668 #ifdef HAVE_IBV_DEVX_ASYNC 2669 if (sh->intr_handle_devx.fd >= 0) 2670 rte_intr_callback_unregister(&sh->intr_handle_devx, 2671 mlx5_dev_interrupt_handler_devx, sh); 2672 if (sh->devx_comp) 2673 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp); 2674 #endif 2675 } 2676 2677 /** 2678 * Read statistics by a named counter. 2679 * 2680 * @param[in] priv 2681 * Pointer to the private device data structure. 2682 * @param[in] ctr_name 2683 * Pointer to the name of the statistic counter to read 2684 * @param[out] stat 2685 * Pointer to read statistic value. 2686 * @return 2687 * 0 on success and stat is valud, 1 if failed to read the value 2688 * rte_errno is set. 2689 * 2690 */ 2691 int 2692 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name, 2693 uint64_t *stat) 2694 { 2695 int fd; 2696 2697 if (priv->sh) { 2698 if (priv->q_counters != NULL && 2699 strcmp(ctr_name, "out_of_buffer") == 0) 2700 return mlx5_devx_cmd_queue_counter_query(priv->sh->ctx, 2701 0, (uint32_t *)stat); 2702 MKSTR(path, "%s/ports/%d/hw_counters/%s", 2703 priv->sh->ibdev_path, 2704 priv->dev_port, 2705 ctr_name); 2706 fd = open(path, O_RDONLY); 2707 /* 2708 * in switchdev the file location is not per port 2709 * but rather in <ibdev_path>/hw_counters/<file_name>. 2710 */ 2711 if (fd == -1) { 2712 MKSTR(path1, "%s/hw_counters/%s", 2713 priv->sh->ibdev_path, 2714 ctr_name); 2715 fd = open(path1, O_RDONLY); 2716 } 2717 if (fd != -1) { 2718 char buf[21] = {'\0'}; 2719 ssize_t n = read(fd, buf, sizeof(buf)); 2720 2721 close(fd); 2722 if (n != -1) { 2723 *stat = strtoull(buf, NULL, 10); 2724 return 0; 2725 } 2726 } 2727 } 2728 *stat = 0; 2729 return 1; 2730 } 2731 2732 /** 2733 * Set the reg_mr and dereg_mr call backs 2734 * 2735 * @param reg_mr_cb[out] 2736 * Pointer to reg_mr func 2737 * @param dereg_mr_cb[out] 2738 * Pointer to dereg_mr func 2739 * 2740 */ 2741 void 2742 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 2743 mlx5_dereg_mr_t *dereg_mr_cb) 2744 { 2745 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr; 2746 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr; 2747 } 2748 2749 /** 2750 * Remove a MAC address from device 2751 * 2752 * @param dev 2753 * Pointer to Ethernet device structure. 2754 * @param index 2755 * MAC address index. 2756 */ 2757 void 2758 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2759 { 2760 struct mlx5_priv *priv = dev->data->dev_private; 2761 const int vf = priv->config.vf; 2762 2763 if (vf) 2764 mlx5_nl_mac_addr_remove(priv->nl_socket_route, 2765 mlx5_ifindex(dev), priv->mac_own, 2766 &dev->data->mac_addrs[index], index); 2767 } 2768 2769 /** 2770 * Adds a MAC address to the device 2771 * 2772 * @param dev 2773 * Pointer to Ethernet device structure. 2774 * @param mac_addr 2775 * MAC address to register. 2776 * @param index 2777 * MAC address index. 2778 * 2779 * @return 2780 * 0 on success, a negative errno value otherwise 2781 */ 2782 int 2783 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2784 uint32_t index) 2785 { 2786 struct mlx5_priv *priv = dev->data->dev_private; 2787 const int vf = priv->config.vf; 2788 int ret = 0; 2789 2790 if (vf) 2791 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route, 2792 mlx5_ifindex(dev), priv->mac_own, 2793 mac, index); 2794 return ret; 2795 } 2796 2797 /** 2798 * Modify a VF MAC address 2799 * 2800 * @param priv 2801 * Pointer to device private data. 2802 * @param mac_addr 2803 * MAC address to modify into. 2804 * @param iface_idx 2805 * Net device interface index 2806 * @param vf_index 2807 * VF index 2808 * 2809 * @return 2810 * 0 on success, a negative errno value otherwise 2811 */ 2812 int 2813 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, 2814 unsigned int iface_idx, 2815 struct rte_ether_addr *mac_addr, 2816 int vf_index) 2817 { 2818 return mlx5_nl_vf_mac_addr_modify 2819 (priv->nl_socket_route, iface_idx, mac_addr, vf_index); 2820 } 2821 2822 /** 2823 * Set device promiscuous mode 2824 * 2825 * @param dev 2826 * Pointer to Ethernet device structure. 2827 * @param enable 2828 * 0 - promiscuous is disabled, otherwise - enabled 2829 * 2830 * @return 2831 * 0 on success, a negative error value otherwise 2832 */ 2833 int 2834 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable) 2835 { 2836 struct mlx5_priv *priv = dev->data->dev_private; 2837 2838 return mlx5_nl_promisc(priv->nl_socket_route, 2839 mlx5_ifindex(dev), !!enable); 2840 } 2841 2842 /** 2843 * Set device promiscuous mode 2844 * 2845 * @param dev 2846 * Pointer to Ethernet device structure. 2847 * @param enable 2848 * 0 - all multicase is disabled, otherwise - enabled 2849 * 2850 * @return 2851 * 0 on success, a negative error value otherwise 2852 */ 2853 int 2854 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) 2855 { 2856 struct mlx5_priv *priv = dev->data->dev_private; 2857 2858 return mlx5_nl_allmulti(priv->nl_socket_route, 2859 mlx5_ifindex(dev), !!enable); 2860 } 2861 2862 /** 2863 * Flush device MAC addresses 2864 * 2865 * @param dev 2866 * Pointer to Ethernet device structure. 2867 * 2868 */ 2869 void 2870 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) 2871 { 2872 struct mlx5_priv *priv = dev->data->dev_private; 2873 2874 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 2875 dev->data->mac_addrs, 2876 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 2877 } 2878