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Searched refs:getOpcode (Results 1 – 25 of 1161) sorted by relevance

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/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h41 return isPreISelGenericOpcode(MI->getOpcode()); in classof()
87 switch (MI->getOpcode()) { in classof()
117 return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD; in classof()
125 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD || in classof()
126 MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD; in classof()
134 switch (MI->getOpcode()) { in classof()
149 return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD; in classof()
157 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD; in classof()
177 return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE; in classof()
193 switch (MI->getOpcode()) { in classof()
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/llvm-project/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp154 switch (Inst.getOpcode()) { in isADR()
187 return Inst.getOpcode() == AArch64::ADRP; in isMOVW()
191 return Inst.getOpcode() == AArch64::ADR;
195 return Inst.getOpcode() == AArch64::ADDXri; in isADD()
208 return (Inst.getOpcode() == AArch64::TBNZW || in isADD()
209 Inst.getOpcode() == AArch64::TBNZX || in isADD()
210 Inst.getOpcode() == AArch64::TBZW || in isADD()
211 Inst.getOpcode() == AArch64::TBZX); in isADD()
215 return (Inst.getOpcode() == AArch64::CBNZW || in isLDRB()
216 Inst.getOpcode() in isLDRB()
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MacroFusion.cpp24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
39 switch (FirstMI->getOpcode()) { in isArithmeticBccPair()
73 if (SecondMI.getOpcode() != AArch64::CBZW && in isArithmeticCbzPair()
74 SecondMI.getOpcode() != AArch64::CBZX && in isArithmeticCbzPair()
75 SecondMI.getOpcode() != AArch64::CBNZW && in isArithmeticCbzPair()
76 SecondMI.getOpcode() != AArch64::CBNZX) in isArithmeticCbzPair()
83 switch (FirstMI->getOpcode()) { in isArithmeticCbzPair()
124 switch (SecondMI.getOpcode()) { in isAESPair()
128 return FirstMI == nullptr || FirstMI->getOpcode() == AArch64::AESErr; in isAESPair()
132 return FirstMI == nullptr || FirstMI->getOpcode() == AArch64::AESDrr; in isAESPair()
[all …]
/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp29 switch (MI.getOpcode()) { in isConstantInstr()
51 switch (MI.getOpcode()) { in isInlineAsmDefInstr()
64 switch (MI.getOpcode()) { in isTypeDeclInstr()
79 return MI.getOpcode() == SPIRV::OpTypeForwardPointer; in isDecorationInstr()
84 switch (MI.getOpcode()) { in isHeaderInstr()
97 switch (MI.getOpcode()) { in isHeaderInstr()
119 switch (MI.getOpcode()) { in canUseFastMathFlags()
138 switch (MI.getOpcode()) { in canUseNSW()
155 switch (MI.getOpcode()) {
224 if (I->getOpcode()
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/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC && in INITIALIZE_PASS()
88 Hi.getOpcode() != RISCV::PseudoMovAddr) in INITIALIZE_PASS()
93 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; in INITIALIZE_PASS()
101 if (Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
111 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
116 if (Hi.getOpcode() == RISCV::LUI || Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
122 assert(Hi.getOpcode() == RISCV::AUIPC); in INITIALIZE_PASS()
150 if (Hi.getOpcode() ! in foldOffset()
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/llvm-project/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp82 if (Addr.getOpcode() == ISD::FrameIndex) in INITIALIZE_PASS()
84 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in INITIALIZE_PASS()
85 Addr.getOpcode() == ISD::TargetGlobalAddress || in INITIALIZE_PASS()
86 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in INITIALIZE_PASS()
146 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in selectADDRzii()
147 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRzii()
148 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in selectADDRzii()
177 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in selectADDRzi()
178 Addr.getOpcode() == ISD::TargetGlobalAddress || in selectADDRzi()
179 Addr.getOpcode() in selectADDRzi()
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/llvm-project/llvm/unittests/Transforms/Utils/
H A DIntegerDivisionTest.cpp41 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv); in TEST()
46 EXPECT_TRUE(BB->front().getOpcode() == Instruction::Freeze); in TEST()
49 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub); in TEST()
71 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv); in TEST()
76 EXPECT_TRUE(BB->front().getOpcode() == Instruction::Freeze); in TEST()
79 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI); in TEST()
101 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
106 EXPECT_TRUE(BB->front().getOpcode() == Instruction::Freeze); in TEST()
109 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub); in TEST()
131 EXPECT_TRUE(BB->front().getOpcode() == Instruction::URem); in TEST()
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/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h208 inline unsigned getOpcode() const;
687 unsigned getOpcode() const { return (unsigned)NodeType; }
716 bool isVPOpcode() const { return ISD::isVPOpcode(getOpcode()); }
943 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
1213 inline unsigned SDValue::getOpcode() const {
1214 return Node->getOpcode();
1347 return N->getOpcode() == ISD::ADDRSPACECAST;
1458 switch (getOpcode()) {
1479 switch (N->getOpcode()) {
1537 assert(getOpcode()
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/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp159 if (MI.getOpcode() != BPF::XADDW && MI.getOpcode() != BPF::XADDD) in processAtomicInsts()
/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600EmitClauseMarkers.cpp38 switch (MI.getOpcode()) { in OccupiedDwords()
52 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
55 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
56 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI.getOpcode())) in isALU()
73 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
75 switch (MI.getOpcode()) { in isALU()
89 switch (MI.getOpcode()) { in IsTrivialInst()
119 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() ! in SubstituteKCacheBank()
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H A DR600InstrInfo.cpp35 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
135 if (isALUInstr(MI.getOpcode())) in isLDSRetInstr()
137 if (isVector(MI) || isCubeOp(MI.getOpcode()))
139 switch (MI.getOpcode()) { in canBeConsideredALU()
159 return isTransOnly(MI.getOpcode()); in isTransOnly()
167 return isVectorOnly(MI.getOpcode()); in isVectorOnly()
181 usesVertexCache(MI.getOpcode());
191 usesVertexCache(MI.getOpcode())) ||
192 usesTextureCache(MI.getOpcode()); in usesTextureCache()
214 if (!isALUInstr(MI.getOpcode())) { in definesAddressRegister()
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H A DR600Packetizer.cpp67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
93 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
94 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); in substitutePV()
166 if (!TII->isALUInstr(MI.getOpcode())) in isSoloInstruction()
168 if (MI.getOpcode() == R600::GROUP_BARRIER) in isSoloInstruction()
172 return TII->isLDSInstr(MI.getOpcode()); in isSoloInstruction()
182 int OpI = TII->getOperandIdx(MII->getOpcode(), R60 in isLegalToPacketizeTogether()
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/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp101 while (MI && MI->getOpcode() == TargetOpcode::COPY && in INITIALIZE_PASS_DEPENDENCY()
123 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) { in findLoopComponents()
127 if (T.getOpcode() == ARM::t2LoopEndDec && in findLoopComponents()
148 if (LoopEnd->getOpcode() == ARM::t2LoopEndDec) in findLoopComponents()
153 if (!LoopDec || LoopDec->getOpcode() != ARM::t2LoopDec) { in findLoopComponents()
162 if (!LoopPhi || LoopPhi->getOpcode() != TargetOpcode::PHI || in findLoopComponents()
175 if (!LoopStart || (LoopStart->getOpcode() != ARM::t2DoLoopStart && in findLoopComponents()
176 LoopStart->getOpcode() != ARM::t2WhileLoopSetup && in findLoopComponents()
177 LoopStart->getOpcode() != ARM::t2WhileLoopStartLR)) { in findLoopComponents()
188 assert(MI->getOpcode() in RevertWhileLoopSetup()
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/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGStackify.cpp335 if (MI.getOpcode() == WebAssembly::LOOP) { in placeBlockMarker()
349 if (MI.getOpcode() == WebAssembly::BLOCK || in placeBlockMarker()
350 MI.getOpcode() == WebAssembly::TRY || in placeBlockMarker()
351 MI.getOpcode() == WebAssembly::TRY_TABLE) { in placeBlockMarker()
362 if (MI.getOpcode() == WebAssembly::END_BLOCK || in placeBlockMarker()
363 MI.getOpcode() == WebAssembly::END_LOOP || in placeBlockMarker()
364 MI.getOpcode() == WebAssembly::END_TRY || in placeBlockMarker()
365 MI.getOpcode() == WebAssembly::END_TRY_TABLE) in placeBlockMarker()
399 if (MI.getOpcode() == WebAssembly::LOOP) in placeLoopMarker()
412 if (MI.getOpcode() in placeLoopMarker()
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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp136 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
220 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
221 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
222 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
229 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
230 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
257 switch (MI.getOpcode()) { in canCompareBeNewValueJump()
295 if (def->getOpcode() == TargetOpcode::COPY) in canCompareBeNewValueJump()
347 switch (MI->getOpcode()) { in getNewValueJumpOpcode()
429 switch (MI.getOpcode()) { in isNewValueJumpCandidate()
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/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp110 if (Addr.getOpcode() == ISD::OR && in INITIALIZE_PASS()
111 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) { in INITIALIZE_PASS()
160 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || in selectAddrRiSpls()
161 Addr.getOpcode() == ISD::TargetGlobalAddress)) in selectAddrRiSpls()
165 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode()); in selectAddrRiSpls()
189 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) in selectAddrRiSpls()
242 if (Addr.getOpcode() == ISD::FrameIndex) in isdToLanaiAluCode()
246 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
247 Addr.getOpcode() == ISD::TargetGlobalAddress))
251 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode()); in selectAddrRr()
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/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp115 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
116 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
124 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
125 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
176 unsigned Opc = slot->getOpcode(); in findDelayInstr()
185 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
186 || J->getOpcode() == SP::RESTOREri) { in findDelayInstr()
270 unsigned Opcode = candidate->getOpcode(); in delayHasHazard()
310 switch(MI->getOpcode()) { in insertCallDefsUses()
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H A DSparcISelDAGToDAG.cpp93 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
94 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRri()
95 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRri()
98 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
114 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
119 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
131 if (Addr.getOpcode() == ISD::FrameIndex) return false; in SelectADDRri()
132 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
133 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRrr()
134 Addr.getOpcode() in SelectADDRrr()
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/llvm-project/llvm/include/llvm/IR/
H A DOperator.h42 unsigned getOpcode() const { in getOpcode() function
44 return I->getOpcode(); in getOpcode()
45 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
50 static unsigned getOpcode(const Value *V) { in getOpcode() function
52 return I->getOpcode(); in getOpcode()
54 return CE->getOpcode(); in getOpcode()
127 bool isCommutative() const { return Instruction::isCommutative(getOpcode()); } in classof()
130 return I->getOpcode() == Instruction::Add || in classof()
131 I->getOpcode() == Instruction::Sub || in classof()
132 I->getOpcode() in classof()
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/llvm-project/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp84 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeImm()
94 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeS9()
98 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB && in SelectAddrModeS9()
100 if (Addr.getOpcode() == ISD::FrameIndex) { in SelectAddrModeS9()
114 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeS9()
121 if (Base.getOpcode() == ISD::FrameIndex) { in SelectAddrModeS9()
138 if (Addr.getOpcode() == ARCISD::GAWRAPPER) { in SelectAddrModeFar()
143 if (Addr.getOpcode() == ISD::SUB) in SelectAddrModeFar()
161 if (Addr.getOpcode() == ISD::ADD) { in SelectFrameADDR_ri()
177 switch (N->getOpcode()) { in Select()
/llvm-project/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h56 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
60 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
64 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
68 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
72 return Info->get(Inst.getOpcode()).isCall(); in isCall()
76 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
80 return Info->get(Inst.getOpcode()).isTerminator(); in isTerminator()
91 return Info->get(Inst.getOpcode()).hasDefOfPhysReg(Inst, PC, MCRI); in mayAffectControlFlow()
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTLSDynamicCall.cpp67 bool IsTLSTPRelMI = MI.getOpcode() == PPC::GETtlsTpointer32AIX; in processBlock()
68 bool IsTLSLDAIXMI = (MI.getOpcode() == PPC::TLSLDAIX8 || in processBlock()
69 MI.getOpcode() == PPC::TLSLDAIX); in processBlock()
71 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
72 MI.getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
73 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
74 MI.getOpcode() != PPC::ADDItlsldLADDR32 && in processBlock()
75 MI.getOpcode() != PPC::TLSGDAIX && in processBlock()
76 MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL && in processBlock()
82 if (MI.getOpcode() in processBlock()
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H A DPPCBranchSelector.cpp141 if (TII->isPrefixed(MI.getOpcode())) { in ComputeBlockSizes()
328 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
330 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
333 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
334 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
357 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
368 } else if (I->getOpcode() in runOnMachineFunction()
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp276 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
281 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
730 switch (StoreVal.getOpcode()) { in getStoreSource()
980 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
988 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
989 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
996 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) ||
1053 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isAnyConstantBuildVector()
1070 if (V.getOpcode() ! in reassociationCanBreakAddressingModePattern()
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/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp104 if (MI->getOpcode() == TargetOpcode::G_LOAD || in getRegBankFromRegClass()
105 MI->getOpcode() == TargetOpcode::G_STORE) { in getRegBankFromRegClass()
138 if (NonCopyInstr->getOpcode() == TargetOpcode::COPY && in isGprbTwoInstrUnalignedLoadOrStore()
160 while (Ret->getOpcode() == TargetOpcode::COPY && in addDefUses()
174 while (Ret->getOpcode() == TargetOpcode::COPY &&
182 assert(isAmbiguous(MI->getOpcode()) &&
187 if (MI->getOpcode() == TargetOpcode::G_LOAD) in skipCopiesOutgoing()
190 if (MI->getOpcode() == TargetOpcode::G_STORE) in skipCopiesOutgoing()
200 if (MI->getOpcode() == TargetOpcode::G_SELECT) { in skipCopiesIncoming()
207 if (MI->getOpcode() in skipCopiesIncoming()
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