[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to on

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to only spill 32 bits.

I've added CodeGenOnly instructions for load/store using GPRF32 as that gave better results than insert_subreg/extract_subreg.

Function arguments use this new GPRF32 register class for f32 arguments with Zfinx. Eliminating the need to use RISCVISD::FMV* nodes.

This is similar to #107446 which adds a 16 bit register class.

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[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

This patches adds a 16 bit register class for use with Zhinx
instructions. This makes them more similar to Zfh instructions and
allows us t

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

This patches adds a 16 bit register class for use with Zhinx
instructions. This makes them more similar to Zfh instructions and
allows us to only spill 16 bits.

I've added CodeGenOnly instructions for load/store using GPRF16 as that
gave better results than insert_subreg/extract_subreg. I'm using FSGNJ
for GPRF16 copy with Zhinx as that gave better results. Zhinxmin will
use ADDI+subreg operations.

Function arguments use this new GPRF16 register class for f16 arguments
with Zhinxmin. Eliminating the need to use RISCVISD::FMV* nodes.

I plan to extend this idea to Zfinx next.

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[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)

If the register is used by a non-memory constraint we should disable the
fold.

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)

If the register is used by a non-memory constraint we should disable the
fold. Otherwise, we may leave CommonOffset unassigned.

Fixes #100779.

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[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)

This allows register allocation to rematerialize these instead of
spilling and reloading. We need to ma

[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)

This allows register allocation to rematerialize these instead of
spilling and reloading. We need to make it a single instruction due to
limitations in rematerialization.

This pseudo is expanded to an LUI+ADDI pair between regalloc and post RA
scheduling.

This improves the dynamic instruction count on 531.deepsjeng_r from
spec2017 by 3.2% for the train dataset. 500.perlbench and 502.gcc see a
1% improvement. There are couple regressions, but they are 0.1% or
smaller.

AArch64 has similar pseudo instructions like MOVaddr

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[RISCV] Merge ADDI with X0 into base offset (#78940)

If offset is `addi rd, x0, imm`, merge imm into base offset.

[RISCV] Teach RISCVMergeBaseOffset to handle inline asm (#78945)

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Differential Rev

[RISCV] Teach RISCVMergeBaseOffset to handle inline asm (#78945)

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Differential Revision: https://reviews.llvm.org/D158062

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[RISCV] Prevent RISCVMergeBaseOffsetOpt from calling getVRegDef on a physical register. (#78762)

Fixes #78679.

[Target] Remove unnecessary includes (NFC)

[RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress

We can get `BlockAddress` in user code via `Labels as Values` so
we should be able to merge the access to `BlockAddress`.

Reviewed By: crai

[RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress

We can get `BlockAddress` in user code via `Labels as Values` so
we should be able to merge the access to `BlockAddress`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D159429

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Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm"

This reverts commit f281543a48905e58359c6b0f1b9c3b42bd67e315.

Sami Tolvanen reports that this breaks the Linux kernel's arch=RISCV
d

Revert "[RISCV] Teach RISCVMergeBaseOffset to handle inline asm"

This reverts commit f281543a48905e58359c6b0f1b9c3b42bd67e315.

Sami Tolvanen reports that this breaks the Linux kernel's arch=RISCV
defconfig.

Link: https://github.com/ClangBuiltLinux/linux/issues/1928

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[RISCV] Teach RISCVMergeBaseOffset to handle inline asm

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Reviewed By: craig.topper

[RISCV] Teach RISCVMergeBaseOffset to handle inline asm

For inline asm with memory operands, we can merge the offset into
the second operand of memory constraint operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158062

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[RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.

The register being replaced might have a more restrictive register
class due to requirements of the using instruction.

[RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.

The register being replaced might have a more restrictive register
class due to requirements of the using instruction. We should
constrain the register class to preserve any restrictions.

This was found in our downstream on a custom instruction. I don't
have a test case for upstream currently.

Differential Revision: https://reviews.llvm.org/D154920

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[RISCV] Replace RISCV->RISC-V in strings.

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

D14644

[RISCV] Replace RISCV->RISC-V in strings.

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

D146449 already updated comments. Strings may have more user impact.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146451

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[RISCV] Make RISCVMergeBaseOffsetOpt a class instead of a struct. NFC

This lets us remove 'private:' from the top of the class.
While there collect the other private member variable at the top
of th

[RISCV] Make RISCVMergeBaseOffsetOpt a class instead of a struct. NFC

This lets us remove 'private:' from the top of the class.
While there collect the other private member variable at the top
of the class.

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[RISCV] Reduce duplicated code in RISCVMergeBaseOffsetOpt::detectFoldable. NFC

The LUI and AUIPC share quite a few similarities. This refactors the code
to share what we can.

Reviewed By: asb

Diff

[RISCV] Reduce duplicated code in RISCVMergeBaseOffsetOpt::detectFoldable. NFC

The LUI and AUIPC share quite a few similarities. This refactors the code
to share what we can.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D140345

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[RISCV] Teach RISCVMergeBaseOffset to handle constant pools.

Primarily this allows us to fold the addi from PseudoLLA expansion
into a load.

If the linker is able to GP relax the constant pool acce

[RISCV] Teach RISCVMergeBaseOffset to handle constant pools.

Primarily this allows us to fold the addi from PseudoLLA expansion
into a load.

If the linker is able to GP relax the constant pool access we'll
end up with a GP relative load.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D140341

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[RISCV] Pull out repeated calls to getOperand. NFC

Remove else after return.

[RISCV] Use std::optional in RISCVMergeBaseOffset.cpp (NFC)

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasva

[RISCV] Use std::optional in RISCVMergeBaseOffset.cpp (NFC)

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716

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[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.

This used to print from the ADDI where the operand number was
correct. It recently changed to print from the LUI or AUIPC which
n

[RISCV] Fix operand number in debug message in RISCVMergeBaseOffset.

This used to print from the ADDI where the operand number was
correct. It recently changed to print from the LUI or AUIPC which
needs to use operand 1 instead of 2.

This shows up as a crash with -debug.

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[RISCV] Teach RISCVMergeBaseOffset to merge %lo/%pcrel_lo into load/store after folding arithmetic.

It's possible we have:
lui a0, %hi(sym)
addi a0, %lo(sym)
addi a0, <offset1>
lw a0, <offset2>(a0)

[RISCV] Teach RISCVMergeBaseOffset to merge %lo/%pcrel_lo into load/store after folding arithmetic.

It's possible we have:
lui a0, %hi(sym)
addi a0, %lo(sym)
addi a0, <offset1>
lw a0, <offset2>(a0)

We want to arrive at
lui a0, %hi(sym+offset1+offset2)
lw a0, %lo(sym+offset1+offset2)

We currently fail to do this because we only consider loads/stores
if we didn't find any arithmetic.

This patch splits arithmetic folding and load/store folding into
two separate phases. The load/store folding can no longer assume
the offset in hi/lo is 0 so we must combine the offsets. I've applied
the same simm32 limit that we applied in the arithmetic folding.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D130931

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[RISCV] Eagerly delete instructions in MergeBaseOffset.

The only iterator we're holding points to HiLUI and we never
delete that so I think it is safe to delete everything else
immediately.

I want

[RISCV] Eagerly delete instructions in MergeBaseOffset.

The only iterator we're holding points to HiLUI and we never
delete that so I think it is safe to delete everything else
immediately.

I want to split detectAndFoldOffset into two phases. First, combine
LUI+ADDI with any ADD/ADDI/SHXADD that comes after it. This may
open opportunities to fold the ADDI from the LUI+ADDI into a
load/store address. So the load/store folding should run as a
second phase even if the ADD/ADDI/SHXADD made changes.

In order to do this we need to eagerly delete instructions in the
first phase so that we don't have dead users of the LUI+ADDI
when we start the second phase.

Patches to split the phases will come later.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D130119

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[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

Builds upon D123264, adding support for merging the low part of the LLA
address into the load/store instruction offsets.

Differential

[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

Builds upon D123264, adding support for merging the low part of the LLA
address into the load/store instruction offsets.

Differential Revision: https://reviews.llvm.org/D123265

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[RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global.

The pass was previously limited to LUI+ADDI being used by a single
instruction.

This patch allows the pass to optimize mu

[RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global.

The pass was previously limited to LUI+ADDI being used by a single
instruction.

This patch allows the pass to optimize multiple memory operations
that use the same offset. Each of them will receive a separate %lo
relocation. My main motivation is to handle a read-modify-write
where we have a load and store to the same address, but I didn't
restrict it to that case.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128599

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[Target, CodeGen] Use isImm(), isReg(), etc (NFC)

Recommit "[RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates."

With fix for sanitizer build bot failure.