Lines Matching refs:getOpcode
276 assert(N->getOpcode() != ISD::DELETED_NODE &&
281 if (N->getOpcode() == ISD::HANDLENODE)
730 switch (StoreVal.getOpcode()) {
980 if (N.getOpcode() == ISD::SETCC) {
988 (N.getOpcode() == ISD::STRICT_FSETCC ||
989 N.getOpcode() == ISD::STRICT_FSETCCS)) {
996 if (N.getOpcode() != ISD::SELECT_CC || !TLI.isConstTrueVal(N.getOperand(2)) ||
1053 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR)
1070 if (V.getOpcode() != ISD::BUILD_VECTOR)
1079 (LD->getOperand(2).getOpcode() != ISD::TargetConstant ||
1097 if (N0.getOpcode() != ISD::ADD)
1104 if ((N1.getOpcode() == ISD::VSCALE ||
1105 ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) &&
1106 N1.getOperand(0).getOpcode() == ISD::VSCALE &&
1109 int64_t ScalableOffset = N1.getOpcode() == ISD::VSCALE
1112 (N1.getOpcode() == ISD::SHL
1177 if (GA->getOpcode() == ISD::GlobalAddress && TLI.isOffsetFoldingLegal(GA))
1209 if (N0.getOpcode() != Opc)
1217 if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() &&
1285 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC &&
1286 N01->getOpcode() == ISD::SETCC) {
1330 if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc &&
1456 unsigned Opc = Op.getOpcode();
1523 unsigned Opc = Op.getOpcode();
1591 unsigned Opc = Op.getOpcode();
1624 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1640 unsigned Opc = Op.getOpcode();
1653 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1671 unsigned Opc = Op.getOpcode();
1813 assert(N->getOpcode() != ISD::DELETED_NODE &&
1814 RV.getOpcode() != ISD::DELETED_NODE &&
1832 if (RV.getOpcode() != ISD::EntryToken)
1849 switch (N->getOpcode()) {
2029 assert(N->getOpcode() != ISD::DELETED_NODE &&
2032 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
2033 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
2045 switch (N->getOpcode()) {
2074 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode())) {
2081 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
2140 if (N->hasOneUse() && N->user_begin()->getOpcode() == ISD::TokenFactor)
2169 switch (Op.getOpcode()) {
2255 switch (CurNode->getOpcode()) {
2338 if (N->getOpcode() == ISD::TRUNCATE) {
2387 if (N->getOpcode() == ISD::ADD) {
2396 } else if (N->getOpcode() == ISD::SUB) {
2427 if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse())
2435 unsigned Opcode = N->getOpcode();
2460 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&
2464 auto BinOpcode = BO->getOpcode();
2470 if (TLI.isCommutativeBinOp(BO->getOpcode()))
2480 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
2496 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2564 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2570 bool IsAdd = N->getOpcode() == ISD::ADD;
2574 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2620 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2625 bool IsAdd = N->getOpcode() == ISD::ADD;
2629 ShiftOp.getOpcode() != ISD::SRL)
2705 if (N0.getOpcode() == ISD::SUB) {
2722 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2823 return DAG.getNode(N1.getOpcode(), DL, VT, B, C);
2834 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2855 if (N0.getOpcode() == ISD::ADD) {
2874 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
2885 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
3005 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
3012 if (N0.getOpcode() == ISD::ADD &&
3013 N0.getOperand(1).getOpcode() == ISD::VSCALE &&
3014 N1.getOpcode() == ISD::VSCALE) {
3022 if (N0.getOpcode() == ISD::STEP_VECTOR &&
3023 N1.getOpcode() == ISD::STEP_VECTOR) {
3031 if (N0.getOpcode() == ISD::ADD &&
3032 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR &&
3033 N1.getOpcode() == ISD::STEP_VECTOR) {
3045 unsigned Opcode = N->getOpcode();
3092 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
3097 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
3116 if (V.getOpcode() != ISD::UADDO_CARRY && V.getOpcode() != ISD::USUBO_CARRY &&
3117 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
3121 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
3140 if (N1.getOpcode() == ISD::ZERO_EXTEND)
3143 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
3148 if (N10.getValueType() != VT && N10.getOpcode() == ISD::TRUNCATE)
3181 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
3190 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) {
3207 if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 &&
3218 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
3226 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3236 if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1)) &&
3294 if (V.getOpcode() != ISD::XOR)
3308 bool IsSigned = (ISD::SADDO == N->getOpcode());
3321 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
3363 if (N1.getOpcode() == ISD::UADDO_CARRY && isNullConstant(N1.getOperand(1))) {
3393 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3477 if (Carry1.getOpcode() != ISD::UADDO)
3486 if (Carry0.getOpcode() == ISD::UADDO_CARRY &&
3489 } else if (Carry0.getOpcode() == ISD::UADDO &&
3573 unsigned Opcode = Carry0.getOpcode();
3574 if (Opcode != Carry1.getOpcode())
3631 if (N->getOpcode() == ISD::AND)
3653 if ((N0.getOpcode() == ISD::ADD ||
3654 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
3747 if (N->getOpcode() != ISD::SUB ||
3757 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
3766 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) {
3776 if (Op1.getOpcode() == ISD::TRUNCATE &&
3777 Op1.getOperand(0).getOpcode() == ISD::UMIN &&
3781 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0)
3784 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0)
3884 if (N->getOpcode() == ISD::FREEZE && N.hasOneUse())
3924 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3927 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3948 if (N1.getOpcode() == ISD::ABS && N1.hasOneUse() &&
3965 unsigned NewOpc = ISD::getInverseMinMaxOpcode(N1->getOpcode());
3973 if (N1S && N1S.getOpcode() == ISD::SUB &&
3984 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
3988 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3992 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3996 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
4000 if (N0.getOpcode() == ISD::ADD) {
4007 if (N1.getOpcode() == ISD::ADD) {
4014 if (N0.getOpcode() == ISD::SUB) {
4021 if (N0.getOpcode() == ISD::SUB) {
4094 N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
4100 if (N1.getOpcode() == ISD::ADD && N1.hasOneUse() &&
4107 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
4113 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
4122 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
4147 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4157 if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) {
4163 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) {
4171 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
4183 if (N1.getOpcode() == ISD::SHL) {
4190 if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) &&
4246 unsigned Opcode = N->getOpcode();
4318 bool IsSigned = (ISD::SSUBO == N->getOpcode());
4362 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
4413 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
4609 if (!UseVP && N0.getOpcode() == ISD::VSCALE && NC1) {
4617 if (!UseVP && N0.getOpcode() == ISD::STEP_VECTOR &&
4652 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector");
4708 unsigned Opcode = Node->getOpcode();
4742 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
4748 unsigned UserOpc = User->getOpcode();
4778 unsigned Opc = N->getOpcode();
5044 if (N1.getOpcode() == ISD::SHL) {
5082 unsigned Opcode = N->getOpcode();
5127 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) &&
5311 unsigned Opcode = N->getOpcode();
5407 unsigned Opcode = N->getOpcode();
5485 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
5495 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
5600 bool IsSigned = (ISD::SMULO == N->getOpcode());
5623 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
5665 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0)))
5686 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) {
5706 switch (N0.getOpcode()) {
5711 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT;
5722 if (N0.getOperand(0).getOpcode() != ISD::SETCC)
5767 if (!Fp || Fp.getOpcode() != ISD::FP_TO_SINT)
5790 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) ||
5791 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT)
5823 unsigned Opcode = N->getOpcode();
5853 bool IsSatBroken = Opcode == ISD::UMIN && N0.getOpcode() == ISD::SMAX;
5907 unsigned LogicOpcode = N->getOpcode();
5908 unsigned HandOpcode = N0.getOpcode();
5910 assert(HandOpcode == N1.getOpcode() && "Bad input!");
6299 (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) &&
6305 if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC ||
6394 bool IsOr = (LogicOp->getOpcode() == ISD::OR);
6401 getMinMaxOpcodeForFP(Operand1, Operand2, CC, LogicOp->getOpcode(),
6416 CCL == (LogicOp->getOpcode() == ISD::AND ? ISD::SETNE : ISD::SETEQ) &&
6494 if (T.getOpcode() != ISD::AND)
6524 if (N1.getOpcode() == ISD::ADD)
6528 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
6700 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
6709 switch(Op.getOpcode()) {
6733 EVT VT = Op.getOpcode() == ISD::AssertZext ?
6806 if (And.getOpcode() == ISD ::AND)
6835 if (And.getOpcode() == ISD ::AND)
6855 assert(N->getOpcode() == ISD::AND);
6871 OuterShift = M->getOpcode();
6907 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op");
6911 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse())
6928 if (Src.getOpcode() == ISD::TRUNCATE && Src.hasOneUse())
6933 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse())
7007 unsigned LogicOpcode = N->getOpcode();
7015 unsigned ShiftOpcode = ShiftOp.getOpcode();
7016 if (LogicOp.getOpcode() != LogicOpcode ||
7028 if (LogicOp.getOperand(0).getOpcode() == ShiftOpcode &&
7032 } else if (LogicOp.getOperand(1).getOpcode() == ShiftOpcode &&
7055 unsigned LogicOpcode = N->getOpcode();
7058 if (LeftHand.getOpcode() != LogicOpcode ||
7059 RightHand.getOpcode() != LogicOpcode)
7178 if (N0.getOpcode() == ISD::OR &&
7182 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
7204 if (ISD::isExtOpcode(N0.getOpcode())) {
7205 unsigned ExtOpc = N0.getOpcode();
7207 if (N0Op0.getOpcode() == ISD::AND &&
7228 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7230 N0.getOperand(0).getOpcode() == ISD::LOAD &&
7232 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
7234 cast<LoadSDNode>((N0.getOpcode() == ISD::LOAD) ? N0 : N0.getOperand(0));
7332 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C &&
7333 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
7375 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector())
7392 if (N0.getOpcode() == N1.getOpcode())
7439 if (X.getOpcode() == ISD::ZERO_EXTEND &&
7442 if (X.getOpcode() == ISD::SIGN_EXTEND &&
7477 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
7496 if (LHS->getOpcode() != ISD::SIGN_EXTEND)
7542 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
7544 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
7546 if (N0.getOpcode() == ISD::AND) {
7559 if (N1.getOpcode() == ISD::AND) {
7569 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
7571 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
7585 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
7596 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
7653 unsigned Opc = N.getOpcode();
7658 unsigned Opc0 = N0.getOpcode();
7735 if (N.getOpcode() == ISD::OR)
7739 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
7757 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&
7761 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
7775 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
7826 } else if (N0.getOpcode() == ISD::OR) {
7872 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
7898 if (N0.getOpcode() == ISD::AND &&
7899 N1.getOpcode() == ISD::AND &&
7919 if (V->getOpcode() == ISD::ZERO_EXTEND || V->getOpcode() == ISD::TRUNCATE)
7925 if (N0Resized.getOpcode() == ISD::AND) {
7968 if (V->getOpcode() == ISD::ZERO_EXTEND)
7974 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL &&
7980 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL &&
8143 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() &&
8159 if (N0.getOpcode() == N1.getOpcode())
8191 if (Op.getOpcode() == ISD::AND &&
8203 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
8238 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL)
8252 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst &&
8253 ExtractFrom.getOpcode() == ISD::ADD &&
8269 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant;
8270 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift)
8277 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
8278 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
8283 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() ||
8406 if (Neg.getOpcode() != ISD::SUB)
8441 (NegOp1.getOpcode() == ISD::TRUNCATE && Pos == NegOp1.getOperand(0)))
8453 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
8526 if (Op.getOpcode() != BinOpc)
8553 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) &&
8592 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
8638 if (LHSShift.getOpcode() == RHSShift.getOpcode())
8642 if (RHSShift.getOpcode() == ISD::SHL) {
8649 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL)
8695 if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR)
8764 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
8765 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
8766 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
8767 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
8768 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
8769 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
8770 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
8771 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
8860 (Op.getOpcode() != ISD::LOAD || !Op.getValueType().isVector()))
8865 if (Op.getOpcode() != ISD::LOAD && VectorIndex.has_value())
8875 switch (Op.getOpcode()) {
8921 return Op.getOpcode() == ISD::ZERO_EXTEND
9023 switch (Value.getOpcode()) {
9116 if (Trunc.getOpcode() != ISD::TRUNCATE)
9122 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) &&
9277 assert(N->getOpcode() == ISD::OR &&
9476 assert(N->getOpcode() == ISD::XOR);
9488 if (And.getOpcode() != ISD::AND || !And.hasOneUse())
9491 if (Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse())
9622 unsigned N0Opcode = N0.getOpcode();
9698 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB &&
9705 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD &&
9722 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
9761 if (N0Opcode == N1.getOpcode())
9796 unsigned LogicOpcode = LogicOp.getOpcode();
9802 unsigned ShiftOpcode = Shift->getOpcode();
9809 if (V.getOpcode() != ShiftOpcode || !V.hasOneUse())
9886 switch (LHS.getOpcode()) {
9894 if (N->getOpcode() != ISD::SHL)
9903 bool IsShiftByConstant = (BinOpLHSVal.getOpcode() == ISD::SHL ||
9904 BinOpLHSVal.getOpcode() == ISD::SRA ||
9905 BinOpLHSVal.getOpcode() == ISD::SRL) &&
9907 bool IsCopyOrSelect = BinOpLHSVal.getOpcode() == ISD::CopyFromReg ||
9908 BinOpLHSVal.getOpcode() == ISD::SELECT;
9920 N->getOpcode(), DL, VT, {LHS.getOperand(1), N->getOperand(1)})) {
9921 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0),
9923 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS);
9930 assert(N->getOpcode() == ISD::TRUNCATE);
9931 assert(N->getOperand(0).getOpcode() == ISD::AND);
9981 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt);
9995 if (N1.getOpcode() == ISD::TRUNCATE &&
9996 N1.getOperand(0).getOpcode() == ISD::AND) {
9998 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1);
10001 unsigned NextOp = N0.getOpcode();
10010 bool SameSide = (N->getOpcode() == NextOp);
10024 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
10056 if (N0.getOpcode() == ISD::AND) {
10061 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
10080 if (N1.getOpcode() == ISD::TRUNCATE &&
10081 N1.getOperand(0).getOpcode() == ISD::AND) {
10087 if (N0.getOpcode() == ISD::SHL) {
10116 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
10117 N0.getOpcode() == ISD::ANY_EXTEND ||
10118 N0.getOpcode() == ISD::SIGN_EXTEND) &&
10119 N0.getOperand(0).getOpcode() == ISD::SHL) {
10149 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0));
10159 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
10160 N0.getOperand(0).getOpcode() == ISD::SRL) {
10181 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10205 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff);
10213 if (N0.getOpcode() == ISD::SRL &&
10241 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
10252 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
10261 if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
10263 return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
10270 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
10271 N0.getOperand(0).getOpcode() == ISD::ADD &&
10276 if (SDValue ExtC = DAG.FoldConstantArithmetic(N0.getOpcode(), DL, VT,
10280 SDValue ExtX = DAG.getNode(N0.getOpcode(), DL, VT, Add.getOperand(0));
10288 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) {
10302 if (((N1.getOpcode() == ISD::CTTZ &&
10304 N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
10319 if (N0.getOpcode() == ISD::VSCALE && N1C) {
10327 if (N0.getOpcode() == ISD::STEP_VECTOR &&
10345 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
10356 if (ShiftOperand.getOpcode() != ISD::MUL)
10363 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND;
10364 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND;
10374 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
10405 if (LeftOp.getOpcode() != RightOp.getOpcode())
10449 bool IsSigned = N->getOpcode() == ISD::SRA;
10456 unsigned Opcode = N->getOpcode();
10463 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) {
10469 if (OldLHS.getOpcode() == Opcode && OldRHS.getOpcode() == Opcode) {
10470 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0),
10474 if (OldLHS.getOpcode() == Opcode && OldLHS.hasOneUse()) {
10476 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0),
10480 if (OldRHS.getOpcode() == Opcode && OldRHS.hasOneUse()) {
10482 return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder,
10521 if (N0.getOpcode() == ISD::SRA) {
10538 if (N1.getOpcode() == ISD::BUILD_VECTOR)
10540 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) {
10556 if (N0.getOpcode() == ISD::SHL && N1C) {
10594 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C &&
10596 bool IsAdd = N0.getOpcode() == ISD::ADD;
10598 if (Shl.getOpcode() == ISD::SHL && Shl.getOperand(1) == N1 &&
10634 if (N1.getOpcode() == ISD::TRUNCATE &&
10635 N1.getOperand(0).getOpcode() == ISD::AND) {
10644 if (N0.getOpcode() == ISD::TRUNCATE &&
10645 (N0.getOperand(0).getOpcode() == ISD::SRL ||
10646 N0.getOperand(0).getOpcode() == ISD::SRA) &&
10722 if (N0.getOpcode() == ISD::SRL) {
10746 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
10747 N0.getOperand(0).getOpcode() == ISD::SRL) {
10784 if (N0.getOpcode() == ISD::SHL &&
10819 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
10843 if (N0.getOpcode() == ISD::SRA)
10849 if (N1C && N0.getOpcode() == ISD::CTLZ &&
10883 if (N1.getOpcode() == ISD::TRUNCATE &&
10884 N1.getOperand(0).getOpcode() == ISD::AND) {
10930 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse())
10933 if (User->getOpcode() == ISD::BRCOND || User->getOpcode() == ISD::AND ||
10934 User->getOpcode() == ISD::OR || User->getOpcode() == ISD::XOR)
10954 bool IsFSHL = N->getOpcode() == ISD::FSHL;
10976 return DAG.getNode(N->getOpcode(), DL, VT, N0, N1,
11075 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
11082 if (N->getOpcode() == ISD::SSHLSAT && N1C &&
11087 if (N->getOpcode() == ISD::USHLSAT && N1C &&
11103 if (N->getOpcode() == ISD::TRUNCATE)
11106 if (N->getOpcode() != ISD::ABS)
11113 if (AbsOp1.getOpcode() != ISD::SUB)
11119 unsigned Opc0 = Op0.getOpcode();
11123 if (Opc0 != Op1.getOpcode() ||
11178 if (N0.getOpcode() == ISD::ABS)
11189 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
11213 if (N0.getOpcode() == ISD::BSWAP)
11220 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) {
11228 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) {
11250 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
11256 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
11277 if (N0.getOpcode() == ISD::BITREVERSE)
11365 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) {
11370 if ((N0.getOpcode() == ISD::SRL &&
11372 (N0.getOpcode() == ISD::SHL &&
11460 const unsigned Opcode = N->getOpcode();
11558 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() ||
11588 if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse())
11724 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT ||
11725 N->getOpcode() == ISD::VP_SELECT) &&
11910 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
11923 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
11937 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
11956 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
11975 if (N0.getOpcode() == ISD::USUBO && N0.getResNo() == 1 &&
11977 N1.getOpcode() == ISD::SUB && N2.getOperand(0) == N1.getOperand(1) &&
11983 if (N0.getOpcode() == ISD::USUBO && N0.getResNo() == 1 &&
11985 N2.getOpcode() == ISD::SUB && N2.getOperand(0) == N1.getOperand(1) &&
11994 if (N0.getOpcode() == ISD::SETCC) {
12014 N2.getOpcode() == ISD::ADD && Cond0 == N2.getOperand(0)) {
12074 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
12075 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
12076 Cond.getOpcode() == ISD::BUILD_VECTOR);
12140 if (Index.getOpcode() != ISD::ADD)
12164 if (Index.getOpcode() == ISD::ZERO_EXTEND) {
12177 if (Index.getOpcode() == ISD::SIGN_EXTEND &&
12273 if (N->getOpcode() != ISD::DELETED_NODE)
12307 if (N->getOpcode() != ISD::DELETED_NODE)
12317 if ((Value.getOpcode() == ISD::TRUNCATE) && Value->hasOneUse() &&
12629 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N2 && N1->hasOneUse() &&
12644 if (N0.getOpcode() == ISD::SETCC) {
12652 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
12655 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
12701 if (LHS.getOpcode() == ISD::LOAD && LHS.hasOneUse() &&
12734 if (Other && Other.getOpcode() == ISD::ADD) {
12751 if (OpRHS.getOpcode() == CondRHS.getOpcode() &&
12752 (OpRHS.getOpcode() == ISD::BUILD_VECTOR ||
12753 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) &&
12785 if (Other && Other.getOpcode() == ISD::TRUNCATE &&
12786 Other.getOperand(0).getOpcode() == ISD::SUB &&
12790 if (LHS == OpLHS && RHS == OpRHS && LHS.getOpcode() == ISD::ZERO_EXTEND)
12805 Other.getOpcode() == ISD::SUB && OpRHS == CondRHS)
12808 if (OpRHS.getOpcode() == ISD::BUILD_VECTOR ||
12809 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) {
12810 if (CondRHS.getOpcode() == ISD::BUILD_VECTOR ||
12811 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) {
12820 if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD &&
12833 if (SatCC == ISD::SETLT && Other.getOpcode() == ISD::XOR &&
12862 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
12863 N2.getOpcode() == ISD::CONCAT_VECTORS &&
12916 if (SCC.getOpcode() == ISD::SETCC) {
12938 N->hasOneUse() && N->user_begin()->getOpcode() == ISD::BRCOND;
12948 if (PreferSetCC && Combined.getOpcode() != ISD::SETCC) {
12975 return A.getOpcode() == ISD::AND &&
12976 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) &&
12980 return (B.getOpcode() == ISD::ROTL || B.getOpcode() == ISD::ROTR) &&
13023 unsigned ShiftOpc = ShiftOrRotate.getOpcode();
13118 unsigned Opcode = N->getOpcode();
13125 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) ||
13146 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes &&
13164 unsigned Opcode = N->getOpcode();
13180 if (N0->getOpcode() == ISD::SELECT) {
13257 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
13280 if (User->getOpcode() == ISD::CopyToReg)
13287 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
13327 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
13328 N->getOpcode() == ISD::ZERO_EXTEND) &&
13348 if (N0->getOpcode() != ISD::LOAD)
13360 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI))
13364 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
13415 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode());
13423 assert(N->getOpcode() == ISD::ZERO_EXTEND);
13431 if (!ISD::isBitwiseLogicOp(N0.getOpcode()) ||
13432 N0.getOperand(1).getOpcode() != ISD::Constant ||
13433 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT)))
13438 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) ||
13439 N1.getOperand(1).getOpcode() != ISD::Constant ||
13440 (LegalOperations && !TLI.isOperationLegal(N1.getOpcode(), VT)))
13455 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
13472 SDValue Shift = DAG.getNode(N1.getOpcode(), DL1, VT, ExtLoad,
13477 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift,
13501 unsigned CastOpcode = Cast->getOpcode();
13515 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() ||
13516 VSel.getOperand(0).getOpcode() != ISD::SETCC)
13589 if (User->getOpcode() == ISD::SETCC) {
13670 if (!ALoad || ALoad->getOpcode() != ISD::ATOMIC_LOAD)
13697 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
13698 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext");
13701 if (LegalOperations || SetCC.getOpcode() != ISD::SETCC ||
13724 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
13733 if (N0.getOpcode() != ISD::SETCC)
13806 if (User->getOpcode() != ExtOpcode || User->getValueType(0) != VT)
13873 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
13878 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
13879 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
13884 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
13887 if ((N00.getOpcode() == ISD::TRUNCATE || TLI.isTruncateFree(N00, ExtVT)) &&
13894 if (N0.getOpcode() == ISD::TRUNCATE) {
13976 if (ISD::isBitwiseLogicOp(N0.getOpcode()) &&
13978 N0.getOperand(1).getOpcode() == ISD::Constant &&
13979 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
13993 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
14034 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
14036 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND &&
14043 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
14045 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
14084 assert((Extend->getOpcode() == ISD::ZERO_EXTEND ||
14085 Extend->getOpcode() == ISD::ANY_EXTEND) &&
14089 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse())
14106 assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend.");
14113 if (Abs.getOpcode() != ISD::ABS || !Abs.hasOneUse())
14148 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
14150 if (N0.getOpcode() == ISD::ZERO_EXTEND)
14157 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
14158 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG)
14183 if (N0.getOpcode() == ISD::TRUNCATE) {
14257 if (N0.getOpcode() == ISD::AND &&
14258 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
14259 N0.getOperand(1).getOpcode() == ISD::Constant &&
14294 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && !TLI.isZExtFree(N0, VT) &&
14296 N0.getOperand(1).getOpcode() == ISD::Constant &&
14297 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
14305 if (N0.getOpcode() == ISD::AND) {
14322 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
14359 if (N0.getOpcode() == ISD::SETCC) {
14405 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
14410 if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) {
14411 if (N0.getOpcode() == ISD::SHL) {
14431 return DAG.getNode(N0.getOpcode(), DL, VT,
14474 if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND ||
14475 N0.getOpcode() == ISD::SIGN_EXTEND) {
14477 if (N0.getOpcode() == ISD::ZERO_EXTEND)
14479 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Flags);
14485 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
14486 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG ||
14487 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
14488 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
14492 if (N0.getOpcode() == ISD::TRUNCATE) {
14505 if (N0.getOpcode() == ISD::TRUNCATE)
14510 if (N0.getOpcode() == ISD::AND &&
14511 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
14512 N0.getOperand(1).getOpcode() == ISD::Constant &&
14561 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) &&
14577 if (N0.getOpcode() == ISD::SETCC) {
14628 unsigned Opcode = N->getOpcode();
14634 if (N0.getOpcode() == Opcode &&
14638 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
14639 N0.getOperand(0).getOpcode() == Opcode) {
14658 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
14659 N0.getOperand(0).getOpcode() == ISD::AssertSext &&
14689 switch (N0.getOpcode()) {
14704 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS);
14717 unsigned Opc = N->getOpcode();
14795 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) {
14843 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND &&
14878 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
14984 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
14992 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
15004 if (ISD::isExtVecInRegOpcode(N0.getOpcode())) {
15009 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
15021 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
15045 if (N0.getOpcode() == ISD::SRL) {
15125 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) {
15135 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() &&
15136 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
15157 unsigned InregOpcode = N->getOpcode();
15171 if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS)
15194 return N->getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG
15310 if (Src.getOpcode() == ISD::SMIN || Src.getOpcode() == ISD::SMAX) {
15317 } else if (Src.getOpcode() == ISD::UMIN) {
15341 if (N0.getOpcode() == ISD::TRUNCATE)
15353 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
15354 N0.getOpcode() == ISD::SIGN_EXTEND ||
15355 N0.getOpcode() == ISD::ANY_EXTEND) {
15358 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
15369 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
15381 if (N->hasOneUse() && (N->user_begin()->getOpcode() == ISD::ANY_EXTEND))
15401 if (Src.getOpcode() == ISD::SRL && Src.getOperand(0)->hasOneUse()) {
15410 if (Src.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
15434 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse() &&
15448 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
15472 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
15487 if (N0.getOpcode() == ISD::SPLAT_VECTOR &&
15500 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
15501 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
15529 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
15549 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
15594 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
15614 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
15616 if (N00.getOpcode() == ISD::SIGN_EXTEND ||
15617 N00.getOpcode() == ISD::ZERO_EXTEND ||
15618 N00.getOpcode() == ISD::ANY_EXTEND) {
15633 switch (N0.getOpcode()) {
15646 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) {
15649 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR);
15660 if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) ||
15661 TLI.isOperationLegal(N0.getOpcode(), VT)) &&
15666 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2));
15674 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
15677 hasOperation(N0.getOpcode(), VT)) {
15689 if (Elt.getOpcode() != ISD::MERGE_VALUES)
15697 assert(N->getOpcode() == ISD::BUILD_PAIR);
15750 switch (N0.getOpcode()) {
15791 if (N0.getOpcode() == ISD::OR)
15816 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() &&
15838 if (N0.getOpcode() == ISD::BITCAST)
15843 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() &&
15846 return (V.getOpcode() == ISD::BITCAST &&
15852 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
15897 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
15898 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
15910 if (N0.getOpcode() == ISD::FNEG) {
15914 assert(N0.getOpcode() == ISD::FABS);
15929 if (N0.getOpcode() == ISD::FNEG)
15932 assert(N0.getOpcode() == ISD::FABS);
15948 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() &&
16012 if (N0.getOpcode() == ISD::BUILD_PAIR)
16018 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && VT.isScalarInteger()) {
16029 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
16037 if (Op.getOpcode() == ISD::BITCAST &&
16083 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
16099 N0.getOpcode() == ISD::SELECT_CC ||
16100 N0.getOpcode() == ISD::SETCC ||
16101 N0.getOpcode() == ISD::BUILD_VECTOR ||
16102 N0.getOpcode() == ISD::BUILD_PAIR ||
16103 N0.getOpcode() == ISD::VECTOR_SHUFFLE ||
16104 N0.getOpcode() == ISD::CONCAT_VECTORS;
16112 if (N0.getOpcode() == ISD::BUILD_VECTOR) {
16160 if (MaybePoisonOperand.getOpcode() == ISD::UNDEF)
16166 if (FrozenMaybePoisonOperand.getOpcode() == ISD::FREEZE &&
16176 if (N->getOpcode() == ISD::DELETED_NODE)
16188 if (Op.getOpcode() == ISD::UNDEF)
16199 R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops);
16286 assert(N.getOpcode() == ISD::FMUL);
16404 return FMA.getOpcode() == ISD::DELETED_NODE ? SDValue(N, 0) : FMA;
16481 if (N0.getOpcode() == ISD::FP_EXTEND) {
16499 if (N12.getOpcode() == ISD::FP_EXTEND) {
16516 if (N1.getOpcode() == ISD::FP_EXTEND) {
16871 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation");
16877 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1;
16903 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) {
16926 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) {
16962 if (Fused.getOpcode() != ISD::DELETED_NODE)
16980 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17018 if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL)
17044 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
17048 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
17059 if (N1CFP && N0.getOpcode() == ISD::FADD &&
17069 if (N0.getOpcode() == ISD::FMUL) {
17081 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
17090 if (N1.getOpcode() == ISD::FMUL) {
17102 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
17111 if (N0.getOpcode() == ISD::FADD) {
17121 if (N1.getOpcode() == ISD::FADD) {
17132 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
17149 if (Fused.getOpcode() != ISD::DELETED_NODE)
17194 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17244 N1.getOpcode() == ISD::FADD) {
17288 if (ConstOpIdx == 1 && N->getOpcode() == ISD::FDIV)
17293 if (Pow2Op.getOpcode() != ISD::UINT_TO_FP &&
17294 (Pow2Op.getOpcode() != ISD::SINT_TO_FP ||
17319 N->getOpcode() == ISD::FMUL ? CurExp : (CurExp - MaxExpChange);
17322 N->getOpcode() == ISD::FDIV ? CurExp : (CurExp + MaxExpChange);
17367 DAG.getNode(N->getOpcode() == ISD::FMUL ? ISD::ADD : ISD::SUB, DL,
17383 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17406 N0.getOpcode() == ISD::FMUL) {
17420 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() &&
17464 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
17467 if (Select.getOpcode() != ISD::SELECT)
17475 Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0) == X &&
17536 DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1, N2}))
17699 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
17701 if (U->getOperand(1).getOpcode() == ISD::FSQRT &&
17748 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17791 if (N1.getOpcode() == ISD::FSQRT) {
17794 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
17795 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
17802 } else if (N1.getOpcode() == ISD::FP_ROUND &&
17803 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
17810 } else if (N1.getOpcode() == ISD::FMUL) {
17814 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
17817 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
17827 if (Y.getOpcode() == ISD::FABS && Y.hasOneUse())
17864 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
17897 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17974 if (N1.getOpcode() != ISD::FP_EXTEND &&
17975 N1.getOpcode() != ISD::FP_ROUND)
18009 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
18010 N0.getOpcode() == ISD::FCOPYSIGN)
18014 if (N1.getOpcode() == ISD::FABS)
18018 if (N1.getOpcode() == ISD::FCOPYSIGN)
18133 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
18137 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
18171 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
18179 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
18180 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() &&
18218 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
18234 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
18239 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
18240 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
18315 DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0}))
18332 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
18336 if (N0.getOpcode() == ISD::FP_ROUND) {
18370 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() &&
18395 if (N->hasOneUse() && N->user_begin()->getOpcode() == ISD::FP_ROUND)
18403 if (N0.getOpcode() == ISD::FP16_TO_FP &&
18409 if (N0.getOpcode() == ISD::FP_ROUND && N0.getConstantOperandVal(1) == 1) {
18462 switch (N0.getOpcode()) {
18513 if (N0.getOpcode() == ISD::FSUB &&
18531 unsigned Opc = N->getOpcode();
18543 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
18594 if (N0.getOpcode() == ISD::FABS)
18599 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
18615 if (N1->getOpcode() == ISD::FREEZE && N1.hasOneUse()) {
18630 if (N1->getOpcode() == ISD::SETCC && N1.hasOneUse()) {
18650 if (S0->getOpcode() == ISD::FREEZE && S0.hasOneUse() && S1C) {
18656 if (S1->getOpcode() == ISD::FREEZE && S1.hasOneUse() && S0C) {
18678 if (N1.getOpcode() == ISD::SETCC &&
18699 if (N.getOpcode() == ISD::SRL ||
18700 (N.getOpcode() == ISD::TRUNCATE &&
18702 N.getOperand(0).getOpcode() == ISD::SRL))) {
18704 if (N.getOpcode() == ISD::TRUNCATE)
18727 if (Op0.getOpcode() == ISD::AND && Op1.getOpcode() == ISD::Constant) {
18730 if (AndOp1.getOpcode() == ISD::Constant) {
18746 if (N.getOpcode() == ISD::XOR) {
18753 while (N.getOpcode() == ISD::XOR) {
18766 if (N.getOpcode() != ISD::XOR)
18772 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
18775 if (isBitwiseNot(N) && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR &&
18818 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
18888 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
18960 if (Use.getUser()->getOpcode() != ISD::ADD &&
18961 Use.getUser()->getOpcode() != ISD::SUB) {
19057 int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
19058 int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
19096 (PtrUse->getOpcode() != ISD::ADD && PtrUse->getOpcode() != ISD::SUB))
19131 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SUB) {
19239 assert((Inc.getOpcode() != ISD::TargetConstant ||
19242 if (Inc.getOpcode() == ISD::TargetConstant) {
19312 if (Chain.getOpcode() == ISD::CALLSEQ_START)
19317 if (Chain.getOpcode() == ISD::TokenFactor) {
19870 if (User->getOpcode() != ISD::BITCAST)
20087 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
20095 if (User->getOpcode() != ISD::TRUNCATE)
20138 if (SliceInst.getOpcode() != ISD::LOAD)
20140 assert(SliceInst->getOpcode() == ISD::LOAD &&
20160 if (V->getOpcode() != ISD::AND ||
20209 else if (Chain->getOpcode() == ISD::TokenFactor &&
20318 unsigned Opc = Value.getOpcode();
20348 if (Value.getOperand(1).getOpcode() != ISD::Constant)
20538 if (User->getOpcode() == ISD::MUL) { // We have another multiply use.
20574 if (OtherOp->getOpcode() == ISD::ADD &&
20716 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
20717 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) {
20723 Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
20913 if (OtherBC.getOpcode() != ISD::EXTRACT_VECTOR_ELT &&
20914 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR)
21019 if (N->getOpcode() == ISD::TokenFactor) {
21716 if (Value.getOpcode() == ISD::TargetConstantFP)
21802 if (Value.getOpcode() != ISD::INSERT_VECTOR_ELT || !Value.hasOneUse())
21874 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
21939 if ((Value.getOpcode() == ISD::ZERO_EXTEND ||
21940 Value.getOpcode() == ISD::SIGN_EXTEND ||
21941 Value.getOpcode() == ISD::ANY_EXTEND) &&
21959 if (N->getOpcode() != ISD::DELETED_NODE)
22057 if ((Value.getOpcode() == ISD::FP_ROUND ||
22058 Value.getOpcode() == ISD::TRUNCATE) &&
22078 if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N))
22117 switch (Chain.getOpcode()) {
22197 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR)
22204 if (Op1.getOpcode() != ISD::SHL) {
22206 if (Op1.getOpcode() != ISD::SHL)
22222 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() ||
22225 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() ||
22232 EVT LowTy = (Lo.getOperand(0).getOpcode() == ISD::BITCAST)
22235 EVT HighTy = (Hi.getOperand(0).getOpcode() == ISD::BITCAST)
22272 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
22300 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) {
22337 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT &&
22367 assert(N->getOpcode() == ISD::INSERT_VECTOR_ELT &&
22371 if (InsertVal.getOpcode() != ISD::BITCAST || !InsertVal.hasOneUse() ||
22448 if (Scalar.getOpcode() == ISD::ZERO_EXTEND ||
22449 Scalar.getOpcode() == ISD::SIGN_EXTEND ||
22450 Scalar.getOpcode() == ISD::ANY_EXTEND) {
22451 Extend = Scalar.getOpcode();
22461 if (Vec.getOpcode() != Extend)
22531 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
22554 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
22567 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
22631 if (CurVec.getOpcode() == ISD::BUILD_VECTOR && CurVec.hasOneUse()) {
22638 if (CurVec.getOpcode() == ISD::SCALAR_TO_VECTOR && CurVec.hasOneUse()) {
22644 if (CurVec.getOpcode() == ISD::INSERT_VECTOR_ELT && CurVec.hasOneUse())
22661 if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) {
22806 unsigned Opc = Vec.getOpcode();
22936 switch (User->getOpcode()) {
22965 if (User->getOpcode() != ISD::BUILD_VECTOR)
23034 if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT &&
23042 if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) {
23067 if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) ||
23068 VecOp.getOpcode() == ISD::SPLAT_VECTOR) &&
23070 assert((VecOp.getOpcode() != ISD::BUILD_VECTOR ||
23074 VecOp.getOpcode() == ISD::BUILD_VECTOR ? IndexC->getZExtValue() : 0;
23117 if (IndexC && VecOp.getOpcode() == ISD::BITCAST && VecVT.isInteger() &&
23130 BCSrc.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23170 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) {
23188 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
23213 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
23226 if (N->getOpcode() != ISD::DELETED_NODE)
23234 if (N->getOpcode() != ISD::DELETED_NODE)
23252 if (VecOp.getOpcode() == ISD::BITCAST) {
23287 } else if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23314 if (VecOp.getOpcode() == ISD::BITCAST) {
23326 } else if (VecOp.getOpcode() == ISD::CONCAT_VECTORS && !BCNumEltsChanged &&
23391 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
23392 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
23448 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
23449 Cast.getOpcode() == ISD::ZERO_EXTEND ||
23487 assert(N->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector");
23512 if (Op.getOpcode() == ISD::BITCAST)
23524 if (In.getOpcode() != ISD::TRUNCATE)
23529 if (In.getOpcode() != ISD::SRL) {
23709 assert(BV->getOpcode() == ISD::BUILD_VECTOR && "Expected build vector");
23736 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() ||
23737 Zext.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
23848 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
24042 bool IsLeftShuffle = L.getOpcode() == ISD::VECTOR_SHUFFLE &&
24051 bool IsRightShuffle = R.getOpcode() == ISD::VECTOR_SHUFFLE &&
24091 unsigned Opc = Op.getOpcode();
24094 Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24183 if (Op.getOpcode() != ISD::ZERO_EXTEND)
24292 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) &&
24360 if (ISD::BITCAST == Op.getOpcode() &&
24363 else if (ISD::UNDEF == Op.getOpcode())
24410 if (Op.getOpcode() != ISD::CONCAT_VECTORS)
24462 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
24514 unsigned CastOpcode = N->getOperand(0).getOpcode();
24539 if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() ||
24702 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() &&
24714 if (!LegalOperations && Scalar.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24726 if (Scalar->getOpcode() == ISD::TRUNCATE &&
24758 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
24770 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
24782 if (ISD::UNDEF == Op.getOpcode())
24785 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
24841 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
24873 if (V.getOpcode() == ISD::INSERT_SUBVECTOR &&
24878 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS &&
24892 unsigned BinOpcode = BinOp.getOpcode();
24941 unsigned BOpcode = BinOp.getOpcode();
25023 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2)
25125 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR &&
25284 if (ExtIdx == 0 && V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) {
25294 if (V.getOpcode() == ISD::SPLAT_VECTOR)
25302 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
25318 if (V.getOpcode() == ISD::BITCAST &&
25367 if (V.getOpcode() == ISD::CONCAT_VECTORS) {
25409 if (V.getOpcode() == ISD::BUILD_VECTOR) {
25441 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
25483 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
25484 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 ||
25648 if (S.getOpcode() == ISD::BUILD_VECTOR) {
25650 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR) {
25903 unsigned Opcode = N0.getOpcode();
26059 if (Op0.getOpcode() != ISD::BITCAST)
26063 (!Op1.isUndef() && (Op1.getOpcode() != ISD::BITCAST ||
26309 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) {
26319 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags());
26329 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0)
26332 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT)
26339 if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() &&
26341 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR ||
26342 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) {
26359 if (V->getOpcode() == ISD::BITCAST) {
26366 if (V->getOpcode() == ISD::BUILD_VECTOR) {
26429 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
26432 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
26441 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() &&
26470 assert(RHS.getOpcode() == ISD::CONCAT_VECTORS && "Can't find subvectors");
26515 if (N1.getOpcode() == ISD::CONCAT_VECTORS)
26518 if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
26589 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
26594 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
26768 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
26769 N0.getOpcode() != ISD::VECTOR_SHUFFLE) {
26786 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE &&
26787 N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
26801 if (N->getOperand(i).getOpcode() == ISD::VECTOR_SHUFFLE &&
26828 unsigned SrcOpcode = N0.getOpcode();
26831 (SrcOpcode == N1.getOpcode() && N->isOnlyUserOf(N1.getNode())))) {
26842 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE ||
26843 Op10.getOpcode() == ISD::VECTOR_SHUFFLE ||
26844 Op01.getOpcode() == ISD::VECTOR_SHUFFLE ||
26845 Op11.getOpcode() == ISD::VECTOR_SHUFFLE)) {
26927 unsigned Opcode = Scalar.getOpcode();
26944 if (C && EE.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27023 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
27045 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && N1.getOperand(0) == N0 &&
27051 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR)
27059 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST &&
27060 N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR &&
27073 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
27090 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
27099 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
27108 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) &&
27109 N1.getOpcode() == ISD::BITCAST) {
27146 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() &&
27161 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
27182 if (N0->getOpcode() == ISD::FP16_TO_FP)
27189 auto Op = N->getOpcode();
27196 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) {
27206 SDValue Folded = DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N),
27215 if (N0->getOpcode() == ISD::BF16_TO_FP)
27229 unsigned Opcode = N->getOpcode();
27255 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
27270 (N0.getOpcode() == ISD::SIGN_EXTEND ||
27271 N0.getOpcode() == ISD::ZERO_EXTEND ||
27272 N0.getOpcode() == ISD::ANY_EXTEND) &&
27277 return DAG.getNode(N0.getOpcode(), SDLoc(N), N->getValueType(0), Red);
27295 if (N->getOpcode() == ISD::VP_GATHER)
27299 if (N->getOpcode() == ISD::VP_SCATTER)
27303 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_LOAD)
27307 if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE)
27315 if (auto EVLIdx = ISD::getVPExplicitVectorLengthIdx(N->getOpcode()))
27317 if (auto MaskIdx = ISD::getVPMaskIdx(N->getOpcode()))
27323 switch (N->getOpcode()) {
27343 if (ISD::isVPBinaryOp(N->getOpcode()))
27355 if (ISD::isVPReduction(N->getOpcode()))
27456 assert(N->getOpcode() == ISD::AND && "Unexpected opcode!");
27468 if (RHS.getOpcode() != ISD::BUILD_VECTOR)
27546 unsigned Opcode = N->getOpcode();
27559 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR &&
27560 N1.getOpcode() == ISD::SPLAT_VECTOR;
27577 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode()) {
27607 unsigned Opcode = N->getOpcode();
27616 (N0.getOpcode() == ISD::SPLAT_VECTOR ||
27642 unsigned Opcode = N->getOpcode();
27672 Shuf0->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) {
27681 Shuf1->getOperand(0).getOpcode() != ISD::INSERT_VECTOR_ELT) {
27694 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() &&
27695 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() &&
27715 return Concat.getOpcode() == ISD::CONCAT_VECTORS &&
27752 assert(N0.getOpcode() == ISD::SETCC &&
27764 if (SCC.getOpcode() == ISD::SELECT_CC) {
27792 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
27799 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
27806 if (Cmp.getOpcode() == ISD::SETCC) {
27826 if (LHS.getOpcode() != RHS.getOpcode() ||
27834 if (LHS.getOpcode() == ISD::LOAD) {
27863 LLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex ||
27864 RLD->getBasePtr().getOpcode() == ISD::TargetFrameIndex ||
27865 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
27892 if (TheSelect->getOpcode() == ISD::SELECT) {
28053 unsigned BinOpc = N1.getOpcode();
28054 if (!TLI.isBinOp(BinOpc) || (N2.getOpcode() != BinOpc) ||
28105 bool IsFabs = N->getOpcode() == ISD::FABS;
28108 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse())
28236 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
28323 if ((Count.getOpcode() == ISD::CTTZ ||
28324 Count.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
28330 if ((Count.getOpcode() == ISD::CTLZ ||
28331 Count.getOpcode() == ISD::CTLZ_ZERO_UNDEF) &&
28471 switch (V.getOpcode()) {
28505 if (Op.getOpcode() == ISD::SPLAT_VECTOR)
28532 if (Op.getOpcode() == ISD::SHL) {
28543 if ((Op.getOpcode() == ISD::SELECT || Op.getOpcode() == ISD::VSELECT) &&
28554 if ((Op.getOpcode() == ISD::UMIN || Op.getOpcode() == ISD::UMAX) &&
28564 return DAG.getNode(Op.getOpcode(), DL, VT, LogX, LogY);
28966 switch (C.getOpcode()) {
29029 if (Chain.getOpcode() == ISD::TokenFactor) {