| /netbsd-src/external/apache2/llvm/dist/clang/lib/AST/ |
| H A D | PrintfFormatString.cpp | 418 const PrintfSpecifierResult &FSR = ParsePrintfSpecifier(H, I, E, argIndex, in ParsePrintfString() local
423 if (FSR.shouldStop()) in ParsePrintfString()
427 if (!FSR.hasValue()) in ParsePrintfString()
430 if (!H.HandlePrintfSpecifier(FSR.getValue(), FSR.getStart(), in ParsePrintfString()
431 I - FSR.getStart())) in ParsePrintfString()
448 const PrintfSpecifierResult &FSR = ParsePrintfSpecifier(H, I, E, argIndex, in ParseFormatStringHasSArg() local
453 if (FSR.shouldStop()) in ParseFormatStringHasSArg()
457 if (!FSR.hasValue()) in ParseFormatStringHasSArg()
459 const analyze_printf::PrintfSpecifier &FS = FSR.getValue(); in ParseFormatStringHasSArg()
474 const PrintfSpecifierResult &FSR = in parseFormatStringHasFormattingSpecifiers() local
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| H A D | ScanfFormatString.cpp | 549 const ScanfSpecifierResult &FSR = ParseScanfSpecifier(H, I, E, argIndex, in ParseScanfString() local
553 if (FSR.shouldStop()) in ParseScanfString()
557 if (!FSR.hasValue()) in ParseScanfString()
560 if (!H.HandleScanfSpecifier(FSR.getValue(), FSR.getStart(), in ParseScanfString()
561 I - FSR.getStart())) { in ParseScanfString()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 204 unsigned TSR, unsigned FR, unsigned FSR);
779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { in buildMux() argument
806 .addReg(FR, 0, FSR); in buildMux()
818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local
826 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()
835 FR = SR, FSR = SSR; in updatePhiNodes()
844 FP.PredR, TR, TSR, FR, FSR); in updatePhiNodes()
850 MuxSR = FSR; in updatePhiNodes()
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| /netbsd-src/lib/libc/arch/sparc64/gen/ |
| H A D | modf.S | 126 st %fsr, [%fp + BIAS - 4] ! %l5 = current FSR mode
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| /netbsd-src/lib/libc/arch/sparc/gen/ |
| H A D | modf.S | 131 st %fsr, [%fp - 4] ! %l5 = current FSR mode
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| /netbsd-src/sys/arch/arm/sociox/ |
| H A D | sni_i2c.c | 81 #define FSR 0x18 /* bus clock frequency */ macro
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| /netbsd-src/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | ia64-ic.tbl | 82 mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR]
151 mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR]
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| H A D | ia64-waw.tbl | 27 AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
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| H A D | ia64-raw.tbl | 23 AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF
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| /netbsd-src/external/gpl3/gdb/dist/opcodes/ |
| H A D | ia64-ic.tbl | 82 mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR]
151 mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR]
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| H A D | ia64-waw.tbl | 27 AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
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| H A D | ia64-raw.tbl | 23 AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF
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| /netbsd-src/external/gpl3/gdb.old/dist/opcodes/ |
| H A D | ia64-ic.tbl | 82 mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR]
151 mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR]
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| H A D | ia64-waw.tbl | 27 AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
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| H A D | ia64-raw.tbl | 23 AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF
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| /netbsd-src/external/gpl3/binutils/dist/opcodes/ |
| H A D | ia64-ic.tbl | 82 mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR]
151 mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR]
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| H A D | ia64-waw.tbl | 27 AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
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| H A D | ia64-raw.tbl | 23 AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 62 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
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| H A D | SparcInstrInfo.td | 553 let Defs = [FSR] in {
616 let Defs = [FSR] in {
629 let rd = 1, Defs = [FSR] in {
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 66 FSR, enumerator
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| H A D | RISCVInstrInfoB.td | 27 def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
267 def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
835 (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
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| H A D | RISCVISelLowering.cpp | 2017 unsigned Opc = Op.getOpcode() == ISD::FSHL ? RISCVISD::FSL : RISCVISD::FSR; in LowerOperation()
5595 case RISCVISD::FSR: { in PerformDAGCombine()
7910 NODE_NAME_CASE(FSR) in getTargetNodeName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 1019 case Sparc::FSR: in parseSparcAsmOperand()
1156 RegNo = Sparc::FSR; in matchRegisterName()
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| /netbsd-src/external/gpl3/gdb/dist/sim/arm/ |
| H A D | ChangeLog-2021 | 1081 * armcopro.c (XScale_check_memacc): Set the FSR and FAR registers
1216 (XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
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