xref: /netbsd-src/lib/libc/arch/sparc64/gen/modf.S (revision 4d12bfcd155352508213ace5ccc59ce930ea2974)
1*4d12bfcdSjoerg/*	$NetBSD: modf.S,v 1.5 2013/09/12 15:36:16 joerg Exp $	*/
2cf009bccSeeh
3cf009bccSeeh/*
4cf009bccSeeh * Copyright (c) 1992, 1993
5cf009bccSeeh *	The Regents of the University of California.  All rights reserved.
6cf009bccSeeh *
7cf009bccSeeh * This software was developed by the Computer Systems Engineering group
8cf009bccSeeh * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9cf009bccSeeh * contributed to Berkeley.
10cf009bccSeeh *
11cf009bccSeeh * Redistribution and use in source and binary forms, with or without
12cf009bccSeeh * modification, are permitted provided that the following conditions
13cf009bccSeeh * are met:
14cf009bccSeeh * 1. Redistributions of source code must retain the above copyright
15cf009bccSeeh *    notice, this list of conditions and the following disclaimer.
16cf009bccSeeh * 2. Redistributions in binary form must reproduce the above copyright
17cf009bccSeeh *    notice, this list of conditions and the following disclaimer in the
18cf009bccSeeh *    documentation and/or other materials provided with the distribution.
19eb7c1594Sagc * 3. Neither the name of the University nor the names of its contributors
20cf009bccSeeh *    may be used to endorse or promote products derived from this software
21cf009bccSeeh *    without specific prior written permission.
22cf009bccSeeh *
23cf009bccSeeh * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24cf009bccSeeh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25cf009bccSeeh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26cf009bccSeeh * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27cf009bccSeeh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28cf009bccSeeh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29cf009bccSeeh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30cf009bccSeeh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31cf009bccSeeh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32cf009bccSeeh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33cf009bccSeeh * SUCH DAMAGE.
34cf009bccSeeh *
35cf009bccSeeh * from: Header: modf.s,v 1.3 92/06/20 00:00:54 torek Exp
36cf009bccSeeh */
37cf009bccSeeh
38cf009bccSeeh#include <machine/asm.h>
39cf009bccSeeh#if defined(LIBC_SCCS) && !defined(lint)
40cf009bccSeeh#if 0
41cf009bccSeeh	.asciz "@(#)modf.s	8.1 (Berkeley) 6/4/93"
42cf009bccSeeh#else
43*4d12bfcdSjoerg	RCSID("$NetBSD: modf.S,v 1.5 2013/09/12 15:36:16 joerg Exp $")
44cf009bccSeeh#endif
45cf009bccSeeh#endif /* LIBC_SCCS and not lint */
46cf009bccSeeh
47cf009bccSeeh#include <machine/fsr.h>
48cf009bccSeeh
49cf009bccSeeh/*
50cf009bccSeeh * double modf(double val, double *iptr)
51cf009bccSeeh *
52cf009bccSeeh * Returns the fractional part of `val', storing the integer part of
53cf009bccSeeh * `val' in *iptr.  Both *iptr and the return value have the same sign
54cf009bccSeeh * as `val'.
55cf009bccSeeh *
56cf009bccSeeh * Method:
57cf009bccSeeh *
58cf009bccSeeh * We use the fpu's normalization hardware to compute the integer portion
59cf009bccSeeh * of the double precision argument.  Sun IEEE double precision numbers
60cf009bccSeeh * have 52 bits of mantissa, 11 bits of exponent, and one bit of sign,
61cf009bccSeeh * with the sign occupying bit 31 of word 0, and the exponent bits 30:20
62cf009bccSeeh * of word 0.  Thus, values >= 2^52 are by definition integers.
63cf009bccSeeh *
64cf009bccSeeh * If we take a value that is in the range [+0..2^52) and add 2^52, all
65cf009bccSeeh * of the fractional bits fall out and all of the integer bits are summed
66cf009bccSeeh * with 2^52.  If we then subtract 2^52, we get those integer bits back.
67cf009bccSeeh * This must be done with rounding set to `towards 0' or `towards -inf'.
68cf009bccSeeh * `Toward -inf' fails when the value is 0 (we get -0 back)....
69cf009bccSeeh *
70cf009bccSeeh * Note that this method will work anywhere, but is machine dependent in
71cf009bccSeeh * various aspects.
72cf009bccSeeh *
73cf009bccSeeh * Stack usage:
7432ceb997Seeh *	4@[%fp + BIAS - 4]	saved %fsr
7532ceb997Seeh *	4@[%fp + BIAS - 8]	new %fsr with rounding set to `towards 0'
7632ceb997Seeh *	8@[%fp + BIAS - 16]	space for moving between %i and %f registers
77cf009bccSeeh * Register usage:
785d73d716Seeh *	%f0:f1		double val;
79cf009bccSeeh *	%l0		scratch
80cf009bccSeeh *	%l1		sign bit (0x80000000)
815d73d716Seeh *	%i1		double *iptr;
82cf009bccSeeh *	%f2:f3		`magic number' 2^52, in fpu registers
83cf009bccSeeh *	%f4:f5		double v, in fpu registers
845d73d716Seeh *	%f6:f7		double temp.
85cf009bccSeeh */
86cf009bccSeeh
87cf009bccSeeh	.align	8
88cf009bccSeehLmagic:
89cf009bccSeeh	.word	0x43300000	! sign = 0, exponent = 52 + 1023, mantissa = 0
90cf009bccSeeh	.word	0		! (i.e., .double 0r4503599627370496e+00)
91cf009bccSeeh
92cf009bccSeehL0:
93cf009bccSeeh	.word	0		! 0.0
94cf009bccSeeh	.word	0
95cf009bccSeeh
96cf009bccSeehENTRY(modf)
9732ceb997Seeh	save	%sp, -CC64FSZ-16, %sp
98cf009bccSeeh
99cf009bccSeeh	/*
1005d73d716Seeh	 * First, compute v = abs(val)
101cf009bccSeeh	 */
1025d73d716Seeh	fabsd	%f0, %f4		! %f4:f5 = v
1035d73d716Seeh	fcmped	%fcc1, %f0, %f4		! %fcc1 = (val == abs(val))
104*4d12bfcdSjoerg#ifdef __PIC__
105cf009bccSeeh	PICCY_SET(Lmagic, %l0, %o7)
106cf009bccSeeh	ldd	[%l0], %f2
107cf009bccSeeh#else
108cf009bccSeeh	sethi	%hi(Lmagic), %l0
109cf009bccSeeh	ldd	[%l0 + %lo(Lmagic)], %f2
110cf009bccSeeh#endif
111cf009bccSeeh
112cf009bccSeeh	/*
113cf009bccSeeh	 * Is %f4:f5 >= %f2:f3 ?  If so, it is all integer bits.
114cf009bccSeeh	 * It is probably less, though.
115cf009bccSeeh	 */
116cf009bccSeeh	fcmped	%f4, %f2
117cf009bccSeeh	fbuge	Lbig			! if >= (or unordered), go out
118cf009bccSeeh	nop
119cf009bccSeeh
120cf009bccSeeh	/*
121cf009bccSeeh	 * v < 2^52, so add 2^52, then subtract 2^52, but do it all
122cf009bccSeeh	 * with rounding set towards zero.  We leave any enabled
123cf009bccSeeh	 * traps enabled, but change the rounding mode.  This might
124cf009bccSeeh	 * not be so good.  Oh well....
125cf009bccSeeh	 */
12632ceb997Seeh	st	%fsr, [%fp + BIAS - 4]	! %l5 = current FSR mode
127cf009bccSeeh	set	FSR_RD, %l3		! %l3 = rounding direction mask
12832ceb997Seeh	ld	[%fp + BIAS - 4], %l5
129cf009bccSeeh	set	FSR_RD_RZ << FSR_RD_SHIFT, %l4
130cf009bccSeeh	andn	%l5, %l3, %l6
131cf009bccSeeh	or	%l6, %l4, %l6		! round towards zero, please
132cf009bccSeeh	and	%l5, %l3, %l5		! save original rounding mode
13332ceb997Seeh	st	%l6, [%fp + BIAS - 8]
13432ceb997Seeh	ld	[%fp + BIAS - 8], %fsr
135cf009bccSeeh
136cf009bccSeeh	faddd	%f4, %f2, %f4		! %f4:f5 += 2^52
137cf009bccSeeh	fsubd	%f4, %f2, %f4		! %f4:f5 -= 2^52
138cf009bccSeeh
139cf009bccSeeh	/*
140cf009bccSeeh	 * Restore %fsr, but leave exceptions accrued.
141cf009bccSeeh	 */
14232ceb997Seeh	st	%fsr, [%fp + BIAS - 4]
14332ceb997Seeh	ld	[%fp + BIAS - 4], %l6
144cf009bccSeeh	andn	%l6, %l3, %l6		! %l6 = %fsr & ~FSR_RD;
145cf009bccSeeh	or	%l5, %l6, %l5		! %l5 |= %l6;
14632ceb997Seeh	st	%l5, [%fp + BIAS - 4]
14732ceb997Seeh	ld	[%fp + BIAS - 4], %fsr	! restore %fsr, leaving accrued stuff
148cf009bccSeeh
149cf009bccSeeh	/*
150cf009bccSeeh	 * Now insert the original sign in %f4:f5.
1515d73d716Seeh	 * %fcc1 should still have the reults of (val == abs(val))
1525d73d716Seeh	 * from above, so we use a conditional move on %fcc1 to:
1535d73d716Seeh	 *
1545d73d716Seeh	 *	%f4 = (val == abs(val)) ? %f4 : -%f4
1555d73d716Seeh	 *
156cf009bccSeeh	 */
1575d73d716Seeh	fnegd	%f4, %f6
1585d73d716Seeh	fmovdnz	%fcc1, %f6, %f4
159cf009bccSeeh1:
160cf009bccSeeh
161cf009bccSeeh	/*
162cf009bccSeeh	 * The value in %f4:f5 is now the integer portion of the original
1635d73d716Seeh	 * argument.  We need to store this in *ival (%i1), subtract it
1645d73d716Seeh	 * from the original value argument (%d0), and return the result.
165cf009bccSeeh	 */
1665d73d716Seeh	std	%f4, [%i1]		! *ival = %f4:f5;
167cf009bccSeeh	fsubd	%f0, %f4, %f0		! %f0:f1 -= %f4:f5;
168cf009bccSeeh	ret
169cf009bccSeeh	restore
170cf009bccSeeh
171cf009bccSeehLbig:
172cf009bccSeeh	/*
173cf009bccSeeh	 * We get here if the original comparison of %f4:f5 (v) to
174cf009bccSeeh	 * %f2:f3 (2^52) came out `greater or unordered'.  In this
175cf009bccSeeh	 * case the integer part is the original value, and the
176cf009bccSeeh	 * fractional part is 0.
177cf009bccSeeh	 */
178*4d12bfcdSjoerg#ifdef __PIC__
179cf009bccSeeh	PICCY_SET(L0, %l0, %o7)
1805d73d716Seeh	std	%f0, [%i1]		! *ival = val;
181cf009bccSeeh	ldd	[%l0], %f0		! return 0.0;
182cf009bccSeeh#else
183cf009bccSeeh	sethi	%hi(L0), %l0
1845d73d716Seeh	std	%f0, [%i1]		! *ival = val;
185cf009bccSeeh	ldd	[%l0 + %lo(L0)], %f0	! return 0.0;
186cf009bccSeeh#endif
187cf009bccSeeh	ret
188cf009bccSeeh	restore
1895d73d716Seeh
190