Home
last modified time | relevance | path

Searched refs:vsll (Results 1 – 25 of 92) sorted by relevance

1234

/llvm-project/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-vsx.c25 vector signed long long vsll = { 255LL, -937LL }; variable
344 res_vsll = vec_div(vsll, vsll); in test1()
395 res_vsll = vec_perm(vsll, vsll, vuc); in test1()
438 res_vsll = vec_splat(vsll, 1); in test1()
456 res_vsi = vec_pack(vsll, vsll); in test1()
468 res_vsll = vec_vperm(vsll, vsll, vu in test1()
[all...]
H A Dbuiltins-ppc-p8vector.c30 vector signed long long vsll = { 1, 2 }; variable
73 res_vsll = vec_abs(vsll); in test1()
79 res_vsll = vec_add(vsll, vsll); in test1()
152 res_vsll = vec_mergee(vsll, vsll); in test1()
187 res_vbll = vec_cmpeq(vsll, vsll); in test1()
196 res_vbll = vec_cmpge(vsll, vsll); in test1()
[all...]
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Dvsll.ll7 declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8(
17 ; CHECK-NEXT: vsll.vv v8, v8, v9
20 %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8(
29 declare <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8(
41 ; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t
44 %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.nxv1i8(
54 declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8(
64 ; CHECK-NEXT: vsll.vv v8, v8, v9
67 %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8(
76 declare <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.nxv2i8(
[all …]
H A Dfixed-vectors-vshl-vp.ll15 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
27 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
37 ; CHECK-NEXT: vsll.vv v8, v8, v9
47 ; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t
59 ; CHECK-NEXT: vsll.vx v8, v8, a0
71 ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t
81 ; CHECK-NEXT: vsll.vi v8, v8, 3
93 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
105 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
115 ; CHECK-NEXT: vsll.vv v8, v8, v9
[all …]
H A Dvshl-sdnode.ll9 ; CHECK-NEXT: vsll.vx v8, v8, a0
21 ; CHECK-NEXT: vsll.vi v8, v8, 6
31 ; CHECK-NEXT: vsll.vx v8, v8, a0
43 ; CHECK-NEXT: vsll.vi v8, v8, 6
53 ; CHECK-NEXT: vsll.vx v8, v8, a0
65 ; CHECK-NEXT: vsll.vi v8, v8, 6
75 ; CHECK-NEXT: vsll.vx v8, v8, a0
87 ; CHECK-NEXT: vsll.vi v8, v8, 6
97 ; CHECK-NEXT: vsll.vx v8, v8, a0
109 ; CHECK-NEXT: vsll.vi v8, v8, 6
[all …]
H A Dfixed-vectors-bitreverse-vp.ll15 ; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
23 ; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
28 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
42 ; CHECK-NEXT: vsll.vi v9, v9, 4
49 ; CHECK-NEXT: vsll.vi v8, v8, 2
69 ; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
77 ; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
82 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
96 ; CHECK-NEXT: vsll.vi v9, v9, 4
103 ; CHECK-NEXT: vsll
[all...]
H A Dbitreverse-sdnode.ll11 ; CHECK-NEXT: vsll.vi v9, v8, 4
19 ; CHECK-NEXT: vsll.vi v8, v8, 2
42 ; CHECK-NEXT: vsll.vi v9, v8, 4
50 ; CHECK-NEXT: vsll.vi v8, v8, 2
73 ; CHECK-NEXT: vsll.vi v9, v8, 4
81 ; CHECK-NEXT: vsll.vi v8, v8, 2
104 ; CHECK-NEXT: vsll.vi v9, v8, 4
112 ; CHECK-NEXT: vsll.vi v8, v8, 2
135 ; CHECK-NEXT: vsll.vi v10, v8, 4
143 ; CHECK-NEXT: vsll
[all...]
H A Dbswap-sdnode.ll12 ; CHECK-NEXT: vsll.vi v8, v8, 8
31 ; CHECK-NEXT: vsll.vi v8, v8, 8
50 ; CHECK-NEXT: vsll.vi v8, v8, 8
69 ; CHECK-NEXT: vsll.vi v8, v8, 8
88 ; CHECK-NEXT: vsll.vi v8, v8, 8
107 ; CHECK-NEXT: vsll.vi v8, v8, 8
132 ; CHECK-NEXT: vsll.vi v10, v10, 8
133 ; CHECK-NEXT: vsll.vi v8, v8, 24
159 ; CHECK-NEXT: vsll.vi v10, v10, 8
160 ; CHECK-NEXT: vsll
[all...]
H A Dbitreverse-vp.ll19 ; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
27 ; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
32 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
52 ; CHECK-NEXT: vsll.vi v9, v9, 4
59 ; CHECK-NEXT: vsll.vi v8, v8, 2
85 ; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
93 ; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
98 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
118 ; CHECK-NEXT: vsll.vi v9, v9, 4
125 ; CHECK-NEXT: vsll
[all...]
H A Dfixed-vectors-bswap-vp.ll14 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
26 ; CHECK-NEXT: vsll.vi v8, v8, 8
40 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
52 ; CHECK-NEXT: vsll.vi v8, v8, 8
66 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
78 ; CHECK-NEXT: vsll.vi v8, v8, 8
92 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
104 ; CHECK-NEXT: vsll.vi v8, v8, 8
124 ; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
125 ; CHECK-NEXT: vsll
[all...]
H A Dfixed-vectors-bitreverse.ll15 ; CHECK-NEXT: vsll.vi v8, v8, 8
22 ; CHECK-NEXT: vsll.vi v8, v8, 4
29 ; CHECK-NEXT: vsll.vi v8, v8, 2
68 ; CHECK-NEXT: vsll.vi v8, v8, 24
69 ; CHECK-NEXT: vsll.vi v10, v10, 8
77 ; CHECK-NEXT: vsll.vi v8, v8, 4
84 ; CHECK-NEXT: vsll.vi v8, v8, 2
129 ; RV32-NEXT: vsll.vx v13, v8, a3
133 ; RV32-NEXT: vsll.vx v11, v11, a4
151 ; RV32-NEXT: vsll
[all...]
H A Dvshl-vp.ll16 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
30 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
40 ; CHECK-NEXT: vsll.vv v8, v8, v9
50 ; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t
62 ; CHECK-NEXT: vsll.vx v8, v8, a0
74 ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t
84 ; CHECK-NEXT: vsll.vi v8, v8, 3
96 ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
106 ; CHECK-NEXT: vsll.vv v8, v8, v9
116 ; CHECK-NEXT: vsll
[all...]
H A Dfixed-vectors-bswap.ll13 ; CHECK-NEXT: vsll.vi v8, v8, 8
45 ; CHECK-NEXT: vsll.vi v8, v8, 24
46 ; CHECK-NEXT: vsll.vi v10, v10, 8
87 ; RV32-NEXT: vsll.vx v13, v8, a2
91 ; RV32-NEXT: vsll.vx v11, v11, a3
99 ; RV32-NEXT: vsll.vi v8, v8, 24
100 ; RV32-NEXT: vsll.vi v9, v9, 8
132 ; RV64-NEXT: vsll.vi v10, v10, 8
133 ; RV64-NEXT: vsll.vi v12, v12, 24
135 ; RV64-NEXT: vsll
[all...]
H A Dbswap-vp.ll18 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
36 ; CHECK-NEXT: vsll.vi v8, v8, 8
56 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
74 ; CHECK-NEXT: vsll.vi v8, v8, 8
94 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
112 ; CHECK-NEXT: vsll.vi v8, v8, 8
132 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
150 ; CHECK-NEXT: vsll.vi v8, v8, 8
170 ; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
188 ; CHECK-NEXT: vsll
[all...]
H A Dfixed-vectors-fshr-fshl-vp.ll10 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
13 ; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
32 ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
44 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
47 ; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
66 ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
78 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
81 ; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
100 ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
112 ; CHECK-NEXT: vsll
[all...]
H A Dfixed-vectors-vwsll.ll17 ; CHECK-NEXT: vsll.vv v8, v10, v12
38 ; CHECK-NEXT: vsll.vv v8, v10, v12
58 ; CHECK-NEXT: vsll.vx v8, v10, a0
82 ; CHECK-NEXT: vsll.vv v8, v10, v12
108 ; CHECK-NEXT: vsll.vv v8, v10, v12
133 ; CHECK-NEXT: vsll.vv v8, v10, v12
158 ; CHECK-NEXT: vsll.vv v8, v10, v12
183 ; CHECK-NEXT: vsll.vv v8, v10, v12
208 ; CHECK-NEXT: vsll.vv v8, v10, v12
230 ; CHECK-NEXT: vsll
[all...]
H A Dushl_sat_vec.ll13 ; CHECK-NEXT: vsll.vv v10, v8, v9
26 ; CHECK-NEXT: vsll.vv v10, v8, v9
39 ; CHECK-NEXT: vsll.vv v10, v8, v9
52 ; CHECK-NEXT: vsll.vv v10, v8, v9
70 ; CHECK-NEXT: vsll.vv v12, v8, v10
83 ; CHECK-NEXT: vsll.vv v12, v8, v10
96 ; CHECK-NEXT: vsll.vv v12, v8, v10
109 ; CHECK-NEXT: vsll.vv v12, v8, v10
H A Dvwsll-sdnode.ll17 ; CHECK-NEXT: vsll.vv v8, v10, v12
38 ; CHECK-NEXT: vsll.vv v8, v10, v12
58 ; CHECK-NEXT: vsll.vx v8, v10, a0
82 ; CHECK-NEXT: vsll.vv v8, v10, v12
107 ; CHECK-NEXT: vsll.vv v8, v10, v12
132 ; CHECK-NEXT: vsll.vv v8, v10, v12
157 ; CHECK-NEXT: vsll.vv v8, v10, v12
182 ; CHECK-NEXT: vsll.vv v8, v10, v12
207 ; CHECK-NEXT: vsll.vv v8, v10, v12
229 ; CHECK-NEXT: vsll
[all...]
H A Dfixed-vectors-vrol.ll15 ; CHECK-NEXT: vsll.vv v10, v8, v10
37 ; CHECK-NEXT: vsll.vv v10, v8, v10
62 ; CHECK-NEXT: vsll.vv v10, v8, v10
84 ; CHECK-NEXT: vsll.vv v10, v8, v10
109 ; CHECK-NEXT: vsll.vv v10, v8, v10
131 ; CHECK-NEXT: vsll.vv v10, v8, v10
156 ; CHECK-NEXT: vsll.vv v10, v8, v10
178 ; CHECK-NEXT: vsll.vv v10, v8, v10
203 ; CHECK-NEXT: vsll.vv v10, v8, v10
225 ; CHECK-NEXT: vsll
[all...]
H A Dsplat-vector-split-i64-vl-sdnode.ll31 ; CHECK-NEXT: vsll.vx v18, v8, a2
35 ; CHECK-NEXT: vsll.vx v12, v12, a3
53 ; CHECK-NEXT: vsll.vi v8, v8, 24
54 ; CHECK-NEXT: vsll.vi v10, v10, 8
67 ; CHECK-NEXT: vsll.vi v8, v8, 4
72 ; CHECK-NEXT: vsll.vi v8, v8, 2
H A Dfshr-fshl-vp.ll10 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
13 ; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
32 ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
44 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
47 ; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
66 ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
78 ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
81 ; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
100 ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
112 ; CHECK-NEXT: vsll
[all...]
/llvm-project/llvm/test/MC/LoongArch/lsx/
H A Dsll.s6 vsll.b $vr31, $vr13, $vr5
7 # CHECK-INST: vsll.b $vr31, $vr13, $vr5
10 vsll.h $vr31, $vr1, $vr4
11 # CHECK-INST: vsll.h $vr31, $vr1, $vr4
14 vsll.w $vr8, $vr19, $vr19
15 # CHECK-INST: vsll.w $vr8, $vr19, $vr19
18 vsll.d $vr6, $vr25, $vr6
19 # CHECK-INST: vsll.d $vr6, $vr25, $vr6
/llvm-project/llvm/test/CodeGen/LoongArch/lsx/
H A Dintrinsic-sll.ll4 declare <16 x i8> @llvm.loongarch.lsx.vsll.b(<16 x i8>, <16 x i8>)
9 ; CHECK-NEXT: vsll.b $vr0, $vr0, $vr1
12 %res = call <16 x i8> @llvm.loongarch.lsx.vsll.b(<16 x i8> %va, <16 x i8> %vb)
16 declare <8 x i16> @llvm.loongarch.lsx.vsll.h(<8 x i16>, <8 x i16>)
21 ; CHECK-NEXT: vsll.h $vr0, $vr0, $vr1
24 %res = call <8 x i16> @llvm.loongarch.lsx.vsll.h(<8 x i16> %va, <8 x i16> %vb)
28 declare <4 x i32> @llvm.loongarch.lsx.vsll.w(<4 x i32>, <4 x i32>)
33 ; CHECK-NEXT: vsll.w $vr0, $vr0, $vr1
36 %res = call <4 x i32> @llvm.loongarch.lsx.vsll.w(<4 x i32> %va, <4 x i32> %vb)
40 declare <2 x i64> @llvm.loongarch.lsx.vsll.d(<2 x i64>, <2 x i64>)
[all …]
/llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/
H A Dvsll.ll16 ; CHECK-NEXT: vsll %v0, %v0, %v1
18 …%3 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvvl(<256 x double> %0, <256 x double> %1, i32…
23 declare <256 x double> @llvm.ve.vl.vsll.vvvl(<256 x double>, <256 x double>, i32)
31 ; CHECK-NEXT: vsll %v2, %v0, %v1
36 …%4 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvvvl(<256 x double> %0, <256 x double> %1, <2…
41 declare <256 x double> @llvm.ve.vl.vsll.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
49 ; CHECK-NEXT: vsll %v0, %v0, %s0
51 %3 = tail call fast <256 x double> @llvm.ve.vl.vsll.vvsl(<256 x double> %0, i64 %1, i32 256)
56 declare <256 x double> @llvm.ve.vl.vsll.vvsl(<256 x double>, i64, i32)
64 ; CHECK-NEXT: vsll %v1, %v0, %s0
[all …]
/llvm-project/llvm/test/MC/VE/
H A DVSLL.s6 # CHECK-INST: vsll %v11, %v22, %s20
8 vsll %v11, %v22, %s20 label
10 # CHECK-INST: vsll %vix, %vix, %vix
12 vsll %vix, %vix, %vix label

1234