xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
6
7declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
8
9define <1 x i8> @vrol_vv_v1i8(<1 x i8> %a, <1 x i8> %b) {
10; CHECK-LABEL: vrol_vv_v1i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
13; CHECK-NEXT:    vand.vi v10, v9, 7
14; CHECK-NEXT:    vrsub.vi v9, v9, 0
15; CHECK-NEXT:    vsll.vv v10, v8, v10
16; CHECK-NEXT:    vand.vi v9, v9, 7
17; CHECK-NEXT:    vsrl.vv v8, v8, v9
18; CHECK-NEXT:    vor.vv v8, v10, v8
19; CHECK-NEXT:    ret
20;
21; CHECK-ZVKB-LABEL: vrol_vv_v1i8:
22; CHECK-ZVKB:       # %bb.0:
23; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
24; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
25; CHECK-ZVKB-NEXT:    ret
26  %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b)
27  ret <1 x i8> %x
28}
29
30define <1 x i8> @vrol_vx_v1i8(<1 x i8> %a, i8 %b) {
31; CHECK-LABEL: vrol_vx_v1i8:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
34; CHECK-NEXT:    vmv.s.x v9, a0
35; CHECK-NEXT:    vand.vi v10, v9, 7
36; CHECK-NEXT:    vrsub.vi v9, v9, 0
37; CHECK-NEXT:    vsll.vv v10, v8, v10
38; CHECK-NEXT:    vand.vi v9, v9, 7
39; CHECK-NEXT:    vsrl.vv v8, v8, v9
40; CHECK-NEXT:    vor.vv v8, v10, v8
41; CHECK-NEXT:    ret
42;
43; CHECK-ZVKB-LABEL: vrol_vx_v1i8:
44; CHECK-ZVKB:       # %bb.0:
45; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
46; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
47; CHECK-ZVKB-NEXT:    ret
48  %b.head = insertelement <1 x i8> poison, i8 %b, i32 0
49  %b.splat = shufflevector <1 x i8> %b.head, <1 x i8> poison, <1 x i32> zeroinitializer
50  %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b.splat)
51  ret <1 x i8> %x
52}
53
54declare <2 x i8> @llvm.fshl.v2i8(<2 x i8>, <2 x i8>, <2 x i8>)
55
56define <2 x i8> @vrol_vv_v2i8(<2 x i8> %a, <2 x i8> %b) {
57; CHECK-LABEL: vrol_vv_v2i8:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
60; CHECK-NEXT:    vand.vi v10, v9, 7
61; CHECK-NEXT:    vrsub.vi v9, v9, 0
62; CHECK-NEXT:    vsll.vv v10, v8, v10
63; CHECK-NEXT:    vand.vi v9, v9, 7
64; CHECK-NEXT:    vsrl.vv v8, v8, v9
65; CHECK-NEXT:    vor.vv v8, v10, v8
66; CHECK-NEXT:    ret
67;
68; CHECK-ZVKB-LABEL: vrol_vv_v2i8:
69; CHECK-ZVKB:       # %bb.0:
70; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
71; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
72; CHECK-ZVKB-NEXT:    ret
73  %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b)
74  ret <2 x i8> %x
75}
76
77define <2 x i8> @vrol_vx_v2i8(<2 x i8> %a, i8 %b) {
78; CHECK-LABEL: vrol_vx_v2i8:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
81; CHECK-NEXT:    vmv.v.x v9, a0
82; CHECK-NEXT:    vand.vi v10, v9, 7
83; CHECK-NEXT:    vrsub.vi v9, v9, 0
84; CHECK-NEXT:    vsll.vv v10, v8, v10
85; CHECK-NEXT:    vand.vi v9, v9, 7
86; CHECK-NEXT:    vsrl.vv v8, v8, v9
87; CHECK-NEXT:    vor.vv v8, v10, v8
88; CHECK-NEXT:    ret
89;
90; CHECK-ZVKB-LABEL: vrol_vx_v2i8:
91; CHECK-ZVKB:       # %bb.0:
92; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
93; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
94; CHECK-ZVKB-NEXT:    ret
95  %b.head = insertelement <2 x i8> poison, i8 %b, i32 0
96  %b.splat = shufflevector <2 x i8> %b.head, <2 x i8> poison, <2 x i32> zeroinitializer
97  %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b.splat)
98  ret <2 x i8> %x
99}
100
101declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
102
103define <4 x i8> @vrol_vv_v4i8(<4 x i8> %a, <4 x i8> %b) {
104; CHECK-LABEL: vrol_vv_v4i8:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
107; CHECK-NEXT:    vand.vi v10, v9, 7
108; CHECK-NEXT:    vrsub.vi v9, v9, 0
109; CHECK-NEXT:    vsll.vv v10, v8, v10
110; CHECK-NEXT:    vand.vi v9, v9, 7
111; CHECK-NEXT:    vsrl.vv v8, v8, v9
112; CHECK-NEXT:    vor.vv v8, v10, v8
113; CHECK-NEXT:    ret
114;
115; CHECK-ZVKB-LABEL: vrol_vv_v4i8:
116; CHECK-ZVKB:       # %bb.0:
117; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
118; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
119; CHECK-ZVKB-NEXT:    ret
120  %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b)
121  ret <4 x i8> %x
122}
123
124define <4 x i8> @vrol_vx_v4i8(<4 x i8> %a, i8 %b) {
125; CHECK-LABEL: vrol_vx_v4i8:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
128; CHECK-NEXT:    vmv.v.x v9, a0
129; CHECK-NEXT:    vand.vi v10, v9, 7
130; CHECK-NEXT:    vrsub.vi v9, v9, 0
131; CHECK-NEXT:    vsll.vv v10, v8, v10
132; CHECK-NEXT:    vand.vi v9, v9, 7
133; CHECK-NEXT:    vsrl.vv v8, v8, v9
134; CHECK-NEXT:    vor.vv v8, v10, v8
135; CHECK-NEXT:    ret
136;
137; CHECK-ZVKB-LABEL: vrol_vx_v4i8:
138; CHECK-ZVKB:       # %bb.0:
139; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
140; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
141; CHECK-ZVKB-NEXT:    ret
142  %b.head = insertelement <4 x i8> poison, i8 %b, i32 0
143  %b.splat = shufflevector <4 x i8> %b.head, <4 x i8> poison, <4 x i32> zeroinitializer
144  %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b.splat)
145  ret <4 x i8> %x
146}
147
148declare <8 x i8> @llvm.fshl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>)
149
150define <8 x i8> @vrol_vv_v8i8(<8 x i8> %a, <8 x i8> %b) {
151; CHECK-LABEL: vrol_vv_v8i8:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
154; CHECK-NEXT:    vand.vi v10, v9, 7
155; CHECK-NEXT:    vrsub.vi v9, v9, 0
156; CHECK-NEXT:    vsll.vv v10, v8, v10
157; CHECK-NEXT:    vand.vi v9, v9, 7
158; CHECK-NEXT:    vsrl.vv v8, v8, v9
159; CHECK-NEXT:    vor.vv v8, v10, v8
160; CHECK-NEXT:    ret
161;
162; CHECK-ZVKB-LABEL: vrol_vv_v8i8:
163; CHECK-ZVKB:       # %bb.0:
164; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
165; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
166; CHECK-ZVKB-NEXT:    ret
167  %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b)
168  ret <8 x i8> %x
169}
170
171define <8 x i8> @vrol_vx_v8i8(<8 x i8> %a, i8 %b) {
172; CHECK-LABEL: vrol_vx_v8i8:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
175; CHECK-NEXT:    vmv.v.x v9, a0
176; CHECK-NEXT:    vand.vi v10, v9, 7
177; CHECK-NEXT:    vrsub.vi v9, v9, 0
178; CHECK-NEXT:    vsll.vv v10, v8, v10
179; CHECK-NEXT:    vand.vi v9, v9, 7
180; CHECK-NEXT:    vsrl.vv v8, v8, v9
181; CHECK-NEXT:    vor.vv v8, v10, v8
182; CHECK-NEXT:    ret
183;
184; CHECK-ZVKB-LABEL: vrol_vx_v8i8:
185; CHECK-ZVKB:       # %bb.0:
186; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
187; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
188; CHECK-ZVKB-NEXT:    ret
189  %b.head = insertelement <8 x i8> poison, i8 %b, i32 0
190  %b.splat = shufflevector <8 x i8> %b.head, <8 x i8> poison, <8 x i32> zeroinitializer
191  %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b.splat)
192  ret <8 x i8> %x
193}
194
195declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
196
197define <16 x i8> @vrol_vv_v16i8(<16 x i8> %a, <16 x i8> %b) {
198; CHECK-LABEL: vrol_vv_v16i8:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
201; CHECK-NEXT:    vand.vi v10, v9, 7
202; CHECK-NEXT:    vrsub.vi v9, v9, 0
203; CHECK-NEXT:    vsll.vv v10, v8, v10
204; CHECK-NEXT:    vand.vi v9, v9, 7
205; CHECK-NEXT:    vsrl.vv v8, v8, v9
206; CHECK-NEXT:    vor.vv v8, v10, v8
207; CHECK-NEXT:    ret
208;
209; CHECK-ZVKB-LABEL: vrol_vv_v16i8:
210; CHECK-ZVKB:       # %bb.0:
211; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
212; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
213; CHECK-ZVKB-NEXT:    ret
214  %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b)
215  ret <16 x i8> %x
216}
217
218define <16 x i8> @vrol_vx_v16i8(<16 x i8> %a, i8 %b) {
219; CHECK-LABEL: vrol_vx_v16i8:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
222; CHECK-NEXT:    vmv.v.x v9, a0
223; CHECK-NEXT:    vand.vi v10, v9, 7
224; CHECK-NEXT:    vrsub.vi v9, v9, 0
225; CHECK-NEXT:    vsll.vv v10, v8, v10
226; CHECK-NEXT:    vand.vi v9, v9, 7
227; CHECK-NEXT:    vsrl.vv v8, v8, v9
228; CHECK-NEXT:    vor.vv v8, v10, v8
229; CHECK-NEXT:    ret
230;
231; CHECK-ZVKB-LABEL: vrol_vx_v16i8:
232; CHECK-ZVKB:       # %bb.0:
233; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
234; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
235; CHECK-ZVKB-NEXT:    ret
236  %b.head = insertelement <16 x i8> poison, i8 %b, i32 0
237  %b.splat = shufflevector <16 x i8> %b.head, <16 x i8> poison, <16 x i32> zeroinitializer
238  %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b.splat)
239  ret <16 x i8> %x
240}
241
242declare <32 x i8> @llvm.fshl.v32i8(<32 x i8>, <32 x i8>, <32 x i8>)
243
244define <32 x i8> @vrol_vv_v32i8(<32 x i8> %a, <32 x i8> %b) {
245; CHECK-LABEL: vrol_vv_v32i8:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    li a0, 32
248; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
249; CHECK-NEXT:    vand.vi v12, v10, 7
250; CHECK-NEXT:    vrsub.vi v10, v10, 0
251; CHECK-NEXT:    vsll.vv v12, v8, v12
252; CHECK-NEXT:    vand.vi v10, v10, 7
253; CHECK-NEXT:    vsrl.vv v8, v8, v10
254; CHECK-NEXT:    vor.vv v8, v12, v8
255; CHECK-NEXT:    ret
256;
257; CHECK-ZVKB-LABEL: vrol_vv_v32i8:
258; CHECK-ZVKB:       # %bb.0:
259; CHECK-ZVKB-NEXT:    li a0, 32
260; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
261; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
262; CHECK-ZVKB-NEXT:    ret
263  %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b)
264  ret <32 x i8> %x
265}
266
267define <32 x i8> @vrol_vx_v32i8(<32 x i8> %a, i8 %b) {
268; CHECK-LABEL: vrol_vx_v32i8:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    li a1, 32
271; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
272; CHECK-NEXT:    vmv.v.x v10, a0
273; CHECK-NEXT:    vand.vi v12, v10, 7
274; CHECK-NEXT:    vrsub.vi v10, v10, 0
275; CHECK-NEXT:    vsll.vv v12, v8, v12
276; CHECK-NEXT:    vand.vi v10, v10, 7
277; CHECK-NEXT:    vsrl.vv v8, v8, v10
278; CHECK-NEXT:    vor.vv v8, v12, v8
279; CHECK-NEXT:    ret
280;
281; CHECK-ZVKB-LABEL: vrol_vx_v32i8:
282; CHECK-ZVKB:       # %bb.0:
283; CHECK-ZVKB-NEXT:    li a1, 32
284; CHECK-ZVKB-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
285; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
286; CHECK-ZVKB-NEXT:    ret
287  %b.head = insertelement <32 x i8> poison, i8 %b, i32 0
288  %b.splat = shufflevector <32 x i8> %b.head, <32 x i8> poison, <32 x i32> zeroinitializer
289  %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b.splat)
290  ret <32 x i8> %x
291}
292
293declare <64 x i8> @llvm.fshl.v64i8(<64 x i8>, <64 x i8>, <64 x i8>)
294
295define <64 x i8> @vrol_vv_v64i8(<64 x i8> %a, <64 x i8> %b) {
296; CHECK-LABEL: vrol_vv_v64i8:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    li a0, 64
299; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
300; CHECK-NEXT:    vand.vi v16, v12, 7
301; CHECK-NEXT:    vrsub.vi v12, v12, 0
302; CHECK-NEXT:    vsll.vv v16, v8, v16
303; CHECK-NEXT:    vand.vi v12, v12, 7
304; CHECK-NEXT:    vsrl.vv v8, v8, v12
305; CHECK-NEXT:    vor.vv v8, v16, v8
306; CHECK-NEXT:    ret
307;
308; CHECK-ZVKB-LABEL: vrol_vv_v64i8:
309; CHECK-ZVKB:       # %bb.0:
310; CHECK-ZVKB-NEXT:    li a0, 64
311; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
312; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
313; CHECK-ZVKB-NEXT:    ret
314  %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b)
315  ret <64 x i8> %x
316}
317
318define <64 x i8> @vrol_vx_v64i8(<64 x i8> %a, i8 %b) {
319; CHECK-LABEL: vrol_vx_v64i8:
320; CHECK:       # %bb.0:
321; CHECK-NEXT:    li a1, 64
322; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
323; CHECK-NEXT:    vmv.v.x v12, a0
324; CHECK-NEXT:    vand.vi v16, v12, 7
325; CHECK-NEXT:    vrsub.vi v12, v12, 0
326; CHECK-NEXT:    vsll.vv v16, v8, v16
327; CHECK-NEXT:    vand.vi v12, v12, 7
328; CHECK-NEXT:    vsrl.vv v8, v8, v12
329; CHECK-NEXT:    vor.vv v8, v16, v8
330; CHECK-NEXT:    ret
331;
332; CHECK-ZVKB-LABEL: vrol_vx_v64i8:
333; CHECK-ZVKB:       # %bb.0:
334; CHECK-ZVKB-NEXT:    li a1, 64
335; CHECK-ZVKB-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
336; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
337; CHECK-ZVKB-NEXT:    ret
338  %b.head = insertelement <64 x i8> poison, i8 %b, i32 0
339  %b.splat = shufflevector <64 x i8> %b.head, <64 x i8> poison, <64 x i32> zeroinitializer
340  %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b.splat)
341  ret <64 x i8> %x
342}
343
344declare <1 x i16> @llvm.fshl.v1i16(<1 x i16>, <1 x i16>, <1 x i16>)
345
346define <1 x i16> @vrol_vv_v1i16(<1 x i16> %a, <1 x i16> %b) {
347; CHECK-LABEL: vrol_vv_v1i16:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
350; CHECK-NEXT:    vand.vi v10, v9, 15
351; CHECK-NEXT:    vrsub.vi v9, v9, 0
352; CHECK-NEXT:    vsll.vv v10, v8, v10
353; CHECK-NEXT:    vand.vi v9, v9, 15
354; CHECK-NEXT:    vsrl.vv v8, v8, v9
355; CHECK-NEXT:    vor.vv v8, v10, v8
356; CHECK-NEXT:    ret
357;
358; CHECK-ZVKB-LABEL: vrol_vv_v1i16:
359; CHECK-ZVKB:       # %bb.0:
360; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
361; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
362; CHECK-ZVKB-NEXT:    ret
363  %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b)
364  ret <1 x i16> %x
365}
366
367define <1 x i16> @vrol_vx_v1i16(<1 x i16> %a, i16 %b) {
368; CHECK-LABEL: vrol_vx_v1i16:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
371; CHECK-NEXT:    vmv.s.x v9, a0
372; CHECK-NEXT:    vand.vi v10, v9, 15
373; CHECK-NEXT:    vrsub.vi v9, v9, 0
374; CHECK-NEXT:    vsll.vv v10, v8, v10
375; CHECK-NEXT:    vand.vi v9, v9, 15
376; CHECK-NEXT:    vsrl.vv v8, v8, v9
377; CHECK-NEXT:    vor.vv v8, v10, v8
378; CHECK-NEXT:    ret
379;
380; CHECK-ZVKB-LABEL: vrol_vx_v1i16:
381; CHECK-ZVKB:       # %bb.0:
382; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
383; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
384; CHECK-ZVKB-NEXT:    ret
385  %b.head = insertelement <1 x i16> poison, i16 %b, i32 0
386  %b.splat = shufflevector <1 x i16> %b.head, <1 x i16> poison, <1 x i32> zeroinitializer
387  %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b.splat)
388  ret <1 x i16> %x
389}
390
391declare <2 x i16> @llvm.fshl.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
392
393define <2 x i16> @vrol_vv_v2i16(<2 x i16> %a, <2 x i16> %b) {
394; CHECK-LABEL: vrol_vv_v2i16:
395; CHECK:       # %bb.0:
396; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
397; CHECK-NEXT:    vand.vi v10, v9, 15
398; CHECK-NEXT:    vrsub.vi v9, v9, 0
399; CHECK-NEXT:    vsll.vv v10, v8, v10
400; CHECK-NEXT:    vand.vi v9, v9, 15
401; CHECK-NEXT:    vsrl.vv v8, v8, v9
402; CHECK-NEXT:    vor.vv v8, v10, v8
403; CHECK-NEXT:    ret
404;
405; CHECK-ZVKB-LABEL: vrol_vv_v2i16:
406; CHECK-ZVKB:       # %bb.0:
407; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
408; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
409; CHECK-ZVKB-NEXT:    ret
410  %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b)
411  ret <2 x i16> %x
412}
413
414define <2 x i16> @vrol_vx_v2i16(<2 x i16> %a, i16 %b) {
415; CHECK-LABEL: vrol_vx_v2i16:
416; CHECK:       # %bb.0:
417; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
418; CHECK-NEXT:    vmv.v.x v9, a0
419; CHECK-NEXT:    vand.vi v10, v9, 15
420; CHECK-NEXT:    vrsub.vi v9, v9, 0
421; CHECK-NEXT:    vsll.vv v10, v8, v10
422; CHECK-NEXT:    vand.vi v9, v9, 15
423; CHECK-NEXT:    vsrl.vv v8, v8, v9
424; CHECK-NEXT:    vor.vv v8, v10, v8
425; CHECK-NEXT:    ret
426;
427; CHECK-ZVKB-LABEL: vrol_vx_v2i16:
428; CHECK-ZVKB:       # %bb.0:
429; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
430; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
431; CHECK-ZVKB-NEXT:    ret
432  %b.head = insertelement <2 x i16> poison, i16 %b, i32 0
433  %b.splat = shufflevector <2 x i16> %b.head, <2 x i16> poison, <2 x i32> zeroinitializer
434  %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b.splat)
435  ret <2 x i16> %x
436}
437
438declare <4 x i16> @llvm.fshl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
439
440define <4 x i16> @vrol_vv_v4i16(<4 x i16> %a, <4 x i16> %b) {
441; CHECK-LABEL: vrol_vv_v4i16:
442; CHECK:       # %bb.0:
443; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
444; CHECK-NEXT:    vand.vi v10, v9, 15
445; CHECK-NEXT:    vrsub.vi v9, v9, 0
446; CHECK-NEXT:    vsll.vv v10, v8, v10
447; CHECK-NEXT:    vand.vi v9, v9, 15
448; CHECK-NEXT:    vsrl.vv v8, v8, v9
449; CHECK-NEXT:    vor.vv v8, v10, v8
450; CHECK-NEXT:    ret
451;
452; CHECK-ZVKB-LABEL: vrol_vv_v4i16:
453; CHECK-ZVKB:       # %bb.0:
454; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
455; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
456; CHECK-ZVKB-NEXT:    ret
457  %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b)
458  ret <4 x i16> %x
459}
460
461define <4 x i16> @vrol_vx_v4i16(<4 x i16> %a, i16 %b) {
462; CHECK-LABEL: vrol_vx_v4i16:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
465; CHECK-NEXT:    vmv.v.x v9, a0
466; CHECK-NEXT:    vand.vi v10, v9, 15
467; CHECK-NEXT:    vrsub.vi v9, v9, 0
468; CHECK-NEXT:    vsll.vv v10, v8, v10
469; CHECK-NEXT:    vand.vi v9, v9, 15
470; CHECK-NEXT:    vsrl.vv v8, v8, v9
471; CHECK-NEXT:    vor.vv v8, v10, v8
472; CHECK-NEXT:    ret
473;
474; CHECK-ZVKB-LABEL: vrol_vx_v4i16:
475; CHECK-ZVKB:       # %bb.0:
476; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
477; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
478; CHECK-ZVKB-NEXT:    ret
479  %b.head = insertelement <4 x i16> poison, i16 %b, i32 0
480  %b.splat = shufflevector <4 x i16> %b.head, <4 x i16> poison, <4 x i32> zeroinitializer
481  %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b.splat)
482  ret <4 x i16> %x
483}
484
485declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
486
487define <8 x i16> @vrol_vv_v8i16(<8 x i16> %a, <8 x i16> %b) {
488; CHECK-LABEL: vrol_vv_v8i16:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
491; CHECK-NEXT:    vand.vi v10, v9, 15
492; CHECK-NEXT:    vrsub.vi v9, v9, 0
493; CHECK-NEXT:    vsll.vv v10, v8, v10
494; CHECK-NEXT:    vand.vi v9, v9, 15
495; CHECK-NEXT:    vsrl.vv v8, v8, v9
496; CHECK-NEXT:    vor.vv v8, v10, v8
497; CHECK-NEXT:    ret
498;
499; CHECK-ZVKB-LABEL: vrol_vv_v8i16:
500; CHECK-ZVKB:       # %bb.0:
501; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
502; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
503; CHECK-ZVKB-NEXT:    ret
504  %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b)
505  ret <8 x i16> %x
506}
507
508define <8 x i16> @vrol_vx_v8i16(<8 x i16> %a, i16 %b) {
509; CHECK-LABEL: vrol_vx_v8i16:
510; CHECK:       # %bb.0:
511; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
512; CHECK-NEXT:    vmv.v.x v9, a0
513; CHECK-NEXT:    vand.vi v10, v9, 15
514; CHECK-NEXT:    vrsub.vi v9, v9, 0
515; CHECK-NEXT:    vsll.vv v10, v8, v10
516; CHECK-NEXT:    vand.vi v9, v9, 15
517; CHECK-NEXT:    vsrl.vv v8, v8, v9
518; CHECK-NEXT:    vor.vv v8, v10, v8
519; CHECK-NEXT:    ret
520;
521; CHECK-ZVKB-LABEL: vrol_vx_v8i16:
522; CHECK-ZVKB:       # %bb.0:
523; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
524; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
525; CHECK-ZVKB-NEXT:    ret
526  %b.head = insertelement <8 x i16> poison, i16 %b, i32 0
527  %b.splat = shufflevector <8 x i16> %b.head, <8 x i16> poison, <8 x i32> zeroinitializer
528  %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b.splat)
529  ret <8 x i16> %x
530}
531
532declare <16 x i16> @llvm.fshl.v16i16(<16 x i16>, <16 x i16>, <16 x i16>)
533
534define <16 x i16> @vrol_vv_v16i16(<16 x i16> %a, <16 x i16> %b) {
535; CHECK-LABEL: vrol_vv_v16i16:
536; CHECK:       # %bb.0:
537; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
538; CHECK-NEXT:    vand.vi v12, v10, 15
539; CHECK-NEXT:    vrsub.vi v10, v10, 0
540; CHECK-NEXT:    vsll.vv v12, v8, v12
541; CHECK-NEXT:    vand.vi v10, v10, 15
542; CHECK-NEXT:    vsrl.vv v8, v8, v10
543; CHECK-NEXT:    vor.vv v8, v12, v8
544; CHECK-NEXT:    ret
545;
546; CHECK-ZVKB-LABEL: vrol_vv_v16i16:
547; CHECK-ZVKB:       # %bb.0:
548; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
549; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
550; CHECK-ZVKB-NEXT:    ret
551  %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b)
552  ret <16 x i16> %x
553}
554
555define <16 x i16> @vrol_vx_v16i16(<16 x i16> %a, i16 %b) {
556; CHECK-LABEL: vrol_vx_v16i16:
557; CHECK:       # %bb.0:
558; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
559; CHECK-NEXT:    vmv.v.x v10, a0
560; CHECK-NEXT:    vand.vi v12, v10, 15
561; CHECK-NEXT:    vrsub.vi v10, v10, 0
562; CHECK-NEXT:    vsll.vv v12, v8, v12
563; CHECK-NEXT:    vand.vi v10, v10, 15
564; CHECK-NEXT:    vsrl.vv v8, v8, v10
565; CHECK-NEXT:    vor.vv v8, v12, v8
566; CHECK-NEXT:    ret
567;
568; CHECK-ZVKB-LABEL: vrol_vx_v16i16:
569; CHECK-ZVKB:       # %bb.0:
570; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
571; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
572; CHECK-ZVKB-NEXT:    ret
573  %b.head = insertelement <16 x i16> poison, i16 %b, i32 0
574  %b.splat = shufflevector <16 x i16> %b.head, <16 x i16> poison, <16 x i32> zeroinitializer
575  %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b.splat)
576  ret <16 x i16> %x
577}
578
579declare <32 x i16> @llvm.fshl.v32i16(<32 x i16>, <32 x i16>, <32 x i16>)
580
581define <32 x i16> @vrol_vv_v32i16(<32 x i16> %a, <32 x i16> %b) {
582; CHECK-LABEL: vrol_vv_v32i16:
583; CHECK:       # %bb.0:
584; CHECK-NEXT:    li a0, 32
585; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
586; CHECK-NEXT:    vand.vi v16, v12, 15
587; CHECK-NEXT:    vrsub.vi v12, v12, 0
588; CHECK-NEXT:    vsll.vv v16, v8, v16
589; CHECK-NEXT:    vand.vi v12, v12, 15
590; CHECK-NEXT:    vsrl.vv v8, v8, v12
591; CHECK-NEXT:    vor.vv v8, v16, v8
592; CHECK-NEXT:    ret
593;
594; CHECK-ZVKB-LABEL: vrol_vv_v32i16:
595; CHECK-ZVKB:       # %bb.0:
596; CHECK-ZVKB-NEXT:    li a0, 32
597; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
598; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
599; CHECK-ZVKB-NEXT:    ret
600  %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b)
601  ret <32 x i16> %x
602}
603
604define <32 x i16> @vrol_vx_v32i16(<32 x i16> %a, i16 %b) {
605; CHECK-LABEL: vrol_vx_v32i16:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    li a1, 32
608; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
609; CHECK-NEXT:    vmv.v.x v12, a0
610; CHECK-NEXT:    vand.vi v16, v12, 15
611; CHECK-NEXT:    vrsub.vi v12, v12, 0
612; CHECK-NEXT:    vsll.vv v16, v8, v16
613; CHECK-NEXT:    vand.vi v12, v12, 15
614; CHECK-NEXT:    vsrl.vv v8, v8, v12
615; CHECK-NEXT:    vor.vv v8, v16, v8
616; CHECK-NEXT:    ret
617;
618; CHECK-ZVKB-LABEL: vrol_vx_v32i16:
619; CHECK-ZVKB:       # %bb.0:
620; CHECK-ZVKB-NEXT:    li a1, 32
621; CHECK-ZVKB-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
622; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
623; CHECK-ZVKB-NEXT:    ret
624  %b.head = insertelement <32 x i16> poison, i16 %b, i32 0
625  %b.splat = shufflevector <32 x i16> %b.head, <32 x i16> poison, <32 x i32> zeroinitializer
626  %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b.splat)
627  ret <32 x i16> %x
628}
629
630declare <1 x i32> @llvm.fshl.v1i32(<1 x i32>, <1 x i32>, <1 x i32>)
631
632define <1 x i32> @vrol_vv_v1i32(<1 x i32> %a, <1 x i32> %b) {
633; CHECK-LABEL: vrol_vv_v1i32:
634; CHECK:       # %bb.0:
635; CHECK-NEXT:    li a0, 31
636; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
637; CHECK-NEXT:    vrsub.vi v10, v9, 0
638; CHECK-NEXT:    vand.vx v9, v9, a0
639; CHECK-NEXT:    vand.vx v10, v10, a0
640; CHECK-NEXT:    vsll.vv v9, v8, v9
641; CHECK-NEXT:    vsrl.vv v8, v8, v10
642; CHECK-NEXT:    vor.vv v8, v9, v8
643; CHECK-NEXT:    ret
644;
645; CHECK-ZVKB-LABEL: vrol_vv_v1i32:
646; CHECK-ZVKB:       # %bb.0:
647; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
648; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
649; CHECK-ZVKB-NEXT:    ret
650  %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b)
651  ret <1 x i32> %x
652}
653
654define <1 x i32> @vrol_vx_v1i32(<1 x i32> %a, i32 %b) {
655; CHECK-LABEL: vrol_vx_v1i32:
656; CHECK:       # %bb.0:
657; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
658; CHECK-NEXT:    vmv.s.x v9, a0
659; CHECK-NEXT:    li a0, 31
660; CHECK-NEXT:    vand.vx v10, v9, a0
661; CHECK-NEXT:    vrsub.vi v9, v9, 0
662; CHECK-NEXT:    vsll.vv v10, v8, v10
663; CHECK-NEXT:    vand.vx v9, v9, a0
664; CHECK-NEXT:    vsrl.vv v8, v8, v9
665; CHECK-NEXT:    vor.vv v8, v10, v8
666; CHECK-NEXT:    ret
667;
668; CHECK-ZVKB-LABEL: vrol_vx_v1i32:
669; CHECK-ZVKB:       # %bb.0:
670; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
671; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
672; CHECK-ZVKB-NEXT:    ret
673  %b.head = insertelement <1 x i32> poison, i32 %b, i32 0
674  %b.splat = shufflevector <1 x i32> %b.head, <1 x i32> poison, <1 x i32> zeroinitializer
675  %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b.splat)
676  ret <1 x i32> %x
677}
678
679declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
680
681define <2 x i32> @vrol_vv_v2i32(<2 x i32> %a, <2 x i32> %b) {
682; CHECK-LABEL: vrol_vv_v2i32:
683; CHECK:       # %bb.0:
684; CHECK-NEXT:    li a0, 31
685; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
686; CHECK-NEXT:    vrsub.vi v10, v9, 0
687; CHECK-NEXT:    vand.vx v9, v9, a0
688; CHECK-NEXT:    vand.vx v10, v10, a0
689; CHECK-NEXT:    vsll.vv v9, v8, v9
690; CHECK-NEXT:    vsrl.vv v8, v8, v10
691; CHECK-NEXT:    vor.vv v8, v9, v8
692; CHECK-NEXT:    ret
693;
694; CHECK-ZVKB-LABEL: vrol_vv_v2i32:
695; CHECK-ZVKB:       # %bb.0:
696; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
697; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
698; CHECK-ZVKB-NEXT:    ret
699  %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b)
700  ret <2 x i32> %x
701}
702
703define <2 x i32> @vrol_vx_v2i32(<2 x i32> %a, i32 %b) {
704; CHECK-LABEL: vrol_vx_v2i32:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
707; CHECK-NEXT:    vmv.v.x v9, a0
708; CHECK-NEXT:    li a0, 31
709; CHECK-NEXT:    vand.vx v10, v9, a0
710; CHECK-NEXT:    vrsub.vi v9, v9, 0
711; CHECK-NEXT:    vsll.vv v10, v8, v10
712; CHECK-NEXT:    vand.vx v9, v9, a0
713; CHECK-NEXT:    vsrl.vv v8, v8, v9
714; CHECK-NEXT:    vor.vv v8, v10, v8
715; CHECK-NEXT:    ret
716;
717; CHECK-ZVKB-LABEL: vrol_vx_v2i32:
718; CHECK-ZVKB:       # %bb.0:
719; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
720; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
721; CHECK-ZVKB-NEXT:    ret
722  %b.head = insertelement <2 x i32> poison, i32 %b, i32 0
723  %b.splat = shufflevector <2 x i32> %b.head, <2 x i32> poison, <2 x i32> zeroinitializer
724  %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b.splat)
725  ret <2 x i32> %x
726}
727
728declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
729
730define <4 x i32> @vrol_vv_v4i32(<4 x i32> %a, <4 x i32> %b) {
731; CHECK-LABEL: vrol_vv_v4i32:
732; CHECK:       # %bb.0:
733; CHECK-NEXT:    li a0, 31
734; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
735; CHECK-NEXT:    vrsub.vi v10, v9, 0
736; CHECK-NEXT:    vand.vx v9, v9, a0
737; CHECK-NEXT:    vand.vx v10, v10, a0
738; CHECK-NEXT:    vsll.vv v9, v8, v9
739; CHECK-NEXT:    vsrl.vv v8, v8, v10
740; CHECK-NEXT:    vor.vv v8, v9, v8
741; CHECK-NEXT:    ret
742;
743; CHECK-ZVKB-LABEL: vrol_vv_v4i32:
744; CHECK-ZVKB:       # %bb.0:
745; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
746; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
747; CHECK-ZVKB-NEXT:    ret
748  %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b)
749  ret <4 x i32> %x
750}
751
752define <4 x i32> @vrol_vx_v4i32(<4 x i32> %a, i32 %b) {
753; CHECK-LABEL: vrol_vx_v4i32:
754; CHECK:       # %bb.0:
755; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
756; CHECK-NEXT:    vmv.v.x v9, a0
757; CHECK-NEXT:    li a0, 31
758; CHECK-NEXT:    vand.vx v10, v9, a0
759; CHECK-NEXT:    vrsub.vi v9, v9, 0
760; CHECK-NEXT:    vsll.vv v10, v8, v10
761; CHECK-NEXT:    vand.vx v9, v9, a0
762; CHECK-NEXT:    vsrl.vv v8, v8, v9
763; CHECK-NEXT:    vor.vv v8, v10, v8
764; CHECK-NEXT:    ret
765;
766; CHECK-ZVKB-LABEL: vrol_vx_v4i32:
767; CHECK-ZVKB:       # %bb.0:
768; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
769; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
770; CHECK-ZVKB-NEXT:    ret
771  %b.head = insertelement <4 x i32> poison, i32 %b, i32 0
772  %b.splat = shufflevector <4 x i32> %b.head, <4 x i32> poison, <4 x i32> zeroinitializer
773  %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b.splat)
774  ret <4 x i32> %x
775}
776
777declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
778
779define <8 x i32> @vrol_vv_v8i32(<8 x i32> %a, <8 x i32> %b) {
780; CHECK-LABEL: vrol_vv_v8i32:
781; CHECK:       # %bb.0:
782; CHECK-NEXT:    li a0, 31
783; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
784; CHECK-NEXT:    vrsub.vi v12, v10, 0
785; CHECK-NEXT:    vand.vx v10, v10, a0
786; CHECK-NEXT:    vand.vx v12, v12, a0
787; CHECK-NEXT:    vsll.vv v10, v8, v10
788; CHECK-NEXT:    vsrl.vv v8, v8, v12
789; CHECK-NEXT:    vor.vv v8, v10, v8
790; CHECK-NEXT:    ret
791;
792; CHECK-ZVKB-LABEL: vrol_vv_v8i32:
793; CHECK-ZVKB:       # %bb.0:
794; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
795; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
796; CHECK-ZVKB-NEXT:    ret
797  %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b)
798  ret <8 x i32> %x
799}
800
801define <8 x i32> @vrol_vx_v8i32(<8 x i32> %a, i32 %b) {
802; CHECK-LABEL: vrol_vx_v8i32:
803; CHECK:       # %bb.0:
804; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
805; CHECK-NEXT:    vmv.v.x v10, a0
806; CHECK-NEXT:    li a0, 31
807; CHECK-NEXT:    vand.vx v12, v10, a0
808; CHECK-NEXT:    vrsub.vi v10, v10, 0
809; CHECK-NEXT:    vsll.vv v12, v8, v12
810; CHECK-NEXT:    vand.vx v10, v10, a0
811; CHECK-NEXT:    vsrl.vv v8, v8, v10
812; CHECK-NEXT:    vor.vv v8, v12, v8
813; CHECK-NEXT:    ret
814;
815; CHECK-ZVKB-LABEL: vrol_vx_v8i32:
816; CHECK-ZVKB:       # %bb.0:
817; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
818; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
819; CHECK-ZVKB-NEXT:    ret
820  %b.head = insertelement <8 x i32> poison, i32 %b, i32 0
821  %b.splat = shufflevector <8 x i32> %b.head, <8 x i32> poison, <8 x i32> zeroinitializer
822  %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b.splat)
823  ret <8 x i32> %x
824}
825
826declare <16 x i32> @llvm.fshl.v16i32(<16 x i32>, <16 x i32>, <16 x i32>)
827
828define <16 x i32> @vrol_vv_v16i32(<16 x i32> %a, <16 x i32> %b) {
829; CHECK-LABEL: vrol_vv_v16i32:
830; CHECK:       # %bb.0:
831; CHECK-NEXT:    li a0, 31
832; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
833; CHECK-NEXT:    vrsub.vi v16, v12, 0
834; CHECK-NEXT:    vand.vx v12, v12, a0
835; CHECK-NEXT:    vand.vx v16, v16, a0
836; CHECK-NEXT:    vsll.vv v12, v8, v12
837; CHECK-NEXT:    vsrl.vv v8, v8, v16
838; CHECK-NEXT:    vor.vv v8, v12, v8
839; CHECK-NEXT:    ret
840;
841; CHECK-ZVKB-LABEL: vrol_vv_v16i32:
842; CHECK-ZVKB:       # %bb.0:
843; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
844; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
845; CHECK-ZVKB-NEXT:    ret
846  %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b)
847  ret <16 x i32> %x
848}
849
850define <16 x i32> @vrol_vx_v16i32(<16 x i32> %a, i32 %b) {
851; CHECK-LABEL: vrol_vx_v16i32:
852; CHECK:       # %bb.0:
853; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
854; CHECK-NEXT:    vmv.v.x v12, a0
855; CHECK-NEXT:    li a0, 31
856; CHECK-NEXT:    vand.vx v16, v12, a0
857; CHECK-NEXT:    vrsub.vi v12, v12, 0
858; CHECK-NEXT:    vsll.vv v16, v8, v16
859; CHECK-NEXT:    vand.vx v12, v12, a0
860; CHECK-NEXT:    vsrl.vv v8, v8, v12
861; CHECK-NEXT:    vor.vv v8, v16, v8
862; CHECK-NEXT:    ret
863;
864; CHECK-ZVKB-LABEL: vrol_vx_v16i32:
865; CHECK-ZVKB:       # %bb.0:
866; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
867; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
868; CHECK-ZVKB-NEXT:    ret
869  %b.head = insertelement <16 x i32> poison, i32 %b, i32 0
870  %b.splat = shufflevector <16 x i32> %b.head, <16 x i32> poison, <16 x i32> zeroinitializer
871  %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b.splat)
872  ret <16 x i32> %x
873}
874
875declare <1 x i64> @llvm.fshl.v1i64(<1 x i64>, <1 x i64>, <1 x i64>)
876
877define <1 x i64> @vrol_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {
878; CHECK-LABEL: vrol_vv_v1i64:
879; CHECK:       # %bb.0:
880; CHECK-NEXT:    li a0, 63
881; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
882; CHECK-NEXT:    vrsub.vi v10, v9, 0
883; CHECK-NEXT:    vand.vx v9, v9, a0
884; CHECK-NEXT:    vand.vx v10, v10, a0
885; CHECK-NEXT:    vsll.vv v9, v8, v9
886; CHECK-NEXT:    vsrl.vv v8, v8, v10
887; CHECK-NEXT:    vor.vv v8, v9, v8
888; CHECK-NEXT:    ret
889;
890; CHECK-ZVKB-LABEL: vrol_vv_v1i64:
891; CHECK-ZVKB:       # %bb.0:
892; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
893; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
894; CHECK-ZVKB-NEXT:    ret
895  %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)
896  ret <1 x i64> %x
897}
898
899define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) {
900; CHECK-LABEL: vrol_vx_v1i64:
901; CHECK:       # %bb.0:
902; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
903; CHECK-NEXT:    vmv.s.x v9, a0
904; CHECK-NEXT:    li a0, 63
905; CHECK-NEXT:    vand.vx v10, v9, a0
906; CHECK-NEXT:    vrsub.vi v9, v9, 0
907; CHECK-NEXT:    vsll.vv v10, v8, v10
908; CHECK-NEXT:    vand.vx v9, v9, a0
909; CHECK-NEXT:    vsrl.vv v8, v8, v9
910; CHECK-NEXT:    vor.vv v8, v10, v8
911; CHECK-NEXT:    ret
912;
913; CHECK-ZVKB-LABEL: vrol_vx_v1i64:
914; CHECK-ZVKB:       # %bb.0:
915; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
916; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
917; CHECK-ZVKB-NEXT:    ret
918  %b.head = insertelement <1 x i64> poison, i64 %b, i32 0
919  %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer
920  %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)
921  ret <1 x i64> %x
922}
923
924declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
925
926define <2 x i64> @vrol_vv_v2i64(<2 x i64> %a, <2 x i64> %b) {
927; CHECK-LABEL: vrol_vv_v2i64:
928; CHECK:       # %bb.0:
929; CHECK-NEXT:    li a0, 63
930; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
931; CHECK-NEXT:    vrsub.vi v10, v9, 0
932; CHECK-NEXT:    vand.vx v9, v9, a0
933; CHECK-NEXT:    vand.vx v10, v10, a0
934; CHECK-NEXT:    vsll.vv v9, v8, v9
935; CHECK-NEXT:    vsrl.vv v8, v8, v10
936; CHECK-NEXT:    vor.vv v8, v9, v8
937; CHECK-NEXT:    ret
938;
939; CHECK-ZVKB-LABEL: vrol_vv_v2i64:
940; CHECK-ZVKB:       # %bb.0:
941; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
942; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v9
943; CHECK-ZVKB-NEXT:    ret
944  %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b)
945  ret <2 x i64> %x
946}
947
948define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) {
949; RV32-LABEL: vrol_vx_v2i64:
950; RV32:       # %bb.0:
951; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
952; RV32-NEXT:    vmv.v.x v9, a0
953; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
954; RV32-NEXT:    vmv.v.i v10, 0
955; RV32-NEXT:    vwsub.vx v11, v10, a0
956; RV32-NEXT:    li a0, 63
957; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
958; RV32-NEXT:    vand.vx v9, v9, a0
959; RV32-NEXT:    vand.vx v10, v11, a0
960; RV32-NEXT:    vsrl.vv v10, v8, v10
961; RV32-NEXT:    vsll.vv v8, v8, v9
962; RV32-NEXT:    vor.vv v8, v8, v10
963; RV32-NEXT:    ret
964;
965; RV64-LABEL: vrol_vx_v2i64:
966; RV64:       # %bb.0:
967; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
968; RV64-NEXT:    vmv.v.x v9, a0
969; RV64-NEXT:    li a0, 63
970; RV64-NEXT:    vand.vx v10, v9, a0
971; RV64-NEXT:    vrsub.vi v9, v9, 0
972; RV64-NEXT:    vsll.vv v10, v8, v10
973; RV64-NEXT:    vand.vx v9, v9, a0
974; RV64-NEXT:    vsrl.vv v8, v8, v9
975; RV64-NEXT:    vor.vv v8, v10, v8
976; RV64-NEXT:    ret
977;
978; CHECK-ZVKB-LABEL: vrol_vx_v2i64:
979; CHECK-ZVKB:       # %bb.0:
980; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
981; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
982; CHECK-ZVKB-NEXT:    ret
983  %b.head = insertelement <2 x i64> poison, i64 %b, i32 0
984  %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer
985  %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)
986  ret <2 x i64> %x
987}
988
989declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
990
991define <4 x i64> @vrol_vv_v4i64(<4 x i64> %a, <4 x i64> %b) {
992; CHECK-LABEL: vrol_vv_v4i64:
993; CHECK:       # %bb.0:
994; CHECK-NEXT:    li a0, 63
995; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
996; CHECK-NEXT:    vrsub.vi v12, v10, 0
997; CHECK-NEXT:    vand.vx v10, v10, a0
998; CHECK-NEXT:    vand.vx v12, v12, a0
999; CHECK-NEXT:    vsll.vv v10, v8, v10
1000; CHECK-NEXT:    vsrl.vv v8, v8, v12
1001; CHECK-NEXT:    vor.vv v8, v10, v8
1002; CHECK-NEXT:    ret
1003;
1004; CHECK-ZVKB-LABEL: vrol_vv_v4i64:
1005; CHECK-ZVKB:       # %bb.0:
1006; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1007; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v10
1008; CHECK-ZVKB-NEXT:    ret
1009  %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b)
1010  ret <4 x i64> %x
1011}
1012
1013define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) {
1014; RV32-LABEL: vrol_vx_v4i64:
1015; RV32:       # %bb.0:
1016; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1017; RV32-NEXT:    vmv.v.x v10, a0
1018; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1019; RV32-NEXT:    vmv.v.i v12, 0
1020; RV32-NEXT:    vwsub.vx v14, v12, a0
1021; RV32-NEXT:    li a0, 63
1022; RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1023; RV32-NEXT:    vand.vx v10, v10, a0
1024; RV32-NEXT:    vand.vx v12, v14, a0
1025; RV32-NEXT:    vsrl.vv v12, v8, v12
1026; RV32-NEXT:    vsll.vv v8, v8, v10
1027; RV32-NEXT:    vor.vv v8, v8, v12
1028; RV32-NEXT:    ret
1029;
1030; RV64-LABEL: vrol_vx_v4i64:
1031; RV64:       # %bb.0:
1032; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1033; RV64-NEXT:    vmv.v.x v10, a0
1034; RV64-NEXT:    li a0, 63
1035; RV64-NEXT:    vand.vx v12, v10, a0
1036; RV64-NEXT:    vrsub.vi v10, v10, 0
1037; RV64-NEXT:    vsll.vv v12, v8, v12
1038; RV64-NEXT:    vand.vx v10, v10, a0
1039; RV64-NEXT:    vsrl.vv v8, v8, v10
1040; RV64-NEXT:    vor.vv v8, v12, v8
1041; RV64-NEXT:    ret
1042;
1043; CHECK-ZVKB-LABEL: vrol_vx_v4i64:
1044; CHECK-ZVKB:       # %bb.0:
1045; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1046; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
1047; CHECK-ZVKB-NEXT:    ret
1048  %b.head = insertelement <4 x i64> poison, i64 %b, i32 0
1049  %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer
1050  %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)
1051  ret <4 x i64> %x
1052}
1053
1054declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
1055
1056define <8 x i64> @vrol_vv_v8i64(<8 x i64> %a, <8 x i64> %b) {
1057; CHECK-LABEL: vrol_vv_v8i64:
1058; CHECK:       # %bb.0:
1059; CHECK-NEXT:    li a0, 63
1060; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1061; CHECK-NEXT:    vrsub.vi v16, v12, 0
1062; CHECK-NEXT:    vand.vx v12, v12, a0
1063; CHECK-NEXT:    vand.vx v16, v16, a0
1064; CHECK-NEXT:    vsll.vv v12, v8, v12
1065; CHECK-NEXT:    vsrl.vv v8, v8, v16
1066; CHECK-NEXT:    vor.vv v8, v12, v8
1067; CHECK-NEXT:    ret
1068;
1069; CHECK-ZVKB-LABEL: vrol_vv_v8i64:
1070; CHECK-ZVKB:       # %bb.0:
1071; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1072; CHECK-ZVKB-NEXT:    vrol.vv v8, v8, v12
1073; CHECK-ZVKB-NEXT:    ret
1074  %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b)
1075  ret <8 x i64> %x
1076}
1077
1078define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {
1079; RV32-LABEL: vrol_vx_v8i64:
1080; RV32:       # %bb.0:
1081; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1082; RV32-NEXT:    vmv.v.x v12, a0
1083; RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1084; RV32-NEXT:    vmv.v.i v16, 0
1085; RV32-NEXT:    vwsub.vx v20, v16, a0
1086; RV32-NEXT:    li a0, 63
1087; RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
1088; RV32-NEXT:    vand.vx v12, v12, a0
1089; RV32-NEXT:    vand.vx v16, v20, a0
1090; RV32-NEXT:    vsrl.vv v16, v8, v16
1091; RV32-NEXT:    vsll.vv v8, v8, v12
1092; RV32-NEXT:    vor.vv v8, v8, v16
1093; RV32-NEXT:    ret
1094;
1095; RV64-LABEL: vrol_vx_v8i64:
1096; RV64:       # %bb.0:
1097; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1098; RV64-NEXT:    vmv.v.x v12, a0
1099; RV64-NEXT:    li a0, 63
1100; RV64-NEXT:    vand.vx v16, v12, a0
1101; RV64-NEXT:    vrsub.vi v12, v12, 0
1102; RV64-NEXT:    vsll.vv v16, v8, v16
1103; RV64-NEXT:    vand.vx v12, v12, a0
1104; RV64-NEXT:    vsrl.vv v8, v8, v12
1105; RV64-NEXT:    vor.vv v8, v16, v8
1106; RV64-NEXT:    ret
1107;
1108; CHECK-ZVKB-LABEL: vrol_vx_v8i64:
1109; CHECK-ZVKB:       # %bb.0:
1110; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1111; CHECK-ZVKB-NEXT:    vrol.vx v8, v8, a0
1112; CHECK-ZVKB-NEXT:    ret
1113  %b.head = insertelement <8 x i64> poison, i64 %b, i32 0
1114  %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer
1115  %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
1116  ret <8 x i64> %x
1117}
1118