xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll (revision d85f1054fbb04c5299848bf81aa350442f9a56c7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV32
5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV64
6
7; ==============================================================================
8; i32 -> i64
9; ==============================================================================
10
11define <4 x i64> @vwsll_vv_v4i64_sext(<4 x i32> %a, <4 x i32> %b) {
12; CHECK-LABEL: vwsll_vv_v4i64_sext:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
15; CHECK-NEXT:    vzext.vf2 v10, v8
16; CHECK-NEXT:    vsext.vf2 v12, v9
17; CHECK-NEXT:    vsll.vv v8, v10, v12
18; CHECK-NEXT:    ret
19;
20; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_sext:
21; CHECK-ZVBB:       # %bb.0:
22; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
23; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
24; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
25; CHECK-ZVBB-NEXT:    ret
26  %x = zext <4 x i32> %a to <4 x i64>
27  %y = sext <4 x i32> %b to <4 x i64>
28  %z = shl <4 x i64> %x, %y
29  ret <4 x i64> %z
30}
31
32define <4 x i64> @vwsll_vv_v4i64_zext(<4 x i32> %a, <4 x i32> %b) {
33; CHECK-LABEL: vwsll_vv_v4i64_zext:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
36; CHECK-NEXT:    vzext.vf2 v10, v8
37; CHECK-NEXT:    vzext.vf2 v12, v9
38; CHECK-NEXT:    vsll.vv v8, v10, v12
39; CHECK-NEXT:    ret
40;
41; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_zext:
42; CHECK-ZVBB:       # %bb.0:
43; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
44; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
45; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
46; CHECK-ZVBB-NEXT:    ret
47  %x = zext <4 x i32> %a to <4 x i64>
48  %y = zext <4 x i32> %b to <4 x i64>
49  %z = shl <4 x i64> %x, %y
50  ret <4 x i64> %z
51}
52
53define <4 x i64> @vwsll_vx_i64_v4i64(<4 x i32> %a, i64 %b) {
54; CHECK-LABEL: vwsll_vx_i64_v4i64:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
57; CHECK-NEXT:    vzext.vf2 v10, v8
58; CHECK-NEXT:    vsll.vx v8, v10, a0
59; CHECK-NEXT:    ret
60;
61; CHECK-ZVBB-LABEL: vwsll_vx_i64_v4i64:
62; CHECK-ZVBB:       # %bb.0:
63; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
64; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
65; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
66; CHECK-ZVBB-NEXT:    ret
67  %head = insertelement <4 x i64> poison, i64 %b, i32 0
68  %splat = shufflevector <4 x i64> %head, <4 x i64> poison, <4 x i32> zeroinitializer
69  %x = zext <4 x i32> %a to <4 x i64>
70  %z = shl <4 x i64> %x, %splat
71  ret <4 x i64> %z
72}
73
74define <4 x i64> @vwsll_vx_i32_v4i64_sext(<4 x i32> %a, i32 %b) {
75; CHECK-LABEL: vwsll_vx_i32_v4i64_sext:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
78; CHECK-NEXT:    vmv.v.x v9, a0
79; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
80; CHECK-NEXT:    vzext.vf2 v10, v8
81; CHECK-NEXT:    vsext.vf2 v12, v9
82; CHECK-NEXT:    vsll.vv v8, v10, v12
83; CHECK-NEXT:    ret
84;
85; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_sext:
86; CHECK-ZVBB:       # %bb.0:
87; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
88; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
89; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
90; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
91; CHECK-ZVBB-NEXT:    ret
92  %head = insertelement <4 x i32> poison, i32 %b, i32 0
93  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
94  %x = zext <4 x i32> %a to <4 x i64>
95  %y = sext <4 x i32> %splat to <4 x i64>
96  %z = shl <4 x i64> %x, %y
97  ret <4 x i64> %z
98}
99
100define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) {
101; CHECK-LABEL: vwsll_vx_i32_v4i64_zext:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
104; CHECK-NEXT:    vmv.v.x v9, a0
105; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
106; CHECK-NEXT:    vzext.vf2 v10, v8
107; CHECK-NEXT:    vzext.vf2 v12, v9
108; CHECK-NEXT:    vsll.vv v8, v10, v12
109; CHECK-NEXT:    ret
110;
111; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_zext:
112; CHECK-ZVBB:       # %bb.0:
113; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
114; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
115; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
116; CHECK-ZVBB-NEXT:    ret
117  %head = insertelement <4 x i32> poison, i32 %b, i32 0
118  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
119  %x = zext <4 x i32> %a to <4 x i64>
120  %y = zext <4 x i32> %splat to <4 x i64>
121  %z = shl <4 x i64> %x, %y
122  ret <4 x i64> %z
123}
124
125define <4 x i64> @vwsll_vx_i16_v4i64_sext(<4 x i32> %a, i16 %b) {
126; CHECK-LABEL: vwsll_vx_i16_v4i64_sext:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
129; CHECK-NEXT:    vmv.v.x v9, a0
130; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
131; CHECK-NEXT:    vzext.vf2 v10, v8
132; CHECK-NEXT:    vsext.vf4 v12, v9
133; CHECK-NEXT:    vsll.vv v8, v10, v12
134; CHECK-NEXT:    ret
135;
136; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_sext:
137; CHECK-ZVBB:       # %bb.0:
138; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
139; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
140; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
141; CHECK-ZVBB-NEXT:    ret
142  %head = insertelement <4 x i16> poison, i16 %b, i32 0
143  %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer
144  %x = zext <4 x i32> %a to <4 x i64>
145  %y = sext <4 x i16> %splat to <4 x i64>
146  %z = shl <4 x i64> %x, %y
147  ret <4 x i64> %z
148}
149
150define <4 x i64> @vwsll_vx_i16_v4i64_zext(<4 x i32> %a, i16 %b) {
151; CHECK-LABEL: vwsll_vx_i16_v4i64_zext:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
154; CHECK-NEXT:    vmv.v.x v9, a0
155; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
156; CHECK-NEXT:    vzext.vf2 v10, v8
157; CHECK-NEXT:    vzext.vf4 v12, v9
158; CHECK-NEXT:    vsll.vv v8, v10, v12
159; CHECK-NEXT:    ret
160;
161; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_zext:
162; CHECK-ZVBB:       # %bb.0:
163; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
164; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
165; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
166; CHECK-ZVBB-NEXT:    ret
167  %head = insertelement <4 x i16> poison, i16 %b, i32 0
168  %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer
169  %x = zext <4 x i32> %a to <4 x i64>
170  %y = zext <4 x i16> %splat to <4 x i64>
171  %z = shl <4 x i64> %x, %y
172  ret <4 x i64> %z
173}
174
175define <4 x i64> @vwsll_vx_i8_v4i64_sext(<4 x i32> %a, i8 %b) {
176; CHECK-LABEL: vwsll_vx_i8_v4i64_sext:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
179; CHECK-NEXT:    vmv.v.x v9, a0
180; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
181; CHECK-NEXT:    vzext.vf2 v10, v8
182; CHECK-NEXT:    vsext.vf8 v12, v9
183; CHECK-NEXT:    vsll.vv v8, v10, v12
184; CHECK-NEXT:    ret
185;
186; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_sext:
187; CHECK-ZVBB:       # %bb.0:
188; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
189; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
190; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
191; CHECK-ZVBB-NEXT:    ret
192  %head = insertelement <4 x i8> poison, i8 %b, i32 0
193  %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer
194  %x = zext <4 x i32> %a to <4 x i64>
195  %y = sext <4 x i8> %splat to <4 x i64>
196  %z = shl <4 x i64> %x, %y
197  ret <4 x i64> %z
198}
199
200define <4 x i64> @vwsll_vx_i8_v4i64_zext(<4 x i32> %a, i8 %b) {
201; CHECK-LABEL: vwsll_vx_i8_v4i64_zext:
202; CHECK:       # %bb.0:
203; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
204; CHECK-NEXT:    vmv.v.x v9, a0
205; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
206; CHECK-NEXT:    vzext.vf2 v10, v8
207; CHECK-NEXT:    vzext.vf8 v12, v9
208; CHECK-NEXT:    vsll.vv v8, v10, v12
209; CHECK-NEXT:    ret
210;
211; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_zext:
212; CHECK-ZVBB:       # %bb.0:
213; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
214; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
215; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
216; CHECK-ZVBB-NEXT:    ret
217  %head = insertelement <4 x i8> poison, i8 %b, i32 0
218  %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer
219  %x = zext <4 x i32> %a to <4 x i64>
220  %y = zext <4 x i8> %splat to <4 x i64>
221  %z = shl <4 x i64> %x, %y
222  ret <4 x i64> %z
223}
224
225define <4 x i64> @vwsll_vi_v4i64(<4 x i32> %a) {
226; CHECK-LABEL: vwsll_vi_v4i64:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
229; CHECK-NEXT:    vzext.vf2 v10, v8
230; CHECK-NEXT:    vsll.vi v8, v10, 2
231; CHECK-NEXT:    ret
232;
233; CHECK-ZVBB-LABEL: vwsll_vi_v4i64:
234; CHECK-ZVBB:       # %bb.0:
235; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
236; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
237; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
238; CHECK-ZVBB-NEXT:    ret
239  %x = zext <4 x i32> %a to <4 x i64>
240  %z = shl <4 x i64> %x, splat (i64 2)
241  ret <4 x i64> %z
242}
243
244; ==============================================================================
245; i16 -> i32
246; ==============================================================================
247
248define <8 x i32> @vwsll_vv_v8i32_sext(<8 x i16> %a, <8 x i16> %b) {
249; CHECK-LABEL: vwsll_vv_v8i32_sext:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
252; CHECK-NEXT:    vzext.vf2 v10, v8
253; CHECK-NEXT:    vsext.vf2 v12, v9
254; CHECK-NEXT:    vsll.vv v8, v10, v12
255; CHECK-NEXT:    ret
256;
257; CHECK-ZVBB-LABEL: vwsll_vv_v8i32_sext:
258; CHECK-ZVBB:       # %bb.0:
259; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
260; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
261; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
262; CHECK-ZVBB-NEXT:    ret
263  %x = zext <8 x i16> %a to <8 x i32>
264  %y = sext <8 x i16> %b to <8 x i32>
265  %z = shl <8 x i32> %x, %y
266  ret <8 x i32> %z
267}
268
269define <8 x i32> @vwsll_vv_v8i32_zext(<8 x i16> %a, <8 x i16> %b) {
270; CHECK-LABEL: vwsll_vv_v8i32_zext:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
273; CHECK-NEXT:    vzext.vf2 v10, v8
274; CHECK-NEXT:    vzext.vf2 v12, v9
275; CHECK-NEXT:    vsll.vv v8, v10, v12
276; CHECK-NEXT:    ret
277;
278; CHECK-ZVBB-LABEL: vwsll_vv_v8i32_zext:
279; CHECK-ZVBB:       # %bb.0:
280; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
281; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
282; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
283; CHECK-ZVBB-NEXT:    ret
284  %x = zext <8 x i16> %a to <8 x i32>
285  %y = zext <8 x i16> %b to <8 x i32>
286  %z = shl <8 x i32> %x, %y
287  ret <8 x i32> %z
288}
289
290define <8 x i32> @vwsll_vx_i64_v8i32(<8 x i16> %a, i64 %b) {
291; CHECK-LABEL: vwsll_vx_i64_v8i32:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
294; CHECK-NEXT:    vzext.vf2 v10, v8
295; CHECK-NEXT:    vsll.vx v8, v10, a0
296; CHECK-NEXT:    ret
297;
298; CHECK-ZVBB-LABEL: vwsll_vx_i64_v8i32:
299; CHECK-ZVBB:       # %bb.0:
300; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
301; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
302; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
303; CHECK-ZVBB-NEXT:    ret
304  %head = insertelement <8 x i64> poison, i64 %b, i32 0
305  %splat = shufflevector <8 x i64> %head, <8 x i64> poison, <8 x i32> zeroinitializer
306  %x = zext <8 x i16> %a to <8 x i32>
307  %y = trunc <8 x i64> %splat to <8 x i32>
308  %z = shl <8 x i32> %x, %y
309  ret <8 x i32> %z
310}
311
312define <8 x i32> @vwsll_vx_i32_v8i32(<8 x i16> %a, i32 %b) {
313; CHECK-LABEL: vwsll_vx_i32_v8i32:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
316; CHECK-NEXT:    vzext.vf2 v10, v8
317; CHECK-NEXT:    vsll.vx v8, v10, a0
318; CHECK-NEXT:    ret
319;
320; CHECK-ZVBB-LABEL: vwsll_vx_i32_v8i32:
321; CHECK-ZVBB:       # %bb.0:
322; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
323; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
324; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
325; CHECK-ZVBB-NEXT:    ret
326  %head = insertelement <8 x i32> poison, i32 %b, i32 0
327  %splat = shufflevector <8 x i32> %head, <8 x i32> poison, <8 x i32> zeroinitializer
328  %x = zext <8 x i16> %a to <8 x i32>
329  %z = shl <8 x i32> %x, %splat
330  ret <8 x i32> %z
331}
332
333define <8 x i32> @vwsll_vx_i16_v8i32_sext(<8 x i16> %a, i16 %b) {
334; CHECK-LABEL: vwsll_vx_i16_v8i32_sext:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
337; CHECK-NEXT:    vmv.v.x v9, a0
338; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
339; CHECK-NEXT:    vzext.vf2 v10, v8
340; CHECK-NEXT:    vsext.vf2 v12, v9
341; CHECK-NEXT:    vsll.vv v8, v10, v12
342; CHECK-NEXT:    ret
343;
344; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_sext:
345; CHECK-ZVBB:       # %bb.0:
346; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
347; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
348; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
349; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
350; CHECK-ZVBB-NEXT:    ret
351  %head = insertelement <8 x i16> poison, i16 %b, i32 0
352  %splat = shufflevector <8 x i16> %head, <8 x i16> poison, <8 x i32> zeroinitializer
353  %x = zext <8 x i16> %a to <8 x i32>
354  %y = sext <8 x i16> %splat to <8 x i32>
355  %z = shl <8 x i32> %x, %y
356  ret <8 x i32> %z
357}
358
359define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) {
360; CHECK-LABEL: vwsll_vx_i16_v8i32_zext:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
363; CHECK-NEXT:    vmv.v.x v9, a0
364; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
365; CHECK-NEXT:    vzext.vf2 v10, v8
366; CHECK-NEXT:    vzext.vf2 v12, v9
367; CHECK-NEXT:    vsll.vv v8, v10, v12
368; CHECK-NEXT:    ret
369;
370; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_zext:
371; CHECK-ZVBB:       # %bb.0:
372; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
373; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
374; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
375; CHECK-ZVBB-NEXT:    ret
376  %head = insertelement <8 x i16> poison, i16 %b, i32 0
377  %splat = shufflevector <8 x i16> %head, <8 x i16> poison, <8 x i32> zeroinitializer
378  %x = zext <8 x i16> %a to <8 x i32>
379  %y = zext <8 x i16> %splat to <8 x i32>
380  %z = shl <8 x i32> %x, %y
381  ret <8 x i32> %z
382}
383
384define <8 x i32> @vwsll_vx_i8_v8i32_sext(<8 x i16> %a, i8 %b) {
385; CHECK-LABEL: vwsll_vx_i8_v8i32_sext:
386; CHECK:       # %bb.0:
387; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
388; CHECK-NEXT:    vmv.v.x v9, a0
389; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
390; CHECK-NEXT:    vzext.vf2 v10, v8
391; CHECK-NEXT:    vsext.vf4 v12, v9
392; CHECK-NEXT:    vsll.vv v8, v10, v12
393; CHECK-NEXT:    ret
394;
395; CHECK-ZVBB-LABEL: vwsll_vx_i8_v8i32_sext:
396; CHECK-ZVBB:       # %bb.0:
397; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
398; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
399; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
400; CHECK-ZVBB-NEXT:    ret
401  %head = insertelement <8 x i8> poison, i8 %b, i32 0
402  %splat = shufflevector <8 x i8> %head, <8 x i8> poison, <8 x i32> zeroinitializer
403  %x = zext <8 x i16> %a to <8 x i32>
404  %y = sext <8 x i8> %splat to <8 x i32>
405  %z = shl <8 x i32> %x, %y
406  ret <8 x i32> %z
407}
408
409define <8 x i32> @vwsll_vx_i8_v8i32_zext(<8 x i16> %a, i8 %b) {
410; CHECK-LABEL: vwsll_vx_i8_v8i32_zext:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
413; CHECK-NEXT:    vmv.v.x v9, a0
414; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
415; CHECK-NEXT:    vzext.vf2 v10, v8
416; CHECK-NEXT:    vzext.vf4 v12, v9
417; CHECK-NEXT:    vsll.vv v8, v10, v12
418; CHECK-NEXT:    ret
419;
420; CHECK-ZVBB-LABEL: vwsll_vx_i8_v8i32_zext:
421; CHECK-ZVBB:       # %bb.0:
422; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
423; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
424; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
425; CHECK-ZVBB-NEXT:    ret
426  %head = insertelement <8 x i8> poison, i8 %b, i32 0
427  %splat = shufflevector <8 x i8> %head, <8 x i8> poison, <8 x i32> zeroinitializer
428  %x = zext <8 x i16> %a to <8 x i32>
429  %y = zext <8 x i8> %splat to <8 x i32>
430  %z = shl <8 x i32> %x, %y
431  ret <8 x i32> %z
432}
433
434define <8 x i32> @vwsll_vi_v8i32(<8 x i16> %a) {
435; CHECK-LABEL: vwsll_vi_v8i32:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
438; CHECK-NEXT:    vzext.vf2 v10, v8
439; CHECK-NEXT:    vsll.vi v8, v10, 2
440; CHECK-NEXT:    ret
441;
442; CHECK-ZVBB-LABEL: vwsll_vi_v8i32:
443; CHECK-ZVBB:       # %bb.0:
444; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
445; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
446; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
447; CHECK-ZVBB-NEXT:    ret
448  %x = zext <8 x i16> %a to <8 x i32>
449  %z = shl <8 x i32> %x, splat (i32 2)
450  ret <8 x i32> %z
451}
452
453; ==============================================================================
454; i8 -> i16
455; ==============================================================================
456
457define <16 x i16> @vwsll_vv_v16i16_sext(<16 x i8> %a, <16 x i8> %b) {
458; CHECK-LABEL: vwsll_vv_v16i16_sext:
459; CHECK:       # %bb.0:
460; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
461; CHECK-NEXT:    vzext.vf2 v10, v8
462; CHECK-NEXT:    vsext.vf2 v12, v9
463; CHECK-NEXT:    vsll.vv v8, v10, v12
464; CHECK-NEXT:    ret
465;
466; CHECK-ZVBB-LABEL: vwsll_vv_v16i16_sext:
467; CHECK-ZVBB:       # %bb.0:
468; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
469; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
470; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
471; CHECK-ZVBB-NEXT:    ret
472  %x = zext <16 x i8> %a to <16 x i16>
473  %y = sext <16 x i8> %b to <16 x i16>
474  %z = shl <16 x i16> %x, %y
475  ret <16 x i16> %z
476}
477
478define <16 x i16> @vwsll_vv_v16i16_zext(<16 x i8> %a, <16 x i8> %b) {
479; CHECK-LABEL: vwsll_vv_v16i16_zext:
480; CHECK:       # %bb.0:
481; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
482; CHECK-NEXT:    vzext.vf2 v10, v8
483; CHECK-NEXT:    vzext.vf2 v12, v9
484; CHECK-NEXT:    vsll.vv v8, v10, v12
485; CHECK-NEXT:    ret
486;
487; CHECK-ZVBB-LABEL: vwsll_vv_v16i16_zext:
488; CHECK-ZVBB:       # %bb.0:
489; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
490; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
491; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
492; CHECK-ZVBB-NEXT:    ret
493  %x = zext <16 x i8> %a to <16 x i16>
494  %y = zext <16 x i8> %b to <16 x i16>
495  %z = shl <16 x i16> %x, %y
496  ret <16 x i16> %z
497}
498
499define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) {
500; RV32-LABEL: vwsll_vx_i64_v16i16:
501; RV32:       # %bb.0:
502; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
503; RV32-NEXT:    vmv.v.x v16, a0
504; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
505; RV32-NEXT:    vrgather.vi v24, v16, 0
506; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
507; RV32-NEXT:    vzext.vf2 v10, v8
508; RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
509; RV32-NEXT:    vnsrl.wi v12, v24, 0
510; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
511; RV32-NEXT:    vnsrl.wi v8, v12, 0
512; RV32-NEXT:    vsll.vv v8, v10, v8
513; RV32-NEXT:    ret
514;
515; RV64-LABEL: vwsll_vx_i64_v16i16:
516; RV64:       # %bb.0:
517; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
518; RV64-NEXT:    vmv.v.x v16, a0
519; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
520; RV64-NEXT:    vzext.vf2 v10, v8
521; RV64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
522; RV64-NEXT:    vnsrl.wi v12, v16, 0
523; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
524; RV64-NEXT:    vnsrl.wi v8, v12, 0
525; RV64-NEXT:    vsll.vv v8, v10, v8
526; RV64-NEXT:    ret
527;
528; CHECK-ZVBB-RV32-LABEL: vwsll_vx_i64_v16i16:
529; CHECK-ZVBB-RV32:       # %bb.0:
530; CHECK-ZVBB-RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
531; CHECK-ZVBB-RV32-NEXT:    vmv.v.x v16, a0
532; CHECK-ZVBB-RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
533; CHECK-ZVBB-RV32-NEXT:    vrgather.vi v24, v16, 0
534; CHECK-ZVBB-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
535; CHECK-ZVBB-RV32-NEXT:    vzext.vf2 v10, v8
536; CHECK-ZVBB-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
537; CHECK-ZVBB-RV32-NEXT:    vnsrl.wi v12, v24, 0
538; CHECK-ZVBB-RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
539; CHECK-ZVBB-RV32-NEXT:    vnsrl.wi v8, v12, 0
540; CHECK-ZVBB-RV32-NEXT:    vsll.vv v8, v10, v8
541; CHECK-ZVBB-RV32-NEXT:    ret
542;
543; CHECK-ZVBB-RV64-LABEL: vwsll_vx_i64_v16i16:
544; CHECK-ZVBB-RV64:       # %bb.0:
545; CHECK-ZVBB-RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
546; CHECK-ZVBB-RV64-NEXT:    vwsll.vx v10, v8, a0
547; CHECK-ZVBB-RV64-NEXT:    vmv2r.v v8, v10
548; CHECK-ZVBB-RV64-NEXT:    ret
549  %head = insertelement <8 x i64> poison, i64 %b, i32 0
550  %splat = shufflevector <8 x i64> %head, <8 x i64> poison, <16 x i32> zeroinitializer
551  %x = zext <16 x i8> %a to <16 x i16>
552  %y = trunc <16 x i64> %splat to <16 x i16>
553  %z = shl <16 x i16> %x, %y
554  ret <16 x i16> %z
555}
556
557define <16 x i16> @vwsll_vx_i32_v16i16(<16 x i8> %a, i32 %b) {
558; CHECK-LABEL: vwsll_vx_i32_v16i16:
559; CHECK:       # %bb.0:
560; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
561; CHECK-NEXT:    vmv.v.x v12, a0
562; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
563; CHECK-NEXT:    vzext.vf2 v10, v8
564; CHECK-NEXT:    vnsrl.wi v8, v12, 0
565; CHECK-NEXT:    vsll.vv v8, v10, v8
566; CHECK-NEXT:    ret
567;
568; CHECK-ZVBB-LABEL: vwsll_vx_i32_v16i16:
569; CHECK-ZVBB:       # %bb.0:
570; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
571; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
572; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
573; CHECK-ZVBB-NEXT:    ret
574  %head = insertelement <16 x i32> poison, i32 %b, i32 0
575  %splat = shufflevector <16 x i32> %head, <16 x i32> poison, <16 x i32> zeroinitializer
576  %x = zext <16 x i8> %a to <16 x i16>
577  %y = trunc <16 x i32> %splat to <16 x i16>
578  %z = shl <16 x i16> %x, %y
579  ret <16 x i16> %z
580}
581
582define <16 x i16> @vwsll_vx_i16_v16i16(<16 x i8> %a, i16 %b) {
583; CHECK-LABEL: vwsll_vx_i16_v16i16:
584; CHECK:       # %bb.0:
585; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
586; CHECK-NEXT:    vzext.vf2 v10, v8
587; CHECK-NEXT:    vsll.vx v8, v10, a0
588; CHECK-NEXT:    ret
589;
590; CHECK-ZVBB-LABEL: vwsll_vx_i16_v16i16:
591; CHECK-ZVBB:       # %bb.0:
592; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
593; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
594; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
595; CHECK-ZVBB-NEXT:    ret
596  %head = insertelement <16 x i16> poison, i16 %b, i32 0
597  %splat = shufflevector <16 x i16> %head, <16 x i16> poison, <16 x i32> zeroinitializer
598  %x = zext <16 x i8> %a to <16 x i16>
599  %z = shl <16 x i16> %x, %splat
600  ret <16 x i16> %z
601}
602
603define <16 x i16> @vwsll_vx_i8_v16i16_sext(<16 x i8> %a, i8 %b) {
604; CHECK-LABEL: vwsll_vx_i8_v16i16_sext:
605; CHECK:       # %bb.0:
606; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
607; CHECK-NEXT:    vmv.v.x v9, a0
608; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
609; CHECK-NEXT:    vzext.vf2 v10, v8
610; CHECK-NEXT:    vsext.vf2 v12, v9
611; CHECK-NEXT:    vsll.vv v8, v10, v12
612; CHECK-NEXT:    ret
613;
614; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_sext:
615; CHECK-ZVBB:       # %bb.0:
616; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
617; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
618; CHECK-ZVBB-NEXT:    vwsll.vv v10, v8, v9
619; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
620; CHECK-ZVBB-NEXT:    ret
621  %head = insertelement <16 x i8> poison, i8 %b, i32 0
622  %splat = shufflevector <16 x i8> %head, <16 x i8> poison, <16 x i32> zeroinitializer
623  %x = zext <16 x i8> %a to <16 x i16>
624  %y = sext <16 x i8> %splat to <16 x i16>
625  %z = shl <16 x i16> %x, %y
626  ret <16 x i16> %z
627}
628
629define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) {
630; CHECK-LABEL: vwsll_vx_i8_v16i16_zext:
631; CHECK:       # %bb.0:
632; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
633; CHECK-NEXT:    vmv.v.x v9, a0
634; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
635; CHECK-NEXT:    vzext.vf2 v10, v8
636; CHECK-NEXT:    vzext.vf2 v12, v9
637; CHECK-NEXT:    vsll.vv v8, v10, v12
638; CHECK-NEXT:    ret
639;
640; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_zext:
641; CHECK-ZVBB:       # %bb.0:
642; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
643; CHECK-ZVBB-NEXT:    vwsll.vx v10, v8, a0
644; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
645; CHECK-ZVBB-NEXT:    ret
646  %head = insertelement <16 x i8> poison, i8 %b, i32 0
647  %splat = shufflevector <16 x i8> %head, <16 x i8> poison, <16 x i32> zeroinitializer
648  %x = zext <16 x i8> %a to <16 x i16>
649  %y = zext <16 x i8> %splat to <16 x i16>
650  %z = shl <16 x i16> %x, %y
651  ret <16 x i16> %z
652}
653
654define <16 x i16> @vwsll_vi_v16i16(<16 x i8> %a) {
655; CHECK-LABEL: vwsll_vi_v16i16:
656; CHECK:       # %bb.0:
657; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
658; CHECK-NEXT:    vzext.vf2 v10, v8
659; CHECK-NEXT:    vsll.vi v8, v10, 2
660; CHECK-NEXT:    ret
661;
662; CHECK-ZVBB-LABEL: vwsll_vi_v16i16:
663; CHECK-ZVBB:       # %bb.0:
664; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
665; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
666; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
667; CHECK-ZVBB-NEXT:    ret
668  %x = zext <16 x i8> %a to <16 x i16>
669  %z = shl <16 x i16> %x, splat (i16 2)
670  ret <16 x i16> %z
671}
672
673; ==============================================================================
674; i8 -> i64
675; ==============================================================================
676
677define <4 x i64> @vwsll_vv_v4i64_v4i8_sext(<4 x i8> %a, <4 x i8> %b) {
678; CHECK-LABEL: vwsll_vv_v4i64_v4i8_sext:
679; CHECK:       # %bb.0:
680; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
681; CHECK-NEXT:    vzext.vf8 v10, v8
682; CHECK-NEXT:    vsext.vf8 v12, v9
683; CHECK-NEXT:    vsll.vv v8, v10, v12
684; CHECK-NEXT:    ret
685;
686; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_sext:
687; CHECK-ZVBB:       # %bb.0:
688; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
689; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
690; CHECK-ZVBB-NEXT:    vsext.vf8 v12, v9
691; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
692; CHECK-ZVBB-NEXT:    ret
693  %x = zext <4 x i8> %a to <4 x i64>
694  %y = sext <4 x i8> %b to <4 x i64>
695  %z = shl <4 x i64> %x, %y
696  ret <4 x i64> %z
697}
698
699define <4 x i64> @vwsll_vv_v4i64_v4i8_zext(<4 x i8> %a, <4 x i8> %b) {
700; CHECK-LABEL: vwsll_vv_v4i64_v4i8_zext:
701; CHECK:       # %bb.0:
702; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
703; CHECK-NEXT:    vzext.vf8 v10, v8
704; CHECK-NEXT:    vzext.vf8 v12, v9
705; CHECK-NEXT:    vsll.vv v8, v10, v12
706; CHECK-NEXT:    ret
707;
708; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_zext:
709; CHECK-ZVBB:       # %bb.0:
710; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
711; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
712; CHECK-ZVBB-NEXT:    vzext.vf4 v11, v9
713; CHECK-ZVBB-NEXT:    vwsll.vv v8, v10, v11
714; CHECK-ZVBB-NEXT:    ret
715  %x = zext <4 x i8> %a to <4 x i64>
716  %y = zext <4 x i8> %b to <4 x i64>
717  %z = shl <4 x i64> %x, %y
718  ret <4 x i64> %z
719}
720
721define <4 x i64> @vwsll_vx_i64_v4i64_v4i8(<4 x i8> %a, i64 %b) {
722; CHECK-LABEL: vwsll_vx_i64_v4i64_v4i8:
723; CHECK:       # %bb.0:
724; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
725; CHECK-NEXT:    vzext.vf8 v10, v8
726; CHECK-NEXT:    vsll.vx v8, v10, a0
727; CHECK-NEXT:    ret
728;
729; CHECK-ZVBB-LABEL: vwsll_vx_i64_v4i64_v4i8:
730; CHECK-ZVBB:       # %bb.0:
731; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
732; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
733; CHECK-ZVBB-NEXT:    vsll.vx v8, v10, a0
734; CHECK-ZVBB-NEXT:    ret
735  %head = insertelement <4 x i64> poison, i64 %b, i32 0
736  %splat = shufflevector <4 x i64> %head, <4 x i64> poison, <4 x i32> zeroinitializer
737  %x = zext <4 x i8> %a to <4 x i64>
738  %z = shl <4 x i64> %x, %splat
739  ret <4 x i64> %z
740}
741
742define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_sext(<4 x i8> %a, i32 %b) {
743; CHECK-LABEL: vwsll_vx_i32_v4i64_v4i8_sext:
744; CHECK:       # %bb.0:
745; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
746; CHECK-NEXT:    vmv.v.x v9, a0
747; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
748; CHECK-NEXT:    vzext.vf8 v10, v8
749; CHECK-NEXT:    vsext.vf2 v12, v9
750; CHECK-NEXT:    vsll.vv v8, v10, v12
751; CHECK-NEXT:    ret
752;
753; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_sext:
754; CHECK-ZVBB:       # %bb.0:
755; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
756; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
757; CHECK-ZVBB-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
758; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
759; CHECK-ZVBB-NEXT:    vsext.vf2 v12, v9
760; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
761; CHECK-ZVBB-NEXT:    ret
762  %head = insertelement <4 x i32> poison, i32 %b, i32 0
763  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
764  %x = zext <4 x i8> %a to <4 x i64>
765  %y = sext <4 x i32> %splat to <4 x i64>
766  %z = shl <4 x i64> %x, %y
767  ret <4 x i64> %z
768}
769
770define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_zext(<4 x i8> %a, i32 %b) {
771; CHECK-LABEL: vwsll_vx_i32_v4i64_v4i8_zext:
772; CHECK:       # %bb.0:
773; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
774; CHECK-NEXT:    vmv.v.x v9, a0
775; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
776; CHECK-NEXT:    vzext.vf8 v10, v8
777; CHECK-NEXT:    vzext.vf2 v12, v9
778; CHECK-NEXT:    vsll.vv v8, v10, v12
779; CHECK-NEXT:    ret
780;
781; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_zext:
782; CHECK-ZVBB:       # %bb.0:
783; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
784; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
785; CHECK-ZVBB-NEXT:    vwsll.vx v8, v10, a0
786; CHECK-ZVBB-NEXT:    ret
787  %head = insertelement <4 x i32> poison, i32 %b, i32 0
788  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
789  %x = zext <4 x i8> %a to <4 x i64>
790  %y = zext <4 x i32> %splat to <4 x i64>
791  %z = shl <4 x i64> %x, %y
792  ret <4 x i64> %z
793}
794
795define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_sext(<4 x i8> %a, i16 %b) {
796; CHECK-LABEL: vwsll_vx_i16_v4i64_v4i8_sext:
797; CHECK:       # %bb.0:
798; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
799; CHECK-NEXT:    vmv.v.x v9, a0
800; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
801; CHECK-NEXT:    vzext.vf8 v10, v8
802; CHECK-NEXT:    vsext.vf4 v12, v9
803; CHECK-NEXT:    vsll.vv v8, v10, v12
804; CHECK-NEXT:    ret
805;
806; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_sext:
807; CHECK-ZVBB:       # %bb.0:
808; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
809; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
810; CHECK-ZVBB-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
811; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
812; CHECK-ZVBB-NEXT:    vsext.vf4 v12, v9
813; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
814; CHECK-ZVBB-NEXT:    ret
815  %head = insertelement <4 x i16> poison, i16 %b, i32 0
816  %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer
817  %x = zext <4 x i8> %a to <4 x i64>
818  %y = sext <4 x i16> %splat to <4 x i64>
819  %z = shl <4 x i64> %x, %y
820  ret <4 x i64> %z
821}
822
823define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_zext(<4 x i8> %a, i16 %b) {
824; CHECK-LABEL: vwsll_vx_i16_v4i64_v4i8_zext:
825; CHECK:       # %bb.0:
826; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
827; CHECK-NEXT:    vmv.v.x v9, a0
828; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
829; CHECK-NEXT:    vzext.vf8 v10, v8
830; CHECK-NEXT:    vzext.vf4 v12, v9
831; CHECK-NEXT:    vsll.vv v8, v10, v12
832; CHECK-NEXT:    ret
833;
834; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_zext:
835; CHECK-ZVBB:       # %bb.0:
836; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
837; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
838; CHECK-ZVBB-NEXT:    vwsll.vx v8, v10, a0
839; CHECK-ZVBB-NEXT:    ret
840  %head = insertelement <4 x i16> poison, i16 %b, i32 0
841  %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer
842  %x = zext <4 x i8> %a to <4 x i64>
843  %y = zext <4 x i16> %splat to <4 x i64>
844  %z = shl <4 x i64> %x, %y
845  ret <4 x i64> %z
846}
847
848define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_sext(<4 x i8> %a, i8 %b) {
849; CHECK-LABEL: vwsll_vx_i8_v4i64_v4i8_sext:
850; CHECK:       # %bb.0:
851; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
852; CHECK-NEXT:    vmv.v.x v9, a0
853; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
854; CHECK-NEXT:    vzext.vf8 v10, v8
855; CHECK-NEXT:    vsext.vf8 v12, v9
856; CHECK-NEXT:    vsll.vv v8, v10, v12
857; CHECK-NEXT:    ret
858;
859; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_sext:
860; CHECK-ZVBB:       # %bb.0:
861; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
862; CHECK-ZVBB-NEXT:    vmv.v.x v9, a0
863; CHECK-ZVBB-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
864; CHECK-ZVBB-NEXT:    vzext.vf8 v10, v8
865; CHECK-ZVBB-NEXT:    vsext.vf8 v12, v9
866; CHECK-ZVBB-NEXT:    vsll.vv v8, v10, v12
867; CHECK-ZVBB-NEXT:    ret
868  %head = insertelement <4 x i8> poison, i8 %b, i32 0
869  %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer
870  %x = zext <4 x i8> %a to <4 x i64>
871  %y = sext <4 x i8> %splat to <4 x i64>
872  %z = shl <4 x i64> %x, %y
873  ret <4 x i64> %z
874}
875
876define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_zext(<4 x i8> %a, i8 %b) {
877; CHECK-LABEL: vwsll_vx_i8_v4i64_v4i8_zext:
878; CHECK:       # %bb.0:
879; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
880; CHECK-NEXT:    vmv.v.x v9, a0
881; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
882; CHECK-NEXT:    vzext.vf8 v10, v8
883; CHECK-NEXT:    vzext.vf8 v12, v9
884; CHECK-NEXT:    vsll.vv v8, v10, v12
885; CHECK-NEXT:    ret
886;
887; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_zext:
888; CHECK-ZVBB:       # %bb.0:
889; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
890; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
891; CHECK-ZVBB-NEXT:    vwsll.vx v8, v10, a0
892; CHECK-ZVBB-NEXT:    ret
893  %head = insertelement <4 x i8> poison, i8 %b, i32 0
894  %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer
895  %x = zext <4 x i8> %a to <4 x i64>
896  %y = zext <4 x i8> %splat to <4 x i64>
897  %z = shl <4 x i64> %x, %y
898  ret <4 x i64> %z
899}
900
901define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) {
902; CHECK-LABEL: vwsll_vi_v4i64_v4i8:
903; CHECK:       # %bb.0:
904; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
905; CHECK-NEXT:    vzext.vf8 v10, v8
906; CHECK-NEXT:    vsll.vi v8, v10, 2
907; CHECK-NEXT:    ret
908;
909; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8:
910; CHECK-ZVBB:       # %bb.0:
911; CHECK-ZVBB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
912; CHECK-ZVBB-NEXT:    vzext.vf4 v10, v8
913; CHECK-ZVBB-NEXT:    vwsll.vi v8, v10, 2
914; CHECK-ZVBB-NEXT:    ret
915  %x = zext <4 x i8> %a to <4 x i64>
916  %z = shl <4 x i64> %x, splat (i64 2)
917  ret <4 x i64> %z
918}
919