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Searched refs:Instr (Results 1 – 25 of 199) sorted by relevance

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/llvm-project/llvm/tools/llvm-cfi-verify/lib/
H A DFileAnalysis.h77 struct Instr { struct
97 const Instr *getInstruction(uint64_t Address) const;
101 const Instr &getInstructionOrDie(uint64_t Address) const;
106 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const;
107 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const;
110 bool isCFITrap(const Instr &InstrMeta) const;
114 bool willTrapOnCFIViolation(const Instr &InstrMeta) const;
120 bool canFallThrough(const Instr &InstrMeta) const;
129 const Instr *getDefiniteNextInstruction(const Instr &InstrMeta) const;
134 std::set<const Instr *>
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H A DFileAnalysis.cpp39 using Instr = llvm::cfi_verify::FileAnalysis::Instr; typedef
125 const Instr *
126 FileAnalysis::getPrevInstructionSequential(const Instr &InstrMeta) const { in getPrevInstructionSequential()
127 std::map<uint64_t, Instr>::const_iterator KV = in getPrevInstructionSequential()
138 const Instr *
139 FileAnalysis::getNextInstructionSequential(const Instr &InstrMeta) const { in getNextInstructionSequential()
140 std::map<uint64_t, Instr>::const_iterator KV = in getNextInstructionSequential()
151 bool FileAnalysis::usesRegisterOperand(const Instr &InstrMeta) const { in usesRegisterOperand()
159 const Instr *FileAnalysis::getInstruction(uint64_t Address) const { in getInstruction()
167 const Instr &FileAnalysis::getInstructionOrDie(uint64_t Address) const { in getInstructionOrDie()
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/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_aarch64.cpp279 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation() local
280 if (!aarch64::isLDRLiteral(Instr)) in addSingleRelocation()
288 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation()
289 if (!aarch64::isADR(Instr)) in addSingleRelocation()
305 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation()
306 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
307 aarch64::getPageOffset12Shift(Instr) != 0) in addSingleRelocation()
316 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addSingleRelocation()
317 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
318 aarch64::getPageOffset12Shift(Instr) ! in addSingleRelocation()
198 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
207 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
224 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
235 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
246 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
257 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
268 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
290 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
301 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
312 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
323 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
332 uint32_t Instr = *(const ulittle32_t *)FixupContent; addSingleRelocation() local
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/llvm-project/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp756 static bool narrowSDivOrSRem(BinaryOperator *Instr, const ConstantRange &LCR, in narrowSDivOrSRem()
758 assert(Instr->getOpcode() == Instruction::SDiv || in narrowSDivOrSRem()
759 Instr->getOpcode() == Instruction::SRem); in narrowSDivOrSRem()
761 // Find the smallest power of two bitwidth that's sufficient to hold Instr's in narrowSDivOrSRem()
763 unsigned OrigWidth = Instr->getType()->getScalarSizeInBits(); in narrowSDivOrSRem()
785 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
786 auto *TruncTy = Instr->getType()->getWithNewBitWidth(NewWidth); in narrowSDivOrSRem()
787 auto *LHS = B.CreateTruncOrBitCast(Instr->getOperand(0), TruncTy, in narrowSDivOrSRem()
788 Instr->getName() + ".lhs.trunc"); in narrowSDivOrSRem()
789 auto *RHS = B.CreateTruncOrBitCast(Instr in narrowSDivOrSRem()
748 narrowSDivOrSRem(BinaryOperator * Instr,const ConstantRange & LCR,const ConstantRange & RCR) narrowSDivOrSRem() argument
794 expandUDivOrURem(BinaryOperator * Instr,const ConstantRange & XCR,const ConstantRange & YCR) expandUDivOrURem() argument
877 narrowUDivOrURem(BinaryOperator * Instr,const ConstantRange & XCR,const ConstantRange & YCR) narrowUDivOrURem() argument
914 processUDivOrURem(BinaryOperator * Instr,LazyValueInfo * LVI) processUDivOrURem() argument
1044 processSDivOrSRem(BinaryOperator * Instr,LazyValueInfo * LVI) processSDivOrSRem() argument
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/llvm-project/llvm/tools/llvm-exegesis/lib/
H A DCodeTemplate.cpp27 InstructionTemplate::InstructionTemplate(const Instruction *Instr) in InstructionTemplate() argument
28 : Instr(Instr), VariableValues(Instr->Variables.size()) {} in InstructionTemplate()
41 return Instr->Description.getOpcode(); in getOpcode()
53 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
57 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
61 return any_of(Instr->Variables, [this](const Variable &Var) { in hasImmediateVariables()
62 return Instr->getPrimaryOperand(Var).isImmediate(); in hasImmediateVariables()
68 Result.setOpcode(Instr->Description.Opcode); in build()
69 for (const auto &Op : Instr->Operands) in build()
H A DSerialSnippetGenerator.cpp38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, in computeAliasingInstructions() argument
53 if (OtherOpcode == Instr->Description.getOpcode()) in computeAliasingInstructions()
60 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters)) in computeAliasingInstructions()
68 static ExecutionMode getExecutionModes(const Instruction &Instr, in computeAliasingInstructions()
71 if (Instr.hasAliasingImplicitRegisters()) in computeAliasingInstructions()
73 if (Instr.hasTiedRegisters()) in computeAliasingInstructions()
75 if (Instr.hasMemoryOperands()) in getExecutionModes() argument
77 if (Instr.hasAliasingNotMemoryRegisters(ForbiddenRegisters)) in getExecutionModes()
79 if (Instr.hasOneUseOrOneDef()) in getExecutionModes()
116 "Instr mus in appendCodeTemplates()
137 const Instruction &Instr = Variant.getInstr(); appendCodeTemplates() local
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H A DParallelSnippetGenerator.cpp82 static bool hasVariablesWithTiedOperands(const Instruction &Instr) { in hasVariablesWithTiedOperands() argument
84 for (const auto &Var : Instr.Variables) in hasVariablesWithTiedOperands()
152 const Instruction &Instr = IT.getInstr(); in generateSingleRegisterForInstrAvoidingDefUseOverlap() local
197 Instr.Variables[Op.getVariableIndex()].hasTiedOperands(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
220 const Instruction &Instr = IT.getInstr(); in generateSingleSnippetForInstrAvoidingDefUseOverlap() local
221 for (const Operand &Op : Instr.Operands) { in generateSingleSnippetForInstrAvoidingDefUseOverlap()
297 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates() local
300 Instr.hasMemoryOperands() in generateCodeTemplates()
304 const AliasingConfigurations SelfAliasing(Instr, Instr, ForbiddenRegister in generateCodeTemplates()
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/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.h21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
H A DMVETPAndVPTOptimisationsPass.cpp75 MachineInstr &Instr,
573 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) {
574 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP"); in GetCondCode() argument
575 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
605 // Returns true if Instr writes to VCCR.
606 static bool IsWritingToVCCR(MachineInstr &Instr) {
607 if (Instr.getNumOperands() == 0) in IsWritingToVCCR() argument
609 MachineOperand &Dst = Instr.getOperand(0); in IsWritingToVCCR()
615 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo(); in IsWritingToVCCR()
621 // <Instr tha
630 ReplaceRegisterUseWithVPNOT(MachineBasicBlock & MBB,MachineInstr & Instr,MachineOperand & User,Register Target) ReplaceRegisterUseWithVPNOT() argument
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/llvm-project/bolt/lib/Core/
H A DExceptions.cpp385 for (MCInst &Instr : *BB) { in updateEHRanges()
386 if (!BC.MIB->isCall(Instr)) in updateEHRanges()
390 const bool Throws = BC.MIB->isInvoke(Instr); in updateEHRanges()
400 BC.MIB->getEHInfo(Instr)) in updateEHRanges()
410 if (MCSymbol *InstrLabel = BC.MIB->getInstLabel(Instr)) { in updateEHRanges()
414 EHSymbol = BC.MIB->getOrCreateInstLabel(Instr, "EH", BC.Ctx.get()); in updateEHRanges()
517 const CFIProgram::Instruction &Instr) { in fillCFIInfoFor()
518 uint8_t Opcode = Instr.Opcode; in fillCFIInfoFor() argument
521 switch (Instr.Opcode) { in fillCFIInfoFor()
529 Offset += CodeAlignment * int64_t(Instr in fillCFIInfoFor()
658 for (const CFIProgram::Instruction &Instr : CurFDE.getLinkedCIE()->cfis()) fillCFIInfoFor() local
662 for (const CFIProgram::Instruction &Instr : CurFDE.cfis()) fillCFIInfoFor() local
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H A DBinaryFunction.cpp678 static std::string mutateDWARFExpressionTargetReg(const MCCFIInstruction &Instr, in printRelocations()
680 StringRef ExprBytes = Instr.getValues();
703 void BinaryFunction::mutateCFIRegisterFor(const MCInst &Instr, in mutateDWARFExpressionTargetReg()
705 const MCCFIInstruction *OldCFI = getCFIFor(Instr);
711 setCFIFor(Instr, MCCFIInstruction::cfiDefCfa(nullptr, NewReg, in mutateCFIRegisterFor()
715 setCFIFor(Instr, MCCFIInstruction::createDefCfaRegister(nullptr, NewReg)); in mutateCFIRegisterFor()
718 setCFIFor(Instr, MCCFIInstruction::createOffset(nullptr, NewReg, in mutateCFIRegisterFor()
722 setCFIFor(Instr, MCCFIInstruction::createRegister(nullptr, NewReg, in mutateCFIRegisterFor()
726 setCFIFor(Instr, MCCFIInstruction::createSameValue(nullptr, NewReg)); in mutateCFIRegisterFor()
729 setCFIFor(Instr, in mutateCFIRegisterFor()
681 mutateDWARFExpressionTargetReg(const MCCFIInstruction & Instr,MCPhysReg NewReg) mutateDWARFExpressionTargetReg() argument
706 mutateCFIRegisterFor(const MCInst & Instr,MCPhysReg NewReg) mutateCFIRegisterFor() argument
746 mutateCFIOffsetFor(const MCInst & Instr,int64_t NewOffset) mutateCFIOffsetFor() argument
1181 MCInst Instr; disassembleInstructionAtOffset() local
1854 MCInst &Instr = *II; postProcessIndirectBranches() local
1917 __anon5de2701c0c02(const MCInst &Instr) postProcessIndirectBranches() argument
2067 MCInst &Instr = I->second; buildCFG() local
2556 const MCCFIInstruction &Instr = FDE[I]; advanceTo() local
2592 const MCCFIInstruction &Instr = CIE[I]; CFISnapshot() local
2706 MCCFIInstruction *Instr = &FrameInstructions[CurState]; replayCFIInstrs() local
2764 __anon5de2701c1102(const MCCFIInstruction &Instr) unwindCFIState() argument
2839 const MCCFIInstruction &Instr = FrameInstructions[I]; unwindCFIState() local
3435 MCInst &Instr = *II; propagateGnuArgsSizeInfo() local
3937 MCInst *Instr = BB->getLastNonPseudoInstr(); replaceJumpTableEntryIn() local
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/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h423 // Returns whether the Instr is LD/ST (imm12) in getMoveWide16Shift() argument
424 inline bool isLoadStoreImm12(uint32_t Instr) { in getMoveWide16Shift()
426 return (Instr & LoadStoreImm12Mask) == 0x39000000; in getMoveWide16Shift()
429 inline bool isTestAndBranchImm14(uint32_t Instr) { in getMoveWide16Shift()
431 return (Instr & TestAndBranchImm14Mask) == 0x36000000;
434 inline bool isCondBranchImm19(uint32_t Instr) { in applyFixup()
436 return (Instr & CondBranchImm19Mask) == 0x54000000; in applyFixup()
439 inline bool isCompAndBranchImm19(uint32_t Instr) { in applyFixup()
441 return (Instr & CompAndBranchImm19Mask) == 0x34000000; in applyFixup()
444 inline bool isADR(uint32_t Instr) { in applyFixup()
362 isLoadStoreImm12(uint32_t Instr) isLoadStoreImm12() argument
367 isTestAndBranchImm14(uint32_t Instr) isTestAndBranchImm14() argument
372 isCondBranchImm19(uint32_t Instr) isCondBranchImm19() argument
377 isCompAndBranchImm19(uint32_t Instr) isCompAndBranchImm19() argument
382 isADR(uint32_t Instr) isADR() argument
387 isLDRLiteral(uint32_t Instr) isLDRLiteral() argument
398 getPageOffset12Shift(uint32_t Instr) getPageOffset12Shift() argument
414 isMoveWideImm16(uint32_t Instr) isMoveWideImm16() argument
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp51 MachineInstr *Instr; member in __anon341fe04a0111::RegSeqInfo
55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) { in RegSeqInfo()
58 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
70 return RSI.Instr == Instr; in operator ==()
182 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
183 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
187 Register SrcVec = BaseRSI->Instr in RebuildVector()
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/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h494 InterleaveGroup(InstTy *Instr, int32_t Stride, Align Alignment) in insertMember()
495 : Alignment(Alignment), InsertPos(Instr) { in insertMember()
500 Members[0] = Instr; in insertMember()
508 /// Try to insert a new member \p Instr with index \p Index and in insertMember()
513 bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign) { in insertMember()
551 Members[Key] = Instr; in requiresScalarEpilogue()
565 uint32_t getIndex(const InstTy *Instr) const {
567 if (I.second == Instr)
666 /// Check if \p Instr belongs to any interleave group.
667 bool isInterleaved(Instruction *Instr) cons
459 InterleaveGroup(InstTy * Instr,int32_t Stride,Align Alignment) InterleaveGroup() argument
478 insertMember(InstTy * Instr,int32_t Index,Align NewAlign) insertMember() argument
530 getIndex(const InstTy * Instr) getIndex() argument
632 isInterleaved(Instruction * Instr) isInterleaved() argument
640 getInterleaveGroup(const Instruction * Instr) getInterleaveGroup() argument
715 createInterleaveGroup(Instruction * Instr,int Stride,Align Alignment) createInterleaveGroup() argument
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/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
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/llvm-project/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp81 static const char *isInvalidMemoryInstr(const Instruction &Instr) { in isInvalidMemoryInstr() argument
82 switch (Instr.Description.TSFlags & X86II::FormMask) { in isInvalidMemoryInstr()
181 return (Instr.Description.Opcode == X86::POP16r || in isInvalidMemoryInstr()
182 Instr.Description.Opcode == X86::POP32r || in isInvalidMemoryInstr()
183 Instr.Description.Opcode == X86::PUSH16r || in isInvalidMemoryInstr()
184 Instr.Description.Opcode == X86::PUSH32r) in isInvalidMemoryInstr()
216 static const char *isInvalidOpcode(const Instruction &Instr) { in isInvalidOpcode() argument
217 const auto OpcodeName = Instr.Name; in isInvalidOpcode()
218 if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo) in isInvalidOpcode()
224 switch (Instr in isInvalidOpcode()
257 getX86FPFlags(const Instruction & Instr) getX86FPFlags() argument
272 generateLEATemplatesCommon(const Instruction & Instr,const BitVector & ForbiddenRegisters,const LLVMState & State,const SnippetGenerator::Options & Opts,std::function<void (unsigned,unsigned,BitVector & CandidateDestRegs)> RestrictDestRegs) generateLEATemplatesCommon() argument
349 const Instruction &Instr = Variant.getInstr(); generateCodeTemplates() local
409 const Instruction &Instr = Variant.getInstr(); generateCodeTemplates() local
881 randomizeTargetMCOperand(const Instruction & Instr,const Variable & Var,MCOperand & AssignedValue,const BitVector & ForbiddenRegs) const randomizeTargetMCOperand() argument
1299 generateInstructionVariants(const Instruction & Instr,unsigned MaxConfigsPerOpcode) const generateInstructionVariants() argument
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/llvm-project/bolt/lib/Profile/
H A DYAMLProfileWriter.cpp260 for (const MCInst &Instr : *BB) {
261 if (!BC.MIB->isCall(Instr) && !BC.MIB->isIndirectBranch(Instr))
266 std::optional<uint32_t> Offset = BC.MIB->getOffset(Instr);
271 if (BC.MIB->isIndirectCall(Instr) || BC.MIB->isIndirectBranch(Instr)) {
273 Instr, "CallProfile");
288 const MCSymbol *CalleeSymbol = BC.MIB->getTargetSymbol(Instr);
295 return BC.MIB->getAnnotationWithDefault(Instr, Ann, 0ull);
297 if (BC.MIB->getConditionalTailCall(Instr)) {
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/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
165 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
182 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
185 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
190 switch (Instr.getOpcode()) { in getInstruction()
202 auto& Op = Instr.getOperand(1); in getInstruction()
212 auto Op = Instr.getOperand(0); in getInstruction()
213 Instr.clear(); in getInstruction()
214 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
215 Instr.addOperand(Op); in getInstruction()
/llvm-project/llvm/test/TableGen/
H A DPaste.td4 class Instr<int i> {
9 def Vx#NAME#PS : Instr<0>;
10 def Vx#NAME#PD : Instr<1>;
11 def Vy#NAME#PS : Instr<2>;
12 def Vy#NAME#PD : Instr<3>;
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp270 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr,
274 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
278 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
282 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
285 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
289 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
293 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
297 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
302 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
306 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
272 shouldConvertUse(const Constant * Cst,const Instruction * Instr,unsigned OpIdx) shouldConvertUse() argument
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/llvm-project/bolt/lib/Passes/
H A DAsmDump.cpp39 void dumpCFI(const BinaryFunction &BF, const MCInst &Instr, AsmPrinter &MAP) { in dumpCFI() argument
40 const MCCFIInstruction *CFIInstr = BF.getCFIFor(Instr); in dumpCFI()
173 for (const MCInst &Instr : *BB) { in dumpFunction()
175 if (BC.MIB->isPseudo(Instr)) { in dumpFunction()
176 if (BC.MIB->isCFI(Instr)) in dumpFunction()
177 dumpCFI(BF, Instr, *MAP.get()); in dumpFunction()
182 bool IsCall = BC.MIB->isCall(Instr); in dumpFunction()
183 for (const MCOperand &Operand : MCPlus::primeOperands(Instr)) { in dumpFunction()
197 if (&Instr == LastInst && (BB->succ_size() || IsCall)) in dumpFunction()
200 BC.InstPrinter->printInst(&Instr, in dumpFunction()
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H A DVeneerElimination.cpp88 for (MCInst &Instr : BB) { in runOnFunctions()
89 if (!BC.MIB->isCall(Instr) || BC.MIB->isIndirectCall(Instr)) in runOnFunctions()
92 const MCSymbol *TargetSymbol = BC.MIB->getTargetSymbol(Instr, 0);
98 BC.MIB->replaceBranchTarget(Instr, It->second, BC.Ctx.get());
/llvm-project/llvm/include/llvm/CodeGen/
H A DDbgEntityHistoryCalculator.h78 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry() argument
79 : Instr(Instr, Kind), EndIndex(NoEntry) {} in Entry()
81 const MachineInstr *getInstr() const { return Instr.getPointer(); } in getInstr()
83 EntryKind getEntryKind() const { return Instr.getInt(); } in getEntryKind()
92 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
/llvm-project/llvm/lib/CodeGen/
H A DRemoveRedundantDebugValues.cpp138 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsForwardScan() local
139 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsForwardScan()
140 Instr->eraseFromParent(); in reduceDbgValsForwardScan()
193 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsBackwardScan() local
194 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsBackwardScan()
195 Instr->eraseFromParent(); in reduceDbgValsBackwardScan()
/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp28 const Instruction &Instr) { in markDefsDivergent()
29 return markDivergent(cast<Value>(&Instr)); in markDefsDivergent() argument
58 const Instruction &Instr) { in pushUsers()
59 assert(!isAlwaysUniform(Instr)); in pushUsers() argument
60 if (Instr.isTerminator()) in pushUsers()
62 pushUsers(cast<Value>(&Instr)); in pushUsers()

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