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Searched refs:Opcode (Results 1 – 25 of 686) sorted by relevance

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/freebsd-src/contrib/llvm-project/lldb/include/lldb/Core/
H A DOpcode.h29 class Opcode {
41 Opcode() = default;
43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
70 m_type = Opcode::eTypeInvalid; in Clear()
73 Opcode::Type GetType() const { return m_type; } in GetType()
77 case Opcode::eTypeInvalid:
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp63 bool isLoadInst(unsigned Opcode);
77 unsigned Opcode);
97 static bool isST(unsigned Opcode) { in isST()
98 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isST()
99 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32()
103 return Opcode == BPF::STB32 || Opcode in isSTX32()
96 isST(unsigned Opcode) isST() argument
101 isSTX32(unsigned Opcode) isSTX32() argument
105 isSTX64(unsigned Opcode) isSTX64() argument
110 isLDX32(unsigned Opcode) isLDX32() argument
114 isLDX64(unsigned Opcode) isLDX64() argument
119 isLDSX(unsigned Opcode) isLDSX() argument
123 isLoadInst(unsigned Opcode) isLoadInst() argument
143 unsigned Opcode = DefInst->getOpcode(); checkADDrr() local
177 checkShift(MachineRegisterInfo * MRI,MachineBasicBlock & MBB,MachineOperand * RelocOp,const GlobalValue * GVal,unsigned Opcode) checkShift() argument
207 unsigned Opcode = I->getParent()->getOpcode(); processCandidate() local
287 unsigned Opcode = Inst->getOpcode(); processInst() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h104 static BranchPredicate getBranchPredicate(unsigned Opcode);
133 unsigned Opcode) const;
136 unsigned Opcode) const;
139 unsigned Opcode, bool Swap = false) const;
142 unsigned Opcode,
158 unsigned Opcode,
412 bool isSALU(uint16_t Opcode) const { in isSALU() argument
413 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
420 bool isVALU(uint16_t Opcode) const { in isVALU() argument
421 return get(Opcode) in isVALU()
428 isImage(uint16_t Opcode) isImage() argument
436 isVMEM(uint16_t Opcode) isVMEM() argument
444 isSOP1(uint16_t Opcode) isSOP1() argument
452 isSOP2(uint16_t Opcode) isSOP2() argument
460 isSOPC(uint16_t Opcode) isSOPC() argument
468 isSOPK(uint16_t Opcode) isSOPK() argument
476 isSOPP(uint16_t Opcode) isSOPP() argument
484 isPacked(uint16_t Opcode) isPacked() argument
492 isVOP1(uint16_t Opcode) isVOP1() argument
500 isVOP2(uint16_t Opcode) isVOP2() argument
508 isVOP3(uint16_t Opcode) isVOP3() argument
516 isSDWA(uint16_t Opcode) isSDWA() argument
524 isVOPC(uint16_t Opcode) isVOPC() argument
532 isMUBUF(uint16_t Opcode) isMUBUF() argument
540 isMTBUF(uint16_t Opcode) isMTBUF() argument
548 isSMRD(uint16_t Opcode) isSMRD() argument
558 isDS(uint16_t Opcode) isDS() argument
566 isLDSDMA(uint16_t Opcode) isLDSDMA() argument
574 isGWS(uint16_t Opcode) isGWS() argument
584 isMIMG(uint16_t Opcode) isMIMG() argument
592 isVIMAGE(uint16_t Opcode) isVIMAGE() argument
600 isVSAMPLE(uint16_t Opcode) isVSAMPLE() argument
608 isGather4(uint16_t Opcode) isGather4() argument
623 isSegmentSpecificFLAT(uint16_t Opcode) isSegmentSpecificFLAT() argument
632 isFLATGlobal(uint16_t Opcode) isFLATGlobal() argument
640 isFLATScratch(uint16_t Opcode) isFLATScratch() argument
645 isFLAT(uint16_t Opcode) isFLAT() argument
661 isEXP(uint16_t Opcode) isEXP() argument
669 isAtomicNoRet(uint16_t Opcode) isAtomicNoRet() argument
677 isAtomicRet(uint16_t Opcode) isAtomicRet() argument
686 isAtomic(uint16_t Opcode) isAtomic() argument
699 isWQM(uint16_t Opcode) isWQM() argument
707 isDisableWQM(uint16_t Opcode) isDisableWQM() argument
715 isVGPRSpill(uint16_t Opcode) isVGPRSpill() argument
723 isSGPRSpill(uint16_t Opcode) isSGPRSpill() argument
727 isSpillOpcode(uint16_t Opcode) isSpillOpcode() argument
732 isWWMRegSpillOpcode(uint16_t Opcode) isWWMRegSpillOpcode() argument
739 isChainCallOpcode(uint64_t Opcode) isChainCallOpcode() argument
748 isDPP(uint16_t Opcode) isDPP() argument
756 isTRANS(uint16_t Opcode) isTRANS() argument
764 isVOP3P(uint16_t Opcode) isVOP3P() argument
772 isVINTRP(uint16_t Opcode) isVINTRP() argument
780 isMAI(uint16_t Opcode) isMAI() argument
797 isWMMA(uint16_t Opcode) isWMMA() argument
809 isSWMMAC(uint16_t Opcode) isSWMMAC() argument
813 isDOT(uint16_t Opcode) isDOT() argument
821 isLDSDIR(uint16_t Opcode) isLDSDIR() argument
829 isVINTERP(uint16_t Opcode) isVINTERP() argument
849 sopkIsZext(uint16_t Opcode) sopkIsZext() argument
859 isScalarStore(uint16_t Opcode) isScalarStore() argument
867 isFixedSize(uint16_t Opcode) isFixedSize() argument
875 hasFPClamp(uint16_t Opcode) hasFPClamp() argument
895 usesFPDPRounding(uint16_t Opcode) usesFPDPRounding() argument
903 isFPAtomic(uint16_t Opcode) isFPAtomic() argument
914 isBarrierStart(unsigned Opcode) isBarrierStart() argument
926 doesNotReadTiedSource(uint16_t Opcode) doesNotReadTiedSource() argument
930 getNonSoftWaitcntOpcode(unsigned Opcode) getNonSoftWaitcntOpcode() argument
1088 getOpSize(uint16_t Opcode,unsigned OpNo) getOpSize() argument
1220 getMCOpcodeFromPseudo(unsigned Opcode) getMCOpcodeFromPseudo() argument
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H A DR600InstrInfo.h84 bool isALUInstr(unsigned Opcode) const;
85 bool hasInstrModifiers(unsigned Opcode) const;
86 bool isLDSInstr(unsigned Opcode) const;
87 bool isLDSRetInstr(unsigned Opcode) const;
93 bool isTransOnly(unsigned Opcode) const;
95 bool isVectorOnly(unsigned Opcode) const;
97 bool isExport(unsigned Opcode) const;
99 bool usesVertexCache(unsigned Opcode) const;
101 bool usesTextureCache(unsigned Opcode) const;
104 bool mustBeLastInClause(unsigned Opcode) const;
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/freebsd-src/contrib/llvm-project/lldb/source/Core/
H A DOpcode.cpp24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
62 lldb::ByteOrder Opcode::GetDataByteOrder() const { in GetDataByteOrder()
67 case Opcode::eTypeInvalid: in GetDataByteOrder()
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/freebsd-src/contrib/llvm-project/clang/lib/AST/Interp/
H A DOpcodes.td1 //===--- Opcodes.td - Opcode defitions for the constexpr VM -----*- C++ -*-===//
129 class Opcode {
140 class AluOpcode : Opcode {
145 class FloatOpcode : Opcode {
149 class IntegerOpcode : Opcode {
158 class JumpOpcode : Opcode {
176 def Ret : Opcode {
184 def RetVoid : Opcode {
190 def RetValue : Opcode {
196 def NoRet : Opcode {}
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in createInstruments()
171 switch (Opcode) { in createInstruments()
199 llvm_unreachable("Could not determine EEW from Opcode"); in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in getEEWAndEMUL()
209 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in getEEWAndEMUL()
210 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in getEEWAndEMUL()
211 Opcode == RISCV::VLE16_V || Opcode in getEEWAndEMUL()
189 getEEWAndEMUL(unsigned Opcode,RISCVII::VLMUL LMUL,uint8_t SEW) getEEWAndEMUL() argument
228 opcodeHasEEWAndEMULInfo(unsigned short Opcode) opcodeHasEEWAndEMULInfo() argument
243 unsigned short Opcode = MCI.getOpcode(); getSchedClassID() local
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstruction.h290 static const char *getOpcodeName(unsigned Opcode);
292 static inline bool isTerminator(unsigned Opcode) {
293 return Opcode >= TermOpsBegin && Opcode < TermOpsEnd;
296 static inline bool isUnaryOp(unsigned Opcode) {
297 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
299 static inline bool isBinaryOp(unsigned Opcode) {
300 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEn
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp107 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
122 switch (Opcode) { in getIntImmCostInst()
426 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
433 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
453 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
455 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
478 if (Opcode == Instruction::FAdd || Opcode in getArithmeticInstrCost()
103 getIntImmCostInst(unsigned Opcode,unsigned Idx,const APInt & Imm,Type * Ty,TTI::TargetCostKind CostKind,Instruction * Inst) getIntImmCostInst() argument
422 getArithmeticInstrCost(unsigned Opcode,Type * Ty,TTI::TargetCostKind CostKind,TTI::OperandValueInfo Op1Info,TTI::OperandValueInfo Op2Info,ArrayRef<const Value * > Args,const Instruction * CxtI) getArithmeticInstrCost() argument
750 getBoolVecToIntConversionCost(unsigned Opcode,Type * Dst,const Instruction * I) getBoolVecToIntConversionCost() argument
766 getCastInstrCost(unsigned Opcode,Type * Dst,Type * Src,TTI::CastContextHint CCH,TTI::TargetCostKind CostKind,const Instruction * I) getCastInstrCost() argument
960 getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy,CmpInst::Predicate VecPred,TTI::TargetCostKind CostKind,const Instruction * I) getCmpSelInstrCost() argument
1045 getVectorInstrCost(unsigned Opcode,Type * Val,TTI::TargetCostKind CostKind,unsigned Index,Value * Op0,Value * Op1) getVectorInstrCost() argument
1156 getMemoryOpCost(unsigned Opcode,Type * Src,MaybeAlign Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,TTI::OperandValueInfo OpInfo,const Instruction * I) getMemoryOpCost() argument
1234 getInterleavedMemoryOpCost(unsigned Opcode,Type * VecTy,unsigned Factor,ArrayRef<unsigned> Indices,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,bool UseMaskForCond,bool UseMaskForGaps) getInterleavedMemoryOpCost() argument
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H A DSystemZInstrInfo.cpp196 unsigned Opcode = getOpcodeForOffset( in expandRXYPseudo() local
199 MI.setDesc(get(Opcode)); in expandRXYPseudo()
208 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode; in expandLOCPseudo() local
209 MI.setDesc(get(Opcode)); in expandLOCPseudo()
270 unsigned Opcode; in emitGRX32Move() local
274 Opcode = SystemZ::RISBHH; in emitGRX32Move()
276 Opcode = SystemZ::RISBHL; in emitGRX32Move()
278 Opcode = SystemZ::RISBLH; in emitGRX32Move()
284 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
759 unsigned Opcode in PredicateInstruction()
691 unsigned Opcode = MI.getOpcode(); isPredicable() local
743 unsigned Opcode = MI.getOpcode(); PredicateInstruction() local
848 unsigned Opcode = copyPhysReg() local
857 unsigned Opcode; copyPhysReg() local
938 interpretAndImmediate(unsigned Opcode) interpretAndImmediate() argument
1027 unsigned Opcode = MI.getOpcode(); foldMemoryOperandImpl() local
1646 getOpcodeForOffset(unsigned Opcode,int64_t Offset,const MachineInstr * MI) const getOpcodeForOffset() argument
1752 getFusedCompare(unsigned Opcode,SystemZII::FusedCompareType Type,const MachineInstr * MI) const getFusedCompare() argument
1963 unsigned Opcode = 0; loadImmediate() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp97 // Return log2(widthInBytes) of load/store done by Opcode.
98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth() argument
99 switch (Opcode) { in log2LdstWidth()
122 // Return bit field size of immediate operand of Opcode.
123 static unsigned offsetMask(unsigned Opcode) { in compressibleSPOffset() argument
124 switch (Opcode) { in compressibleSPOffset()
148 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in isCompressibleLoad()
149 return offsetMask(Opcode) << log2LdstWidth(Opcode); in isCompressibleLoad()
154 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in isCompressibleStore()
117 compressedLDSTOffsetMask(unsigned Opcode) compressedLDSTOffsetMask() argument
131 getBaseAdjustForCompression(int64_t Offset,unsigned Opcode) getBaseAdjustForCompression() argument
146 const unsigned Opcode = MI.getOpcode(); isCompressibleLoad() local
155 const unsigned Opcode = MI.getOpcode(); isCompressibleStore() local
174 const unsigned Opcode = MI.getOpcode(); getRegImmPairPreventingCompression() local
281 unsigned Opcode = MI.getOpcode(); updateOperands() local
360 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) runOnMachineFunction() local
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H A DRISCVTargetTransformInfo.cpp161 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
177 switch (Opcode) { in getIntImmCostInst()
252 if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) { in shouldExpandReduction()
611 RISCVTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, in getInterleavedMemoryOpCost()
616 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getInterleavedMemoryOpCost()
619 return getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind); in getInterleavedMemoryOpCost()
623 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost()
653 Opcode, LegalVTy, Alignment, AddressSpace, CostKind); in getGatherScatterOpCost()
666 getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace, CostKind);
674 if (Opcode
142 getIntImmCostInst(unsigned Opcode,unsigned Idx,const APInt & Imm,Type * Ty,TTI::TargetCostKind CostKind,Instruction * Inst) getIntImmCostInst() argument
545 getMaskedMemoryOpCost(unsigned Opcode,Type * Src,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind) getMaskedMemoryOpCost() argument
557 getInterleavedMemoryOpCost(unsigned Opcode,Type * VecTy,unsigned Factor,ArrayRef<unsigned> Indices,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,bool UseMaskForCond,bool UseMaskForGaps) getInterleavedMemoryOpCost() argument
636 getGatherScatterOpCost(unsigned Opcode,Type * DataTy,const Value * Ptr,bool VariableMask,Align Alignment,TTI::TargetCostKind CostKind,const Instruction * I) getGatherScatterOpCost() argument
839 getCastInstrCost(unsigned Opcode,Type * Dst,Type * Src,TTI::CastContextHint CCH,TTI::TargetCostKind CostKind,const Instruction * I) getCastInstrCost() argument
954 getArithmeticReductionCost(unsigned Opcode,VectorType * Ty,std::optional<FastMathFlags> FMF,TTI::TargetCostKind CostKind) getArithmeticReductionCost() argument
989 getExtendedReductionCost(unsigned Opcode,bool IsUnsigned,Type * ResTy,VectorType * ValTy,FastMathFlags FMF,TTI::TargetCostKind CostKind) getExtendedReductionCost() argument
1034 getMemoryOpCost(unsigned Opcode,Type * Src,MaybeAlign Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,TTI::OperandValueInfo OpInfo,const Instruction * I) getMemoryOpCost() argument
1062 getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy,CmpInst::Predicate VecPred,TTI::TargetCostKind CostKind,const Instruction * I) getCmpSelInstrCost() argument
1145 getCFInstrCost(unsigned Opcode,TTI::TargetCostKind CostKind,const Instruction * I) getCFInstrCost() argument
1154 getVectorInstrCost(unsigned Opcode,Type * Val,TTI::TargetCostKind CostKind,unsigned Index,Value * Op0,Value * Op1) getVectorInstrCost() argument
1269 getArithmeticInstrCost(unsigned Opcode,Type * Ty,TTI::TargetCostKind CostKind,TTI::OperandValueInfo Op1Info,TTI::OperandValueInfo Op2Info,ArrayRef<const Value * > Args,const Instruction * CxtI) getArithmeticInstrCost() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp133 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
138 Opcode in isXMMLoadOpcode()
143 isYMMLoadOpcode(unsigned Opcode) isYMMLoadOpcode() argument
153 isPotentialBlockedMemCpyLd(unsigned Opcode) isPotentialBlockedMemCpyLd() argument
209 isPotentialBlockingStoreInst(unsigned Opcode,unsigned LoadOpcode) isPotentialBlockingStoreInst() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp112 static Desc getDescImpl(ArrayRef<Desc> Descriptions, unsigned Opcode) { in getDescImpl() argument
114 if (Opcode >= Descriptions.size()) in getDescImpl()
116 return Descriptions[Opcode]; in getDescImpl()
119 static Desc getOpDesc(unsigned Opcode) { in getOpDesc() argument
121 return getDescImpl(Descriptions, Opcode); in getOpDesc()
135 static Desc getSubOpDesc(unsigned Opcode, unsigned SubOpcode) { in getSubOpDesc() argument
136 assert(Opcode == DW_OP_LLVM_user); in getSubOpDesc()
145 Opcode = Data.getU8(&Offset); in extract()
147 Desc = getOpDesc(Opcode); in extract()
161 Desc = getSubOpDesc(Opcode, Operand in extract()
259 prettyPrintRegisterOp(DWARFUnit * U,raw_ostream & OS,DIDumpOptions DumpOpts,uint8_t Opcode,ArrayRef<uint64_t> Operands) prettyPrintRegisterOp() argument
445 uint8_t Opcode = Op.getCode(); printCompactDWARFExpr() local
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.h85 unsigned Opcode; member
89 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
90 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
91 : Opcode(Opcode), Idx(Idx), Type(Type) {} in InstrAspect()
94 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type;
158 const unsigned OpcodeIdx = Aspect.Opcode in setAction()
180 setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode,const unsigned TypeIdx,SizeChangeStrategy S) setLegalizeScalarToDifferentSizeStrategy() argument
191 setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode,const unsigned TypeIdx,SizeChangeStrategy S) setLegalizeVectorElementToDifferentSizeStrategy() argument
311 setScalarAction(const unsigned Opcode,const unsigned TypeIndex,const SizeAndActionsVec & SizeAndActions) setScalarAction() argument
317 setPointerAction(const unsigned Opcode,const unsigned TypeIndex,const unsigned AddressSpace,const SizeAndActionsVec & SizeAndActions) setPointerAction() argument
334 setScalarInVectorAction(const unsigned Opcode,const unsigned TypeIndex,const SizeAndActionsVec & SizeAndActions) setScalarInVectorAction() argument
345 setVectorNumElementAction(const unsigned Opcode,const unsigned TypeIndex,const unsigned ElementSize,const SizeAndActionsVec & SizeAndActions) setVectorNumElementAction() argument
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetOpcodes.h30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
H A DISDOpcodes.h1466 inline bool isBitwiseLogicOp(unsigned Opcode) {
1467 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
1474 /// Whether this is a vector-predicated Opcode. in isIndexTypeSigned()
1475 bool isVPOpcode(unsigned Opcode);
1478 bool isVPBinaryOp(unsigned Opcode);
1481 bool isVPReduction(unsigned Opcode);
1484 std::optional<unsigned> getVPMaskIdx(unsigned Opcode);
1487 std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);
1398 isBitwiseLogicOp(unsigned Opcode) isBitwiseLogicOp() argument
1577 isExtOpcode(unsigned Opcode) isExtOpcode() argument
1582 isExtVecInRegOpcode(unsigned Opcode) isExtVecInRegOpcode() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerInfo.cpp80 OS << "Opcode=" << Opcode << ", Tys={"; in print()
269 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode()
270 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
271 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
274 unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const { in getActionDefinitionsIdx()
275 unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); in getActionDefinitionsIdx()
277 LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias in getActionDefinitionsIdx()
287 LegalizerInfo::getActionDefinitions(unsigned Opcode) cons in getActionDefinitions()
291 getActionDefinitionsBuilder(unsigned Opcode) getActionDefinitionsBuilder() argument
382 for (unsigned Opcode = FirstOp; Opcode <= LastOp; ++Opcode) { verify() local
411 for (unsigned Opcode : FailedOpcodes) verify() local
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/freebsd-src/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
100 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx()
101 ((Opcode & 0x3f) << 2) + 4); in Decode_00xxxxxx()
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
106 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx()
107 ((Opcode & 0x3f) << 2) + 4); in Decode_01xxxxxx()
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101()
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
130 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h72 void EmitInt8(unsigned Opcode) { in EmitInt8() argument
73 Ops.push_back(Opcode & 0xff); in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16() argument
78 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
79 Ops.push_back(Opcode & 0xff); in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes() argument
84 Ops.insert(Ops.end(), Opcode, Opcode + Size); in emitBytes()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTargetTransformInfo.cpp164 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getIntrinsicInstrCost()
170 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); in getIntrinsicInstrCost()
175 if (Opcode == Instruction::Store) in getAddressComputationCost()
176 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getAddressComputationCost()
217 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind, in getMemoryOpCost()
222 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
225 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMemoryOpCost()
239 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getMaskedMemoryOpCost()
241 return BaseT::getGatherScatterOpCost(Opcode, DataT in getMaskedMemoryOpCost()
178 getMemoryOpCost(unsigned Opcode,Type * Src,MaybeAlign Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,TTI::OperandValueInfo OpInfo,const Instruction * I) getMemoryOpCost() argument
236 getMaskedMemoryOpCost(unsigned Opcode,Type * Src,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind) getMaskedMemoryOpCost() argument
252 getGatherScatterOpCost(unsigned Opcode,Type * DataTy,const Value * Ptr,bool VariableMask,Align Alignment,TTI::TargetCostKind CostKind,const Instruction * I) getGatherScatterOpCost() argument
259 getInterleavedMemoryOpCost(unsigned Opcode,Type * VecTy,unsigned Factor,ArrayRef<unsigned> Indices,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,bool UseMaskForCond,bool UseMaskForGaps) getInterleavedMemoryOpCost() argument
271 getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy,CmpInst::Predicate VecPred,TTI::TargetCostKind CostKind,const Instruction * I) getCmpSelInstrCost() argument
287 getArithmeticInstrCost(unsigned Opcode,Type * Ty,TTI::TargetCostKind CostKind,TTI::OperandValueInfo Op1Info,TTI::OperandValueInfo Op2Info,ArrayRef<const Value * > Args,const Instruction * CxtI) getArithmeticInstrCost() argument
307 getCastInstrCost(unsigned Opcode,Type * DstTy,Type * SrcTy,TTI::CastContextHint CCH,TTI::TargetCostKind CostKind,const Instruction * I) getCastInstrCost() argument
334 getVectorInstrCost(unsigned Opcode,Type * Val,TTI::TargetCostKind CostKind,unsigned Index,Value * Op0,Value * Op1) getVectorInstrCost() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp190 static unsigned getOppositeBranchOpc(unsigned Opcode) { in getOppositeBranchOpc() argument
191 switch (Opcode) { in getOppositeBranchOpc()
405 unsigned Opcode = 0; in storeRegToStackSlot() local
408 Opcode = CSKY::ST32W; // Optimize for 16bit in storeRegToStackSlot()
410 Opcode = CSKY::SPILL_CARRY; in storeRegToStackSlot()
413 Opcode = CSKY::FST_S; in storeRegToStackSlot()
415 Opcode = CSKY::FST_D; in storeRegToStackSlot()
417 Opcode = CSKY::f2FST_S; in storeRegToStackSlot()
419 Opcode = CSKY::f2FST_D; in storeRegToStackSlot()
428 BuildMI(MBB, I, DL, get(Opcode)) in storeRegToStackSlot()
449 unsigned Opcode = 0; loadRegFromStackSlot() local
521 unsigned Opcode = 0; copyPhysReg() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp178 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
221 unsigned Opcode = MI.getOpcode(); in getMemoryOpOffset() local
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
228 Opcode in getMemoryOpOffset()
256 getLoadStoreMultipleOpcode(unsigned Opcode,ARM_AM::AMSubMode Mode) getLoadStoreMultipleOpcode() argument
341 getLoadStoreMultipleSubMode(unsigned Opcode) getLoadStoreMultipleSubMode() argument
629 CreateLoadStoreMulti(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) CreateLoadStoreMulti() argument
836 CreateLoadStoreDouble(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,int Offset,unsigned Base,bool BaseKill,unsigned Opcode,ARMCC::CondCodes Pred,unsigned PredReg,const DebugLoc & DL,ArrayRef<std::pair<unsigned,bool>> Regs,ArrayRef<MachineInstr * > Instrs) const CreateLoadStoreDouble() argument
862 unsigned Opcode = First->getOpcode(); MergeOpsUpdate() local
991 unsigned Opcode = MI.getOpcode(); mayCombineMisaligned() local
1006 unsigned Opcode = FirstMI->getOpcode(); FormCandidates() local
1298 unsigned Opcode = MI->getOpcode(); MergeBaseUpdateLSMultiple() local
1476 unsigned Opcode = MI->getOpcode(); MergeBaseUpdateLoadStore() local
1614 unsigned Opcode = MI.getOpcode(); MergeBaseUpdateLSDouble() local
1678 unsigned Opcode = MI.getOpcode(); isMemoryOp() local
1763 unsigned Opcode = MI->getOpcode(); FixInvalidRegPairOp() local
1896 unsigned Opcode = MBBI->getOpcode(); LoadStoreMultipleOpti() local
2000 unsigned Opcode = Merged->getOpcode(); LoadStoreMultipleOpti() local
2051 unsigned Opcode = PrevMI.getOpcode(); MergeReturnIntoLDM() local
2263 unsigned Opcode = Op0->getOpcode(); CanFormLdStDWord() local
2993 isLegalOrConvertableAddressImm(unsigned Opcode,int Imm,const TargetInstrInfo * TII,int & CodesizeEstimate) isLegalOrConvertableAddressImm() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp230 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
235 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); in getIntImmCostInst()
246 switch (Opcode) { in getIntImmCostInst()
553 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, in vectorCostAdjustmentFactor() argument
571 int ISD = TLI->InstructionOpcodeToISD(Opcode); in vectorCostAdjustmentFactor()
585 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
589 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); in getArithmeticInstrCost()
591 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Ty, nullptr); in getArithmeticInstrCost()
597 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
602 Opcode, T in getArithmeticInstrCost()
628 getCFInstrCost(unsigned Opcode,TTI::TargetCostKind CostKind,const Instruction * I) getCFInstrCost() argument
637 getCastInstrCost(unsigned Opcode,Type * Dst,Type * Src,TTI::CastContextHint CCH,TTI::TargetCostKind CostKind,const Instruction * I) getCastInstrCost() argument
657 getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy,CmpInst::Predicate VecPred,TTI::TargetCostKind CostKind,const Instruction * I) getCmpSelInstrCost() argument
675 getVectorInstrCost(unsigned Opcode,Type * Val,TTI::TargetCostKind CostKind,unsigned Index,Value * Op0,Value * Op1) getVectorInstrCost() argument
755 getMemoryOpCost(unsigned Opcode,Type * Src,MaybeAlign Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,TTI::OperandValueInfo OpInfo,const Instruction * I) getMemoryOpCost() argument
845 getInterleavedMemoryOpCost(unsigned Opcode,Type * VecTy,unsigned Factor,ArrayRef<unsigned> Indices,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,bool UseMaskForCond,bool UseMaskForGaps) getInterleavedMemoryOpCost() argument
1004 hasActiveVectorLength(unsigned Opcode,Type * DataType,Align Alignment) const hasActiveVectorLength() argument
1032 getVPMemoryOpCost(unsigned Opcode,Type * Src,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,const Instruction * I) getVPMemoryOpCost() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp71 unsigned Opcode = Inst.getOpcode(); in checkCustomHazard()
77 switch (Opcode) { in checkCustomHazard()
181 unsigned Opcode = Inst.getOpcode(); in computeWaitCnt()
183 switch (Opcode) { in computeWaitCnt()
200 << MCII.getName(Opcode) << " will be completely " in computeWaitCnt()
203 switch (Opcode) { in computeWaitCnt()
248 unsigned Opcode = Inst->getOpcode(); in generateWaitCntInfo()
249 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo() local
253 if (isAlwaysGDS(Opcode) || hasModifiersSet(Inst, AMDGPU::OpName::gds)) in generateWaitCntInfo()
267 } else if (isVMEM(MCID) && !AMDGPU::getMUBUFIsBufferInv(Opcode)) { in generateWaitCntInfo()
72 unsigned Opcode = Inst.getOpcode(); checkCustomHazard() local
182 unsigned Opcode = Inst.getOpcode(); computeWaitCnt() local
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