Lines Matching refs:Opcode

196   unsigned Opcode = getOpcodeForOffset(
199 MI.setDesc(get(Opcode));
208 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
209 MI.setDesc(get(Opcode));
270 unsigned Opcode;
274 Opcode = SystemZ::RISBHH;
276 Opcode = SystemZ::RISBHL;
278 Opcode = SystemZ::RISBLH;
284 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
759 unsigned Opcode = MI.getOpcode();
760 if (Opcode == SystemZ::Return ||
761 Opcode == SystemZ::Return_XPLINK ||
762 Opcode == SystemZ::Trap ||
763 Opcode == SystemZ::CallJG ||
764 Opcode == SystemZ::CallBR)
811 unsigned Opcode = MI.getOpcode();
812 if (Opcode == SystemZ::Trap) {
819 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
820 MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn
828 if (Opcode == SystemZ::CallJG) {
842 if (Opcode == SystemZ::CallBR) {
932 unsigned Opcode =
934 BuildMI(MBB, MBBI, DL, get(Opcode))
966 unsigned Opcode;
968 Opcode = SystemZ::LGR;
971 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
973 Opcode = SystemZ::LDR;
975 Opcode = SystemZ::LXR;
977 Opcode = SystemZ::VLR32;
979 Opcode = SystemZ::VLR64;
981 Opcode = SystemZ::VLR;
983 Opcode = SystemZ::CPYA;
987 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
1047 static LogicOp interpretAndImmediate(unsigned Opcode) {
1048 switch (Opcode) {
1161 SystemZInstrInfo::getInverseOpcode(unsigned Opcode) const {
1163 switch (Opcode) {
1198 unsigned Opcode = MI.getOpcode();
1213 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1239 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1242 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1244 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1253 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1255 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1258 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1260 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1268 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1270 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1273 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1275 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1284 switch (Opcode) {
1309 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1310 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1311 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1381 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1408 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1409 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1894 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1897 const MCInstrDesc &MCID = get(Opcode);
1901 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1907 return Opcode;
1911 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1915 // Check whether Opcode allows signed 20-bit displacements.
1917 return Opcode;
1923 switch (Opcode) {
1940 bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
1941 const MCInstrDesc &MCID = get(Opcode);
1943 return SystemZ::getDisp12Opcode(Opcode) >= 0;
1944 return SystemZ::getDisp20Opcode(Opcode) >= 0;
1947 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1948 switch (Opcode) {
2000 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
2003 switch (Opcode) {
2024 switch (Opcode) {
2045 switch (Opcode) {
2066 switch (Opcode) {
2087 switch (Opcode) {
2188 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
2191 switch (Opcode) {
2211 unsigned Opcode = 0;
2213 Opcode = SystemZ::LGHI;
2215 Opcode = SystemZ::LLILL;
2217 Opcode = SystemZ::LLILH;
2221 Opcode = SystemZ::LGFI;
2222 if (Opcode) {
2223 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);