Lines Matching refs:Opcode
178 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
221 unsigned Opcode = MI.getOpcode();
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
228 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi ||
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
256 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {
257 switch (Opcode) {
341 static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode) {
342 switch (Opcode) {
512 // The offsets are scaled by 1, 2 or 4 depending on the Opcode.
630 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
650 if (Opcode == ARM::tLDRi)
652 else if (Opcode == ARM::tSTRi)
658 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
668 } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
671 if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return nullptr;
685 if (isi32Load(Opcode)) {
695 if (!isLoadSingle(Opcode))
730 (!isi32Store(Opcode) || !ContainsReg(Regs, Base));
780 bool isDef = isLoadSingle(Opcode);
784 Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
785 if (!Opcode)
803 if (Opcode == ARM::tLDMIA) {
806 Opcode = ARM::tLDMIA_UPD;
809 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
821 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
837 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
841 bool IsLoad = isi32Load(Opcode);
842 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");
863 unsigned Opcode = First->getOpcode();
864 bool IsLoad = isLoadSingle(Opcode);
914 Opcode, Pred, PredReg, DL, Regs,
918 Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);
943 if (isLoadSingle(Opcode)) {
964 assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD);
992 unsigned Opcode = MI.getOpcode();
993 if (!isi32Load(Opcode) && !isi32Store(Opcode))
1007 unsigned Opcode = FirstMI->getOpcode();
1008 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
1028 if (STI->isCortexM3() && isi32Load(Opcode) &&
1049 switch (Opcode) {
1299 unsigned Opcode = MI->getOpcode();
1314 ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);
1349 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
1477 unsigned Opcode = MI->getOpcode();
1479 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
1480 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
1481 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
1482 if (isi32Load(Opcode) || isi32Store(Opcode))
1503 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1505 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1511 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1514 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1524 bool isLd = isLoadSingle(Opcode);
1615 unsigned Opcode = MI.getOpcode();
1616 assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) &&
1640 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;
1645 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;
1662 assert(TII->get(Opcode).getNumOperands() == 6 &&
1664 "Unexpected number of operands in Opcode specification.");
1679 unsigned Opcode = MI.getOpcode();
1680 switch (Opcode) {
1764 unsigned Opcode = MI->getOpcode();
1765 // FIXME: Code/comments below check Opcode == t2STRDi8, but this check returns
1767 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)
1780 (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();
1782 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&
1788 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
1789 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1897 unsigned Opcode = MBBI->getOpcode();
1907 CurrOpc = Opcode;
1913 if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
1922 if (isLoadSingle(Opcode)) {
2001 unsigned Opcode = Merged->getOpcode();
2002 if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8)
2052 unsigned Opcode = PrevMI.getOpcode();
2053 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
2054 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
2055 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
2060 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
2061 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
2265 unsigned Opcode = Op0->getOpcode();
2266 if (Opcode == ARM::LDRi12) {
2268 } else if (Opcode == ARM::STRi12) {
2270 } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
2274 } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
2990 // Given a memory access Opcode, check that the give Imm would be a valid Offset
2995 static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm,
2998 if (isLegalAddressImm(Opcode, Imm, TII))
3002 const MCInstrDesc &Desc = TII->get(Opcode);