| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 51 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); computeLegalValueVTs() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); CreateRegs() local
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| H A D | SelectionDAGBuilder.cpp | 356 MVT RegisterVT; getCopyFromPartsVector() local
761 MVT RegisterVT; getCopyToPartsVector() local
865 MVT RegisterVT = RegsForValue() local
894 MVT RegisterVT = isABIMangled() getCopyFromRegs() local
977 MVT RegisterVT = isABIMangled() getCopyToRegs() local
1062 MVT RegisterVT = RegVTs[Value]; AddInlineAsmOperands() local
1079 MVT RegisterVT = std::get<1>(CountAndVT); getRegsAndSizes() local
10753 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT); LowerCallTo() local
10819 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), LowerCallTo() local
11103 MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(), LowerCallTo() local
11398 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); LowerArguments() local
11528 MVT RegisterVT = TLI->getRegisterTypeForCallingConv( LowerArguments() local
[all...] |
| H A D | FastISel.cpp | 1011 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
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| H A D | SelectionDAG.cpp | 2476 MVT RegisterVT; getReducedAlign() local
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 443 getNumRegisters(LLVMContext & Context,EVT VT,std::optional<MVT> RegisterVT) getNumRegisters() argument
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1254 getVectorTypeBreakdownMVT(MVT VT,MVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT,TargetLoweringBase * TLI) getVectorTypeBreakdownMVT() argument
1640 MVT RegisterVT; computeRegisterProperties() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 110 MVT RegisterVT; getRegisterTypeForCallingConv() local
144 MVT RegisterVT; getNumRegistersForCallingConv() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1180 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) getVectorTypeBreakdownForCallingConv() argument
1721 MVT RegisterVT; getRegisterType() local
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| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 3135 getNumRegisters(LLVMContext & Context,EVT VT,std::optional<MVT> RegisterVT=std::nullopt) const getNumRegisters() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1197 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); analyzeFormalArgumentsCompute() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 22014 MVT RegisterVT = OutArg.VT; constructArgInfos() local
22047 MVT RegisterVT = constructArgInfos() local
22061 MVT RegisterVT = constructArgInfos() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 28418 MVT RegisterVT; getRegisterTypeForCallingConv() local
[all...] |