[NFC][DAGISel] Remove dead code.

[VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG support.

The generic implementation is umin(TC, VF * vscale).

Lowering to vsetvli for RISC-V will come in a futur

[VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG support.

The generic implementation is umin(TC, VF * vscale).

Lowering to vsetvli for RISC-V will come in a future patch.

This patch is a pre-requisite to be able to CodeGen vectorized code from
D99750.

Reviewed By: reames, frasercrmck

Differential Revision: https://reviews.llvm.org/D149916

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[SelectionDAGBuilder] Handle entry_value dbg.value intrinsics

Summary:
DbgValue intrinsics whose expression is an entry_value and whose address is
described an llvm::Argument must be lowered to the

[SelectionDAGBuilder] Handle entry_value dbg.value intrinsics

Summary:
DbgValue intrinsics whose expression is an entry_value and whose address is
described an llvm::Argument must be lowered to the corresponding livein physical
register for that Argument.

Depends on D151329

Reviewers: aprantl

Subscribers:

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[SelectionDAGBuilder] Use getPtrExtOrTrunc in place of getZExtOrTrunc. NFC

This getZExtOrTrunc seems to have been added when getPtrExtOrTrunc
was introduced. getPtrExtOrTrunc is currently equivalent

[SelectionDAGBuilder] Use getPtrExtOrTrunc in place of getZExtOrTrunc. NFC

This getZExtOrTrunc seems to have been added when getPtrExtOrTrunc
was introduced. getPtrExtOrTrunc is currently equivalent to getZExtOrTrunc,
but could be changed for some target in the future.

Reviewed By: t.p.northover

Differential Revision: https://reviews.llvm.org/D149680

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[1/11][IR] Permit load/store/alloca for struct of the same scalable vector type

This patch-set aims to simplify the existing RVV segment load/store
intrinsics to use a type that represents a tuple o

[1/11][IR] Permit load/store/alloca for struct of the same scalable vector type

This patch-set aims to simplify the existing RVV segment load/store
intrinsics to use a type that represents a tuple of vectors instead.

To achieve this, first we need to relax the current limitation for an
aggregate type to be a target of load/store/alloca when the aggregate
type contains homogeneous scalable vector types. Then to adjust the
prolog of an LLVM function during lowering to clang. Finally we
re-define the RVV segment load/store intrinsics to use the tuple types.

The pull request under the RVV intrinsic specification is
riscv-non-isa/rvv-intrinsic-doc#198

---

This is the 1st patch of the patch-set. This patch is originated from
D98169.

This patch allows aggregate type (StructType) that contains homogeneous
scalable vector types to be a target of load/store/alloca. The RFC of
this patch was posted in LLVM Discourse.

https://discourse.llvm.org/t/rfc-ir-permit-load-store-alloca-for-struct-of-the-same-scalable-vector-type/69527

The main changes in this patch are:

Extend `StructLayout::StructSize` from `uint64_t` to `TypeSize` to
accommodate an expression of scalable size.

Allow `StructType:isSized` to also return true for homogeneous
scalable vector types.

Let `Type::isScalableTy` return true when `Type` is `StructType`
and contains scalable vectors

Extra description is added in the LLVM Language Reference Manual on the
relaxation of this patch.

Authored-by: Hsiangkai Wang <kai.wang@sifive.com>
Co-Authored-by: eop Chen <eop.chen@sifive.com>

Reviewed By: craig.topper, nikic

Differential Revision: https://reviews.llvm.org/D146872

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[DebugInfo][SelectionDAG] Do not drop dbg intrinsics with empty metadata locs

Without this patch SelectionDAG silently drops dbg.values using `!{}` operands.

Related to https://discourse.llvm.org/t

[DebugInfo][SelectionDAG] Do not drop dbg intrinsics with empty metadata locs

Without this patch SelectionDAG silently drops dbg.values using `!{}` operands.

Related to https://discourse.llvm.org/t/auto-undef-debug-uses-of-a-deleted-value

This causes assignment-tracking to behaviour to match non-assignment-tracking
behaviour after a recent change (see D140990).

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D150767

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[MachineFunction][DebugInfo][nfc] Introduce EntryValue variable kind

MachineFunction keeps a table of variables whose addresses never change
throughout the function. Today, the only kinds of locatio

[MachineFunction][DebugInfo][nfc] Introduce EntryValue variable kind

MachineFunction keeps a table of variables whose addresses never change
throughout the function. Today, the only kinds of locations it can
handle are stack slots.

However, we could expand this for variables whose address is derived
from the value a register had upon function entry. One case where this
happens is with variables alive across coroutine funclets: these can
be placed in a coroutine frame object whose pointer is placed in a
register that is an argument to coroutine funclets.

```
define @foo(ptr %frame_ptr) {
dbg.declare(%frame_ptr, !some_var,
!DIExpression(EntryValue, <ptr_arithmetic>))
```

This is a patch in a series that aims to improve the debug information
generated by the CoroSplit pass in the context of `swiftasync`
arguments. Variables stored in the coroutine frame _must_ be described
the entry_value of the ABI-defined register containing a pointer to the
coroutine frame. Since these variables have a single location throughout
their lifetime, they are candidates for being stored in the
MachineFunction table.

Differential Revision: https://reviews.llvm.org/D149879

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[SelectionDAG][NFCI] Use common logic for identifying MMI vars

After function argument lowering, but prior to instruction selection,
dbg declares pointing to function arguments are lowered using spe

[SelectionDAG][NFCI] Use common logic for identifying MMI vars

After function argument lowering, but prior to instruction selection,
dbg declares pointing to function arguments are lowered using special
logic.

Later, during instruction selection (both "fast" and regular ISel), this
logic is "repeated" in order to identify which intrinsics have already
been lowered. This is bad for two reasons:

1. The logic is not _really_ repeated, the code is different, which
could lead to duplicate lowering of the intrinsic.
2. Even if the logic were repeated properly, this is still code
duplication.

This patch addresses these issues by storing all preprocessed
dbg.declare intrinsics in a set inside FuncInfo; the set is queried upon
instruction selection.

Differential Revision: https://reviews.llvm.org/D149682

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Revert part of D149033 b/c original code is correct

This reverts part of D149033 and rG8f966cedea594d9a91e585e88a80a42c04049e6c. The added test case
is kept to avoid future regression.

Reviewed By

Revert part of D149033 b/c original code is correct

This reverts part of D149033 and rG8f966cedea594d9a91e585e88a80a42c04049e6c. The added test case
is kept to avoid future regression.

Reviewed By: vzakhari, vdonaldson

Differential Revision: https://reviews.llvm.org/D149639

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[SelectionDAG] Use int64_t to store the integer power of llvm.powi

https://llvm.org/docs/LangRef.html#llvm-powi-intrinsic
The max length of the integer power of `llvm.powi` intrinsic is 32, and
the

[SelectionDAG] Use int64_t to store the integer power of llvm.powi

https://llvm.org/docs/LangRef.html#llvm-powi-intrinsic
The max length of the integer power of `llvm.powi` intrinsic is 32, and
the value can be negative. If we use `int32_t` to store this value, `-Val`
will underflow when it is `INT32_MIN`

The issue was reported in D149033.

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Revert "[SelectionDAG] Use logic right shift to avoid loop hang"

This reverts commit b73229e55543b4ba2b293adcb8b7d6025f01f7d9.

It caused LIT failure on non-X86 targets.

[SelectionDAG] Use logic right shift to avoid loop hang

Issue was reported in D149033, `Val` can be negative value and
arithmetic right shift always keeps the sign bit.

BTW, the redundant code `Val

[SelectionDAG] Use logic right shift to avoid loop hang

Issue was reported in D149033, `Val` can be negative value and
arithmetic right shift always keeps the sign bit.

BTW, the redundant code `Val = -Val` is removed by this patch.

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[NFC]Fix 2 logic dead code

First, in CodeGenPrepare.cpp, line 6891, the VectorCond will always be false
because if not function will return at 6888.
Second, in SelectionDAGBuilder.cpp, line 5443, ge

[NFC]Fix 2 logic dead code

First, in CodeGenPrepare.cpp, line 6891, the VectorCond will always be false
because if not function will return at 6888.
Second, in SelectionDAGBuilder.cpp, line 5443, getSExtValue() will return
value as int type, but now we use unsigned Val to maintain it, which make the
if condition at 5452 meaningless.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D149033

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[DebugInfo] Treat empty metadata operands the same as undef operands in SelectionDAG

Without this patch SelectionDAG silently drops dbg.values using `!{}` operands.

Related to https://discourse.llv

[DebugInfo] Treat empty metadata operands the same as undef operands in SelectionDAG

Without this patch SelectionDAG silently drops dbg.values using `!{}` operands.

Related to https://discourse.llvm.org/t/auto-undef-debug-uses-of-a-deleted-value

Reviewed By: StephenTozer

Differential Revision: https://reviews.llvm.org/D140990

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[Assignment Tracking][SelectionDAG] Downgrade dbg.assigns to dbg.values if assignment tracking is not enabled

We shouldn't be able to reach this code path from source code but this provides
a better

[Assignment Tracking][SelectionDAG] Downgrade dbg.assigns to dbg.values if assignment tracking is not enabled

We shouldn't be able to reach this code path from source code but this provides
a better fail-safe than asserting. The result of the downgrade is a degraded
debugging experience, but it is better than nothing.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D148212

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[llvm] Apply fixes from readability-redundant-control-flow (NFC)

[InstrProf] Temporal Profiling

As described in [0], this extends IRPGO to support //Temporal Profiling//.

When `-pgo-temporal-instrumentation` is used we add the `llvm.instrprof.timestamp()` intrin

[InstrProf] Temporal Profiling

As described in [0], this extends IRPGO to support //Temporal Profiling//.

When `-pgo-temporal-instrumentation` is used we add the `llvm.instrprof.timestamp()` intrinsic to the entry of functions which in turn gets lowered to a call to the compiler-rt function `INSTR_PROF_PROFILE_SET_TIMESTAMP()`. A new field in the `llvm_prf_cnts` section stores each function's timestamp. Then in `llvm-profdata merge` we convert these function timestamps into a //trace// and add it to the indexed profile.

Since these traces could significantly increase the profile size, we've added `-max-temporal-profile-trace-length` and `-temporal-profile-trace-reservoir-size` to limit the length of a trace and the number of traces in a profile, respectively.

In a future diff we plan to use these traces to construct an optimized function order to reduce the number of page faults during startup.

Special thanks to Julian Mestre for helping with reservoir sampling.

[0] https://discourse.llvm.org/t/rfc-temporal-profiling-extension-for-irpgo/68068

Reviewed By: snehasish

Differential Revision: https://reviews.llvm.org/D147287

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[SelectionDAG] Move variable declaration to its first assignment. NFC

We declared this variable and assigned it to true, but then overwrote
it before its first use.

[SelectionDAGBuilder] Use SmallVectorImpl& for function arguments. NFC

Make the reference const since we aren't modifying the vectors.

[SelectionDAG] Rename Flag->Glue. NFC

[Assignment Tracking][NFC] Cache debug-info-assignment-tracking module flag

This reduces CTMark LTO-O3-g compile time by a geomean of 0.1%.

Reviewed By: jmorse

Differential Revision: https://revie

[Assignment Tracking][NFC] Cache debug-info-assignment-tracking module flag

This reduces CTMark LTO-O3-g compile time by a geomean of 0.1%.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D146985

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Reland "[Windows SEH]: HARDWARE EXCEPTION HANDLING (MSVC -EHa) - Part 2"

This reverts commit db6a979ae82410e42430e47afa488936ba8e3025.

Reland D102817 without any change. The previous revert was a m

Reland "[Windows SEH]: HARDWARE EXCEPTION HANDLING (MSVC -EHa) - Part 2"

This reverts commit db6a979ae82410e42430e47afa488936ba8e3025.

Reland D102817 without any change. The previous revert was a mistake.

Differential Revision: https://reviews.llvm.org/D102817

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[llvm] Use isIntOrFPConstant (NFC)

[Assignment Tracking][NFC] Use RawLocationWrapper in VarLocInfo [2/x]

Use RawLocationWrapper rather than a Value to represent the location operand(s)
so that it's possible to represent multiple loca

[Assignment Tracking][NFC] Use RawLocationWrapper in VarLocInfo [2/x]

Use RawLocationWrapper rather than a Value to represent the location operand(s)
so that it's possible to represent multiple location
operands. AssignmentTrackingAnalysis still converts variadic debug intrinsics
to kill locations so this patch is NFC.

Reviewed By: StephenTozer

Differential Revision: https://reviews.llvm.org/D145911

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[AArch64][SME2] Add CodeGen support for target("aarch64.svcount").

This patch adds AArch64 CodeGen support such that the type can be passed
and returned to/from functions, and also adds support to u

[AArch64][SME2] Add CodeGen support for target("aarch64.svcount").

This patch adds AArch64 CodeGen support such that the type can be passed
and returned to/from functions, and also adds support to use this type in
load/store operations and PHI nodes.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D136862

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