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/dpdk/drivers/net/pfe/
H A Dpfe_hal.c118 gemac_enable_rx_checksum_offload(__rte_unused void *base) in gemac_enable_rx_checksum_offload() argument
128 gemac_disable_rx_checksum_offload(__rte_unused void *base) in gemac_disable_rx_checksum_offload() argument
138 gemac_set_speed(void *base, enum mac_speed gem_speed) in gemac_set_speed() argument
140 u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; in gemac_set_speed()
141 u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; in gemac_set_speed()
157 writel(ecr, (base + EMAC_ECNTRL_REG)); in gemac_set_speed()
158 writel(rcr, (base + EMAC_RCNTRL_REG)); in gemac_set_speed()
166 gemac_set_duplex(void *base, int duplex) in gemac_set_duplex() argument
169 writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base in gemac_set_duplex()
171 writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base in gemac_set_duplex()
[all …]
/dpdk/drivers/net/bnx2x/
H A Decore_fw_defs.h18 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
20 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
22 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
25 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
28 (IRO[163].base + ((funcId) * IRO[163].m1))
30 (IRO[153].base + ((funcId) * IRO[153].m1))
32 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
34 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
36 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
38 (IRO[323].base + ((pfId) * IRO[323].m1))
[all …]
/dpdk/drivers/net/qede/base/
H A Decore_iro.h11 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
14 #define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
17 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) (IRO[2].base + \
21 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) (IRO[3].base + \
25 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
28 #define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
31 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) (IRO[6].base + \
35 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) (IRO[7].base + \
39 #define XSTORM_PQ_INFO_OFFSET(pq_id) (IRO[8].base + ((pq_id) * IRO[8].m1))
42 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
[all …]
/dpdk/drivers/common/cnxk/
H A Droc_sso_debug.c9 sso_hws_dump(uintptr_t base, FILE *f) in sso_hws_dump() argument
11 fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base); in sso_hws_dump()
13 plt_read64(base + SSOW_LF_GWS_LINKS)); in sso_hws_dump()
15 plt_read64(base + SSOW_LF_GWS_PENDWQP)); in sso_hws_dump()
17 plt_read64(base + SSOW_LF_GWS_PENDSTATE)); in sso_hws_dump()
19 plt_read64(base + SSOW_LF_GWS_NW_TIM)); in sso_hws_dump()
21 plt_read64(base + SSOW_LF_GWS_TAG)); in sso_hws_dump()
23 plt_read64(base + SSOW_LF_GWS_TAG)); in sso_hws_dump()
25 plt_read64(base + SSOW_LF_GWS_SWTP)); in sso_hws_dump()
27 plt_read64(base + SSOW_LF_GWS_PENDTAG)); in sso_hws_dump()
[all …]
H A Droc_tim_irq.c11 uintptr_t base = (uintptr_t)param; in tim_lf_irq() local
15 ring = (base >> 12) & 0xFF; in tim_lf_irq()
17 intr = plt_read64(base + TIM_LF_NRSPERR_INT); in tim_lf_irq()
19 intr = plt_read64(base + TIM_LF_RAS_INT); in tim_lf_irq()
23 plt_write64(intr, base + TIM_LF_NRSPERR_INT); in tim_lf_irq()
24 plt_write64(intr, base + TIM_LF_RAS_INT); in tim_lf_irq()
28 tim_lf_register_irq(uintptr_t base, struct plt_intr_handle *handle, in tim_lf_register_irq() argument
37 plt_write64(~0ull, base + TIM_LF_NRSPERR_INT); in tim_lf_register_irq()
39 rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec); in tim_lf_register_irq()
41 plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S); in tim_lf_register_irq()
[all …]
H A Droc_sso_irq.c14 intr = plt_read64(rsrc->base + SSO_LF_GGRP_INT); in sso_hwgrp_irq()
21 plt_write64(intr, rsrc->base + SSO_LF_GGRP_INT); in sso_hwgrp_irq()
33 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1C); in sso_hwgrp_register_irq()
37 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1S); in sso_hwgrp_register_irq()
48 intr = plt_read64(rsrc->base + SSOW_LF_GWS_INT); in sso_hws_irq()
55 plt_write64(intr, rsrc->base + SSOW_LF_GWS_INT); in sso_hws_irq()
67 plt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1C); in sso_hws_register_irq()
71 plt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1S); in sso_hws_register_irq()
101 uintptr_t base = in sso_register_irqs_priv() local
105 sso->hws_rsrc[i].base = base; in sso_register_irqs_priv()
[all …]
H A Droc_npa_irq.c14 intr = plt_read64(lf->base + NPA_LF_ERR_INT); in npa_err_irq()
21 plt_write64(intr, lf->base + NPA_LF_ERR_INT); in npa_err_irq()
33 plt_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C); in npa_register_err_irq()
38 plt_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1S); in npa_register_err_irq()
52 plt_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C); in npa_unregister_err_irq()
62 intr = plt_read64(lf->base + NPA_LF_RAS); in npa_ras_irq()
69 plt_write64(intr, lf->base + NPA_LF_RAS); in npa_ras_irq()
81 plt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C); in npa_register_ras_irq()
85 plt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S); in npa_register_ras_irq()
99 plt_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C); in npa_unregister_ras_irq()
[all …]
H A Droc_nix_irq.c14 nix->base + NIX_LF_ERR_INT_ENA_W1S); in nix_err_intr_enb_dis()
16 plt_write64(~0ull, nix->base + NIX_LF_ERR_INT_ENA_W1C); in nix_err_intr_enb_dis()
23 plt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1S); in nix_ras_intr_enb_dis()
25 plt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1C); in nix_ras_intr_enb_dis()
34 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1S(rx_queue_id)); in roc_nix_rx_queue_intr_enable()
43 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(rx_queue_id)); in roc_nix_rx_queue_intr_disable()
69 intr = plt_read64(nix->base + NIX_LF_ERR_INT); in nix_lf_err_irq()
76 plt_write64(intr, nix->base + NIX_LF_ERR_INT); in nix_lf_err_irq()
118 intr = plt_read64(nix->base + NIX_LF_RAS); in nix_lf_ras_irq()
124 plt_write64(intr, nix->base + NIX_LF_RAS); in nix_lf_ras_irq()
[all …]
H A Dcnxk_security_ar.h29 uint64_t base; /**< base of the anti-replay window */ member
61 uint64_t base = ar->base; in cnxk_on_anti_replay_check() local
74 if (likely(seq > base)) { in cnxk_on_anti_replay_check()
75 shift = seq - base; in cnxk_on_anti_replay_check()
107 ar->base = seq; in cnxk_on_anti_replay_check()
111 bit_pos = base - seq; in cnxk_on_anti_replay_check()
130 if (likely(seq > base)) { in cnxk_on_anti_replay_check()
133 shift = seq - base; in cnxk_on_anti_replay_check()
158 ar->base = seq; in cnxk_on_anti_replay_check()
181 if (unlikely((seq + winsz) <= base)) in cnxk_on_anti_replay_check()
H A Droc_ree.c424 uintptr_t base = (uintptr_t)param; in roc_ree_lf_err_intr_handler() local
428 lf_id = (base >> 12) & 0xFF; in roc_ree_lf_err_intr_handler()
430 intr = plt_read64(base + REE_LF_MISC_INT); in roc_ree_lf_err_intr_handler()
437 plt_write64(intr, base + REE_LF_MISC_INT); in roc_ree_lf_err_intr_handler()
442 uintptr_t base) in roc_ree_lf_err_intr_unregister() argument
447 plt_write64(~0ull, base + REE_LF_MISC_INT_ENA_W1C); in roc_ree_lf_err_intr_unregister()
450 roc_ree_lf_err_intr_handler, (void *)base, msix_off); in roc_ree_lf_err_intr_unregister()
456 uintptr_t base; in roc_ree_err_intr_unregister() local
460 base = REE_LF_BAR2(vf, i); in roc_ree_err_intr_unregister()
461 roc_ree_lf_err_intr_unregister(vf, vf->lf_msixoff[i], base); in roc_ree_err_intr_unregister()
[all …]
H A Droc_sso_dp.h9 roc_sso_hws_head_wait(uintptr_t base) in roc_sso_hws_head_wait() argument
11 uintptr_t tag_op = base + SSOW_LF_GWS_TAG; in roc_sso_hws_head_wait()
34 roc_sso_hws_is_head(uintptr_t base) in roc_sso_hws_is_head() argument
36 uintptr_t tag_op = base + SSOW_LF_GWS_TAG; in roc_sso_hws_is_head()
H A Droc_nix_inl_dp.h30 roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx) in roc_nix_inl_ot_ipsec_inb_sa() argument
34 return PLT_PTR_ADD(base, off); in roc_nix_inl_ot_ipsec_inb_sa()
38 roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx) in roc_nix_inl_ot_ipsec_outb_sa() argument
42 return PLT_PTR_ADD(base, off); in roc_nix_inl_ot_ipsec_outb_sa()
/dpdk/drivers/net/pfe/base/
H A Dpfe.h298 void bmu_init(void *base, struct BMU_CFG *cfg);
299 void bmu_reset(void *base);
300 void bmu_enable(void *base);
301 void bmu_disable(void *base);
302 void bmu_set_config(void *base, struct BMU_CFG *cfg);
314 void gemac_init(void *base, void *config);
315 void gemac_disable_rx_checksum_offload(void *base);
316 void gemac_enable_rx_checksum_offload(void *base);
317 void gemac_set_mdc_div(void *base, int mdc_div);
318 void gemac_set_speed(void *base, enum mac_speed gem_speed);
[all …]
/dpdk/app/test/
H A Dtest_cryptodev_mod_test_vectors.h17 } base; member
37 } base; member
54 .base = {
117 .base = {
170 uint8_t base[] = { variable
273 .base = {
308 .base = {
348 .base = {
425 .base = {
519 .base = {
[all …]
H A Dtest_ptr_compress.c20 void *base, in test_ptr_compress_params() argument
37 ptrs[i] = (char *)base + mem_sz - i * align; in test_ptr_compress_params()
39 ptrs[i] = (char *)base + i * align; in test_ptr_compress_params()
44 base, ptrs, offsets32, num_ptrs, align_exp); in test_ptr_compress_params()
45 rte_ptr_decompress_32_shift(base, offsets32, ptrs_out, num_ptrs, in test_ptr_compress_params()
49 base, ptrs, offsets16, num_ptrs, align_exp); in test_ptr_compress_params()
50 rte_ptr_decompress_16_shift(base, offsets16, ptrs_out, num_ptrs, in test_ptr_compress_params()
58 base, mem_sz, align_exp, num_ptrs, in test_ptr_compress_params()
/dpdk/lib/eal/freebsd/include/
H A Drte_os_shim.h21 rte_timespec_get(struct timespec *now, int base) in rte_timespec_get() argument
23 if (base != TIME_UTC || clock_gettime(CLOCK_REALTIME, now) < 0) in rte_timespec_get()
25 return base; in rte_timespec_get()
28 #define timespec_get(ts, base) rte_timespec_get(ts, base) argument
/dpdk/drivers/net/ena/
H A Dmeson.build13 'base/ena_com.c',
14 'base/ena_eth_com.c',
19 includes += include_directories('base', 'base/ena_defs')
/dpdk/lib/eal/ppc/
H A Drte_cycles.c21 static unsigned long base; in get_tsc_freq_arch()
26 if (base != 0) in get_tsc_freq_arch()
42 base = strtoul(ret + 1, NULL, 10); in get_tsc_freq_arch()
47 return (uint64_t) base; in get_tsc_freq_arch()
/dpdk/drivers/bus/dpaa/base/qbman/
H A Dprocess.c46 uint32_t base; /* Return value, the start of the allocated range */ member
56 uint32_t base; member
62 uint32_t base; member
73 int process_alloc(enum dpaa_id_type id_type, uint32_t *base, uint32_t num, in process_alloc() argument
90 base[ret] = id.base + ret; in process_alloc()
94 void process_release(enum dpaa_id_type id_type, uint32_t base, uint32_t num) in process_release() argument
98 .base = base, in process_release()
110 id_type, base, num); in process_release()
113 int process_reserve(enum dpaa_id_type id_type, uint32_t base, uint32_t num) in process_reserve() argument
117 .base = base, in process_reserve()
/dpdk/lib/eal/windows/include/
H A Drte_os_shim.h57 rte_timespec_get(struct timespec *now, int base) in rte_timespec_get()
67 if (base != TIME_UTC) in rte_timespec_get()
75 return base;
78 #define timespec_get(ts, base) rte_timespec_get(ts, base)
55 rte_timespec_get(struct timespec * now,int base) rte_timespec_get() argument
76 timespec_get(ts,base) global() argument
/dpdk/drivers/net/cxgbe/
H A Dmeson.build22 'base/t4_hw.c',
23 'base/t4vf_hw.c',
25 includes += include_directories('base')
/dpdk/drivers/event/cnxk/tx/cn9k/
H A Dtx_all_offload.c20 return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, (uint64_t *)ws->tx_adptr_data, flags); in cn9k_sso_hws_tx_adptr_enq_seg_all_offload()
35 return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, (uint64_t *)ws->tx_adptr_data, in cn9k_sso_hws_tx_adptr_enq_dual_seg_all_offload()
50 return cn9k_sso_hws_event_tx(ws->base, &ev[0], cmd, (uint64_t *)ws->tx_adptr_data, flags); in cn9k_sso_hws_tx_adptr_enq_seg_all_offload_tst()
65 return cn9k_sso_hws_event_tx(ws->base[!ws->vws], &ev[0], cmd, (uint64_t *)ws->tx_adptr_data, in cn9k_sso_hws_tx_adptr_enq_dual_seg_all_offload_tst()
/dpdk/drivers/net/dpaa2/
H A Dmeson.build11 'base/dpaa2_hw_dpni.c',
12 'base/dpaa2_tlu_hash.c',
27 includes += include_directories('base', 'mc')
/dpdk/lib/eal/unix/
H A Deal_debug.c62 uintptr_t base; in rte_dump_stack() local
95 base = (uintptr_t)info.dli_saddr; in rte_dump_stack()
100 base = (uintptr_t)info.dli_fbase; in rte_dump_stack()
105 offset = (uintptr_t)pc - base; in rte_dump_stack()
/dpdk/drivers/raw/ifpga/base/
H A Dopae_eth_group.c73 opae_writeq(v, dev->base + ETH_GROUP_CTRL); in eth_group_write_reg()
102 opae_writeq(v, dev->base + ETH_GROUP_CTRL); in eth_group_read_reg()
104 if (opae_readq_poll_timeout(dev->base + ETH_GROUP_STAT, in eth_group_read_reg()
281 struct eth_group_device *eth_group_probe(void *base) in eth_group_probe() argument
289 dev->base = (u8 *)base; in eth_group_probe()
291 dev->info.info = opae_readq(dev->base + ETH_GROUP_INFO); in eth_group_probe()

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