1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
3 */
4
5 #include "roc_api.h"
6 #include "roc_priv.h"
7
8 static void
tim_lf_irq(void * param)9 tim_lf_irq(void *param)
10 {
11 uintptr_t base = (uintptr_t)param;
12 uint64_t intr;
13 uint8_t ring;
14
15 ring = (base >> 12) & 0xFF;
16
17 intr = plt_read64(base + TIM_LF_NRSPERR_INT);
18 plt_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr);
19 intr = plt_read64(base + TIM_LF_RAS_INT);
20 plt_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr);
21
22 /* Clear interrupt */
23 plt_write64(intr, base + TIM_LF_NRSPERR_INT);
24 plt_write64(intr, base + TIM_LF_RAS_INT);
25 }
26
27 static int
tim_lf_register_irq(uintptr_t base,struct plt_intr_handle * handle,uint16_t msix_offset)28 tim_lf_register_irq(uintptr_t base, struct plt_intr_handle *handle,
29 uint16_t msix_offset)
30 {
31 unsigned int vec;
32 int rc;
33
34 vec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;
35
36 /* Clear err interrupt */
37 plt_write64(~0ull, base + TIM_LF_NRSPERR_INT);
38 /* Set used interrupt vectors */
39 rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);
40 /* Enable hw interrupt */
41 plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);
42
43 vec = msix_offset + TIM_LF_INT_VEC_RAS_INT;
44
45 /* Clear err interrupt */
46 plt_write64(~0ull, base + TIM_LF_RAS_INT);
47 /* Set used interrupt vectors */
48 rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);
49 /* Enable hw interrupt */
50 plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);
51
52 return rc;
53 }
54
55 int
tim_register_irq_priv(struct roc_tim * roc_tim,struct plt_intr_handle * handle,uint8_t ring_id,uint16_t msix_offset)56 tim_register_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,
57 uint8_t ring_id, uint16_t msix_offset)
58 {
59 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
60 uintptr_t base;
61
62 if (msix_offset == MSIX_VECTOR_INVALID) {
63 plt_err("Invalid MSIX offset for TIM LF %d", ring_id);
64 return TIM_ERR_PARAM;
65 }
66
67 base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
68 return tim_lf_register_irq(base, handle, msix_offset);
69 }
70
71 static void
tim_lf_unregister_irq(uintptr_t base,struct plt_intr_handle * handle,uint16_t msix_offset)72 tim_lf_unregister_irq(uintptr_t base, struct plt_intr_handle *handle,
73 uint16_t msix_offset)
74 {
75 unsigned int vec;
76
77 vec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;
78
79 /* Clear err interrupt */
80 plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);
81 dev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);
82
83 vec = msix_offset + TIM_LF_INT_VEC_RAS_INT;
84
85 /* Clear err interrupt */
86 plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);
87 dev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);
88 }
89
90 void
tim_unregister_irq_priv(struct roc_tim * roc_tim,struct plt_intr_handle * handle,uint8_t ring_id,uint16_t msix_offset)91 tim_unregister_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,
92 uint8_t ring_id, uint16_t msix_offset)
93 {
94 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
95 uintptr_t base;
96
97 if (msix_offset == MSIX_VECTOR_INVALID) {
98 plt_err("Invalid MSIX offset for TIM LF %d", ring_id);
99 return;
100 }
101
102 base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
103 tim_lf_unregister_irq(base, handle, msix_offset);
104 }
105