1*309b553cSPavan Nikhilesh /* SPDX-License-Identifier: BSD-3-Clause
2*309b553cSPavan Nikhilesh * Copyright(C) 2021 Marvell.
3*309b553cSPavan Nikhilesh */
4*309b553cSPavan Nikhilesh
5*309b553cSPavan Nikhilesh #include "roc_api.h"
6*309b553cSPavan Nikhilesh #include "roc_priv.h"
7*309b553cSPavan Nikhilesh
8*309b553cSPavan Nikhilesh static void
tim_lf_irq(void * param)9*309b553cSPavan Nikhilesh tim_lf_irq(void *param)
10*309b553cSPavan Nikhilesh {
11*309b553cSPavan Nikhilesh uintptr_t base = (uintptr_t)param;
12*309b553cSPavan Nikhilesh uint64_t intr;
13*309b553cSPavan Nikhilesh uint8_t ring;
14*309b553cSPavan Nikhilesh
15*309b553cSPavan Nikhilesh ring = (base >> 12) & 0xFF;
16*309b553cSPavan Nikhilesh
17*309b553cSPavan Nikhilesh intr = plt_read64(base + TIM_LF_NRSPERR_INT);
18*309b553cSPavan Nikhilesh plt_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr);
19*309b553cSPavan Nikhilesh intr = plt_read64(base + TIM_LF_RAS_INT);
20*309b553cSPavan Nikhilesh plt_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr);
21*309b553cSPavan Nikhilesh
22*309b553cSPavan Nikhilesh /* Clear interrupt */
23*309b553cSPavan Nikhilesh plt_write64(intr, base + TIM_LF_NRSPERR_INT);
24*309b553cSPavan Nikhilesh plt_write64(intr, base + TIM_LF_RAS_INT);
25*309b553cSPavan Nikhilesh }
26*309b553cSPavan Nikhilesh
27*309b553cSPavan Nikhilesh static int
tim_lf_register_irq(uintptr_t base,struct plt_intr_handle * handle,uint16_t msix_offset)28*309b553cSPavan Nikhilesh tim_lf_register_irq(uintptr_t base, struct plt_intr_handle *handle,
29*309b553cSPavan Nikhilesh uint16_t msix_offset)
30*309b553cSPavan Nikhilesh {
31*309b553cSPavan Nikhilesh unsigned int vec;
32*309b553cSPavan Nikhilesh int rc;
33*309b553cSPavan Nikhilesh
34*309b553cSPavan Nikhilesh vec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;
35*309b553cSPavan Nikhilesh
36*309b553cSPavan Nikhilesh /* Clear err interrupt */
37*309b553cSPavan Nikhilesh plt_write64(~0ull, base + TIM_LF_NRSPERR_INT);
38*309b553cSPavan Nikhilesh /* Set used interrupt vectors */
39*309b553cSPavan Nikhilesh rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);
40*309b553cSPavan Nikhilesh /* Enable hw interrupt */
41*309b553cSPavan Nikhilesh plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);
42*309b553cSPavan Nikhilesh
43*309b553cSPavan Nikhilesh vec = msix_offset + TIM_LF_INT_VEC_RAS_INT;
44*309b553cSPavan Nikhilesh
45*309b553cSPavan Nikhilesh /* Clear err interrupt */
46*309b553cSPavan Nikhilesh plt_write64(~0ull, base + TIM_LF_RAS_INT);
47*309b553cSPavan Nikhilesh /* Set used interrupt vectors */
48*309b553cSPavan Nikhilesh rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);
49*309b553cSPavan Nikhilesh /* Enable hw interrupt */
50*309b553cSPavan Nikhilesh plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);
51*309b553cSPavan Nikhilesh
52*309b553cSPavan Nikhilesh return rc;
53*309b553cSPavan Nikhilesh }
54*309b553cSPavan Nikhilesh
55*309b553cSPavan Nikhilesh int
tim_register_irq_priv(struct roc_tim * roc_tim,struct plt_intr_handle * handle,uint8_t ring_id,uint16_t msix_offset)56*309b553cSPavan Nikhilesh tim_register_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,
57*309b553cSPavan Nikhilesh uint8_t ring_id, uint16_t msix_offset)
58*309b553cSPavan Nikhilesh {
59*309b553cSPavan Nikhilesh struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
60*309b553cSPavan Nikhilesh uintptr_t base;
61*309b553cSPavan Nikhilesh
62*309b553cSPavan Nikhilesh if (msix_offset == MSIX_VECTOR_INVALID) {
63*309b553cSPavan Nikhilesh plt_err("Invalid MSIX offset for TIM LF %d", ring_id);
64*309b553cSPavan Nikhilesh return TIM_ERR_PARAM;
65*309b553cSPavan Nikhilesh }
66*309b553cSPavan Nikhilesh
67*309b553cSPavan Nikhilesh base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
68*309b553cSPavan Nikhilesh return tim_lf_register_irq(base, handle, msix_offset);
69*309b553cSPavan Nikhilesh }
70*309b553cSPavan Nikhilesh
71*309b553cSPavan Nikhilesh static void
tim_lf_unregister_irq(uintptr_t base,struct plt_intr_handle * handle,uint16_t msix_offset)72*309b553cSPavan Nikhilesh tim_lf_unregister_irq(uintptr_t base, struct plt_intr_handle *handle,
73*309b553cSPavan Nikhilesh uint16_t msix_offset)
74*309b553cSPavan Nikhilesh {
75*309b553cSPavan Nikhilesh unsigned int vec;
76*309b553cSPavan Nikhilesh
77*309b553cSPavan Nikhilesh vec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;
78*309b553cSPavan Nikhilesh
79*309b553cSPavan Nikhilesh /* Clear err interrupt */
80*309b553cSPavan Nikhilesh plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);
81*309b553cSPavan Nikhilesh dev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);
82*309b553cSPavan Nikhilesh
83*309b553cSPavan Nikhilesh vec = msix_offset + TIM_LF_INT_VEC_RAS_INT;
84*309b553cSPavan Nikhilesh
85*309b553cSPavan Nikhilesh /* Clear err interrupt */
86*309b553cSPavan Nikhilesh plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);
87*309b553cSPavan Nikhilesh dev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);
88*309b553cSPavan Nikhilesh }
89*309b553cSPavan Nikhilesh
90*309b553cSPavan Nikhilesh void
tim_unregister_irq_priv(struct roc_tim * roc_tim,struct plt_intr_handle * handle,uint8_t ring_id,uint16_t msix_offset)91*309b553cSPavan Nikhilesh tim_unregister_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,
92*309b553cSPavan Nikhilesh uint8_t ring_id, uint16_t msix_offset)
93*309b553cSPavan Nikhilesh {
94*309b553cSPavan Nikhilesh struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
95*309b553cSPavan Nikhilesh uintptr_t base;
96*309b553cSPavan Nikhilesh
97*309b553cSPavan Nikhilesh if (msix_offset == MSIX_VECTOR_INVALID) {
98*309b553cSPavan Nikhilesh plt_err("Invalid MSIX offset for TIM LF %d", ring_id);
99*309b553cSPavan Nikhilesh return;
100*309b553cSPavan Nikhilesh }
101*309b553cSPavan Nikhilesh
102*309b553cSPavan Nikhilesh base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
103*309b553cSPavan Nikhilesh tim_lf_unregister_irq(base, handle, msix_offset);
104*309b553cSPavan Nikhilesh }
105