xref: /dpdk/drivers/common/cnxk/roc_nix_inl_dp.h (revision 8df859aabebba2625db95f16d4a2968754733bbc)
1*8df859aaSRahul Bhansali /* SPDX-License-Identifier: BSD-3-Clause
2*8df859aaSRahul Bhansali  * Copyright(C) 2022 Marvell.
3*8df859aaSRahul Bhansali  */
4*8df859aaSRahul Bhansali #ifndef _ROC_NIX_INL_DP_H_
5*8df859aaSRahul Bhansali #define _ROC_NIX_INL_DP_H_
6*8df859aaSRahul Bhansali 
7*8df859aaSRahul Bhansali /* OT INB HW area */
8*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ                                         \
9*8df859aaSRahul Bhansali 	PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN)
10*8df859aaSRahul Bhansali /* OT INB SW reserved area */
11*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128
12*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ                                         \
13*8df859aaSRahul Bhansali 	(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD)
14*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10
15*8df859aaSRahul Bhansali 
16*8df859aaSRahul Bhansali /* OT OUTB HW area */
17*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ                                        \
18*8df859aaSRahul Bhansali 	PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN)
19*8df859aaSRahul Bhansali 
20*8df859aaSRahul Bhansali /* OT OUTB SW reserved area */
21*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD 128
22*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ                                        \
23*8df859aaSRahul Bhansali 	(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD)
24*8df859aaSRahul Bhansali #define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2 9
25*8df859aaSRahul Bhansali 
26*8df859aaSRahul Bhansali /* Alignment of SA Base */
27*8df859aaSRahul Bhansali #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)
28*8df859aaSRahul Bhansali 
29*8df859aaSRahul Bhansali static inline struct roc_ot_ipsec_inb_sa *
roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base,uint64_t idx)30*8df859aaSRahul Bhansali roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx)
31*8df859aaSRahul Bhansali {
32*8df859aaSRahul Bhansali 	uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2;
33*8df859aaSRahul Bhansali 
34*8df859aaSRahul Bhansali 	return PLT_PTR_ADD(base, off);
35*8df859aaSRahul Bhansali }
36*8df859aaSRahul Bhansali 
37*8df859aaSRahul Bhansali static inline struct roc_ot_ipsec_outb_sa *
roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base,uint64_t idx)38*8df859aaSRahul Bhansali roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx)
39*8df859aaSRahul Bhansali {
40*8df859aaSRahul Bhansali 	uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2;
41*8df859aaSRahul Bhansali 
42*8df859aaSRahul Bhansali 	return PLT_PTR_ADD(base, off);
43*8df859aaSRahul Bhansali }
44*8df859aaSRahul Bhansali 
45*8df859aaSRahul Bhansali static inline void *
roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void * sa)46*8df859aaSRahul Bhansali roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void *sa)
47*8df859aaSRahul Bhansali {
48*8df859aaSRahul Bhansali 	return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_INB_HW_SZ);
49*8df859aaSRahul Bhansali }
50*8df859aaSRahul Bhansali 
51*8df859aaSRahul Bhansali static inline void *
roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void * sa)52*8df859aaSRahul Bhansali roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa)
53*8df859aaSRahul Bhansali {
54*8df859aaSRahul Bhansali 	return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ);
55*8df859aaSRahul Bhansali }
56*8df859aaSRahul Bhansali 
57*8df859aaSRahul Bhansali #endif /* _ROC_NIX_INL_DP_H_ */
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