| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v6_0.c | 1341 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1382 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()
1475 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1480 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1484 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1508 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1556 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1594 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1611 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1628 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
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| H A D | amdgpu_atomfirmware.c | 449 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
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| H A D | amdgpu_gfx_v7_0.c | 1640 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1682 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1802 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1807 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1810 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1836 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
3379 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
4278 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4295 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4313 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
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| H A D | amdgpu_gfx.h | 137 unsigned max_sh_per_se; member
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| H A D | amdgpu_gfx_v8_0.c | 1698 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1715 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1762 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1778 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1813 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
3461 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3512 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3623 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3628 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
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| H A D | amdgpu_discovery.c | 395 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
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| H A D | amdgpu_debugfs.c | 158 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
565 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
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| H A D | amdgpu_gfx_v9_0.c | 1686 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
2370 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2381 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2385 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2388 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2529 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
4211 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
6710 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
6715 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
6719 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
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| H A D | amdgpu_gfx_v10_0.c | 1533 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
1544 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
1548 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
1551 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
1572 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
1683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
5332 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
5402 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
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| H A D | amdgpu_amdkfd.c | 459 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_amdkfd_get_cu_info()
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| H A D | amdgpu_atombios.c | 735 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
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| H A D | amdgpu_kms.c | 706 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
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| H A D | amdgpu_device.c | 1683 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
3242 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_kms.c | 456 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
458 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
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| H A D | radeon_si.c | 3114 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3131 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3149 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3166 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3183 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3300 rdev->config.si.max_sh_per_se, in si_gpu_init()
3304 rdev->config.si.max_sh_per_se, in si_gpu_init()
3309 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5336 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
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| H A D | radeon_cik.c | 3208 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3225 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3243 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3261 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3363 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3368 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5815 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6582 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
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| H A D | radeon.h | 2179 unsigned max_sh_per_se; member
2210 unsigned max_sh_per_se; member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| H A D | atomfirmware.h | 1229 uint8_t max_sh_per_se; member
1249 uint8_t max_sh_per_se; member
1274 uint8_t max_sh_per_se; member
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| H A D | atombios.h | 5655 UCHAR max_sh_per_se; member
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