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Searched refs:crtcs (Results 1 – 25 of 37) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/include/drm/
H A Ddrm_atomic.h354 struct __drm_crtcs_state *crtcs; member
496 return state->crtcs[drm_crtc_index(crtc)].state; in drm_atomic_get_existing_crtc_state()
511 return state->crtcs[drm_crtc_index(crtc)].old_state; in drm_atomic_get_old_crtc_state()
525 return state->crtcs[drm_crtc_index(crtc)].new_state; in drm_atomic_get_new_crtc_state()
771 for_each_if ((__state)->crtcs[__i].ptr && \
772 ((crtc) = (__state)->crtcs[__i].ptr, \
774 (old_crtc_state) = (__state)->crtcs[__i].old_state, \
776 (new_crtc_state) = (__state)->crtcs[__i].new_state, 1))
793 for_each_if ((__state)->crtcs[__i].ptr && \
794 ((crtc) = (__state)->crtcs[__i].ptr, \
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/
H A Ddrm_client_modeset.c500 struct drm_crtc **crtcs, *crtc; in drm_client_pick_crtcs() local
515 crtcs = kcalloc(connector_count, sizeof(*crtcs), GFP_KERNEL); in drm_client_pick_crtcs()
516 if (!crtcs) in drm_client_pick_crtcs()
550 crtcs[n] = crtc; in drm_client_pick_crtcs()
551 memcpy(crtcs, best_crtcs, n * sizeof(*crtcs)); in drm_client_pick_crtcs()
553 crtcs, modes, n + 1, width, height); in drm_client_pick_crtcs()
556 memcpy(best_crtcs, crtcs, connector_count * sizeof(*crtcs)); in drm_client_pick_crtcs()
560 kfree(crtcs); in drm_client_pick_crtcs()
568 struct drm_crtc **crtcs, in drm_client_firmware_config() argument
658 if (crtcs[j] == new_crtc) { in drm_client_firmware_config()
[all …]
H A Ddrm_atomic.c76 kfree(state->crtcs); in drm_atomic_state_default_release()
101 state->crtcs = kcalloc(dev->mode_config.num_crtc, in drm_atomic_state_init()
102 sizeof(*state->crtcs), GFP_KERNEL); in drm_atomic_state_init()
103 if (!state->crtcs) in drm_atomic_state_init()
181 struct drm_crtc *crtc = state->crtcs[i].ptr; in drm_atomic_state_default_clear()
187 state->crtcs[i].state); in drm_atomic_state_default_clear()
189 state->crtcs[i].ptr = NULL; in drm_atomic_state_default_clear()
190 state->crtcs[i].state = NULL; in drm_atomic_state_default_clear()
191 state->crtcs[i].old_state = NULL; in drm_atomic_state_default_clear()
192 state->crtcs[i].new_state = NULL; in drm_atomic_state_default_clear()
[all …]
H A Ddrm_atomic_helper.c1461 old_state->crtcs[i].last_vblank_count = drm_crtc_vblank_count(crtc); in drm_atomic_helper_wait_for_vblanks()
1475 if (old_state->crtcs[i].last_vblank_count != in drm_atomic_helper_wait_for_vblanks()
1486 (old_state->crtcs[i].last_vblank_count != in drm_atomic_helper_wait_for_vblanks()
1492 old_state->crtcs[i].last_vblank_count != in drm_atomic_helper_wait_for_vblanks()
1527 struct drm_crtc_commit *commit = old_state->crtcs[i].commit; in drm_atomic_helper_wait_for_flip_done()
1530 crtc = old_state->crtcs[i].ptr; in drm_atomic_helper_wait_for_flip_done()
2109 state->crtcs[i].commit = commit; in drm_atomic_helper_setup_commit()
2813 state->crtcs[i].state = old_crtc_state; in drm_atomic_helper_swap_state()
3289 state->crtcs[i].old_state = crtc->state; in drm_atomic_helper_commit_duplicated_state()
H A Ddrm_atomic_uapi.c348 state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = fence_ptr; in set_out_fence_for_crtc()
356 fence_ptr = state->crtcs[drm_crtc_index(crtc)].out_fence_ptr; in get_out_fence_for_crtc()
357 state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = NULL; in get_out_fence_for_crtc()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_dce_virtual.c241 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_virtual_crtc_init()
417 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS); in dce_virtual_sw_fini()
473 if (adev->mode_info.crtcs[i]) in dce_virtual_hw_fini()
651 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_virtual_pageflip()
710 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) { in dce_virtual_set_crtc_vblank_interrupt_state()
715 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) { in dce_virtual_set_crtc_vblank_interrupt_state()
717 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state()
719 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state()
721 adev->mode_info.crtcs[crtc]->vblank_timer.function = in dce_virtual_set_crtc_vblank_interrupt_state()
723 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state()
[all …]
H A Damdgpu_dce_v6_0.c198 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
1076 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1080 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1081 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1082 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1083 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1084 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1085 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
2475 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2476 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
[all …]
H A Damdgpu_dce_v8_0.c191 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_page_flip()
1109 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v8_0_bandwidth_update()
1113 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v8_0_bandwidth_update()
1114 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1115 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v8_0_bandwidth_update()
2486 if (adev->mode_info.crtcs[i] && in dce_v8_0_crtc_disable()
2487 adev->mode_info.crtcs[i]->enabled && in dce_v8_0_crtc_disable()
2489 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v8_0_crtc_disable()
2616 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v8_0_crtc_init()
3113 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_pageflip_irq()
H A Damdgpu_dce_v10_0.c243 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip()
1172 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update()
1176 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update()
1177 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1178 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update()
2585 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable()
2586 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable()
2588 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2708 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
3144 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
H A Damdgpu_dce_v11_0.c261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_page_flip()
1198 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v11_0_bandwidth_update()
1202 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v11_0_bandwidth_update()
1203 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update()
1204 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v11_0_bandwidth_update()
2664 if (adev->mode_info.crtcs[i] && in dce_v11_0_crtc_disable()
2665 adev->mode_info.crtcs[i]->enabled && in dce_v11_0_crtc_disable()
2667 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v11_0_crtc_disable()
2816 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v11_0_crtc_init()
3270 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_pageflip_irq()
H A Damdgpu_atombios_crtc.c269 if (adev->mode_info.crtcs[i] && in amdgpu_atombios_crtc_program_ss()
270 adev->mode_info.crtcs[i]->enabled && in amdgpu_atombios_crtc_program_ss()
272 pll_id == adev->mode_info.crtcs[i]->pll_id) { in amdgpu_atombios_crtc_program_ss()
H A Damdgpu_display.c83 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; in amdgpu_display_flip_work_func()
870 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in amdgpu_display_get_crtc_scanoutpos()
H A Damdgpu_kms.c489 crtc = (struct drm_crtc *)minfo->crtcs[i]; in amdgpu_info_ioctl()
1146 if (adev->mode_info.crtcs[pipe]) { in amdgpu_get_vblank_counter_kms()
1159 &adev->mode_info.crtcs[pipe]->base.hwmode); in amdgpu_get_vblank_counter_kms()
H A Damdgpu_mode.h321 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_display.h446 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
447 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
463 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
464 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
465 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
472 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
473 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
474 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
/netbsd-src/sys/external/bsd/drm2/drm/
H A Ddrm_lease.c112 drm_lease_filter_crtcs(struct drm_file *file, uint32_t crtcs) in drm_lease_filter_crtcs() argument
114 return crtcs; in drm_lease_filter_crtcs()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_rs690.c258 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
261 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
604 if (rdev->mode_info.crtcs[0]->base.enabled) in rs690_bandwidth_update()
605 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update()
606 if (rdev->mode_info.crtcs[1]->base.enabled) in rs690_bandwidth_update()
607 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs690_bandwidth_update()
631 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rs690_bandwidth_update()
632 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rs690_bandwidth_update()
634 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); in rs690_bandwidth_update()
635 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); in rs690_bandwidth_update()
H A Dradeon_rv515.c1250 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update()
1251 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1252 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_avivo_update()
1253 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rv515_bandwidth_avivo_update()
1256 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update()
1257 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rv515_bandwidth_avivo_update()
1259 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update()
1260 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); in rv515_bandwidth_avivo_update()
1292 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update()
1293 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()
[all …]
H A Dradeon_rs600.c125 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
156 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
942 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
943 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
944 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
945 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
H A Dradeon_display.c291 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank()
347 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank()
372 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip()
419 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func()
692 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
1947 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
H A Dradeon_kms.c266 crtc = (struct drm_crtc *)minfo->crtcs[i]; in radeon_info_ioctl()
780 if (rdev->mode_info.crtcs[pipe]) { in radeon_get_vblank_counter_kms()
793 &rdev->mode_info.crtcs[pipe]->base.hwmode); in radeon_get_vblank_counter_kms()
H A Dradeon_atombios_crtc.c471 if (rdev->mode_info.crtcs[i] && in atombios_crtc_program_ss()
472 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_program_ss()
474 pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_program_ss()
2197 if (rdev->mode_info.crtcs[i] && in atombios_crtc_disable()
2198 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_disable()
2200 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
H A Dradeon_r100.c169 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip()
202 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending()
3249 if (rdev->mode_info.crtcs[0]->base.enabled) { in r100_bandwidth_update()
3251 rdev->mode_info.crtcs[0]->base.primary->fb; in r100_bandwidth_update()
3253 mode1 = &rdev->mode_info.crtcs[0]->base.mode; in r100_bandwidth_update()
3257 if (rdev->mode_info.crtcs[1]->base.enabled) { in r100_bandwidth_update()
3259 rdev->mode_info.crtcs[1]->base.primary->fb; in r100_bandwidth_update()
3261 mode2 = &rdev->mode_info.crtcs[1]->base.mode; in r100_bandwidth_update()
3667 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update()
3670 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
H A Dradeon_evergreen.c1426 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip()
1449 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending()
2339 if (rdev->mode_info.crtcs[i]->base.enabled) in evergreen_bandwidth_update()
2343 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in evergreen_bandwidth_update()
2344 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in evergreen_bandwidth_update()
2345 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2346 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update()
2347 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
2348 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in evergreen_bandwidth_update()
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
H A Dnouveau_dispnv50_disp.c2471 int crtcs, ret, i; in nv50_display_create() local
2513 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; in nv50_display_create()
2516 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; in nv50_display_create()
2518 crtcs = 0x3; in nv50_display_create()
2520 for (i = 0; i < fls(crtcs); i++) { in nv50_display_create()
2523 if (!(crtcs & (1 << i))) in nv50_display_create()
2550 head->msto->encoder.possible_crtcs = crtcs; in nv50_display_create()

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