1 /* $NetBSD: amdgpu_dce_v11_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce_v11_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $");
28
29 #include <drm/drm_fourcc.h>
30 #include <drm/drm_vblank.h>
31
32 #include "amdgpu.h"
33 #include "amdgpu_pm.h"
34 #include "amdgpu_i2c.h"
35 #include "vid.h"
36 #include "atom.h"
37 #include "amdgpu_atombios.h"
38 #include "atombios_crtc.h"
39 #include "atombios_encoders.h"
40 #include "amdgpu_pll.h"
41 #include "amdgpu_connectors.h"
42 #include "amdgpu_display.h"
43 #include "dce_v11_0.h"
44
45 #include "dce/dce_11_0_d.h"
46 #include "dce/dce_11_0_sh_mask.h"
47 #include "dce/dce_11_0_enum.h"
48 #include "oss/oss_3_0_d.h"
49 #include "oss/oss_3_0_sh_mask.h"
50 #include "gmc/gmc_8_1_d.h"
51 #include "gmc/gmc_8_1_sh_mask.h"
52
53 #include "ivsrcid/ivsrcid_vislands30.h"
54
55 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
56 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
57
58 static const u32 crtc_offsets[] =
59 {
60 CRTC0_REGISTER_OFFSET,
61 CRTC1_REGISTER_OFFSET,
62 CRTC2_REGISTER_OFFSET,
63 CRTC3_REGISTER_OFFSET,
64 CRTC4_REGISTER_OFFSET,
65 CRTC5_REGISTER_OFFSET,
66 CRTC6_REGISTER_OFFSET
67 };
68
69 static const u32 hpd_offsets[] =
70 {
71 HPD0_REGISTER_OFFSET,
72 HPD1_REGISTER_OFFSET,
73 HPD2_REGISTER_OFFSET,
74 HPD3_REGISTER_OFFSET,
75 HPD4_REGISTER_OFFSET,
76 HPD5_REGISTER_OFFSET
77 };
78
79 static const uint32_t dig_offsets[] = {
80 DIG0_REGISTER_OFFSET,
81 DIG1_REGISTER_OFFSET,
82 DIG2_REGISTER_OFFSET,
83 DIG3_REGISTER_OFFSET,
84 DIG4_REGISTER_OFFSET,
85 DIG5_REGISTER_OFFSET,
86 DIG6_REGISTER_OFFSET,
87 DIG7_REGISTER_OFFSET,
88 DIG8_REGISTER_OFFSET
89 };
90
91 static const struct {
92 uint32_t reg;
93 uint32_t vblank;
94 uint32_t vline;
95 uint32_t hpd;
96
97 } interrupt_status_offsets[] = { {
98 .reg = mmDISP_INTERRUPT_STATUS,
99 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
100 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
101 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
102 }, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
107 }, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
112 }, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
117 }, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
122 }, {
123 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
124 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
125 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
126 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
127 } };
128
129 static const u32 cz_golden_settings_a11[] =
130 {
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14300000,
133 };
134
135 static const u32 cz_mgcg_cgcg_init[] =
136 {
137 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
138 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
139 };
140
141 static const u32 stoney_golden_settings_a11[] =
142 {
143 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
144 mmFBC_MISC, 0x1f311fff, 0x14302000,
145 };
146
147 static const u32 polaris11_golden_settings_a11[] =
148 {
149 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
150 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
151 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
152 mmFBC_MISC, 0x9f313fff, 0x14302008,
153 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
154 };
155
156 static const u32 polaris10_golden_settings_a11[] =
157 {
158 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
159 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
160 mmFBC_MISC, 0x9f313fff, 0x14302008,
161 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
162 };
163
dce_v11_0_init_golden_registers(struct amdgpu_device * adev)164 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
165 {
166 switch (adev->asic_type) {
167 case CHIP_CARRIZO:
168 amdgpu_device_program_register_sequence(adev,
169 cz_mgcg_cgcg_init,
170 ARRAY_SIZE(cz_mgcg_cgcg_init));
171 amdgpu_device_program_register_sequence(adev,
172 cz_golden_settings_a11,
173 ARRAY_SIZE(cz_golden_settings_a11));
174 break;
175 case CHIP_STONEY:
176 amdgpu_device_program_register_sequence(adev,
177 stoney_golden_settings_a11,
178 ARRAY_SIZE(stoney_golden_settings_a11));
179 break;
180 case CHIP_POLARIS11:
181 case CHIP_POLARIS12:
182 amdgpu_device_program_register_sequence(adev,
183 polaris11_golden_settings_a11,
184 ARRAY_SIZE(polaris11_golden_settings_a11));
185 break;
186 case CHIP_POLARIS10:
187 case CHIP_VEGAM:
188 amdgpu_device_program_register_sequence(adev,
189 polaris10_golden_settings_a11,
190 ARRAY_SIZE(polaris10_golden_settings_a11));
191 break;
192 default:
193 break;
194 }
195 }
196
dce_v11_0_audio_endpt_rreg(struct amdgpu_device * adev,u32 block_offset,u32 reg)197 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
198 u32 block_offset, u32 reg)
199 {
200 unsigned long flags;
201 u32 r;
202
203 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
205 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
206 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
207
208 return r;
209 }
210
dce_v11_0_audio_endpt_wreg(struct amdgpu_device * adev,u32 block_offset,u32 reg,u32 v)211 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
212 u32 block_offset, u32 reg, u32 v)
213 {
214 unsigned long flags;
215
216 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
217 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
218 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
219 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
220 }
221
dce_v11_0_vblank_get_counter(struct amdgpu_device * adev,int crtc)222 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
223 {
224 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
225 return 0;
226 else
227 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
228 }
229
dce_v11_0_pageflip_interrupt_init(struct amdgpu_device * adev)230 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
231 {
232 unsigned i;
233
234 /* Enable pflip interrupts */
235 for (i = 0; i < adev->mode_info.num_crtc; i++)
236 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
237 }
238
dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device * adev)239 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
240 {
241 unsigned i;
242
243 /* Disable pflip interrupts */
244 for (i = 0; i < adev->mode_info.num_crtc; i++)
245 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
246 }
247
248 /**
249 * dce_v11_0_page_flip - pageflip callback.
250 *
251 * @adev: amdgpu_device pointer
252 * @crtc_id: crtc to cleanup pageflip on
253 * @crtc_base: new address of the crtc (GPU MC address)
254 *
255 * Triggers the actual pageflip by updating the primary
256 * surface base address.
257 */
dce_v11_0_page_flip(struct amdgpu_device * adev,int crtc_id,u64 crtc_base,bool async)258 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
259 int crtc_id, u64 crtc_base, bool async)
260 {
261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
262 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
263 u32 tmp;
264
265 /* flip immediate for async, default is vsync */
266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
267 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
268 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
270 /* update pitch */
271 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
272 fb->pitches[0] / fb->format->cpp[0]);
273 /* update the scanout addresses */
274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
275 upper_32_bits(crtc_base));
276 /* writing to the low address triggers the update */
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
278 lower_32_bits(crtc_base));
279 /* post the write */
280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
281 }
282
dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device * adev,int crtc,u32 * vbl,u32 * position)283 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
284 u32 *vbl, u32 *position)
285 {
286 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
287 return -EINVAL;
288
289 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
290 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
291
292 return 0;
293 }
294
295 /**
296 * dce_v11_0_hpd_sense - hpd sense callback.
297 *
298 * @adev: amdgpu_device pointer
299 * @hpd: hpd (hotplug detect) pin
300 *
301 * Checks if a digital monitor is connected (evergreen+).
302 * Returns true if connected, false if not connected.
303 */
dce_v11_0_hpd_sense(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)304 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
305 enum amdgpu_hpd_id hpd)
306 {
307 bool connected = false;
308
309 if (hpd >= adev->mode_info.num_hpd)
310 return connected;
311
312 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
313 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
314 connected = true;
315
316 return connected;
317 }
318
319 /**
320 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
321 *
322 * @adev: amdgpu_device pointer
323 * @hpd: hpd (hotplug detect) pin
324 *
325 * Set the polarity of the hpd pin (evergreen+).
326 */
dce_v11_0_hpd_set_polarity(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)327 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
328 enum amdgpu_hpd_id hpd)
329 {
330 u32 tmp;
331 bool connected = dce_v11_0_hpd_sense(adev, hpd);
332
333 if (hpd >= adev->mode_info.num_hpd)
334 return;
335
336 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
337 if (connected)
338 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
339 else
340 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
342 }
343
344 /**
345 * dce_v11_0_hpd_init - hpd setup callback.
346 *
347 * @adev: amdgpu_device pointer
348 *
349 * Setup the hpd pins used by the card (evergreen+).
350 * Enable the pin, set the polarity, and enable the hpd interrupts.
351 */
dce_v11_0_hpd_init(struct amdgpu_device * adev)352 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
353 {
354 struct drm_device *dev = adev->ddev;
355 struct drm_connector *connector;
356 struct drm_connector_list_iter iter;
357 u32 tmp;
358
359 drm_connector_list_iter_begin(dev, &iter);
360 drm_for_each_connector_iter(connector, &iter) {
361 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
362
363 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
364 continue;
365
366 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
367 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
368 /* don't try to enable hpd on eDP or LVDS avoid breaking the
369 * aux dp channel on imac and help (but not completely fix)
370 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
371 * also avoid interrupt storms during dpms.
372 */
373 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
374 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
375 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
376 continue;
377 }
378
379 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
380 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
381 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
382
383 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
384 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
385 DC_HPD_CONNECT_INT_DELAY,
386 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
387 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
388 DC_HPD_DISCONNECT_INT_DELAY,
389 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
390 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
391
392 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
393 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
394 }
395 drm_connector_list_iter_end(&iter);
396 }
397
398 /**
399 * dce_v11_0_hpd_fini - hpd tear down callback.
400 *
401 * @adev: amdgpu_device pointer
402 *
403 * Tear down the hpd pins used by the card (evergreen+).
404 * Disable the hpd interrupts.
405 */
dce_v11_0_hpd_fini(struct amdgpu_device * adev)406 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
407 {
408 struct drm_device *dev = adev->ddev;
409 struct drm_connector *connector;
410 struct drm_connector_list_iter iter;
411 u32 tmp;
412
413 drm_connector_list_iter_begin(dev, &iter);
414 drm_for_each_connector_iter(connector, &iter) {
415 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
416
417 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
418 continue;
419
420 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
421 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
422 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
423
424 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
425 }
426 drm_connector_list_iter_end(&iter);
427 }
428
dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device * adev)429 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
430 {
431 return mmDC_GPIO_HPD_A;
432 }
433
dce_v11_0_is_display_hung(struct amdgpu_device * adev)434 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
435 {
436 u32 crtc_hung = 0;
437 u32 crtc_status[6];
438 u32 i, j, tmp;
439
440 for (i = 0; i < adev->mode_info.num_crtc; i++) {
441 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
442 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
443 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
444 crtc_hung |= (1 << i);
445 }
446 }
447
448 for (j = 0; j < 10; j++) {
449 for (i = 0; i < adev->mode_info.num_crtc; i++) {
450 if (crtc_hung & (1 << i)) {
451 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
452 if (tmp != crtc_status[i])
453 crtc_hung &= ~(1 << i);
454 }
455 }
456 if (crtc_hung == 0)
457 return false;
458 udelay(100);
459 }
460
461 return true;
462 }
463
dce_v11_0_set_vga_render_state(struct amdgpu_device * adev,bool render)464 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
465 bool render)
466 {
467 u32 tmp;
468
469 /* Lockout access through VGA aperture*/
470 tmp = RREG32(mmVGA_HDP_CONTROL);
471 if (render)
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
473 else
474 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
475 WREG32(mmVGA_HDP_CONTROL, tmp);
476
477 /* disable VGA render */
478 tmp = RREG32(mmVGA_RENDER_CONTROL);
479 if (render)
480 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
481 else
482 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
483 WREG32(mmVGA_RENDER_CONTROL, tmp);
484 }
485
dce_v11_0_get_num_crtc(struct amdgpu_device * adev)486 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
487 {
488 int num_crtc = 0;
489
490 switch (adev->asic_type) {
491 case CHIP_CARRIZO:
492 num_crtc = 3;
493 break;
494 case CHIP_STONEY:
495 num_crtc = 2;
496 break;
497 case CHIP_POLARIS10:
498 case CHIP_VEGAM:
499 num_crtc = 6;
500 break;
501 case CHIP_POLARIS11:
502 case CHIP_POLARIS12:
503 num_crtc = 5;
504 break;
505 default:
506 num_crtc = 0;
507 }
508 return num_crtc;
509 }
510
dce_v11_0_disable_dce(struct amdgpu_device * adev)511 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
512 {
513 /*Disable VGA render and enabled crtc, if has DCE engine*/
514 if (amdgpu_atombios_has_dce_engine_info(adev)) {
515 u32 tmp;
516 int crtc_enabled, i;
517
518 dce_v11_0_set_vga_render_state(adev, false);
519
520 /*Disable crtc*/
521 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
522 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
523 CRTC_CONTROL, CRTC_MASTER_EN);
524 if (crtc_enabled) {
525 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
527 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
528 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
529 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
530 }
531 }
532 }
533 }
534
dce_v11_0_program_fmt(struct drm_encoder * encoder)535 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
536 {
537 struct drm_device *dev = encoder->dev;
538 struct amdgpu_device *adev = dev->dev_private;
539 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
541 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
542 int bpc = 0;
543 u32 tmp = 0;
544 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
545
546 if (connector) {
547 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
548 bpc = amdgpu_connector_get_monitor_bpc(connector);
549 dither = amdgpu_connector->dither;
550 }
551
552 /* LVDS/eDP FMT is set up by atom */
553 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
554 return;
555
556 /* not needed for analog */
557 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
558 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
559 return;
560
561 if (bpc == 0)
562 return;
563
564 switch (bpc) {
565 case 6:
566 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
567 /* XXX sort out optimal dither settings */
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
572 } else {
573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
575 }
576 break;
577 case 8:
578 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
579 /* XXX sort out optimal dither settings */
580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
585 } else {
586 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
587 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
588 }
589 break;
590 case 10:
591 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
592 /* XXX sort out optimal dither settings */
593 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
596 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
597 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
598 } else {
599 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
600 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
601 }
602 break;
603 default:
604 /* not needed */
605 break;
606 }
607
608 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
609 }
610
611
612 /* display watermark setup */
613 /**
614 * dce_v11_0_line_buffer_adjust - Set up the line buffer
615 *
616 * @adev: amdgpu_device pointer
617 * @amdgpu_crtc: the selected display controller
618 * @mode: the current display mode on the selected display
619 * controller
620 *
621 * Setup up the line buffer allocation for
622 * the selected display controller (CIK).
623 * Returns the line buffer size in pixels.
624 */
dce_v11_0_line_buffer_adjust(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,struct drm_display_mode * mode)625 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
626 struct amdgpu_crtc *amdgpu_crtc,
627 struct drm_display_mode *mode)
628 {
629 u32 tmp, buffer_alloc, i, mem_cfg;
630 u32 pipe_offset = amdgpu_crtc->crtc_id;
631 /*
632 * Line Buffer Setup
633 * There are 6 line buffers, one for each display controllers.
634 * There are 3 partitions per LB. Select the number of partitions
635 * to enable based on the display width. For display widths larger
636 * than 4096, you need use to use 2 display controllers and combine
637 * them using the stereo blender.
638 */
639 if (amdgpu_crtc->base.enabled && mode) {
640 if (mode->crtc_hdisplay < 1920) {
641 mem_cfg = 1;
642 buffer_alloc = 2;
643 } else if (mode->crtc_hdisplay < 2560) {
644 mem_cfg = 2;
645 buffer_alloc = 2;
646 } else if (mode->crtc_hdisplay < 4096) {
647 mem_cfg = 0;
648 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
649 } else {
650 DRM_DEBUG_KMS("Mode too big for LB!\n");
651 mem_cfg = 0;
652 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
653 }
654 } else {
655 mem_cfg = 1;
656 buffer_alloc = 0;
657 }
658
659 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
660 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
661 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
662
663 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
664 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
665 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
666
667 for (i = 0; i < adev->usec_timeout; i++) {
668 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
669 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
670 break;
671 udelay(1);
672 }
673
674 if (amdgpu_crtc->base.enabled && mode) {
675 switch (mem_cfg) {
676 case 0:
677 default:
678 return 4096 * 2;
679 case 1:
680 return 1920 * 2;
681 case 2:
682 return 2560 * 2;
683 }
684 }
685
686 /* controller not enabled, so no lb used */
687 return 0;
688 }
689
690 /**
691 * cik_get_number_of_dram_channels - get the number of dram channels
692 *
693 * @adev: amdgpu_device pointer
694 *
695 * Look up the number of video ram channels (CIK).
696 * Used for display watermark bandwidth calculations
697 * Returns the number of dram channels
698 */
cik_get_number_of_dram_channels(struct amdgpu_device * adev)699 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
700 {
701 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
702
703 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
704 case 0:
705 default:
706 return 1;
707 case 1:
708 return 2;
709 case 2:
710 return 4;
711 case 3:
712 return 8;
713 case 4:
714 return 3;
715 case 5:
716 return 6;
717 case 6:
718 return 10;
719 case 7:
720 return 12;
721 case 8:
722 return 16;
723 }
724 }
725
726 struct dce10_wm_params {
727 u32 dram_channels; /* number of dram channels */
728 u32 yclk; /* bandwidth per dram data pin in kHz */
729 u32 sclk; /* engine clock in kHz */
730 u32 disp_clk; /* display clock in kHz */
731 u32 src_width; /* viewport width */
732 u32 active_time; /* active display time in ns */
733 u32 blank_time; /* blank time in ns */
734 bool interlaced; /* mode is interlaced */
735 fixed20_12 vsc; /* vertical scale ratio */
736 u32 num_heads; /* number of active crtcs */
737 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
738 u32 lb_size; /* line buffer allocated to pipe */
739 u32 vtaps; /* vertical scaler taps */
740 };
741
742 /**
743 * dce_v11_0_dram_bandwidth - get the dram bandwidth
744 *
745 * @wm: watermark calculation data
746 *
747 * Calculate the raw dram bandwidth (CIK).
748 * Used for display watermark bandwidth calculations
749 * Returns the dram bandwidth in MBytes/s
750 */
dce_v11_0_dram_bandwidth(struct dce10_wm_params * wm)751 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
752 {
753 /* Calculate raw DRAM Bandwidth */
754 fixed20_12 dram_efficiency; /* 0.7 */
755 fixed20_12 yclk, dram_channels, bandwidth;
756 fixed20_12 a;
757
758 a.full = dfixed_const(1000);
759 yclk.full = dfixed_const(wm->yclk);
760 yclk.full = dfixed_div(yclk, a);
761 dram_channels.full = dfixed_const(wm->dram_channels * 4);
762 a.full = dfixed_const(10);
763 dram_efficiency.full = dfixed_const(7);
764 dram_efficiency.full = dfixed_div(dram_efficiency, a);
765 bandwidth.full = dfixed_mul(dram_channels, yclk);
766 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
767
768 return dfixed_trunc(bandwidth);
769 }
770
771 /**
772 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
773 *
774 * @wm: watermark calculation data
775 *
776 * Calculate the dram bandwidth used for display (CIK).
777 * Used for display watermark bandwidth calculations
778 * Returns the dram bandwidth for display in MBytes/s
779 */
dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params * wm)780 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
781 {
782 /* Calculate DRAM Bandwidth and the part allocated to display. */
783 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
784 fixed20_12 yclk, dram_channels, bandwidth;
785 fixed20_12 a;
786
787 a.full = dfixed_const(1000);
788 yclk.full = dfixed_const(wm->yclk);
789 yclk.full = dfixed_div(yclk, a);
790 dram_channels.full = dfixed_const(wm->dram_channels * 4);
791 a.full = dfixed_const(10);
792 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
793 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
794 bandwidth.full = dfixed_mul(dram_channels, yclk);
795 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
796
797 return dfixed_trunc(bandwidth);
798 }
799
800 /**
801 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
802 *
803 * @wm: watermark calculation data
804 *
805 * Calculate the data return bandwidth used for display (CIK).
806 * Used for display watermark bandwidth calculations
807 * Returns the data return bandwidth in MBytes/s
808 */
dce_v11_0_data_return_bandwidth(struct dce10_wm_params * wm)809 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
810 {
811 /* Calculate the display Data return Bandwidth */
812 fixed20_12 return_efficiency; /* 0.8 */
813 fixed20_12 sclk, bandwidth;
814 fixed20_12 a;
815
816 a.full = dfixed_const(1000);
817 sclk.full = dfixed_const(wm->sclk);
818 sclk.full = dfixed_div(sclk, a);
819 a.full = dfixed_const(10);
820 return_efficiency.full = dfixed_const(8);
821 return_efficiency.full = dfixed_div(return_efficiency, a);
822 a.full = dfixed_const(32);
823 bandwidth.full = dfixed_mul(a, sclk);
824 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
825
826 return dfixed_trunc(bandwidth);
827 }
828
829 /**
830 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
831 *
832 * @wm: watermark calculation data
833 *
834 * Calculate the dmif bandwidth used for display (CIK).
835 * Used for display watermark bandwidth calculations
836 * Returns the dmif bandwidth in MBytes/s
837 */
dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params * wm)838 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
839 {
840 /* Calculate the DMIF Request Bandwidth */
841 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
842 fixed20_12 disp_clk, bandwidth;
843 fixed20_12 a, b;
844
845 a.full = dfixed_const(1000);
846 disp_clk.full = dfixed_const(wm->disp_clk);
847 disp_clk.full = dfixed_div(disp_clk, a);
848 a.full = dfixed_const(32);
849 b.full = dfixed_mul(a, disp_clk);
850
851 a.full = dfixed_const(10);
852 disp_clk_request_efficiency.full = dfixed_const(8);
853 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
854
855 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
856
857 return dfixed_trunc(bandwidth);
858 }
859
860 /**
861 * dce_v11_0_available_bandwidth - get the min available bandwidth
862 *
863 * @wm: watermark calculation data
864 *
865 * Calculate the min available bandwidth used for display (CIK).
866 * Used for display watermark bandwidth calculations
867 * Returns the min available bandwidth in MBytes/s
868 */
dce_v11_0_available_bandwidth(struct dce10_wm_params * wm)869 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
870 {
871 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
872 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
873 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
874 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
875
876 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
877 }
878
879 /**
880 * dce_v11_0_average_bandwidth - get the average available bandwidth
881 *
882 * @wm: watermark calculation data
883 *
884 * Calculate the average available bandwidth used for display (CIK).
885 * Used for display watermark bandwidth calculations
886 * Returns the average available bandwidth in MBytes/s
887 */
dce_v11_0_average_bandwidth(struct dce10_wm_params * wm)888 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
889 {
890 /* Calculate the display mode Average Bandwidth
891 * DisplayMode should contain the source and destination dimensions,
892 * timing, etc.
893 */
894 fixed20_12 bpp;
895 fixed20_12 line_time;
896 fixed20_12 src_width;
897 fixed20_12 bandwidth;
898 fixed20_12 a;
899
900 a.full = dfixed_const(1000);
901 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
902 line_time.full = dfixed_div(line_time, a);
903 bpp.full = dfixed_const(wm->bytes_per_pixel);
904 src_width.full = dfixed_const(wm->src_width);
905 bandwidth.full = dfixed_mul(src_width, bpp);
906 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
907 bandwidth.full = dfixed_div(bandwidth, line_time);
908
909 return dfixed_trunc(bandwidth);
910 }
911
912 /**
913 * dce_v11_0_latency_watermark - get the latency watermark
914 *
915 * @wm: watermark calculation data
916 *
917 * Calculate the latency watermark (CIK).
918 * Used for display watermark bandwidth calculations
919 * Returns the latency watermark in ns
920 */
dce_v11_0_latency_watermark(struct dce10_wm_params * wm)921 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
922 {
923 /* First calculate the latency in ns */
924 u32 mc_latency = 2000; /* 2000 ns. */
925 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
926 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
927 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
928 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
929 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
930 (wm->num_heads * cursor_line_pair_return_time);
931 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
932 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
933 u32 tmp, dmif_size = 12288;
934 fixed20_12 a, b, c;
935
936 if (wm->num_heads == 0)
937 return 0;
938
939 a.full = dfixed_const(2);
940 b.full = dfixed_const(1);
941 if ((wm->vsc.full > a.full) ||
942 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
943 (wm->vtaps >= 5) ||
944 ((wm->vsc.full >= a.full) && wm->interlaced))
945 max_src_lines_per_dst_line = 4;
946 else
947 max_src_lines_per_dst_line = 2;
948
949 a.full = dfixed_const(available_bandwidth);
950 b.full = dfixed_const(wm->num_heads);
951 a.full = dfixed_div(a, b);
952 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
953 tmp = min(dfixed_trunc(a), tmp);
954
955 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
956
957 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
958 b.full = dfixed_const(1000);
959 c.full = dfixed_const(lb_fill_bw);
960 b.full = dfixed_div(c, b);
961 a.full = dfixed_div(a, b);
962 line_fill_time = dfixed_trunc(a);
963
964 if (line_fill_time < wm->active_time)
965 return latency;
966 else
967 return latency + (line_fill_time - wm->active_time);
968
969 }
970
971 /**
972 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
973 * average and available dram bandwidth
974 *
975 * @wm: watermark calculation data
976 *
977 * Check if the display average bandwidth fits in the display
978 * dram bandwidth (CIK).
979 * Used for display watermark bandwidth calculations
980 * Returns true if the display fits, false if not.
981 */
dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params * wm)982 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
983 {
984 if (dce_v11_0_average_bandwidth(wm) <=
985 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
986 return true;
987 else
988 return false;
989 }
990
991 /**
992 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
993 * average and available bandwidth
994 *
995 * @wm: watermark calculation data
996 *
997 * Check if the display average bandwidth fits in the display
998 * available bandwidth (CIK).
999 * Used for display watermark bandwidth calculations
1000 * Returns true if the display fits, false if not.
1001 */
dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params * wm)1002 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1003 {
1004 if (dce_v11_0_average_bandwidth(wm) <=
1005 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1006 return true;
1007 else
1008 return false;
1009 }
1010
1011 /**
1012 * dce_v11_0_check_latency_hiding - check latency hiding
1013 *
1014 * @wm: watermark calculation data
1015 *
1016 * Check latency hiding (CIK).
1017 * Used for display watermark bandwidth calculations
1018 * Returns true if the display fits, false if not.
1019 */
dce_v11_0_check_latency_hiding(struct dce10_wm_params * wm)1020 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1021 {
1022 u32 lb_partitions = wm->lb_size / wm->src_width;
1023 u32 line_time = wm->active_time + wm->blank_time;
1024 u32 latency_tolerant_lines;
1025 u32 latency_hiding;
1026 fixed20_12 a;
1027
1028 a.full = dfixed_const(1);
1029 if (wm->vsc.full > a.full)
1030 latency_tolerant_lines = 1;
1031 else {
1032 if (lb_partitions <= (wm->vtaps + 1))
1033 latency_tolerant_lines = 1;
1034 else
1035 latency_tolerant_lines = 2;
1036 }
1037
1038 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1039
1040 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1041 return true;
1042 else
1043 return false;
1044 }
1045
1046 /**
1047 * dce_v11_0_program_watermarks - program display watermarks
1048 *
1049 * @adev: amdgpu_device pointer
1050 * @amdgpu_crtc: the selected display controller
1051 * @lb_size: line buffer size
1052 * @num_heads: number of display controllers in use
1053 *
1054 * Calculate and program the display watermarks for the
1055 * selected display controller (CIK).
1056 */
dce_v11_0_program_watermarks(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,u32 lb_size,u32 num_heads)1057 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1058 struct amdgpu_crtc *amdgpu_crtc,
1059 u32 lb_size, u32 num_heads)
1060 {
1061 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1062 struct dce10_wm_params wm_low, wm_high;
1063 u32 active_time;
1064 u32 line_time = 0;
1065 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1066 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1067
1068 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1069 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1070 (u32)mode->clock);
1071 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1072 (u32)mode->clock);
1073 line_time = min(line_time, (u32)65535);
1074
1075 /* watermark for high clocks */
1076 if (adev->pm.dpm_enabled) {
1077 wm_high.yclk =
1078 amdgpu_dpm_get_mclk(adev, false) * 10;
1079 wm_high.sclk =
1080 amdgpu_dpm_get_sclk(adev, false) * 10;
1081 } else {
1082 wm_high.yclk = adev->pm.current_mclk * 10;
1083 wm_high.sclk = adev->pm.current_sclk * 10;
1084 }
1085
1086 wm_high.disp_clk = mode->clock;
1087 wm_high.src_width = mode->crtc_hdisplay;
1088 wm_high.active_time = active_time;
1089 wm_high.blank_time = line_time - wm_high.active_time;
1090 wm_high.interlaced = false;
1091 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1092 wm_high.interlaced = true;
1093 wm_high.vsc = amdgpu_crtc->vsc;
1094 wm_high.vtaps = 1;
1095 if (amdgpu_crtc->rmx_type != RMX_OFF)
1096 wm_high.vtaps = 2;
1097 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1098 wm_high.lb_size = lb_size;
1099 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1100 wm_high.num_heads = num_heads;
1101
1102 /* set for high clocks */
1103 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1104
1105 /* possibly force display priority to high */
1106 /* should really do this at mode validation time... */
1107 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1108 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1109 !dce_v11_0_check_latency_hiding(&wm_high) ||
1110 (adev->mode_info.disp_priority == 2)) {
1111 DRM_DEBUG_KMS("force priority to high\n");
1112 }
1113
1114 /* watermark for low clocks */
1115 if (adev->pm.dpm_enabled) {
1116 wm_low.yclk =
1117 amdgpu_dpm_get_mclk(adev, true) * 10;
1118 wm_low.sclk =
1119 amdgpu_dpm_get_sclk(adev, true) * 10;
1120 } else {
1121 wm_low.yclk = adev->pm.current_mclk * 10;
1122 wm_low.sclk = adev->pm.current_sclk * 10;
1123 }
1124
1125 wm_low.disp_clk = mode->clock;
1126 wm_low.src_width = mode->crtc_hdisplay;
1127 wm_low.active_time = active_time;
1128 wm_low.blank_time = line_time - wm_low.active_time;
1129 wm_low.interlaced = false;
1130 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1131 wm_low.interlaced = true;
1132 wm_low.vsc = amdgpu_crtc->vsc;
1133 wm_low.vtaps = 1;
1134 if (amdgpu_crtc->rmx_type != RMX_OFF)
1135 wm_low.vtaps = 2;
1136 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1137 wm_low.lb_size = lb_size;
1138 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1139 wm_low.num_heads = num_heads;
1140
1141 /* set for low clocks */
1142 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1143
1144 /* possibly force display priority to high */
1145 /* should really do this at mode validation time... */
1146 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1147 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1148 !dce_v11_0_check_latency_hiding(&wm_low) ||
1149 (adev->mode_info.disp_priority == 2)) {
1150 DRM_DEBUG_KMS("force priority to high\n");
1151 }
1152 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1153 }
1154
1155 /* select wm A */
1156 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1157 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1158 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1159 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1160 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1161 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1162 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1163 /* select wm B */
1164 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1165 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1166 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1167 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1168 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1169 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1170 /* restore original selection */
1171 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1172
1173 /* save values for DPM */
1174 amdgpu_crtc->line_time = line_time;
1175 amdgpu_crtc->wm_high = latency_watermark_a;
1176 amdgpu_crtc->wm_low = latency_watermark_b;
1177 /* Save number of lines the linebuffer leads before the scanout */
1178 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1179 }
1180
1181 /**
1182 * dce_v11_0_bandwidth_update - program display watermarks
1183 *
1184 * @adev: amdgpu_device pointer
1185 *
1186 * Calculate and program the display watermarks and line
1187 * buffer allocation (CIK).
1188 */
dce_v11_0_bandwidth_update(struct amdgpu_device * adev)1189 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1190 {
1191 struct drm_display_mode *mode = NULL;
1192 u32 num_heads = 0, lb_size;
1193 int i;
1194
1195 amdgpu_display_update_priority(adev);
1196
1197 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1198 if (adev->mode_info.crtcs[i]->base.enabled)
1199 num_heads++;
1200 }
1201 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1202 mode = &adev->mode_info.crtcs[i]->base.mode;
1203 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1204 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1205 lb_size, num_heads);
1206 }
1207 }
1208
dce_v11_0_audio_get_connected_pins(struct amdgpu_device * adev)1209 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1210 {
1211 int i;
1212 u32 offset, tmp;
1213
1214 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1215 offset = adev->mode_info.audio.pin[i].offset;
1216 tmp = RREG32_AUDIO_ENDPT(offset,
1217 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1218 if (((tmp &
1219 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1220 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1221 adev->mode_info.audio.pin[i].connected = false;
1222 else
1223 adev->mode_info.audio.pin[i].connected = true;
1224 }
1225 }
1226
dce_v11_0_audio_get_pin(struct amdgpu_device * adev)1227 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1228 {
1229 int i;
1230
1231 dce_v11_0_audio_get_connected_pins(adev);
1232
1233 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1234 if (adev->mode_info.audio.pin[i].connected)
1235 return &adev->mode_info.audio.pin[i];
1236 }
1237 DRM_ERROR("No connected audio pins found!\n");
1238 return NULL;
1239 }
1240
dce_v11_0_afmt_audio_select_pin(struct drm_encoder * encoder)1241 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1242 {
1243 struct amdgpu_device *adev = encoder->dev->dev_private;
1244 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1245 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1246 u32 tmp;
1247
1248 if (!dig || !dig->afmt || !dig->afmt->pin)
1249 return;
1250
1251 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1252 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1253 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1254 }
1255
dce_v11_0_audio_write_latency_fields(struct drm_encoder * encoder,struct drm_display_mode * mode)1256 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1257 struct drm_display_mode *mode)
1258 {
1259 struct drm_device *dev = encoder->dev;
1260 struct amdgpu_device *adev = dev->dev_private;
1261 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1262 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1263 struct drm_connector *connector;
1264 struct drm_connector_list_iter iter;
1265 struct amdgpu_connector *amdgpu_connector = NULL;
1266 u32 tmp;
1267 int interlace = 0;
1268
1269 if (!dig || !dig->afmt || !dig->afmt->pin)
1270 return;
1271
1272 drm_connector_list_iter_begin(dev, &iter);
1273 drm_for_each_connector_iter(connector, &iter) {
1274 if (connector->encoder == encoder) {
1275 amdgpu_connector = to_amdgpu_connector(connector);
1276 break;
1277 }
1278 }
1279 drm_connector_list_iter_end(&iter);
1280
1281 if (!amdgpu_connector) {
1282 DRM_ERROR("Couldn't find encoder's connector\n");
1283 return;
1284 }
1285
1286 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1287 interlace = 1;
1288 if (connector->latency_present[interlace]) {
1289 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1290 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1291 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1292 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1293 } else {
1294 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1295 VIDEO_LIPSYNC, 0);
1296 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1297 AUDIO_LIPSYNC, 0);
1298 }
1299 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1300 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1301 }
1302
dce_v11_0_audio_write_speaker_allocation(struct drm_encoder * encoder)1303 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1304 {
1305 struct drm_device *dev = encoder->dev;
1306 struct amdgpu_device *adev = dev->dev_private;
1307 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1308 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1309 struct drm_connector *connector;
1310 struct drm_connector_list_iter iter;
1311 struct amdgpu_connector *amdgpu_connector = NULL;
1312 u32 tmp;
1313 u8 *sadb = NULL;
1314 int sad_count;
1315
1316 if (!dig || !dig->afmt || !dig->afmt->pin)
1317 return;
1318
1319 drm_connector_list_iter_begin(dev, &iter);
1320 drm_for_each_connector_iter(connector, &iter) {
1321 if (connector->encoder == encoder) {
1322 amdgpu_connector = to_amdgpu_connector(connector);
1323 break;
1324 }
1325 }
1326 drm_connector_list_iter_end(&iter);
1327
1328 if (!amdgpu_connector) {
1329 DRM_ERROR("Couldn't find encoder's connector\n");
1330 return;
1331 }
1332
1333 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1334 if (sad_count < 0) {
1335 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1336 sad_count = 0;
1337 }
1338
1339 /* program the speaker allocation */
1340 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1341 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1342 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1343 DP_CONNECTION, 0);
1344 /* set HDMI mode */
1345 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1346 HDMI_CONNECTION, 1);
1347 if (sad_count)
1348 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1349 SPEAKER_ALLOCATION, sadb[0]);
1350 else
1351 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1352 SPEAKER_ALLOCATION, 5); /* stereo */
1353 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1354 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1355
1356 kfree(sadb);
1357 }
1358
dce_v11_0_audio_write_sad_regs(struct drm_encoder * encoder)1359 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1360 {
1361 struct drm_device *dev = encoder->dev;
1362 struct amdgpu_device *adev = dev->dev_private;
1363 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1364 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1365 struct drm_connector *connector;
1366 struct drm_connector_list_iter iter;
1367 struct amdgpu_connector *amdgpu_connector = NULL;
1368 struct cea_sad *sads;
1369 int i, sad_count;
1370
1371 static const u16 eld_reg_to_type[][2] = {
1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1379 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1380 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1381 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1382 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1383 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1384 };
1385
1386 if (!dig || !dig->afmt || !dig->afmt->pin)
1387 return;
1388
1389 drm_connector_list_iter_begin(dev, &iter);
1390 drm_for_each_connector_iter(connector, &iter) {
1391 if (connector->encoder == encoder) {
1392 amdgpu_connector = to_amdgpu_connector(connector);
1393 break;
1394 }
1395 }
1396 drm_connector_list_iter_end(&iter);
1397
1398 if (!amdgpu_connector) {
1399 DRM_ERROR("Couldn't find encoder's connector\n");
1400 return;
1401 }
1402
1403 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1404 if (sad_count < 0)
1405 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1406 if (sad_count <= 0)
1407 return;
1408 BUG_ON(!sads);
1409
1410 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1411 u32 tmp = 0;
1412 u8 stereo_freqs = 0;
1413 int max_channels = -1;
1414 int j;
1415
1416 for (j = 0; j < sad_count; j++) {
1417 struct cea_sad *sad = &sads[j];
1418
1419 if (sad->format == eld_reg_to_type[i][1]) {
1420 if (sad->channels > max_channels) {
1421 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1422 MAX_CHANNELS, sad->channels);
1423 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1424 DESCRIPTOR_BYTE_2, sad->byte2);
1425 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1426 SUPPORTED_FREQUENCIES, sad->freq);
1427 max_channels = sad->channels;
1428 }
1429
1430 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1431 stereo_freqs |= sad->freq;
1432 else
1433 break;
1434 }
1435 }
1436
1437 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1438 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1439 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1440 }
1441
1442 kfree(sads);
1443 }
1444
dce_v11_0_audio_enable(struct amdgpu_device * adev,struct amdgpu_audio_pin * pin,bool enable)1445 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1446 struct amdgpu_audio_pin *pin,
1447 bool enable)
1448 {
1449 if (!pin)
1450 return;
1451
1452 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1453 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1454 }
1455
1456 static const u32 pin_offsets[] =
1457 {
1458 AUD0_REGISTER_OFFSET,
1459 AUD1_REGISTER_OFFSET,
1460 AUD2_REGISTER_OFFSET,
1461 AUD3_REGISTER_OFFSET,
1462 AUD4_REGISTER_OFFSET,
1463 AUD5_REGISTER_OFFSET,
1464 AUD6_REGISTER_OFFSET,
1465 AUD7_REGISTER_OFFSET,
1466 };
1467
dce_v11_0_audio_init(struct amdgpu_device * adev)1468 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1469 {
1470 int i;
1471
1472 if (!amdgpu_audio)
1473 return 0;
1474
1475 adev->mode_info.audio.enabled = true;
1476
1477 switch (adev->asic_type) {
1478 case CHIP_CARRIZO:
1479 case CHIP_STONEY:
1480 adev->mode_info.audio.num_pins = 7;
1481 break;
1482 case CHIP_POLARIS10:
1483 case CHIP_VEGAM:
1484 adev->mode_info.audio.num_pins = 8;
1485 break;
1486 case CHIP_POLARIS11:
1487 case CHIP_POLARIS12:
1488 adev->mode_info.audio.num_pins = 6;
1489 break;
1490 default:
1491 return -EINVAL;
1492 }
1493
1494 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1495 adev->mode_info.audio.pin[i].channels = -1;
1496 adev->mode_info.audio.pin[i].rate = -1;
1497 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1498 adev->mode_info.audio.pin[i].status_bits = 0;
1499 adev->mode_info.audio.pin[i].category_code = 0;
1500 adev->mode_info.audio.pin[i].connected = false;
1501 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1502 adev->mode_info.audio.pin[i].id = i;
1503 /* disable audio. it will be set up later */
1504 /* XXX remove once we switch to ip funcs */
1505 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1506 }
1507
1508 return 0;
1509 }
1510
dce_v11_0_audio_fini(struct amdgpu_device * adev)1511 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1512 {
1513 int i;
1514
1515 if (!amdgpu_audio)
1516 return;
1517
1518 if (!adev->mode_info.audio.enabled)
1519 return;
1520
1521 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1522 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1523
1524 adev->mode_info.audio.enabled = false;
1525 }
1526
1527 /*
1528 * update the N and CTS parameters for a given pixel clock rate
1529 */
dce_v11_0_afmt_update_ACR(struct drm_encoder * encoder,uint32_t clock)1530 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1531 {
1532 struct drm_device *dev = encoder->dev;
1533 struct amdgpu_device *adev = dev->dev_private;
1534 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1535 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1536 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1537 u32 tmp;
1538
1539 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1540 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1541 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1542 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1543 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1544 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1545
1546 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1547 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1548 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1549 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1550 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1551 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1552
1553 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1554 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1555 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1556 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1557 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1558 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1559
1560 }
1561
1562 /*
1563 * build a HDMI Video Info Frame
1564 */
dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder * encoder,void * buffer,size_t size)1565 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1566 void *buffer, size_t size)
1567 {
1568 struct drm_device *dev = encoder->dev;
1569 struct amdgpu_device *adev = dev->dev_private;
1570 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1571 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1572 uint8_t *frame = buffer + 3;
1573 uint8_t *header = buffer;
1574
1575 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1576 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1577 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1578 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1579 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1580 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1581 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1582 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1583 }
1584
dce_v11_0_audio_set_dto(struct drm_encoder * encoder,u32 clock)1585 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1586 {
1587 struct drm_device *dev = encoder->dev;
1588 struct amdgpu_device *adev = dev->dev_private;
1589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1590 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1591 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1592 u32 dto_phase = 24 * 1000;
1593 u32 dto_modulo = clock;
1594 u32 tmp;
1595
1596 if (!dig || !dig->afmt)
1597 return;
1598
1599 /* XXX two dtos; generally use dto0 for hdmi */
1600 /* Express [24MHz / target pixel clock] as an exact rational
1601 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1602 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1603 */
1604 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1605 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1606 amdgpu_crtc->crtc_id);
1607 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1608 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1609 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1610 }
1611
1612 /*
1613 * update the info frames with the data from the current display mode
1614 */
dce_v11_0_afmt_setmode(struct drm_encoder * encoder,struct drm_display_mode * mode)1615 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1616 struct drm_display_mode *mode)
1617 {
1618 struct drm_device *dev = encoder->dev;
1619 struct amdgpu_device *adev = dev->dev_private;
1620 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1621 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1622 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1623 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1624 struct hdmi_avi_infoframe frame;
1625 ssize_t err;
1626 u32 tmp;
1627 int bpc = 8;
1628
1629 if (!dig || !dig->afmt)
1630 return;
1631
1632 /* Silent, r600_hdmi_enable will raise WARN for us */
1633 if (!dig->afmt->enabled)
1634 return;
1635
1636 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1637 if (encoder->crtc) {
1638 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1639 bpc = amdgpu_crtc->bpc;
1640 }
1641
1642 /* disable audio prior to setting up hw */
1643 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1644 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1645
1646 dce_v11_0_audio_set_dto(encoder, mode->clock);
1647
1648 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1649 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1650 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1651
1652 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1653
1654 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1655 switch (bpc) {
1656 case 0:
1657 case 6:
1658 case 8:
1659 case 16:
1660 default:
1661 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1662 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1663 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1664 connector->name, bpc);
1665 break;
1666 case 10:
1667 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1668 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1669 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1670 connector->name);
1671 break;
1672 case 12:
1673 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1674 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1675 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1676 connector->name);
1677 break;
1678 }
1679 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1680
1681 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1682 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1683 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1684 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1685 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1686
1687 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1688 /* enable audio info frames (frames won't be set until audio is enabled) */
1689 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1690 /* required for audio info values to be updated */
1691 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1692 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1693
1694 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1695 /* required for audio info values to be updated */
1696 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1697 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1698
1699 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1700 /* anything other than 0 */
1701 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1702 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1703
1704 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1705
1706 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1707 /* set the default audio delay */
1708 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1709 /* should be suffient for all audio modes and small enough for all hblanks */
1710 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1711 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1712
1713 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1714 /* allow 60958 channel status fields to be updated */
1715 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1716 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1717
1718 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1719 if (bpc > 8)
1720 /* clear SW CTS value */
1721 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1722 else
1723 /* select SW CTS value */
1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1725 /* allow hw to sent ACR packets when required */
1726 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1727 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1728
1729 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1730
1731 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1732 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1733 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1734
1735 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1736 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1737 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1738
1739 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1741 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1742 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1743 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1744 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1745 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1746 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1747
1748 dce_v11_0_audio_write_speaker_allocation(encoder);
1749
1750 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1751 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1752
1753 dce_v11_0_afmt_audio_select_pin(encoder);
1754 dce_v11_0_audio_write_sad_regs(encoder);
1755 dce_v11_0_audio_write_latency_fields(encoder, mode);
1756
1757 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1758 if (err < 0) {
1759 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1760 return;
1761 }
1762
1763 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1764 if (err < 0) {
1765 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1766 return;
1767 }
1768
1769 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1770
1771 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1772 /* enable AVI info frames */
1773 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1774 /* required for audio info values to be updated */
1775 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1776 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1777
1778 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1779 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1780 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1781
1782 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1783 /* send audio packets */
1784 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1785 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1786
1787 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1788 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1789 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1790 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1791
1792 /* enable audio after to setting up hw */
1793 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1794 }
1795
dce_v11_0_afmt_enable(struct drm_encoder * encoder,bool enable)1796 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1797 {
1798 struct drm_device *dev = encoder->dev;
1799 struct amdgpu_device *adev = dev->dev_private;
1800 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1801 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1802
1803 if (!dig || !dig->afmt)
1804 return;
1805
1806 /* Silent, r600_hdmi_enable will raise WARN for us */
1807 if (enable && dig->afmt->enabled)
1808 return;
1809 if (!enable && !dig->afmt->enabled)
1810 return;
1811
1812 if (!enable && dig->afmt->pin) {
1813 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1814 dig->afmt->pin = NULL;
1815 }
1816
1817 dig->afmt->enabled = enable;
1818
1819 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1820 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1821 }
1822
dce_v11_0_afmt_init(struct amdgpu_device * adev)1823 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1824 {
1825 int i;
1826
1827 for (i = 0; i < adev->mode_info.num_dig; i++)
1828 adev->mode_info.afmt[i] = NULL;
1829
1830 /* DCE11 has audio blocks tied to DIG encoders */
1831 for (i = 0; i < adev->mode_info.num_dig; i++) {
1832 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1833 if (adev->mode_info.afmt[i]) {
1834 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1835 adev->mode_info.afmt[i]->id = i;
1836 } else {
1837 int j;
1838 for (j = 0; j < i; j++) {
1839 kfree(adev->mode_info.afmt[j]);
1840 adev->mode_info.afmt[j] = NULL;
1841 }
1842 return -ENOMEM;
1843 }
1844 }
1845 return 0;
1846 }
1847
dce_v11_0_afmt_fini(struct amdgpu_device * adev)1848 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1849 {
1850 int i;
1851
1852 for (i = 0; i < adev->mode_info.num_dig; i++) {
1853 kfree(adev->mode_info.afmt[i]);
1854 adev->mode_info.afmt[i] = NULL;
1855 }
1856 }
1857
1858 static const u32 vga_control_regs[6] =
1859 {
1860 mmD1VGA_CONTROL,
1861 mmD2VGA_CONTROL,
1862 mmD3VGA_CONTROL,
1863 mmD4VGA_CONTROL,
1864 mmD5VGA_CONTROL,
1865 mmD6VGA_CONTROL,
1866 };
1867
dce_v11_0_vga_enable(struct drm_crtc * crtc,bool enable)1868 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1869 {
1870 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1871 struct drm_device *dev = crtc->dev;
1872 struct amdgpu_device *adev = dev->dev_private;
1873 u32 vga_control;
1874
1875 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1876 if (enable)
1877 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1878 else
1879 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1880 }
1881
dce_v11_0_grph_enable(struct drm_crtc * crtc,bool enable)1882 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1883 {
1884 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1885 struct drm_device *dev = crtc->dev;
1886 struct amdgpu_device *adev = dev->dev_private;
1887
1888 if (enable)
1889 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1890 else
1891 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1892 }
1893
dce_v11_0_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1894 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1895 struct drm_framebuffer *fb,
1896 int x, int y, int atomic)
1897 {
1898 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1899 struct drm_device *dev = crtc->dev;
1900 struct amdgpu_device *adev = dev->dev_private;
1901 struct drm_framebuffer *target_fb;
1902 struct drm_gem_object *obj;
1903 struct amdgpu_bo *abo;
1904 uint64_t fb_location, tiling_flags;
1905 uint32_t fb_format, fb_pitch_pixels;
1906 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1907 u32 pipe_config;
1908 u32 tmp, viewport_w, viewport_h;
1909 int r;
1910 bool bypass_lut = false;
1911 struct drm_format_name_buf format_name;
1912
1913 /* no fb bound */
1914 if (!atomic && !crtc->primary->fb) {
1915 DRM_DEBUG_KMS("No FB bound\n");
1916 return 0;
1917 }
1918
1919 if (atomic)
1920 target_fb = fb;
1921 else
1922 target_fb = crtc->primary->fb;
1923
1924 /* If atomic, assume fb object is pinned & idle & fenced and
1925 * just update base pointers
1926 */
1927 obj = target_fb->obj[0];
1928 abo = gem_to_amdgpu_bo(obj);
1929 r = amdgpu_bo_reserve(abo, false);
1930 if (unlikely(r != 0))
1931 return r;
1932
1933 if (!atomic) {
1934 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1935 if (unlikely(r != 0)) {
1936 amdgpu_bo_unreserve(abo);
1937 return -EINVAL;
1938 }
1939 }
1940 fb_location = amdgpu_bo_gpu_offset(abo);
1941
1942 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1943 amdgpu_bo_unreserve(abo);
1944
1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1946
1947 switch (target_fb->format->format) {
1948 case DRM_FORMAT_C8:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1951 break;
1952 case DRM_FORMAT_XRGB4444:
1953 case DRM_FORMAT_ARGB4444:
1954 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1955 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1956 #ifdef __BIG_ENDIAN
1957 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1958 ENDIAN_8IN16);
1959 #endif
1960 break;
1961 case DRM_FORMAT_XRGB1555:
1962 case DRM_FORMAT_ARGB1555:
1963 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1964 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1965 #ifdef __BIG_ENDIAN
1966 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1967 ENDIAN_8IN16);
1968 #endif
1969 break;
1970 case DRM_FORMAT_BGRX5551:
1971 case DRM_FORMAT_BGRA5551:
1972 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1973 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1974 #ifdef __BIG_ENDIAN
1975 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1976 ENDIAN_8IN16);
1977 #endif
1978 break;
1979 case DRM_FORMAT_RGB565:
1980 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1981 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1982 #ifdef __BIG_ENDIAN
1983 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1984 ENDIAN_8IN16);
1985 #endif
1986 break;
1987 case DRM_FORMAT_XRGB8888:
1988 case DRM_FORMAT_ARGB8888:
1989 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1990 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1991 #ifdef __BIG_ENDIAN
1992 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1993 ENDIAN_8IN32);
1994 #endif
1995 break;
1996 case DRM_FORMAT_XRGB2101010:
1997 case DRM_FORMAT_ARGB2101010:
1998 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1999 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2000 #ifdef __BIG_ENDIAN
2001 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2002 ENDIAN_8IN32);
2003 #endif
2004 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2005 bypass_lut = true;
2006 break;
2007 case DRM_FORMAT_BGRX1010102:
2008 case DRM_FORMAT_BGRA1010102:
2009 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2010 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2011 #ifdef __BIG_ENDIAN
2012 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2013 ENDIAN_8IN32);
2014 #endif
2015 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2016 bypass_lut = true;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2021 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2022 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2023 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2024 #ifdef __BIG_ENDIAN
2025 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2026 ENDIAN_8IN32);
2027 #endif
2028 break;
2029 default:
2030 DRM_ERROR("Unsupported screen format %s\n",
2031 drm_get_format_name(target_fb->format->format, &format_name));
2032 return -EINVAL;
2033 }
2034
2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2037
2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2043
2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2046 ARRAY_2D_TILED_THIN1);
2047 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2048 tile_split);
2049 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2050 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2051 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2052 mtaspect);
2053 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2054 ADDR_SURF_MICRO_TILING_DISPLAY);
2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2056 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2057 ARRAY_1D_TILED_THIN1);
2058 }
2059
2060 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2061 pipe_config);
2062
2063 dce_v11_0_vga_enable(crtc, false);
2064
2065 /* Make sure surface address is updated at vertical blank rather than
2066 * horizontal blank
2067 */
2068 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2069 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2070 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2071 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2072
2073 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2074 upper_32_bits(fb_location));
2075 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2076 upper_32_bits(fb_location));
2077 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2078 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2079 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2080 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2081 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2082 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2083
2084 /*
2085 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2086 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2087 * retain the full precision throughout the pipeline.
2088 */
2089 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2090 if (bypass_lut)
2091 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2092 else
2093 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2094 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2095
2096 if (bypass_lut)
2097 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2098
2099 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2100 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2101 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2102 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2103 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2104 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2105
2106 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2107 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2108
2109 dce_v11_0_grph_enable(crtc, true);
2110
2111 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2112 target_fb->height);
2113
2114 x &= ~3;
2115 y &= ~1;
2116 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2117 (x << 16) | y);
2118 viewport_w = crtc->mode.hdisplay;
2119 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2120 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2121 (viewport_w << 16) | viewport_h);
2122
2123 /* set pageflip to happen anywhere in vblank interval */
2124 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2125
2126 if (!atomic && fb && fb != crtc->primary->fb) {
2127 abo = gem_to_amdgpu_bo(fb->obj[0]);
2128 r = amdgpu_bo_reserve(abo, true);
2129 if (unlikely(r != 0))
2130 return r;
2131 amdgpu_bo_unpin(abo);
2132 amdgpu_bo_unreserve(abo);
2133 }
2134
2135 /* Bytes per pixel may have changed */
2136 dce_v11_0_bandwidth_update(adev);
2137
2138 return 0;
2139 }
2140
dce_v11_0_set_interleave(struct drm_crtc * crtc,struct drm_display_mode * mode)2141 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2142 struct drm_display_mode *mode)
2143 {
2144 struct drm_device *dev = crtc->dev;
2145 struct amdgpu_device *adev = dev->dev_private;
2146 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2147 u32 tmp;
2148
2149 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2150 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2151 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2152 else
2153 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2154 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2155 }
2156
dce_v11_0_crtc_load_lut(struct drm_crtc * crtc)2157 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2158 {
2159 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2160 struct drm_device *dev = crtc->dev;
2161 struct amdgpu_device *adev = dev->dev_private;
2162 u16 *r, *g, *b;
2163 int i;
2164 u32 tmp;
2165
2166 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2167
2168 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2169 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2170 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2171
2172 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2173 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2174 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2175
2176 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2177 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2178 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2179
2180 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2181
2182 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2183 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2184 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2185
2186 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2187 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2188 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2189
2190 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2191 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2192
2193 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2194 r = crtc->gamma_store;
2195 g = r + crtc->gamma_size;
2196 b = g + crtc->gamma_size;
2197 for (i = 0; i < 256; i++) {
2198 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2199 ((*r++ & 0xffc0) << 14) |
2200 ((*g++ & 0xffc0) << 4) |
2201 (*b++ >> 6));
2202 }
2203
2204 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2205 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2206 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2207 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2208 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2209
2210 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2211 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2212 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2213
2214 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2215 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2216 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2217
2218 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2219 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2220 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2221
2222 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2223 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2224 /* XXX this only needs to be programmed once per crtc at startup,
2225 * not sure where the best place for it is
2226 */
2227 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2228 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2229 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2230 }
2231
dce_v11_0_pick_dig_encoder(struct drm_encoder * encoder)2232 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2233 {
2234 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2235 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2236
2237 switch (amdgpu_encoder->encoder_id) {
2238 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2239 if (dig->linkb)
2240 return 1;
2241 else
2242 return 0;
2243 break;
2244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2245 if (dig->linkb)
2246 return 3;
2247 else
2248 return 2;
2249 break;
2250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2251 if (dig->linkb)
2252 return 5;
2253 else
2254 return 4;
2255 break;
2256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2257 return 6;
2258 break;
2259 default:
2260 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2261 return 0;
2262 }
2263 }
2264
2265 /**
2266 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2267 *
2268 * @crtc: drm crtc
2269 *
2270 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2271 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2272 * monitors a dedicated PPLL must be used. If a particular board has
2273 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2274 * as there is no need to program the PLL itself. If we are not able to
2275 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2276 * avoid messing up an existing monitor.
2277 *
2278 * Asic specific PLL information
2279 *
2280 * DCE 10.x
2281 * Tonga
2282 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2283 * CI
2284 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2285 *
2286 */
dce_v11_0_pick_pll(struct drm_crtc * crtc)2287 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2288 {
2289 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2290 struct drm_device *dev = crtc->dev;
2291 struct amdgpu_device *adev = dev->dev_private;
2292 u32 pll_in_use;
2293 int pll;
2294
2295 if ((adev->asic_type == CHIP_POLARIS10) ||
2296 (adev->asic_type == CHIP_POLARIS11) ||
2297 (adev->asic_type == CHIP_POLARIS12) ||
2298 (adev->asic_type == CHIP_VEGAM)) {
2299 struct amdgpu_encoder *amdgpu_encoder =
2300 to_amdgpu_encoder(amdgpu_crtc->encoder);
2301 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2302
2303 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2304 return ATOM_DP_DTO;
2305
2306 switch (amdgpu_encoder->encoder_id) {
2307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2308 if (dig->linkb)
2309 return ATOM_COMBOPHY_PLL1;
2310 else
2311 return ATOM_COMBOPHY_PLL0;
2312 break;
2313 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2314 if (dig->linkb)
2315 return ATOM_COMBOPHY_PLL3;
2316 else
2317 return ATOM_COMBOPHY_PLL2;
2318 break;
2319 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2320 if (dig->linkb)
2321 return ATOM_COMBOPHY_PLL5;
2322 else
2323 return ATOM_COMBOPHY_PLL4;
2324 break;
2325 default:
2326 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2327 return ATOM_PPLL_INVALID;
2328 }
2329 }
2330
2331 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2332 if (adev->clock.dp_extclk)
2333 /* skip PPLL programming if using ext clock */
2334 return ATOM_PPLL_INVALID;
2335 else {
2336 /* use the same PPLL for all DP monitors */
2337 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2338 if (pll != ATOM_PPLL_INVALID)
2339 return pll;
2340 }
2341 } else {
2342 /* use the same PPLL for all monitors with the same clock */
2343 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2344 if (pll != ATOM_PPLL_INVALID)
2345 return pll;
2346 }
2347
2348 /* XXX need to determine what plls are available on each DCE11 part */
2349 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2350 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2351 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2352 return ATOM_PPLL1;
2353 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2354 return ATOM_PPLL0;
2355 DRM_ERROR("unable to allocate a PPLL\n");
2356 return ATOM_PPLL_INVALID;
2357 } else {
2358 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2359 return ATOM_PPLL2;
2360 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2361 return ATOM_PPLL1;
2362 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2363 return ATOM_PPLL0;
2364 DRM_ERROR("unable to allocate a PPLL\n");
2365 return ATOM_PPLL_INVALID;
2366 }
2367 return ATOM_PPLL_INVALID;
2368 }
2369
dce_v11_0_lock_cursor(struct drm_crtc * crtc,bool lock)2370 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2371 {
2372 struct amdgpu_device *adev = crtc->dev->dev_private;
2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374 uint32_t cur_lock;
2375
2376 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2377 if (lock)
2378 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2379 else
2380 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2381 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2382 }
2383
dce_v11_0_hide_cursor(struct drm_crtc * crtc)2384 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2385 {
2386 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2387 struct amdgpu_device *adev = crtc->dev->dev_private;
2388 u32 tmp;
2389
2390 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2391 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2392 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2393 }
2394
dce_v11_0_show_cursor(struct drm_crtc * crtc)2395 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2396 {
2397 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2398 struct amdgpu_device *adev = crtc->dev->dev_private;
2399 u32 tmp;
2400
2401 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2402 upper_32_bits(amdgpu_crtc->cursor_addr));
2403 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2404 lower_32_bits(amdgpu_crtc->cursor_addr));
2405
2406 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2407 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2408 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2409 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2410 }
2411
dce_v11_0_cursor_move_locked(struct drm_crtc * crtc,int x,int y)2412 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2413 int x, int y)
2414 {
2415 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2416 struct amdgpu_device *adev = crtc->dev->dev_private;
2417 int xorigin = 0, yorigin = 0;
2418
2419 amdgpu_crtc->cursor_x = x;
2420 amdgpu_crtc->cursor_y = y;
2421
2422 /* avivo cursor are offset into the total surface */
2423 x += crtc->x;
2424 y += crtc->y;
2425 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2426
2427 if (x < 0) {
2428 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2429 x = 0;
2430 }
2431 if (y < 0) {
2432 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2433 y = 0;
2434 }
2435
2436 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2437 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2438 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2439 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2440
2441 return 0;
2442 }
2443
dce_v11_0_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)2444 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2445 int x, int y)
2446 {
2447 int ret;
2448
2449 dce_v11_0_lock_cursor(crtc, true);
2450 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2451 dce_v11_0_lock_cursor(crtc, false);
2452
2453 return ret;
2454 }
2455
dce_v11_0_crtc_cursor_set2(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height,int32_t hot_x,int32_t hot_y)2456 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2457 struct drm_file *file_priv,
2458 uint32_t handle,
2459 uint32_t width,
2460 uint32_t height,
2461 int32_t hot_x,
2462 int32_t hot_y)
2463 {
2464 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2465 struct drm_gem_object *obj;
2466 struct amdgpu_bo *aobj;
2467 int ret;
2468
2469 if (!handle) {
2470 /* turn off cursor */
2471 dce_v11_0_hide_cursor(crtc);
2472 obj = NULL;
2473 goto unpin;
2474 }
2475
2476 if ((width > amdgpu_crtc->max_cursor_width) ||
2477 (height > amdgpu_crtc->max_cursor_height)) {
2478 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2479 return -EINVAL;
2480 }
2481
2482 obj = drm_gem_object_lookup(file_priv, handle);
2483 if (!obj) {
2484 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2485 return -ENOENT;
2486 }
2487
2488 aobj = gem_to_amdgpu_bo(obj);
2489 ret = amdgpu_bo_reserve(aobj, false);
2490 if (ret != 0) {
2491 drm_gem_object_put_unlocked(obj);
2492 return ret;
2493 }
2494
2495 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2496 amdgpu_bo_unreserve(aobj);
2497 if (ret) {
2498 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2499 drm_gem_object_put_unlocked(obj);
2500 return ret;
2501 }
2502 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2503
2504 dce_v11_0_lock_cursor(crtc, true);
2505
2506 if (width != amdgpu_crtc->cursor_width ||
2507 height != amdgpu_crtc->cursor_height ||
2508 hot_x != amdgpu_crtc->cursor_hot_x ||
2509 hot_y != amdgpu_crtc->cursor_hot_y) {
2510 int x, y;
2511
2512 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2513 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2514
2515 dce_v11_0_cursor_move_locked(crtc, x, y);
2516
2517 amdgpu_crtc->cursor_width = width;
2518 amdgpu_crtc->cursor_height = height;
2519 amdgpu_crtc->cursor_hot_x = hot_x;
2520 amdgpu_crtc->cursor_hot_y = hot_y;
2521 }
2522
2523 dce_v11_0_show_cursor(crtc);
2524 dce_v11_0_lock_cursor(crtc, false);
2525
2526 unpin:
2527 if (amdgpu_crtc->cursor_bo) {
2528 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2529 ret = amdgpu_bo_reserve(aobj, true);
2530 if (likely(ret == 0)) {
2531 amdgpu_bo_unpin(aobj);
2532 amdgpu_bo_unreserve(aobj);
2533 }
2534 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2535 }
2536
2537 amdgpu_crtc->cursor_bo = obj;
2538 return 0;
2539 }
2540
dce_v11_0_cursor_reset(struct drm_crtc * crtc)2541 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2542 {
2543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2544
2545 if (amdgpu_crtc->cursor_bo) {
2546 dce_v11_0_lock_cursor(crtc, true);
2547
2548 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2549 amdgpu_crtc->cursor_y);
2550
2551 dce_v11_0_show_cursor(crtc);
2552
2553 dce_v11_0_lock_cursor(crtc, false);
2554 }
2555 }
2556
dce_v11_0_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)2557 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2558 u16 *blue, uint32_t size,
2559 struct drm_modeset_acquire_ctx *ctx)
2560 {
2561 dce_v11_0_crtc_load_lut(crtc);
2562
2563 return 0;
2564 }
2565
dce_v11_0_crtc_destroy(struct drm_crtc * crtc)2566 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2567 {
2568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2569
2570 drm_crtc_cleanup(crtc);
2571 kfree(amdgpu_crtc);
2572 }
2573
2574 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2575 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2576 .cursor_move = dce_v11_0_crtc_cursor_move,
2577 .gamma_set = dce_v11_0_crtc_gamma_set,
2578 .set_config = amdgpu_display_crtc_set_config,
2579 .destroy = dce_v11_0_crtc_destroy,
2580 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2581 };
2582
dce_v11_0_crtc_dpms(struct drm_crtc * crtc,int mode)2583 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2584 {
2585 struct drm_device *dev = crtc->dev;
2586 struct amdgpu_device *adev = dev->dev_private;
2587 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2588 unsigned type;
2589
2590 switch (mode) {
2591 case DRM_MODE_DPMS_ON:
2592 amdgpu_crtc->enabled = true;
2593 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2594 dce_v11_0_vga_enable(crtc, true);
2595 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2596 dce_v11_0_vga_enable(crtc, false);
2597 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2598 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2599 amdgpu_crtc->crtc_id);
2600 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2601 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2602 drm_crtc_vblank_on(crtc);
2603 dce_v11_0_crtc_load_lut(crtc);
2604 break;
2605 case DRM_MODE_DPMS_STANDBY:
2606 case DRM_MODE_DPMS_SUSPEND:
2607 case DRM_MODE_DPMS_OFF:
2608 drm_crtc_vblank_off(crtc);
2609 if (amdgpu_crtc->enabled) {
2610 dce_v11_0_vga_enable(crtc, true);
2611 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2612 dce_v11_0_vga_enable(crtc, false);
2613 }
2614 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2615 amdgpu_crtc->enabled = false;
2616 break;
2617 }
2618 /* adjust pm to dpms */
2619 amdgpu_pm_compute_clocks(adev);
2620 }
2621
dce_v11_0_crtc_prepare(struct drm_crtc * crtc)2622 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2623 {
2624 /* disable crtc pair power gating before programming */
2625 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2626 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2627 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2628 }
2629
dce_v11_0_crtc_commit(struct drm_crtc * crtc)2630 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2631 {
2632 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2633 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2634 }
2635
dce_v11_0_crtc_disable(struct drm_crtc * crtc)2636 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2637 {
2638 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2639 struct drm_device *dev = crtc->dev;
2640 struct amdgpu_device *adev = dev->dev_private;
2641 struct amdgpu_atom_ss ss;
2642 int i;
2643
2644 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2645 if (crtc->primary->fb) {
2646 int r;
2647 struct amdgpu_bo *abo;
2648
2649 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2650 r = amdgpu_bo_reserve(abo, true);
2651 if (unlikely(r))
2652 DRM_ERROR("failed to reserve abo before unpin\n");
2653 else {
2654 amdgpu_bo_unpin(abo);
2655 amdgpu_bo_unreserve(abo);
2656 }
2657 }
2658 /* disable the GRPH */
2659 dce_v11_0_grph_enable(crtc, false);
2660
2661 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2662
2663 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2664 if (adev->mode_info.crtcs[i] &&
2665 adev->mode_info.crtcs[i]->enabled &&
2666 i != amdgpu_crtc->crtc_id &&
2667 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2668 /* one other crtc is using this pll don't turn
2669 * off the pll
2670 */
2671 goto done;
2672 }
2673 }
2674
2675 switch (amdgpu_crtc->pll_id) {
2676 case ATOM_PPLL0:
2677 case ATOM_PPLL1:
2678 case ATOM_PPLL2:
2679 /* disable the ppll */
2680 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2681 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2682 break;
2683 case ATOM_COMBOPHY_PLL0:
2684 case ATOM_COMBOPHY_PLL1:
2685 case ATOM_COMBOPHY_PLL2:
2686 case ATOM_COMBOPHY_PLL3:
2687 case ATOM_COMBOPHY_PLL4:
2688 case ATOM_COMBOPHY_PLL5:
2689 /* disable the ppll */
2690 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2691 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2692 break;
2693 default:
2694 break;
2695 }
2696 done:
2697 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2698 amdgpu_crtc->adjusted_clock = 0;
2699 amdgpu_crtc->encoder = NULL;
2700 amdgpu_crtc->connector = NULL;
2701 }
2702
dce_v11_0_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)2703 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2704 struct drm_display_mode *mode,
2705 struct drm_display_mode *adjusted_mode,
2706 int x, int y, struct drm_framebuffer *old_fb)
2707 {
2708 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2709 struct drm_device *dev = crtc->dev;
2710 struct amdgpu_device *adev = dev->dev_private;
2711
2712 if (!amdgpu_crtc->adjusted_clock)
2713 return -EINVAL;
2714
2715 if ((adev->asic_type == CHIP_POLARIS10) ||
2716 (adev->asic_type == CHIP_POLARIS11) ||
2717 (adev->asic_type == CHIP_POLARIS12) ||
2718 (adev->asic_type == CHIP_VEGAM)) {
2719 struct amdgpu_encoder *amdgpu_encoder =
2720 to_amdgpu_encoder(amdgpu_crtc->encoder);
2721 int encoder_mode =
2722 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2723
2724 /* SetPixelClock calculates the plls and ss values now */
2725 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2726 amdgpu_crtc->pll_id,
2727 encoder_mode, amdgpu_encoder->encoder_id,
2728 adjusted_mode->clock, 0, 0, 0, 0,
2729 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2730 } else {
2731 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2732 }
2733 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2734 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2735 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2736 amdgpu_atombios_crtc_scaler_setup(crtc);
2737 dce_v11_0_cursor_reset(crtc);
2738 /* update the hw version fpr dpm */
2739 amdgpu_crtc->hw_mode = *adjusted_mode;
2740
2741 return 0;
2742 }
2743
dce_v11_0_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2744 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2745 const struct drm_display_mode *mode,
2746 struct drm_display_mode *adjusted_mode)
2747 {
2748 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2749 struct drm_device *dev = crtc->dev;
2750 struct drm_encoder *encoder;
2751
2752 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2753 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2754 if (encoder->crtc == crtc) {
2755 amdgpu_crtc->encoder = encoder;
2756 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2757 break;
2758 }
2759 }
2760 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2761 amdgpu_crtc->encoder = NULL;
2762 amdgpu_crtc->connector = NULL;
2763 return false;
2764 }
2765 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2766 return false;
2767 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2768 return false;
2769 /* pick pll */
2770 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2771 /* if we can't get a PPLL for a non-DP encoder, fail */
2772 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2773 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2774 return false;
2775
2776 return true;
2777 }
2778
dce_v11_0_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)2779 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2780 struct drm_framebuffer *old_fb)
2781 {
2782 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2783 }
2784
dce_v11_0_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)2785 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2786 struct drm_framebuffer *fb,
2787 int x, int y, enum mode_set_atomic state)
2788 {
2789 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2790 }
2791
2792 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2793 .dpms = dce_v11_0_crtc_dpms,
2794 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2795 .mode_set = dce_v11_0_crtc_mode_set,
2796 .mode_set_base = dce_v11_0_crtc_set_base,
2797 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2798 .prepare = dce_v11_0_crtc_prepare,
2799 .commit = dce_v11_0_crtc_commit,
2800 .disable = dce_v11_0_crtc_disable,
2801 };
2802
dce_v11_0_crtc_init(struct amdgpu_device * adev,int index)2803 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2804 {
2805 struct amdgpu_crtc *amdgpu_crtc;
2806
2807 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2808 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2809 if (amdgpu_crtc == NULL)
2810 return -ENOMEM;
2811
2812 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2813
2814 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2815 amdgpu_crtc->crtc_id = index;
2816 adev->mode_info.crtcs[index] = amdgpu_crtc;
2817
2818 amdgpu_crtc->max_cursor_width = 128;
2819 amdgpu_crtc->max_cursor_height = 128;
2820 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2821 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2822
2823 switch (amdgpu_crtc->crtc_id) {
2824 case 0:
2825 default:
2826 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2827 break;
2828 case 1:
2829 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2830 break;
2831 case 2:
2832 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2833 break;
2834 case 3:
2835 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2836 break;
2837 case 4:
2838 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2839 break;
2840 case 5:
2841 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2842 break;
2843 }
2844
2845 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2846 amdgpu_crtc->adjusted_clock = 0;
2847 amdgpu_crtc->encoder = NULL;
2848 amdgpu_crtc->connector = NULL;
2849 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2850
2851 return 0;
2852 }
2853
dce_v11_0_early_init(void * handle)2854 static int dce_v11_0_early_init(void *handle)
2855 {
2856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2857
2858 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2859 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2860
2861 dce_v11_0_set_display_funcs(adev);
2862
2863 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2864
2865 switch (adev->asic_type) {
2866 case CHIP_CARRIZO:
2867 adev->mode_info.num_hpd = 6;
2868 adev->mode_info.num_dig = 9;
2869 break;
2870 case CHIP_STONEY:
2871 adev->mode_info.num_hpd = 6;
2872 adev->mode_info.num_dig = 9;
2873 break;
2874 case CHIP_POLARIS10:
2875 case CHIP_VEGAM:
2876 adev->mode_info.num_hpd = 6;
2877 adev->mode_info.num_dig = 6;
2878 break;
2879 case CHIP_POLARIS11:
2880 case CHIP_POLARIS12:
2881 adev->mode_info.num_hpd = 5;
2882 adev->mode_info.num_dig = 5;
2883 break;
2884 default:
2885 /* FIXME: not supported yet */
2886 return -EINVAL;
2887 }
2888
2889 dce_v11_0_set_irq_funcs(adev);
2890
2891 return 0;
2892 }
2893
dce_v11_0_sw_init(void * handle)2894 static int dce_v11_0_sw_init(void *handle)
2895 {
2896 int r, i;
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
2899 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2900 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2901 if (r)
2902 return r;
2903 }
2904
2905 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2906 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2907 if (r)
2908 return r;
2909 }
2910
2911 /* HPD hotplug */
2912 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2913 if (r)
2914 return r;
2915
2916 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2917
2918 adev->ddev->mode_config.async_page_flip = true;
2919
2920 adev->ddev->mode_config.max_width = 16384;
2921 adev->ddev->mode_config.max_height = 16384;
2922
2923 adev->ddev->mode_config.preferred_depth = 24;
2924 adev->ddev->mode_config.prefer_shadow = 1;
2925
2926 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2927
2928 r = amdgpu_display_modeset_create_props(adev);
2929 if (r)
2930 return r;
2931
2932 adev->ddev->mode_config.max_width = 16384;
2933 adev->ddev->mode_config.max_height = 16384;
2934
2935
2936 /* allocate crtcs */
2937 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2938 r = dce_v11_0_crtc_init(adev, i);
2939 if (r)
2940 return r;
2941 }
2942
2943 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2944 amdgpu_display_print_display_setup(adev->ddev);
2945 else
2946 return -EINVAL;
2947
2948 /* setup afmt */
2949 r = dce_v11_0_afmt_init(adev);
2950 if (r)
2951 return r;
2952
2953 r = dce_v11_0_audio_init(adev);
2954 if (r)
2955 return r;
2956
2957 drm_kms_helper_poll_init(adev->ddev);
2958
2959 adev->mode_info.mode_config_initialized = true;
2960 return 0;
2961 }
2962
dce_v11_0_sw_fini(void * handle)2963 static int dce_v11_0_sw_fini(void *handle)
2964 {
2965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2966
2967 kfree(adev->mode_info.bios_hardcoded_edid);
2968
2969 drm_kms_helper_poll_fini(adev->ddev);
2970
2971 dce_v11_0_audio_fini(adev);
2972
2973 dce_v11_0_afmt_fini(adev);
2974
2975 drm_mode_config_cleanup(adev->ddev);
2976 adev->mode_info.mode_config_initialized = false;
2977
2978 return 0;
2979 }
2980
dce_v11_0_hw_init(void * handle)2981 static int dce_v11_0_hw_init(void *handle)
2982 {
2983 int i;
2984 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2985
2986 dce_v11_0_init_golden_registers(adev);
2987
2988 /* disable vga render */
2989 dce_v11_0_set_vga_render_state(adev, false);
2990 /* init dig PHYs, disp eng pll */
2991 amdgpu_atombios_crtc_powergate_init(adev);
2992 amdgpu_atombios_encoder_init_dig(adev);
2993 if ((adev->asic_type == CHIP_POLARIS10) ||
2994 (adev->asic_type == CHIP_POLARIS11) ||
2995 (adev->asic_type == CHIP_POLARIS12) ||
2996 (adev->asic_type == CHIP_VEGAM)) {
2997 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2998 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2999 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3000 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3001 } else {
3002 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3003 }
3004
3005 /* initialize hpd */
3006 dce_v11_0_hpd_init(adev);
3007
3008 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3009 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3010 }
3011
3012 dce_v11_0_pageflip_interrupt_init(adev);
3013
3014 return 0;
3015 }
3016
dce_v11_0_hw_fini(void * handle)3017 static int dce_v11_0_hw_fini(void *handle)
3018 {
3019 int i;
3020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021
3022 dce_v11_0_hpd_fini(adev);
3023
3024 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3025 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3026 }
3027
3028 dce_v11_0_pageflip_interrupt_fini(adev);
3029
3030 return 0;
3031 }
3032
dce_v11_0_suspend(void * handle)3033 static int dce_v11_0_suspend(void *handle)
3034 {
3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3036
3037 adev->mode_info.bl_level =
3038 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3039
3040 return dce_v11_0_hw_fini(handle);
3041 }
3042
dce_v11_0_resume(void * handle)3043 static int dce_v11_0_resume(void *handle)
3044 {
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046 int ret;
3047
3048 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3049 adev->mode_info.bl_level);
3050
3051 ret = dce_v11_0_hw_init(handle);
3052
3053 /* turn on the BL */
3054 if (adev->mode_info.bl_encoder) {
3055 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3056 adev->mode_info.bl_encoder);
3057 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3058 bl_level);
3059 }
3060
3061 return ret;
3062 }
3063
dce_v11_0_is_idle(void * handle)3064 static bool dce_v11_0_is_idle(void *handle)
3065 {
3066 return true;
3067 }
3068
dce_v11_0_wait_for_idle(void * handle)3069 static int dce_v11_0_wait_for_idle(void *handle)
3070 {
3071 return 0;
3072 }
3073
dce_v11_0_soft_reset(void * handle)3074 static int dce_v11_0_soft_reset(void *handle)
3075 {
3076 u32 srbm_soft_reset = 0, tmp;
3077 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078
3079 if (dce_v11_0_is_display_hung(adev))
3080 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3081
3082 if (srbm_soft_reset) {
3083 tmp = RREG32(mmSRBM_SOFT_RESET);
3084 tmp |= srbm_soft_reset;
3085 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3086 WREG32(mmSRBM_SOFT_RESET, tmp);
3087 tmp = RREG32(mmSRBM_SOFT_RESET);
3088
3089 udelay(50);
3090
3091 tmp &= ~srbm_soft_reset;
3092 WREG32(mmSRBM_SOFT_RESET, tmp);
3093 tmp = RREG32(mmSRBM_SOFT_RESET);
3094
3095 /* Wait a little for things to settle down */
3096 udelay(50);
3097 }
3098 return 0;
3099 }
3100
dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)3101 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3102 int crtc,
3103 enum amdgpu_interrupt_state state)
3104 {
3105 u32 lb_interrupt_mask;
3106
3107 if (crtc >= adev->mode_info.num_crtc) {
3108 DRM_DEBUG("invalid crtc %d\n", crtc);
3109 return;
3110 }
3111
3112 switch (state) {
3113 case AMDGPU_IRQ_STATE_DISABLE:
3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3115 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3116 VBLANK_INTERRUPT_MASK, 0);
3117 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3118 break;
3119 case AMDGPU_IRQ_STATE_ENABLE:
3120 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3121 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3122 VBLANK_INTERRUPT_MASK, 1);
3123 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3124 break;
3125 default:
3126 break;
3127 }
3128 }
3129
dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)3130 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3131 int crtc,
3132 enum amdgpu_interrupt_state state)
3133 {
3134 u32 lb_interrupt_mask;
3135
3136 if (crtc >= adev->mode_info.num_crtc) {
3137 DRM_DEBUG("invalid crtc %d\n", crtc);
3138 return;
3139 }
3140
3141 switch (state) {
3142 case AMDGPU_IRQ_STATE_DISABLE:
3143 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3144 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3145 VLINE_INTERRUPT_MASK, 0);
3146 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3147 break;
3148 case AMDGPU_IRQ_STATE_ENABLE:
3149 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3150 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3151 VLINE_INTERRUPT_MASK, 1);
3152 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3153 break;
3154 default:
3155 break;
3156 }
3157 }
3158
dce_v11_0_set_hpd_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned hpd,enum amdgpu_interrupt_state state)3159 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3160 struct amdgpu_irq_src *source,
3161 unsigned hpd,
3162 enum amdgpu_interrupt_state state)
3163 {
3164 u32 tmp;
3165
3166 if (hpd >= adev->mode_info.num_hpd) {
3167 DRM_DEBUG("invalid hdp %d\n", hpd);
3168 return 0;
3169 }
3170
3171 switch (state) {
3172 case AMDGPU_IRQ_STATE_DISABLE:
3173 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3174 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3175 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3176 break;
3177 case AMDGPU_IRQ_STATE_ENABLE:
3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3179 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3181 break;
3182 default:
3183 break;
3184 }
3185
3186 return 0;
3187 }
3188
dce_v11_0_set_crtc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)3189 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3190 struct amdgpu_irq_src *source,
3191 unsigned type,
3192 enum amdgpu_interrupt_state state)
3193 {
3194 switch (type) {
3195 case AMDGPU_CRTC_IRQ_VBLANK1:
3196 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3197 break;
3198 case AMDGPU_CRTC_IRQ_VBLANK2:
3199 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3200 break;
3201 case AMDGPU_CRTC_IRQ_VBLANK3:
3202 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3203 break;
3204 case AMDGPU_CRTC_IRQ_VBLANK4:
3205 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3206 break;
3207 case AMDGPU_CRTC_IRQ_VBLANK5:
3208 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3209 break;
3210 case AMDGPU_CRTC_IRQ_VBLANK6:
3211 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3212 break;
3213 case AMDGPU_CRTC_IRQ_VLINE1:
3214 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3215 break;
3216 case AMDGPU_CRTC_IRQ_VLINE2:
3217 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3218 break;
3219 case AMDGPU_CRTC_IRQ_VLINE3:
3220 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3221 break;
3222 case AMDGPU_CRTC_IRQ_VLINE4:
3223 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3224 break;
3225 case AMDGPU_CRTC_IRQ_VLINE5:
3226 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3227 break;
3228 case AMDGPU_CRTC_IRQ_VLINE6:
3229 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3230 break;
3231 default:
3232 break;
3233 }
3234 return 0;
3235 }
3236
dce_v11_0_set_pageflip_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3237 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3238 struct amdgpu_irq_src *src,
3239 unsigned type,
3240 enum amdgpu_interrupt_state state)
3241 {
3242 u32 reg;
3243
3244 if (type >= adev->mode_info.num_crtc) {
3245 DRM_ERROR("invalid pageflip crtc %d\n", type);
3246 return -EINVAL;
3247 }
3248
3249 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3250 if (state == AMDGPU_IRQ_STATE_DISABLE)
3251 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3252 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3253 else
3254 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3255 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3256
3257 return 0;
3258 }
3259
dce_v11_0_pageflip_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3260 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *source,
3262 struct amdgpu_iv_entry *entry)
3263 {
3264 unsigned long flags;
3265 unsigned crtc_id;
3266 struct amdgpu_crtc *amdgpu_crtc;
3267 struct amdgpu_flip_work *works;
3268
3269 crtc_id = (entry->src_id - 8) >> 1;
3270 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3271
3272 if (crtc_id >= adev->mode_info.num_crtc) {
3273 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3274 return -EINVAL;
3275 }
3276
3277 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3278 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3279 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3280 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3281
3282 /* IRQ could occur when in initial stage */
3283 if(amdgpu_crtc == NULL)
3284 return 0;
3285
3286 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3287 works = amdgpu_crtc->pflip_works;
3288 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3289 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3290 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3291 amdgpu_crtc->pflip_status,
3292 AMDGPU_FLIP_SUBMITTED);
3293 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3294 return 0;
3295 }
3296
3297 /* page flip completed. clean up */
3298 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3299 amdgpu_crtc->pflip_works = NULL;
3300
3301 /* wakeup usersapce */
3302 if(works->event)
3303 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3304
3305 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3306
3307 drm_crtc_vblank_put(&amdgpu_crtc->base);
3308 schedule_work(&works->unpin_work);
3309
3310 return 0;
3311 }
3312
dce_v11_0_hpd_int_ack(struct amdgpu_device * adev,int hpd)3313 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3314 int hpd)
3315 {
3316 u32 tmp;
3317
3318 if (hpd >= adev->mode_info.num_hpd) {
3319 DRM_DEBUG("invalid hdp %d\n", hpd);
3320 return;
3321 }
3322
3323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3324 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3326 }
3327
dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device * adev,int crtc)3328 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3329 int crtc)
3330 {
3331 u32 tmp;
3332
3333 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3334 DRM_DEBUG("invalid crtc %d\n", crtc);
3335 return;
3336 }
3337
3338 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3339 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3340 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3341 }
3342
dce_v11_0_crtc_vline_int_ack(struct amdgpu_device * adev,int crtc)3343 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3344 int crtc)
3345 {
3346 u32 tmp;
3347
3348 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3349 DRM_DEBUG("invalid crtc %d\n", crtc);
3350 return;
3351 }
3352
3353 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3354 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3355 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3356 }
3357
dce_v11_0_crtc_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3358 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361 {
3362 unsigned crtc = entry->src_id - 1;
3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3364 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3365 crtc);
3366
3367 switch (entry->src_data[0]) {
3368 case 0: /* vblank */
3369 if (disp_int & interrupt_status_offsets[crtc].vblank)
3370 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3371 else
3372 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3373
3374 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3375 drm_handle_vblank(adev->ddev, crtc);
3376 }
3377 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3378
3379 break;
3380 case 1: /* vline */
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3382 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3383 else
3384 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3385
3386 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3387
3388 break;
3389 default:
3390 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3391 break;
3392 }
3393
3394 return 0;
3395 }
3396
dce_v11_0_hpd_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3397 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3398 struct amdgpu_irq_src *source,
3399 struct amdgpu_iv_entry *entry)
3400 {
3401 uint32_t disp_int, mask;
3402 unsigned hpd;
3403
3404 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3405 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3406 return 0;
3407 }
3408
3409 hpd = entry->src_data[0];
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3411 mask = interrupt_status_offsets[hpd].hpd;
3412
3413 if (disp_int & mask) {
3414 dce_v11_0_hpd_int_ack(adev, hpd);
3415 schedule_work(&adev->hotplug_work);
3416 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3417 }
3418
3419 return 0;
3420 }
3421
dce_v11_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)3422 static int dce_v11_0_set_clockgating_state(void *handle,
3423 enum amd_clockgating_state state)
3424 {
3425 return 0;
3426 }
3427
dce_v11_0_set_powergating_state(void * handle,enum amd_powergating_state state)3428 static int dce_v11_0_set_powergating_state(void *handle,
3429 enum amd_powergating_state state)
3430 {
3431 return 0;
3432 }
3433
3434 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3435 .name = "dce_v11_0",
3436 .early_init = dce_v11_0_early_init,
3437 .late_init = NULL,
3438 .sw_init = dce_v11_0_sw_init,
3439 .sw_fini = dce_v11_0_sw_fini,
3440 .hw_init = dce_v11_0_hw_init,
3441 .hw_fini = dce_v11_0_hw_fini,
3442 .suspend = dce_v11_0_suspend,
3443 .resume = dce_v11_0_resume,
3444 .is_idle = dce_v11_0_is_idle,
3445 .wait_for_idle = dce_v11_0_wait_for_idle,
3446 .soft_reset = dce_v11_0_soft_reset,
3447 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3448 .set_powergating_state = dce_v11_0_set_powergating_state,
3449 };
3450
3451 static void
dce_v11_0_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3452 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3453 struct drm_display_mode *mode,
3454 struct drm_display_mode *adjusted_mode)
3455 {
3456 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3457
3458 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3459
3460 /* need to call this here rather than in prepare() since we need some crtc info */
3461 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3462
3463 /* set scaler clears this on some chips */
3464 dce_v11_0_set_interleave(encoder->crtc, mode);
3465
3466 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3467 dce_v11_0_afmt_enable(encoder, true);
3468 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3469 }
3470 }
3471
dce_v11_0_encoder_prepare(struct drm_encoder * encoder)3472 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3473 {
3474 struct amdgpu_device *adev = encoder->dev->dev_private;
3475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3476 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3477
3478 if ((amdgpu_encoder->active_device &
3479 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3480 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3481 ENCODER_OBJECT_ID_NONE)) {
3482 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3483 if (dig) {
3484 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3485 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3486 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3487 }
3488 }
3489
3490 amdgpu_atombios_scratch_regs_lock(adev, true);
3491
3492 if (connector) {
3493 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3494
3495 /* select the clock/data port if it uses a router */
3496 if (amdgpu_connector->router.cd_valid)
3497 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3498
3499 /* turn eDP panel on for mode set */
3500 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3501 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3502 ATOM_TRANSMITTER_ACTION_POWER_ON);
3503 }
3504
3505 /* this is needed for the pll/ss setup to work correctly in some cases */
3506 amdgpu_atombios_encoder_set_crtc_source(encoder);
3507 /* set up the FMT blocks */
3508 dce_v11_0_program_fmt(encoder);
3509 }
3510
dce_v11_0_encoder_commit(struct drm_encoder * encoder)3511 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3512 {
3513 struct drm_device *dev = encoder->dev;
3514 struct amdgpu_device *adev = dev->dev_private;
3515
3516 /* need to call this here as we need the crtc set up */
3517 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3518 amdgpu_atombios_scratch_regs_lock(adev, false);
3519 }
3520
dce_v11_0_encoder_disable(struct drm_encoder * encoder)3521 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3522 {
3523 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3524 struct amdgpu_encoder_atom_dig *dig;
3525
3526 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3527
3528 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3529 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3530 dce_v11_0_afmt_enable(encoder, false);
3531 dig = amdgpu_encoder->enc_priv;
3532 dig->dig_encoder = -1;
3533 }
3534 amdgpu_encoder->active_device = 0;
3535 }
3536
3537 /* these are handled by the primary encoders */
dce_v11_0_ext_prepare(struct drm_encoder * encoder)3538 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3539 {
3540
3541 }
3542
dce_v11_0_ext_commit(struct drm_encoder * encoder)3543 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3544 {
3545
3546 }
3547
3548 static void
dce_v11_0_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3549 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3550 struct drm_display_mode *mode,
3551 struct drm_display_mode *adjusted_mode)
3552 {
3553
3554 }
3555
dce_v11_0_ext_disable(struct drm_encoder * encoder)3556 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3557 {
3558
3559 }
3560
3561 static void
dce_v11_0_ext_dpms(struct drm_encoder * encoder,int mode)3562 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3563 {
3564
3565 }
3566
3567 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3568 .dpms = dce_v11_0_ext_dpms,
3569 .prepare = dce_v11_0_ext_prepare,
3570 .mode_set = dce_v11_0_ext_mode_set,
3571 .commit = dce_v11_0_ext_commit,
3572 .disable = dce_v11_0_ext_disable,
3573 /* no detect for TMDS/LVDS yet */
3574 };
3575
3576 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3577 .dpms = amdgpu_atombios_encoder_dpms,
3578 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3579 .prepare = dce_v11_0_encoder_prepare,
3580 .mode_set = dce_v11_0_encoder_mode_set,
3581 .commit = dce_v11_0_encoder_commit,
3582 .disable = dce_v11_0_encoder_disable,
3583 .detect = amdgpu_atombios_encoder_dig_detect,
3584 };
3585
3586 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3587 .dpms = amdgpu_atombios_encoder_dpms,
3588 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3589 .prepare = dce_v11_0_encoder_prepare,
3590 .mode_set = dce_v11_0_encoder_mode_set,
3591 .commit = dce_v11_0_encoder_commit,
3592 .detect = amdgpu_atombios_encoder_dac_detect,
3593 };
3594
dce_v11_0_encoder_destroy(struct drm_encoder * encoder)3595 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3596 {
3597 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3598 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3599 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3600 kfree(amdgpu_encoder->enc_priv);
3601 drm_encoder_cleanup(encoder);
3602 kfree(amdgpu_encoder);
3603 }
3604
3605 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3606 .destroy = dce_v11_0_encoder_destroy,
3607 };
3608
dce_v11_0_encoder_add(struct amdgpu_device * adev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)3609 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3610 uint32_t encoder_enum,
3611 uint32_t supported_device,
3612 u16 caps)
3613 {
3614 struct drm_device *dev = adev->ddev;
3615 struct drm_encoder *encoder;
3616 struct amdgpu_encoder *amdgpu_encoder;
3617
3618 /* see if we already added it */
3619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3620 amdgpu_encoder = to_amdgpu_encoder(encoder);
3621 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3622 amdgpu_encoder->devices |= supported_device;
3623 return;
3624 }
3625
3626 }
3627
3628 /* add a new one */
3629 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3630 if (!amdgpu_encoder)
3631 return;
3632
3633 encoder = &amdgpu_encoder->base;
3634 switch (adev->mode_info.num_crtc) {
3635 case 1:
3636 encoder->possible_crtcs = 0x1;
3637 break;
3638 case 2:
3639 default:
3640 encoder->possible_crtcs = 0x3;
3641 break;
3642 case 3:
3643 encoder->possible_crtcs = 0x7;
3644 break;
3645 case 4:
3646 encoder->possible_crtcs = 0xf;
3647 break;
3648 case 5:
3649 encoder->possible_crtcs = 0x1f;
3650 break;
3651 case 6:
3652 encoder->possible_crtcs = 0x3f;
3653 break;
3654 }
3655
3656 amdgpu_encoder->enc_priv = NULL;
3657
3658 amdgpu_encoder->encoder_enum = encoder_enum;
3659 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3660 amdgpu_encoder->devices = supported_device;
3661 amdgpu_encoder->rmx_type = RMX_OFF;
3662 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3663 amdgpu_encoder->is_ext_encoder = false;
3664 amdgpu_encoder->caps = caps;
3665
3666 switch (amdgpu_encoder->encoder_id) {
3667 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3669 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3670 DRM_MODE_ENCODER_DAC, NULL);
3671 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3672 break;
3673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3674 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3675 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3676 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3677 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3678 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3679 amdgpu_encoder->rmx_type = RMX_FULL;
3680 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3681 DRM_MODE_ENCODER_LVDS, NULL);
3682 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3683 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3684 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3685 DRM_MODE_ENCODER_DAC, NULL);
3686 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3687 } else {
3688 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3689 DRM_MODE_ENCODER_TMDS, NULL);
3690 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3691 }
3692 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3693 break;
3694 case ENCODER_OBJECT_ID_SI170B:
3695 case ENCODER_OBJECT_ID_CH7303:
3696 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3697 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3698 case ENCODER_OBJECT_ID_TITFP513:
3699 case ENCODER_OBJECT_ID_VT1623:
3700 case ENCODER_OBJECT_ID_HDMI_SI1930:
3701 case ENCODER_OBJECT_ID_TRAVIS:
3702 case ENCODER_OBJECT_ID_NUTMEG:
3703 /* these are handled by the primary encoders */
3704 amdgpu_encoder->is_ext_encoder = true;
3705 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3706 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3707 DRM_MODE_ENCODER_LVDS, NULL);
3708 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3709 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3710 DRM_MODE_ENCODER_DAC, NULL);
3711 else
3712 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3713 DRM_MODE_ENCODER_TMDS, NULL);
3714 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3715 break;
3716 }
3717 }
3718
3719 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3720 .bandwidth_update = &dce_v11_0_bandwidth_update,
3721 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3722 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3723 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3724 .hpd_sense = &dce_v11_0_hpd_sense,
3725 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3726 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3727 .page_flip = &dce_v11_0_page_flip,
3728 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3729 .add_encoder = &dce_v11_0_encoder_add,
3730 .add_connector = &amdgpu_connector_add,
3731 };
3732
dce_v11_0_set_display_funcs(struct amdgpu_device * adev)3733 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3734 {
3735 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3736 }
3737
3738 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3739 .set = dce_v11_0_set_crtc_irq_state,
3740 .process = dce_v11_0_crtc_irq,
3741 };
3742
3743 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3744 .set = dce_v11_0_set_pageflip_irq_state,
3745 .process = dce_v11_0_pageflip_irq,
3746 };
3747
3748 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3749 .set = dce_v11_0_set_hpd_irq_state,
3750 .process = dce_v11_0_hpd_irq,
3751 };
3752
dce_v11_0_set_irq_funcs(struct amdgpu_device * adev)3753 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3754 {
3755 if (adev->mode_info.num_crtc > 0)
3756 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3757 else
3758 adev->crtc_irq.num_types = 0;
3759 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3760
3761 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3762 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3763
3764 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3765 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3766 }
3767
3768 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3769 {
3770 .type = AMD_IP_BLOCK_TYPE_DCE,
3771 .major = 11,
3772 .minor = 0,
3773 .rev = 0,
3774 .funcs = &dce_v11_0_ip_funcs,
3775 };
3776
3777 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3778 {
3779 .type = AMD_IP_BLOCK_TYPE_DCE,
3780 .major = 11,
3781 .minor = 2,
3782 .rev = 0,
3783 .funcs = &dce_v11_0_ip_funcs,
3784 };
3785