1 /* $NetBSD: amdgpu_dce_v6_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce_v6_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
28
29 #include <linux/pci.h>
30
31 #include <drm/drm_fourcc.h>
32 #include <drm/drm_vblank.h>
33
34 #include "amdgpu.h"
35 #include "amdgpu_pm.h"
36 #include "amdgpu_i2c.h"
37 #include "atom.h"
38 #include "amdgpu_atombios.h"
39 #include "atombios_crtc.h"
40 #include "atombios_encoders.h"
41 #include "amdgpu_pll.h"
42 #include "amdgpu_connectors.h"
43 #include "amdgpu_display.h"
44
45 #include "bif/bif_3_0_d.h"
46 #include "bif/bif_3_0_sh_mask.h"
47 #include "oss/oss_1_0_d.h"
48 #include "oss/oss_1_0_sh_mask.h"
49 #include "gca/gfx_6_0_d.h"
50 #include "gca/gfx_6_0_sh_mask.h"
51 #include "gmc/gmc_6_0_d.h"
52 #include "gmc/gmc_6_0_sh_mask.h"
53 #include "dce/dce_6_0_d.h"
54 #include "dce/dce_6_0_sh_mask.h"
55 #include "gca/gfx_7_2_enum.h"
56 #include "dce_v6_0.h"
57 #include "si_enums.h"
58
59 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
60 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
61
62 static const u32 crtc_offsets[6] =
63 {
64 SI_CRTC0_REGISTER_OFFSET,
65 SI_CRTC1_REGISTER_OFFSET,
66 SI_CRTC2_REGISTER_OFFSET,
67 SI_CRTC3_REGISTER_OFFSET,
68 SI_CRTC4_REGISTER_OFFSET,
69 SI_CRTC5_REGISTER_OFFSET
70 };
71
72 static const u32 hpd_offsets[] =
73 {
74 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
75 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
76 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
77 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
78 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
79 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
80 };
81
82 static const uint32_t dig_offsets[] = {
83 SI_CRTC0_REGISTER_OFFSET,
84 SI_CRTC1_REGISTER_OFFSET,
85 SI_CRTC2_REGISTER_OFFSET,
86 SI_CRTC3_REGISTER_OFFSET,
87 SI_CRTC4_REGISTER_OFFSET,
88 SI_CRTC5_REGISTER_OFFSET,
89 (0x13830 - 0x7030) >> 2,
90 };
91
92 static const struct {
93 uint32_t reg;
94 uint32_t vblank;
95 uint32_t vline;
96 uint32_t hpd;
97
98 } interrupt_status_offsets[6] = { {
99 .reg = mmDISP_INTERRUPT_STATUS,
100 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
101 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
102 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
103 }, {
104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
108 }, {
109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
113 }, {
114 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
115 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
116 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
118 }, {
119 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
120 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
121 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
123 }, {
124 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
125 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
126 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
127 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
128 } };
129
dce_v6_0_audio_endpt_rreg(struct amdgpu_device * adev,u32 block_offset,u32 reg)130 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
131 u32 block_offset, u32 reg)
132 {
133 unsigned long flags;
134 u32 r;
135
136 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
138 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
139 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
140
141 return r;
142 }
143
dce_v6_0_audio_endpt_wreg(struct amdgpu_device * adev,u32 block_offset,u32 reg,u32 v)144 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
145 u32 block_offset, u32 reg, u32 v)
146 {
147 unsigned long flags;
148
149 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
150 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
151 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
152 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
153 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
154 }
155
dce_v6_0_vblank_get_counter(struct amdgpu_device * adev,int crtc)156 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
157 {
158 if (crtc >= adev->mode_info.num_crtc)
159 return 0;
160 else
161 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
162 }
163
dce_v6_0_pageflip_interrupt_init(struct amdgpu_device * adev)164 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
165 {
166 unsigned i;
167
168 /* Enable pflip interrupts */
169 for (i = 0; i < adev->mode_info.num_crtc; i++)
170 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
171 }
172
dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device * adev)173 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
174 {
175 unsigned i;
176
177 /* Disable pflip interrupts */
178 for (i = 0; i < adev->mode_info.num_crtc; i++)
179 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
180 }
181
182 /**
183 * dce_v6_0_page_flip - pageflip callback.
184 *
185 * @adev: amdgpu_device pointer
186 * @crtc_id: crtc to cleanup pageflip on
187 * @crtc_base: new address of the crtc (GPU MC address)
188 *
189 * Does the actual pageflip (evergreen+).
190 * During vblank we take the crtc lock and wait for the update_pending
191 * bit to go high, when it does, we release the lock, and allow the
192 * double buffered update to take place.
193 * Returns the current update pending status.
194 */
dce_v6_0_page_flip(struct amdgpu_device * adev,int crtc_id,u64 crtc_base,bool async)195 static void dce_v6_0_page_flip(struct amdgpu_device *adev,
196 int crtc_id, u64 crtc_base, bool async)
197 {
198 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
199 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
200
201 /* flip at hsync for async, default is vsync */
202 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
203 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
204 /* update pitch */
205 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
206 fb->pitches[0] / fb->format->cpp[0]);
207 /* update the scanout addresses */
208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
209 upper_32_bits(crtc_base));
210 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
211 (u32)crtc_base);
212
213 /* post the write */
214 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
215 }
216
dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device * adev,int crtc,u32 * vbl,u32 * position)217 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
218 u32 *vbl, u32 *position)
219 {
220 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
221 return -EINVAL;
222 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
223 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
224
225 return 0;
226
227 }
228
229 /**
230 * dce_v6_0_hpd_sense - hpd sense callback.
231 *
232 * @adev: amdgpu_device pointer
233 * @hpd: hpd (hotplug detect) pin
234 *
235 * Checks if a digital monitor is connected (evergreen+).
236 * Returns true if connected, false if not connected.
237 */
dce_v6_0_hpd_sense(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)238 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
239 enum amdgpu_hpd_id hpd)
240 {
241 bool connected = false;
242
243 if (hpd >= adev->mode_info.num_hpd)
244 return connected;
245
246 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
247 connected = true;
248
249 return connected;
250 }
251
252 /**
253 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
254 *
255 * @adev: amdgpu_device pointer
256 * @hpd: hpd (hotplug detect) pin
257 *
258 * Set the polarity of the hpd pin (evergreen+).
259 */
dce_v6_0_hpd_set_polarity(struct amdgpu_device * adev,enum amdgpu_hpd_id hpd)260 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
261 enum amdgpu_hpd_id hpd)
262 {
263 u32 tmp;
264 bool connected = dce_v6_0_hpd_sense(adev, hpd);
265
266 if (hpd >= adev->mode_info.num_hpd)
267 return;
268
269 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
270 if (connected)
271 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
272 else
273 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
274 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
275 }
276
277 /**
278 * dce_v6_0_hpd_init - hpd setup callback.
279 *
280 * @adev: amdgpu_device pointer
281 *
282 * Setup the hpd pins used by the card (evergreen+).
283 * Enable the pin, set the polarity, and enable the hpd interrupts.
284 */
dce_v6_0_hpd_init(struct amdgpu_device * adev)285 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
286 {
287 struct drm_device *dev = adev->ddev;
288 struct drm_connector *connector;
289 struct drm_connector_list_iter iter;
290 u32 tmp;
291
292 drm_connector_list_iter_begin(dev, &iter);
293 drm_for_each_connector_iter(connector, &iter) {
294 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
295
296 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
297 continue;
298
299 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
300 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
301 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
302
303 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
304 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
305 /* don't try to enable hpd on eDP or LVDS avoid breaking the
306 * aux dp channel on imac and help (but not completely fix)
307 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
308 * also avoid interrupt storms during dpms.
309 */
310 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
311 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
312 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
313 continue;
314 }
315
316 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
317 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
318 }
319 drm_connector_list_iter_end(&iter);
320 }
321
322 /**
323 * dce_v6_0_hpd_fini - hpd tear down callback.
324 *
325 * @adev: amdgpu_device pointer
326 *
327 * Tear down the hpd pins used by the card (evergreen+).
328 * Disable the hpd interrupts.
329 */
dce_v6_0_hpd_fini(struct amdgpu_device * adev)330 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
331 {
332 struct drm_device *dev = adev->ddev;
333 struct drm_connector *connector;
334 struct drm_connector_list_iter iter;
335 u32 tmp;
336
337 drm_connector_list_iter_begin(dev, &iter);
338 drm_for_each_connector_iter(connector, &iter) {
339 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
340
341 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
342 continue;
343
344 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
345 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
346 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
347
348 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
349 }
350 drm_connector_list_iter_end(&iter);
351 }
352
dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device * adev)353 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
354 {
355 return mmDC_GPIO_HPD_A;
356 }
357
dce_v6_0_set_vga_render_state(struct amdgpu_device * adev,bool render)358 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
359 bool render)
360 {
361 if (!render)
362 WREG32(mmVGA_RENDER_CONTROL,
363 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
364
365 }
366
dce_v6_0_get_num_crtc(struct amdgpu_device * adev)367 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
368 {
369 switch (adev->asic_type) {
370 case CHIP_TAHITI:
371 case CHIP_PITCAIRN:
372 case CHIP_VERDE:
373 return 6;
374 case CHIP_OLAND:
375 return 2;
376 default:
377 return 0;
378 }
379 }
380
dce_v6_0_disable_dce(struct amdgpu_device * adev)381 void dce_v6_0_disable_dce(struct amdgpu_device *adev)
382 {
383 /*Disable VGA render and enabled crtc, if has DCE engine*/
384 if (amdgpu_atombios_has_dce_engine_info(adev)) {
385 u32 tmp;
386 int crtc_enabled, i;
387
388 dce_v6_0_set_vga_render_state(adev, false);
389
390 /*Disable crtc*/
391 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
392 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
393 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
394 if (crtc_enabled) {
395 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
396 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
397 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
398 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
399 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
400 }
401 }
402 }
403 }
404
dce_v6_0_program_fmt(struct drm_encoder * encoder)405 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
406 {
407
408 struct drm_device *dev = encoder->dev;
409 struct amdgpu_device *adev = dev->dev_private;
410 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
411 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
412 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
413 int bpc = 0;
414 u32 tmp = 0;
415 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
416
417 if (connector) {
418 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
419 bpc = amdgpu_connector_get_monitor_bpc(connector);
420 dither = amdgpu_connector->dither;
421 }
422
423 /* LVDS FMT is set up by atom */
424 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
425 return;
426
427 if (bpc == 0)
428 return;
429
430
431 switch (bpc) {
432 case 6:
433 if (dither == AMDGPU_FMT_DITHER_ENABLE)
434 /* XXX sort out optimal dither settings */
435 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
436 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
437 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
438 else
439 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
440 break;
441 case 8:
442 if (dither == AMDGPU_FMT_DITHER_ENABLE)
443 /* XXX sort out optimal dither settings */
444 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
445 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
446 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
447 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
448 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
449 else
450 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
451 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
452 break;
453 case 10:
454 default:
455 /* not needed */
456 break;
457 }
458
459 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
460 }
461
462 /**
463 * cik_get_number_of_dram_channels - get the number of dram channels
464 *
465 * @adev: amdgpu_device pointer
466 *
467 * Look up the number of video ram channels (CIK).
468 * Used for display watermark bandwidth calculations
469 * Returns the number of dram channels
470 */
si_get_number_of_dram_channels(struct amdgpu_device * adev)471 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
472 {
473 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
474
475 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
476 case 0:
477 default:
478 return 1;
479 case 1:
480 return 2;
481 case 2:
482 return 4;
483 case 3:
484 return 8;
485 case 4:
486 return 3;
487 case 5:
488 return 6;
489 case 6:
490 return 10;
491 case 7:
492 return 12;
493 case 8:
494 return 16;
495 }
496 }
497
498 struct dce6_wm_params {
499 u32 dram_channels; /* number of dram channels */
500 u32 yclk; /* bandwidth per dram data pin in kHz */
501 u32 sclk; /* engine clock in kHz */
502 u32 disp_clk; /* display clock in kHz */
503 u32 src_width; /* viewport width */
504 u32 active_time; /* active display time in ns */
505 u32 blank_time; /* blank time in ns */
506 bool interlaced; /* mode is interlaced */
507 fixed20_12 vsc; /* vertical scale ratio */
508 u32 num_heads; /* number of active crtcs */
509 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
510 u32 lb_size; /* line buffer allocated to pipe */
511 u32 vtaps; /* vertical scaler taps */
512 };
513
514 /**
515 * dce_v6_0_dram_bandwidth - get the dram bandwidth
516 *
517 * @wm: watermark calculation data
518 *
519 * Calculate the raw dram bandwidth (CIK).
520 * Used for display watermark bandwidth calculations
521 * Returns the dram bandwidth in MBytes/s
522 */
dce_v6_0_dram_bandwidth(struct dce6_wm_params * wm)523 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
524 {
525 /* Calculate raw DRAM Bandwidth */
526 fixed20_12 dram_efficiency; /* 0.7 */
527 fixed20_12 yclk, dram_channels, bandwidth;
528 fixed20_12 a;
529
530 a.full = dfixed_const(1000);
531 yclk.full = dfixed_const(wm->yclk);
532 yclk.full = dfixed_div(yclk, a);
533 dram_channels.full = dfixed_const(wm->dram_channels * 4);
534 a.full = dfixed_const(10);
535 dram_efficiency.full = dfixed_const(7);
536 dram_efficiency.full = dfixed_div(dram_efficiency, a);
537 bandwidth.full = dfixed_mul(dram_channels, yclk);
538 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
539
540 return dfixed_trunc(bandwidth);
541 }
542
543 /**
544 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
545 *
546 * @wm: watermark calculation data
547 *
548 * Calculate the dram bandwidth used for display (CIK).
549 * Used for display watermark bandwidth calculations
550 * Returns the dram bandwidth for display in MBytes/s
551 */
dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params * wm)552 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
553 {
554 /* Calculate DRAM Bandwidth and the part allocated to display. */
555 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
556 fixed20_12 yclk, dram_channels, bandwidth;
557 fixed20_12 a;
558
559 a.full = dfixed_const(1000);
560 yclk.full = dfixed_const(wm->yclk);
561 yclk.full = dfixed_div(yclk, a);
562 dram_channels.full = dfixed_const(wm->dram_channels * 4);
563 a.full = dfixed_const(10);
564 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
565 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
566 bandwidth.full = dfixed_mul(dram_channels, yclk);
567 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
568
569 return dfixed_trunc(bandwidth);
570 }
571
572 /**
573 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
574 *
575 * @wm: watermark calculation data
576 *
577 * Calculate the data return bandwidth used for display (CIK).
578 * Used for display watermark bandwidth calculations
579 * Returns the data return bandwidth in MBytes/s
580 */
dce_v6_0_data_return_bandwidth(struct dce6_wm_params * wm)581 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
582 {
583 /* Calculate the display Data return Bandwidth */
584 fixed20_12 return_efficiency; /* 0.8 */
585 fixed20_12 sclk, bandwidth;
586 fixed20_12 a;
587
588 a.full = dfixed_const(1000);
589 sclk.full = dfixed_const(wm->sclk);
590 sclk.full = dfixed_div(sclk, a);
591 a.full = dfixed_const(10);
592 return_efficiency.full = dfixed_const(8);
593 return_efficiency.full = dfixed_div(return_efficiency, a);
594 a.full = dfixed_const(32);
595 bandwidth.full = dfixed_mul(a, sclk);
596 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
597
598 return dfixed_trunc(bandwidth);
599 }
600
601 /**
602 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
603 *
604 * @wm: watermark calculation data
605 *
606 * Calculate the dmif bandwidth used for display (CIK).
607 * Used for display watermark bandwidth calculations
608 * Returns the dmif bandwidth in MBytes/s
609 */
dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params * wm)610 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
611 {
612 /* Calculate the DMIF Request Bandwidth */
613 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
614 fixed20_12 disp_clk, bandwidth;
615 fixed20_12 a, b;
616
617 a.full = dfixed_const(1000);
618 disp_clk.full = dfixed_const(wm->disp_clk);
619 disp_clk.full = dfixed_div(disp_clk, a);
620 a.full = dfixed_const(32);
621 b.full = dfixed_mul(a, disp_clk);
622
623 a.full = dfixed_const(10);
624 disp_clk_request_efficiency.full = dfixed_const(8);
625 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
626
627 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
628
629 return dfixed_trunc(bandwidth);
630 }
631
632 /**
633 * dce_v6_0_available_bandwidth - get the min available bandwidth
634 *
635 * @wm: watermark calculation data
636 *
637 * Calculate the min available bandwidth used for display (CIK).
638 * Used for display watermark bandwidth calculations
639 * Returns the min available bandwidth in MBytes/s
640 */
dce_v6_0_available_bandwidth(struct dce6_wm_params * wm)641 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
642 {
643 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
644 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
645 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
646 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
647
648 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
649 }
650
651 /**
652 * dce_v6_0_average_bandwidth - get the average available bandwidth
653 *
654 * @wm: watermark calculation data
655 *
656 * Calculate the average available bandwidth used for display (CIK).
657 * Used for display watermark bandwidth calculations
658 * Returns the average available bandwidth in MBytes/s
659 */
dce_v6_0_average_bandwidth(struct dce6_wm_params * wm)660 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
661 {
662 /* Calculate the display mode Average Bandwidth
663 * DisplayMode should contain the source and destination dimensions,
664 * timing, etc.
665 */
666 fixed20_12 bpp;
667 fixed20_12 line_time;
668 fixed20_12 src_width;
669 fixed20_12 bandwidth;
670 fixed20_12 a;
671
672 a.full = dfixed_const(1000);
673 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
674 line_time.full = dfixed_div(line_time, a);
675 bpp.full = dfixed_const(wm->bytes_per_pixel);
676 src_width.full = dfixed_const(wm->src_width);
677 bandwidth.full = dfixed_mul(src_width, bpp);
678 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
679 bandwidth.full = dfixed_div(bandwidth, line_time);
680
681 return dfixed_trunc(bandwidth);
682 }
683
684 /**
685 * dce_v6_0_latency_watermark - get the latency watermark
686 *
687 * @wm: watermark calculation data
688 *
689 * Calculate the latency watermark (CIK).
690 * Used for display watermark bandwidth calculations
691 * Returns the latency watermark in ns
692 */
dce_v6_0_latency_watermark(struct dce6_wm_params * wm)693 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
694 {
695 /* First calculate the latency in ns */
696 u32 mc_latency = 2000; /* 2000 ns. */
697 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
698 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
699 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
700 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
701 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
702 (wm->num_heads * cursor_line_pair_return_time);
703 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
704 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
705 u32 tmp, dmif_size = 12288;
706 fixed20_12 a, b, c;
707
708 if (wm->num_heads == 0)
709 return 0;
710
711 a.full = dfixed_const(2);
712 b.full = dfixed_const(1);
713 if ((wm->vsc.full > a.full) ||
714 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
715 (wm->vtaps >= 5) ||
716 ((wm->vsc.full >= a.full) && wm->interlaced))
717 max_src_lines_per_dst_line = 4;
718 else
719 max_src_lines_per_dst_line = 2;
720
721 a.full = dfixed_const(available_bandwidth);
722 b.full = dfixed_const(wm->num_heads);
723 a.full = dfixed_div(a, b);
724 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
725 tmp = min(dfixed_trunc(a), tmp);
726
727 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
728
729 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
730 b.full = dfixed_const(1000);
731 c.full = dfixed_const(lb_fill_bw);
732 b.full = dfixed_div(c, b);
733 a.full = dfixed_div(a, b);
734 line_fill_time = dfixed_trunc(a);
735
736 if (line_fill_time < wm->active_time)
737 return latency;
738 else
739 return latency + (line_fill_time - wm->active_time);
740
741 }
742
743 /**
744 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
745 * average and available dram bandwidth
746 *
747 * @wm: watermark calculation data
748 *
749 * Check if the display average bandwidth fits in the display
750 * dram bandwidth (CIK).
751 * Used for display watermark bandwidth calculations
752 * Returns true if the display fits, false if not.
753 */
dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params * wm)754 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
755 {
756 if (dce_v6_0_average_bandwidth(wm) <=
757 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
758 return true;
759 else
760 return false;
761 }
762
763 /**
764 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
765 * average and available bandwidth
766 *
767 * @wm: watermark calculation data
768 *
769 * Check if the display average bandwidth fits in the display
770 * available bandwidth (CIK).
771 * Used for display watermark bandwidth calculations
772 * Returns true if the display fits, false if not.
773 */
dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params * wm)774 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
775 {
776 if (dce_v6_0_average_bandwidth(wm) <=
777 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
778 return true;
779 else
780 return false;
781 }
782
783 /**
784 * dce_v6_0_check_latency_hiding - check latency hiding
785 *
786 * @wm: watermark calculation data
787 *
788 * Check latency hiding (CIK).
789 * Used for display watermark bandwidth calculations
790 * Returns true if the display fits, false if not.
791 */
dce_v6_0_check_latency_hiding(struct dce6_wm_params * wm)792 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
793 {
794 u32 lb_partitions = wm->lb_size / wm->src_width;
795 u32 line_time = wm->active_time + wm->blank_time;
796 u32 latency_tolerant_lines;
797 u32 latency_hiding;
798 fixed20_12 a;
799
800 a.full = dfixed_const(1);
801 if (wm->vsc.full > a.full)
802 latency_tolerant_lines = 1;
803 else {
804 if (lb_partitions <= (wm->vtaps + 1))
805 latency_tolerant_lines = 1;
806 else
807 latency_tolerant_lines = 2;
808 }
809
810 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
811
812 if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
813 return true;
814 else
815 return false;
816 }
817
818 /**
819 * dce_v6_0_program_watermarks - program display watermarks
820 *
821 * @adev: amdgpu_device pointer
822 * @amdgpu_crtc: the selected display controller
823 * @lb_size: line buffer size
824 * @num_heads: number of display controllers in use
825 *
826 * Calculate and program the display watermarks for the
827 * selected display controller (CIK).
828 */
dce_v6_0_program_watermarks(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,u32 lb_size,u32 num_heads)829 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
830 struct amdgpu_crtc *amdgpu_crtc,
831 u32 lb_size, u32 num_heads)
832 {
833 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
834 struct dce6_wm_params wm_low, wm_high;
835 u32 dram_channels;
836 u32 active_time;
837 u32 line_time = 0;
838 u32 latency_watermark_a = 0, latency_watermark_b = 0;
839 u32 priority_a_mark = 0, priority_b_mark = 0;
840 u32 priority_a_cnt = PRIORITY_OFF;
841 u32 priority_b_cnt = PRIORITY_OFF;
842 u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
843 fixed20_12 a, b, c;
844
845 if (amdgpu_crtc->base.enabled && num_heads && mode) {
846 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
847 (u32)mode->clock);
848 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
849 (u32)mode->clock);
850 line_time = min(line_time, (u32)65535);
851 priority_a_cnt = 0;
852 priority_b_cnt = 0;
853
854 dram_channels = si_get_number_of_dram_channels(adev);
855
856 /* watermark for high clocks */
857 if (adev->pm.dpm_enabled) {
858 wm_high.yclk =
859 amdgpu_dpm_get_mclk(adev, false) * 10;
860 wm_high.sclk =
861 amdgpu_dpm_get_sclk(adev, false) * 10;
862 } else {
863 wm_high.yclk = adev->pm.current_mclk * 10;
864 wm_high.sclk = adev->pm.current_sclk * 10;
865 }
866
867 wm_high.disp_clk = mode->clock;
868 wm_high.src_width = mode->crtc_hdisplay;
869 wm_high.active_time = active_time;
870 wm_high.blank_time = line_time - wm_high.active_time;
871 wm_high.interlaced = false;
872 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
873 wm_high.interlaced = true;
874 wm_high.vsc = amdgpu_crtc->vsc;
875 wm_high.vtaps = 1;
876 if (amdgpu_crtc->rmx_type != RMX_OFF)
877 wm_high.vtaps = 2;
878 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
879 wm_high.lb_size = lb_size;
880 wm_high.dram_channels = dram_channels;
881 wm_high.num_heads = num_heads;
882
883 if (adev->pm.dpm_enabled) {
884 /* watermark for low clocks */
885 wm_low.yclk =
886 amdgpu_dpm_get_mclk(adev, true) * 10;
887 wm_low.sclk =
888 amdgpu_dpm_get_sclk(adev, true) * 10;
889 } else {
890 wm_low.yclk = adev->pm.current_mclk * 10;
891 wm_low.sclk = adev->pm.current_sclk * 10;
892 }
893
894 wm_low.disp_clk = mode->clock;
895 wm_low.src_width = mode->crtc_hdisplay;
896 wm_low.active_time = active_time;
897 wm_low.blank_time = line_time - wm_low.active_time;
898 wm_low.interlaced = false;
899 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
900 wm_low.interlaced = true;
901 wm_low.vsc = amdgpu_crtc->vsc;
902 wm_low.vtaps = 1;
903 if (amdgpu_crtc->rmx_type != RMX_OFF)
904 wm_low.vtaps = 2;
905 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
906 wm_low.lb_size = lb_size;
907 wm_low.dram_channels = dram_channels;
908 wm_low.num_heads = num_heads;
909
910 /* set for high clocks */
911 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
912 /* set for low clocks */
913 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
914
915 /* possibly force display priority to high */
916 /* should really do this at mode validation time... */
917 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
918 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
919 !dce_v6_0_check_latency_hiding(&wm_high) ||
920 (adev->mode_info.disp_priority == 2)) {
921 DRM_DEBUG_KMS("force priority to high\n");
922 priority_a_cnt |= PRIORITY_ALWAYS_ON;
923 priority_b_cnt |= PRIORITY_ALWAYS_ON;
924 }
925 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
926 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
927 !dce_v6_0_check_latency_hiding(&wm_low) ||
928 (adev->mode_info.disp_priority == 2)) {
929 DRM_DEBUG_KMS("force priority to high\n");
930 priority_a_cnt |= PRIORITY_ALWAYS_ON;
931 priority_b_cnt |= PRIORITY_ALWAYS_ON;
932 }
933
934 a.full = dfixed_const(1000);
935 b.full = dfixed_const(mode->clock);
936 b.full = dfixed_div(b, a);
937 c.full = dfixed_const(latency_watermark_a);
938 c.full = dfixed_mul(c, b);
939 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
940 c.full = dfixed_div(c, a);
941 a.full = dfixed_const(16);
942 c.full = dfixed_div(c, a);
943 priority_a_mark = dfixed_trunc(c);
944 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
945
946 a.full = dfixed_const(1000);
947 b.full = dfixed_const(mode->clock);
948 b.full = dfixed_div(b, a);
949 c.full = dfixed_const(latency_watermark_b);
950 c.full = dfixed_mul(c, b);
951 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
952 c.full = dfixed_div(c, a);
953 a.full = dfixed_const(16);
954 c.full = dfixed_div(c, a);
955 priority_b_mark = dfixed_trunc(c);
956 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
957
958 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
959 }
960
961 /* select wm A */
962 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
963 tmp = arb_control3;
964 tmp &= ~LATENCY_WATERMARK_MASK(3);
965 tmp |= LATENCY_WATERMARK_MASK(1);
966 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
967 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
968 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
969 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
970 /* select wm B */
971 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
972 tmp &= ~LATENCY_WATERMARK_MASK(3);
973 tmp |= LATENCY_WATERMARK_MASK(2);
974 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
975 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
976 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
977 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
978 /* restore original selection */
979 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
980
981 /* write the priority marks */
982 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
983 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
984
985 /* save values for DPM */
986 amdgpu_crtc->line_time = line_time;
987 amdgpu_crtc->wm_high = latency_watermark_a;
988
989 /* Save number of lines the linebuffer leads before the scanout */
990 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
991 }
992
993 /* watermark setup */
dce_v6_0_line_buffer_adjust(struct amdgpu_device * adev,struct amdgpu_crtc * amdgpu_crtc,struct drm_display_mode * mode,struct drm_display_mode * other_mode)994 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
995 struct amdgpu_crtc *amdgpu_crtc,
996 struct drm_display_mode *mode,
997 struct drm_display_mode *other_mode)
998 {
999 u32 tmp, buffer_alloc, i;
1000 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1001 /*
1002 * Line Buffer Setup
1003 * There are 3 line buffers, each one shared by 2 display controllers.
1004 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1005 * the display controllers. The paritioning is done via one of four
1006 * preset allocations specified in bits 21:20:
1007 * 0 - half lb
1008 * 2 - whole lb, other crtc must be disabled
1009 */
1010 /* this can get tricky if we have two large displays on a paired group
1011 * of crtcs. Ideally for multiple large displays we'd assign them to
1012 * non-linked crtcs for maximum line buffer allocation.
1013 */
1014 if (amdgpu_crtc->base.enabled && mode) {
1015 if (other_mode) {
1016 tmp = 0; /* 1/2 */
1017 buffer_alloc = 1;
1018 } else {
1019 tmp = 2; /* whole */
1020 buffer_alloc = 2;
1021 }
1022 } else {
1023 tmp = 0;
1024 buffer_alloc = 0;
1025 }
1026
1027 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1028 DC_LB_MEMORY_CONFIG(tmp));
1029
1030 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1031 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1032 for (i = 0; i < adev->usec_timeout; i++) {
1033 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1034 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1035 break;
1036 udelay(1);
1037 }
1038
1039 if (amdgpu_crtc->base.enabled && mode) {
1040 switch (tmp) {
1041 case 0:
1042 default:
1043 return 4096 * 2;
1044 case 2:
1045 return 8192 * 2;
1046 }
1047 }
1048
1049 /* controller not enabled, so no lb used */
1050 return 0;
1051 }
1052
1053
1054 /**
1055 *
1056 * dce_v6_0_bandwidth_update - program display watermarks
1057 *
1058 * @adev: amdgpu_device pointer
1059 *
1060 * Calculate and program the display watermarks and line
1061 * buffer allocation (CIK).
1062 */
dce_v6_0_bandwidth_update(struct amdgpu_device * adev)1063 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1064 {
1065 struct drm_display_mode *mode0 = NULL;
1066 struct drm_display_mode *mode1 = NULL;
1067 u32 num_heads = 0, lb_size;
1068 int i;
1069
1070 if (!adev->mode_info.mode_config_initialized)
1071 return;
1072
1073 amdgpu_display_update_priority(adev);
1074
1075 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1076 if (adev->mode_info.crtcs[i]->base.enabled)
1077 num_heads++;
1078 }
1079 for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1080 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1081 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1082 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1083 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1084 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1085 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1086 }
1087 }
1088
dce_v6_0_audio_get_connected_pins(struct amdgpu_device * adev)1089 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1090 {
1091 int i;
1092 u32 tmp;
1093
1094 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1095 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
1096 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1097 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1098 PORT_CONNECTIVITY))
1099 adev->mode_info.audio.pin[i].connected = false;
1100 else
1101 adev->mode_info.audio.pin[i].connected = true;
1102 }
1103
1104 }
1105
dce_v6_0_audio_get_pin(struct amdgpu_device * adev)1106 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1107 {
1108 int i;
1109
1110 dce_v6_0_audio_get_connected_pins(adev);
1111
1112 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1113 if (adev->mode_info.audio.pin[i].connected)
1114 return &adev->mode_info.audio.pin[i];
1115 }
1116 DRM_ERROR("No connected audio pins found!\n");
1117 return NULL;
1118 }
1119
dce_v6_0_audio_select_pin(struct drm_encoder * encoder)1120 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
1121 {
1122 struct amdgpu_device *adev = encoder->dev->dev_private;
1123 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1124 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1125
1126 if (!dig || !dig->afmt || !dig->afmt->pin)
1127 return;
1128
1129 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
1130 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
1131 dig->afmt->pin->id));
1132 }
1133
dce_v6_0_audio_write_latency_fields(struct drm_encoder * encoder,struct drm_display_mode * mode)1134 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1135 struct drm_display_mode *mode)
1136 {
1137 struct drm_device *dev = encoder->dev;
1138 struct amdgpu_device *adev = dev->dev_private;
1139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1141 struct drm_connector *connector;
1142 struct drm_connector_list_iter iter;
1143 struct amdgpu_connector *amdgpu_connector = NULL;
1144 int interlace = 0;
1145 u32 tmp;
1146
1147 drm_connector_list_iter_begin(dev, &iter);
1148 drm_for_each_connector_iter(connector, &iter) {
1149 if (connector->encoder == encoder) {
1150 amdgpu_connector = to_amdgpu_connector(connector);
1151 break;
1152 }
1153 }
1154 drm_connector_list_iter_end(&iter);
1155
1156 if (!amdgpu_connector) {
1157 DRM_ERROR("Couldn't find encoder's connector\n");
1158 return;
1159 }
1160
1161 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1162 interlace = 1;
1163
1164 if (connector->latency_present[interlace]) {
1165 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1166 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1167 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1168 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1169 } else {
1170 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1171 VIDEO_LIPSYNC, 0);
1172 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1173 AUDIO_LIPSYNC, 0);
1174 }
1175 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1176 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1177 }
1178
dce_v6_0_audio_write_speaker_allocation(struct drm_encoder * encoder)1179 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1180 {
1181 struct drm_device *dev = encoder->dev;
1182 struct amdgpu_device *adev = dev->dev_private;
1183 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1184 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1185 struct drm_connector *connector;
1186 struct drm_connector_list_iter iter;
1187 struct amdgpu_connector *amdgpu_connector = NULL;
1188 u8 *sadb = NULL;
1189 int sad_count;
1190 u32 tmp;
1191
1192 drm_connector_list_iter_begin(dev, &iter);
1193 drm_for_each_connector_iter(connector, &iter) {
1194 if (connector->encoder == encoder) {
1195 amdgpu_connector = to_amdgpu_connector(connector);
1196 break;
1197 }
1198 }
1199 drm_connector_list_iter_end(&iter);
1200
1201 if (!amdgpu_connector) {
1202 DRM_ERROR("Couldn't find encoder's connector\n");
1203 return;
1204 }
1205
1206 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1207 if (sad_count < 0) {
1208 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1209 sad_count = 0;
1210 }
1211
1212 /* program the speaker allocation */
1213 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1214 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1215 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1216 HDMI_CONNECTION, 0);
1217 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1218 DP_CONNECTION, 0);
1219
1220 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
1221 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1222 DP_CONNECTION, 1);
1223 else
1224 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1225 HDMI_CONNECTION, 1);
1226
1227 if (sad_count)
1228 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1229 SPEAKER_ALLOCATION, sadb[0]);
1230 else
1231 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1232 SPEAKER_ALLOCATION, 5); /* stereo */
1233
1234 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1235 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1236
1237 kfree(sadb);
1238 }
1239
dce_v6_0_audio_write_sad_regs(struct drm_encoder * encoder)1240 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1241 {
1242 struct drm_device *dev = encoder->dev;
1243 struct amdgpu_device *adev = dev->dev_private;
1244 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1245 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1246 struct drm_connector *connector;
1247 struct drm_connector_list_iter iter;
1248 struct amdgpu_connector *amdgpu_connector = NULL;
1249 struct cea_sad *sads;
1250 int i, sad_count;
1251
1252 static const u16 eld_reg_to_type[][2] = {
1253 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1254 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1255 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1256 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1257 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1258 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1259 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1260 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1261 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1262 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1263 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1264 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1265 };
1266
1267 drm_connector_list_iter_begin(dev, &iter);
1268 drm_for_each_connector_iter(connector, &iter) {
1269 if (connector->encoder == encoder) {
1270 amdgpu_connector = to_amdgpu_connector(connector);
1271 break;
1272 }
1273 }
1274 drm_connector_list_iter_end(&iter);
1275
1276 if (!amdgpu_connector) {
1277 DRM_ERROR("Couldn't find encoder's connector\n");
1278 return;
1279 }
1280
1281 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1282 if (sad_count < 0)
1283 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1284 if (sad_count <= 0)
1285 return;
1286
1287 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1288 u32 tmp = 0;
1289 u8 stereo_freqs = 0;
1290 int max_channels = -1;
1291 int j;
1292
1293 for (j = 0; j < sad_count; j++) {
1294 struct cea_sad *sad = &sads[j];
1295
1296 if (sad->format == eld_reg_to_type[i][1]) {
1297 if (sad->channels > max_channels) {
1298 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1299 MAX_CHANNELS, sad->channels);
1300 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1301 DESCRIPTOR_BYTE_2, sad->byte2);
1302 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1303 SUPPORTED_FREQUENCIES, sad->freq);
1304 max_channels = sad->channels;
1305 }
1306
1307 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1308 stereo_freqs |= sad->freq;
1309 else
1310 break;
1311 }
1312 }
1313
1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1315 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1316 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1317 }
1318
1319 kfree(sads);
1320
1321 }
1322
dce_v6_0_audio_enable(struct amdgpu_device * adev,struct amdgpu_audio_pin * pin,bool enable)1323 static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1324 struct amdgpu_audio_pin *pin,
1325 bool enable)
1326 {
1327 if (!pin)
1328 return;
1329
1330 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1331 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1332 }
1333
1334 static const u32 pin_offsets[7] =
1335 {
1336 (0x1780 - 0x1780),
1337 (0x1786 - 0x1780),
1338 (0x178c - 0x1780),
1339 (0x1792 - 0x1780),
1340 (0x1798 - 0x1780),
1341 (0x179d - 0x1780),
1342 (0x17a4 - 0x1780),
1343 };
1344
dce_v6_0_audio_init(struct amdgpu_device * adev)1345 static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1346 {
1347 int i;
1348
1349 if (!amdgpu_audio)
1350 return 0;
1351
1352 adev->mode_info.audio.enabled = true;
1353
1354 switch (adev->asic_type) {
1355 case CHIP_TAHITI:
1356 case CHIP_PITCAIRN:
1357 case CHIP_VERDE:
1358 default:
1359 adev->mode_info.audio.num_pins = 6;
1360 break;
1361 case CHIP_OLAND:
1362 adev->mode_info.audio.num_pins = 2;
1363 break;
1364 }
1365
1366 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1367 adev->mode_info.audio.pin[i].channels = -1;
1368 adev->mode_info.audio.pin[i].rate = -1;
1369 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1370 adev->mode_info.audio.pin[i].status_bits = 0;
1371 adev->mode_info.audio.pin[i].category_code = 0;
1372 adev->mode_info.audio.pin[i].connected = false;
1373 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1374 adev->mode_info.audio.pin[i].id = i;
1375 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1376 }
1377
1378 return 0;
1379 }
1380
dce_v6_0_audio_fini(struct amdgpu_device * adev)1381 static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1382 {
1383 int i;
1384
1385 if (!amdgpu_audio)
1386 return;
1387
1388 if (!adev->mode_info.audio.enabled)
1389 return;
1390
1391 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1392 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1393
1394 adev->mode_info.audio.enabled = false;
1395 }
1396
dce_v6_0_audio_set_vbi_packet(struct drm_encoder * encoder)1397 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
1398 {
1399 struct drm_device *dev = encoder->dev;
1400 struct amdgpu_device *adev = dev->dev_private;
1401 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1402 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1403 u32 tmp;
1404
1405 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1406 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1407 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
1408 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
1409 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1410 }
1411
dce_v6_0_audio_set_acr(struct drm_encoder * encoder,uint32_t clock,int bpc)1412 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
1413 uint32_t clock, int bpc)
1414 {
1415 struct drm_device *dev = encoder->dev;
1416 struct amdgpu_device *adev = dev->dev_private;
1417 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1418 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1419 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1420 u32 tmp;
1421
1422 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1423 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1424 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
1425 bpc > 8 ? 0 : 1);
1426 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1427
1428 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1429 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1430 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1431 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1432 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1433 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1434
1435 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1436 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1437 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1438 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1439 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1440 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1441
1442 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1444 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1445 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1447 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1448 }
1449
dce_v6_0_audio_set_avi_infoframe(struct drm_encoder * encoder,struct drm_display_mode * mode)1450 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
1451 struct drm_display_mode *mode)
1452 {
1453 struct drm_device *dev = encoder->dev;
1454 struct amdgpu_device *adev = dev->dev_private;
1455 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1456 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1457 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1458 struct hdmi_avi_infoframe frame;
1459 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1460 uint8_t *payload = buffer + 3;
1461 uint8_t *header = buffer;
1462 ssize_t err;
1463 u32 tmp;
1464
1465 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1466 if (err < 0) {
1467 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1468 return;
1469 }
1470
1471 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1472 if (err < 0) {
1473 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1474 return;
1475 }
1476
1477 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1478 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24));
1479 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1480 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24));
1481 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1482 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24));
1483 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1484 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24));
1485
1486 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1487 /* anything other than 0 */
1488 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
1489 HDMI_AUDIO_INFO_LINE, 2);
1490 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1491 }
1492
dce_v6_0_audio_set_dto(struct drm_encoder * encoder,u32 clock)1493 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1494 {
1495 struct drm_device *dev = encoder->dev;
1496 struct amdgpu_device *adev = dev->dev_private;
1497 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1498 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1499 u32 tmp;
1500
1501 /*
1502 * Two dtos: generally use dto0 for hdmi, dto1 for dp.
1503 * Express [24MHz / target pixel clock] as an exact rational
1504 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1505 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1506 */
1507 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1508 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1509 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
1510 if (em == ATOM_ENCODER_MODE_HDMI) {
1511 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1512 DCCG_AUDIO_DTO_SEL, 0);
1513 } else if (ENCODER_MODE_IS_DP(em)) {
1514 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1515 DCCG_AUDIO_DTO_SEL, 1);
1516 }
1517 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1518 if (em == ATOM_ENCODER_MODE_HDMI) {
1519 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000);
1520 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);
1521 } else if (ENCODER_MODE_IS_DP(em)) {
1522 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
1523 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
1524 }
1525 }
1526
dce_v6_0_audio_set_packet(struct drm_encoder * encoder)1527 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
1528 {
1529 struct drm_device *dev = encoder->dev;
1530 struct amdgpu_device *adev = dev->dev_private;
1531 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1532 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1533 u32 tmp;
1534
1535 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1536 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1537 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1538
1539 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1540 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1541 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1542
1543 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1544 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1545 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1546
1547 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1548 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1549 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1550 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1551 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1552 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1553 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1554 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1555
1556 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
1557 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
1558 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
1559
1560 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1561 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1562 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1563 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1564
1565 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1566 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
1567 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1568 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1569 }
1570
dce_v6_0_audio_set_mute(struct drm_encoder * encoder,bool mute)1571 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
1572 {
1573 struct drm_device *dev = encoder->dev;
1574 struct amdgpu_device *adev = dev->dev_private;
1575 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1576 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1577 u32 tmp;
1578
1579 tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
1580 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
1581 WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
1582 }
1583
dce_v6_0_audio_hdmi_enable(struct drm_encoder * encoder,bool enable)1584 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
1585 {
1586 struct drm_device *dev = encoder->dev;
1587 struct amdgpu_device *adev = dev->dev_private;
1588 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1589 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1590 u32 tmp;
1591
1592 if (enable) {
1593 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1594 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1595 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1596 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1597 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1598 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1599
1600 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1601 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1602 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1603
1604 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1605 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1606 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1607 } else {
1608 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1609 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
1610 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
1611 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
1612 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
1613 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1614
1615 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1616 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
1617 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1618 }
1619 }
1620
dce_v6_0_audio_dp_enable(struct drm_encoder * encoder,bool enable)1621 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
1622 {
1623 struct drm_device *dev = encoder->dev;
1624 struct amdgpu_device *adev = dev->dev_private;
1625 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1626 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1627 u32 tmp;
1628
1629 if (enable) {
1630 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1631 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1632 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1633
1634 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
1635 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
1636 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
1637
1638 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
1639 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1640 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
1641 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
1642 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1643 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
1644 } else {
1645 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
1646 }
1647 }
1648
dce_v6_0_afmt_setmode(struct drm_encoder * encoder,struct drm_display_mode * mode)1649 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1650 struct drm_display_mode *mode)
1651 {
1652 struct drm_device *dev = encoder->dev;
1653 struct amdgpu_device *adev = dev->dev_private;
1654 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1655 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1656 struct drm_connector *connector;
1657 struct drm_connector_list_iter iter;
1658 struct amdgpu_connector *amdgpu_connector = NULL;
1659 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1660 int bpc = 8;
1661
1662 if (!dig || !dig->afmt)
1663 return;
1664
1665 drm_connector_list_iter_begin(dev, &iter);
1666 drm_for_each_connector_iter(connector, &iter) {
1667 if (connector->encoder == encoder) {
1668 amdgpu_connector = to_amdgpu_connector(connector);
1669 break;
1670 }
1671 }
1672 drm_connector_list_iter_end(&iter);
1673
1674 if (!amdgpu_connector) {
1675 DRM_ERROR("Couldn't find encoder's connector\n");
1676 return;
1677 }
1678
1679 if (!dig->afmt->enabled)
1680 return;
1681
1682 dig->afmt->pin = dce_v6_0_audio_get_pin(adev);
1683 if (!dig->afmt->pin)
1684 return;
1685
1686 if (encoder->crtc) {
1687 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1688 bpc = amdgpu_crtc->bpc;
1689 }
1690
1691 /* disable audio before setting up hw */
1692 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1693
1694 dce_v6_0_audio_set_mute(encoder, true);
1695 dce_v6_0_audio_write_speaker_allocation(encoder);
1696 dce_v6_0_audio_write_sad_regs(encoder);
1697 dce_v6_0_audio_write_latency_fields(encoder, mode);
1698 if (em == ATOM_ENCODER_MODE_HDMI) {
1699 dce_v6_0_audio_set_dto(encoder, mode->clock);
1700 dce_v6_0_audio_set_vbi_packet(encoder);
1701 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc);
1702 } else if (ENCODER_MODE_IS_DP(em)) {
1703 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);
1704 }
1705 dce_v6_0_audio_set_packet(encoder);
1706 dce_v6_0_audio_select_pin(encoder);
1707 dce_v6_0_audio_set_avi_infoframe(encoder, mode);
1708 dce_v6_0_audio_set_mute(encoder, false);
1709 if (em == ATOM_ENCODER_MODE_HDMI) {
1710 dce_v6_0_audio_hdmi_enable(encoder, 1);
1711 } else if (ENCODER_MODE_IS_DP(em)) {
1712 dce_v6_0_audio_dp_enable(encoder, 1);
1713 }
1714
1715 /* enable audio after setting up hw */
1716 dce_v6_0_audio_enable(adev, dig->afmt->pin, true);
1717 }
1718
dce_v6_0_afmt_enable(struct drm_encoder * encoder,bool enable)1719 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1720 {
1721 struct drm_device *dev = encoder->dev;
1722 struct amdgpu_device *adev = dev->dev_private;
1723 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1724 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1725
1726 if (!dig || !dig->afmt)
1727 return;
1728
1729 /* Silent, r600_hdmi_enable will raise WARN for us */
1730 if (enable && dig->afmt->enabled)
1731 return;
1732
1733 if (!enable && !dig->afmt->enabled)
1734 return;
1735
1736 if (!enable && dig->afmt->pin) {
1737 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1738 dig->afmt->pin = NULL;
1739 }
1740
1741 dig->afmt->enabled = enable;
1742
1743 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1744 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1745 }
1746
dce_v6_0_afmt_init(struct amdgpu_device * adev)1747 static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1748 {
1749 int i, j;
1750
1751 for (i = 0; i < adev->mode_info.num_dig; i++)
1752 adev->mode_info.afmt[i] = NULL;
1753
1754 /* DCE6 has audio blocks tied to DIG encoders */
1755 for (i = 0; i < adev->mode_info.num_dig; i++) {
1756 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1757 if (adev->mode_info.afmt[i]) {
1758 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1759 adev->mode_info.afmt[i]->id = i;
1760 } else {
1761 for (j = 0; j < i; j++) {
1762 kfree(adev->mode_info.afmt[j]);
1763 adev->mode_info.afmt[j] = NULL;
1764 }
1765 DRM_ERROR("Out of memory allocating afmt table\n");
1766 return -ENOMEM;
1767 }
1768 }
1769 return 0;
1770 }
1771
dce_v6_0_afmt_fini(struct amdgpu_device * adev)1772 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1773 {
1774 int i;
1775
1776 for (i = 0; i < adev->mode_info.num_dig; i++) {
1777 kfree(adev->mode_info.afmt[i]);
1778 adev->mode_info.afmt[i] = NULL;
1779 }
1780 }
1781
1782 static const u32 vga_control_regs[6] =
1783 {
1784 mmD1VGA_CONTROL,
1785 mmD2VGA_CONTROL,
1786 mmD3VGA_CONTROL,
1787 mmD4VGA_CONTROL,
1788 mmD5VGA_CONTROL,
1789 mmD6VGA_CONTROL,
1790 };
1791
dce_v6_0_vga_enable(struct drm_crtc * crtc,bool enable)1792 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1793 {
1794 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1795 struct drm_device *dev = crtc->dev;
1796 struct amdgpu_device *adev = dev->dev_private;
1797 u32 vga_control;
1798
1799 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1800 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1801 }
1802
dce_v6_0_grph_enable(struct drm_crtc * crtc,bool enable)1803 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1804 {
1805 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1806 struct drm_device *dev = crtc->dev;
1807 struct amdgpu_device *adev = dev->dev_private;
1808
1809 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1810 }
1811
dce_v6_0_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1812 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1813 struct drm_framebuffer *fb,
1814 int x, int y, int atomic)
1815 {
1816 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1817 struct drm_device *dev = crtc->dev;
1818 struct amdgpu_device *adev = dev->dev_private;
1819 struct drm_framebuffer *target_fb;
1820 struct drm_gem_object *obj;
1821 struct amdgpu_bo *abo;
1822 uint64_t fb_location, tiling_flags;
1823 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1824 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1825 u32 viewport_w, viewport_h;
1826 int r;
1827 bool bypass_lut = false;
1828 struct drm_format_name_buf format_name;
1829
1830 /* no fb bound */
1831 if (!atomic && !crtc->primary->fb) {
1832 DRM_DEBUG_KMS("No FB bound\n");
1833 return 0;
1834 }
1835
1836 if (atomic)
1837 target_fb = fb;
1838 else
1839 target_fb = crtc->primary->fb;
1840
1841 /* If atomic, assume fb object is pinned & idle & fenced and
1842 * just update base pointers
1843 */
1844 obj = target_fb->obj[0];
1845 abo = gem_to_amdgpu_bo(obj);
1846 r = amdgpu_bo_reserve(abo, false);
1847 if (unlikely(r != 0))
1848 return r;
1849
1850 if (!atomic) {
1851 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1852 if (unlikely(r != 0)) {
1853 amdgpu_bo_unreserve(abo);
1854 return -EINVAL;
1855 }
1856 }
1857 fb_location = amdgpu_bo_gpu_offset(abo);
1858
1859 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1860 amdgpu_bo_unreserve(abo);
1861
1862 switch (target_fb->format->format) {
1863 case DRM_FORMAT_C8:
1864 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1865 GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1866 break;
1867 case DRM_FORMAT_XRGB4444:
1868 case DRM_FORMAT_ARGB4444:
1869 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1870 GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1871 #ifdef __BIG_ENDIAN
1872 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1873 #endif
1874 break;
1875 case DRM_FORMAT_XRGB1555:
1876 case DRM_FORMAT_ARGB1555:
1877 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1878 GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1879 #ifdef __BIG_ENDIAN
1880 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1881 #endif
1882 break;
1883 case DRM_FORMAT_BGRX5551:
1884 case DRM_FORMAT_BGRA5551:
1885 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1886 GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1887 #ifdef __BIG_ENDIAN
1888 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1889 #endif
1890 break;
1891 case DRM_FORMAT_RGB565:
1892 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1893 GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1894 #ifdef __BIG_ENDIAN
1895 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1896 #endif
1897 break;
1898 case DRM_FORMAT_XRGB8888:
1899 case DRM_FORMAT_ARGB8888:
1900 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1901 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1902 #ifdef __BIG_ENDIAN
1903 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1904 #endif
1905 break;
1906 case DRM_FORMAT_XRGB2101010:
1907 case DRM_FORMAT_ARGB2101010:
1908 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1909 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1910 #ifdef __BIG_ENDIAN
1911 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1912 #endif
1913 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1914 bypass_lut = true;
1915 break;
1916 case DRM_FORMAT_BGRX1010102:
1917 case DRM_FORMAT_BGRA1010102:
1918 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1919 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1920 #ifdef __BIG_ENDIAN
1921 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1922 #endif
1923 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1924 bypass_lut = true;
1925 break;
1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1929 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1930 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) |
1931 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R));
1932 #ifdef __BIG_ENDIAN
1933 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1934 #endif
1935 break;
1936 default:
1937 DRM_ERROR("Unsupported screen format %s\n",
1938 drm_get_format_name(target_fb->format->format, &format_name));
1939 return -EINVAL;
1940 }
1941
1942 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1943 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1944
1945 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1946 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1948 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1949 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1950
1951 fb_format |= GRPH_NUM_BANKS(num_banks);
1952 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1953 fb_format |= GRPH_TILE_SPLIT(tile_split);
1954 fb_format |= GRPH_BANK_WIDTH(bankw);
1955 fb_format |= GRPH_BANK_HEIGHT(bankh);
1956 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1957 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1958 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1959 }
1960
1961 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1962 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1963
1964 dce_v6_0_vga_enable(crtc, false);
1965
1966 /* Make sure surface address is updated at vertical blank rather than
1967 * horizontal blank
1968 */
1969 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1970
1971 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1972 upper_32_bits(fb_location));
1973 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1974 upper_32_bits(fb_location));
1975 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1976 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1977 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1978 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1979 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1980 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1981
1982 /*
1983 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1984 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1985 * retain the full precision throughout the pipeline.
1986 */
1987 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1988 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1989 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1990
1991 if (bypass_lut)
1992 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1993
1994 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1995 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1996 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1997 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1998 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1999 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2000
2001 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2002 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2003
2004 dce_v6_0_grph_enable(crtc, true);
2005
2006 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2007 target_fb->height);
2008 x &= ~3;
2009 y &= ~1;
2010 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2011 (x << 16) | y);
2012 viewport_w = crtc->mode.hdisplay;
2013 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2014
2015 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2016 (viewport_w << 16) | viewport_h);
2017
2018 /* set pageflip to happen anywhere in vblank interval */
2019 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2020
2021 if (!atomic && fb && fb != crtc->primary->fb) {
2022 abo = gem_to_amdgpu_bo(fb->obj[0]);
2023 r = amdgpu_bo_reserve(abo, true);
2024 if (unlikely(r != 0))
2025 return r;
2026 amdgpu_bo_unpin(abo);
2027 amdgpu_bo_unreserve(abo);
2028 }
2029
2030 /* Bytes per pixel may have changed */
2031 dce_v6_0_bandwidth_update(adev);
2032
2033 return 0;
2034
2035 }
2036
dce_v6_0_set_interleave(struct drm_crtc * crtc,struct drm_display_mode * mode)2037 static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
2038 struct drm_display_mode *mode)
2039 {
2040 struct drm_device *dev = crtc->dev;
2041 struct amdgpu_device *adev = dev->dev_private;
2042 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2043
2044 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2045 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
2046 INTERLEAVE_EN);
2047 else
2048 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2049 }
2050
dce_v6_0_crtc_load_lut(struct drm_crtc * crtc)2051 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
2052 {
2053
2054 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2055 struct drm_device *dev = crtc->dev;
2056 struct amdgpu_device *adev = dev->dev_private;
2057 u16 *r, *g, *b;
2058 int i;
2059
2060 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2061
2062 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2063 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2064 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2065 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2066 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2067 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2068 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2069 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2070 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2071 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2072
2073 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2074
2075 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2076 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2077 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2078
2079 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2080 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2081 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2082
2083 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2084 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2085
2086 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2087 r = crtc->gamma_store;
2088 g = r + crtc->gamma_size;
2089 b = g + crtc->gamma_size;
2090 for (i = 0; i < 256; i++) {
2091 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2092 ((*r++ & 0xffc0) << 14) |
2093 ((*g++ & 0xffc0) << 4) |
2094 (*b++ >> 6));
2095 }
2096
2097 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2098 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2099 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2100 ICON_DEGAMMA_MODE(0) |
2101 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2102 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2103 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2104 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2105 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2106 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2107 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2108 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2109 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2110 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2111 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2112 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2113
2114
2115 }
2116
dce_v6_0_pick_dig_encoder(struct drm_encoder * encoder)2117 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
2118 {
2119 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2120 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2121
2122 switch (amdgpu_encoder->encoder_id) {
2123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2124 return dig->linkb ? 1 : 0;
2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2126 return dig->linkb ? 3 : 2;
2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2128 return dig->linkb ? 5 : 4;
2129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2130 return 6;
2131 default:
2132 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2133 return 0;
2134 }
2135 }
2136
2137 /**
2138 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2139 *
2140 * @crtc: drm crtc
2141 *
2142 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2143 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2144 * monitors a dedicated PPLL must be used. If a particular board has
2145 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2146 * as there is no need to program the PLL itself. If we are not able to
2147 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2148 * avoid messing up an existing monitor.
2149 *
2150 *
2151 */
dce_v6_0_pick_pll(struct drm_crtc * crtc)2152 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
2153 {
2154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2155 struct drm_device *dev = crtc->dev;
2156 struct amdgpu_device *adev = dev->dev_private;
2157 u32 pll_in_use;
2158 int pll;
2159
2160 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2161 if (adev->clock.dp_extclk)
2162 /* skip PPLL programming if using ext clock */
2163 return ATOM_PPLL_INVALID;
2164 else
2165 return ATOM_PPLL0;
2166 } else {
2167 /* use the same PPLL for all monitors with the same clock */
2168 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2169 if (pll != ATOM_PPLL_INVALID)
2170 return pll;
2171 }
2172
2173 /* PPLL1, and PPLL2 */
2174 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2175 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2176 return ATOM_PPLL2;
2177 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2178 return ATOM_PPLL1;
2179 DRM_ERROR("unable to allocate a PPLL\n");
2180 return ATOM_PPLL_INVALID;
2181 }
2182
dce_v6_0_lock_cursor(struct drm_crtc * crtc,bool lock)2183 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2184 {
2185 struct amdgpu_device *adev = crtc->dev->dev_private;
2186 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2187 uint32_t cur_lock;
2188
2189 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2190 if (lock)
2191 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2192 else
2193 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2194 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2195 }
2196
dce_v6_0_hide_cursor(struct drm_crtc * crtc)2197 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
2198 {
2199 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2200 struct amdgpu_device *adev = crtc->dev->dev_private;
2201
2202 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2203 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2204 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2205
2206
2207 }
2208
dce_v6_0_show_cursor(struct drm_crtc * crtc)2209 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
2210 {
2211 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2212 struct amdgpu_device *adev = crtc->dev->dev_private;
2213
2214 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2215 upper_32_bits(amdgpu_crtc->cursor_addr));
2216 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2217 lower_32_bits(amdgpu_crtc->cursor_addr));
2218
2219 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2220 CUR_CONTROL__CURSOR_EN_MASK |
2221 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2222 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2223
2224 }
2225
dce_v6_0_cursor_move_locked(struct drm_crtc * crtc,int x,int y)2226 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
2227 int x, int y)
2228 {
2229 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2230 struct amdgpu_device *adev = crtc->dev->dev_private;
2231 int xorigin = 0, yorigin = 0;
2232
2233 int w = amdgpu_crtc->cursor_width;
2234
2235 amdgpu_crtc->cursor_x = x;
2236 amdgpu_crtc->cursor_y = y;
2237
2238 /* avivo cursor are offset into the total surface */
2239 x += crtc->x;
2240 y += crtc->y;
2241 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2242
2243 if (x < 0) {
2244 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2245 x = 0;
2246 }
2247 if (y < 0) {
2248 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2249 y = 0;
2250 }
2251
2252 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2253 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2254 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2255 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2256
2257 return 0;
2258 }
2259
dce_v6_0_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)2260 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
2261 int x, int y)
2262 {
2263 int ret;
2264
2265 dce_v6_0_lock_cursor(crtc, true);
2266 ret = dce_v6_0_cursor_move_locked(crtc, x, y);
2267 dce_v6_0_lock_cursor(crtc, false);
2268
2269 return ret;
2270 }
2271
dce_v6_0_crtc_cursor_set2(struct drm_crtc * crtc,struct drm_file * file_priv,uint32_t handle,uint32_t width,uint32_t height,int32_t hot_x,int32_t hot_y)2272 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
2273 struct drm_file *file_priv,
2274 uint32_t handle,
2275 uint32_t width,
2276 uint32_t height,
2277 int32_t hot_x,
2278 int32_t hot_y)
2279 {
2280 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2281 struct drm_gem_object *obj;
2282 struct amdgpu_bo *aobj;
2283 int ret;
2284
2285 if (!handle) {
2286 /* turn off cursor */
2287 dce_v6_0_hide_cursor(crtc);
2288 obj = NULL;
2289 goto unpin;
2290 }
2291
2292 if ((width > amdgpu_crtc->max_cursor_width) ||
2293 (height > amdgpu_crtc->max_cursor_height)) {
2294 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2295 return -EINVAL;
2296 }
2297
2298 obj = drm_gem_object_lookup(file_priv, handle);
2299 if (!obj) {
2300 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2301 return -ENOENT;
2302 }
2303
2304 aobj = gem_to_amdgpu_bo(obj);
2305 ret = amdgpu_bo_reserve(aobj, false);
2306 if (ret != 0) {
2307 drm_gem_object_put_unlocked(obj);
2308 return ret;
2309 }
2310
2311 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2312 amdgpu_bo_unreserve(aobj);
2313 if (ret) {
2314 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2315 drm_gem_object_put_unlocked(obj);
2316 return ret;
2317 }
2318 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2319
2320 dce_v6_0_lock_cursor(crtc, true);
2321
2322 if (width != amdgpu_crtc->cursor_width ||
2323 height != amdgpu_crtc->cursor_height ||
2324 hot_x != amdgpu_crtc->cursor_hot_x ||
2325 hot_y != amdgpu_crtc->cursor_hot_y) {
2326 int x, y;
2327
2328 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2329 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2330
2331 dce_v6_0_cursor_move_locked(crtc, x, y);
2332
2333 amdgpu_crtc->cursor_width = width;
2334 amdgpu_crtc->cursor_height = height;
2335 amdgpu_crtc->cursor_hot_x = hot_x;
2336 amdgpu_crtc->cursor_hot_y = hot_y;
2337 }
2338
2339 dce_v6_0_show_cursor(crtc);
2340 dce_v6_0_lock_cursor(crtc, false);
2341
2342 unpin:
2343 if (amdgpu_crtc->cursor_bo) {
2344 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2345 ret = amdgpu_bo_reserve(aobj, true);
2346 if (likely(ret == 0)) {
2347 amdgpu_bo_unpin(aobj);
2348 amdgpu_bo_unreserve(aobj);
2349 }
2350 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2351 }
2352
2353 amdgpu_crtc->cursor_bo = obj;
2354 return 0;
2355 }
2356
dce_v6_0_cursor_reset(struct drm_crtc * crtc)2357 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
2358 {
2359 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2360
2361 if (amdgpu_crtc->cursor_bo) {
2362 dce_v6_0_lock_cursor(crtc, true);
2363
2364 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2365 amdgpu_crtc->cursor_y);
2366
2367 dce_v6_0_show_cursor(crtc);
2368 dce_v6_0_lock_cursor(crtc, false);
2369 }
2370 }
2371
dce_v6_0_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)2372 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2373 u16 *blue, uint32_t size,
2374 struct drm_modeset_acquire_ctx *ctx)
2375 {
2376 dce_v6_0_crtc_load_lut(crtc);
2377
2378 return 0;
2379 }
2380
dce_v6_0_crtc_destroy(struct drm_crtc * crtc)2381 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2382 {
2383 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2384
2385 drm_crtc_cleanup(crtc);
2386 kfree(amdgpu_crtc);
2387 }
2388
2389 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2390 .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2391 .cursor_move = dce_v6_0_crtc_cursor_move,
2392 .gamma_set = dce_v6_0_crtc_gamma_set,
2393 .set_config = amdgpu_display_crtc_set_config,
2394 .destroy = dce_v6_0_crtc_destroy,
2395 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2396 };
2397
dce_v6_0_crtc_dpms(struct drm_crtc * crtc,int mode)2398 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2399 {
2400 struct drm_device *dev = crtc->dev;
2401 struct amdgpu_device *adev = dev->dev_private;
2402 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2403 unsigned type;
2404
2405 switch (mode) {
2406 case DRM_MODE_DPMS_ON:
2407 amdgpu_crtc->enabled = true;
2408 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2409 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2410 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2411 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2412 amdgpu_crtc->crtc_id);
2413 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2414 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2415 drm_crtc_vblank_on(crtc);
2416 dce_v6_0_crtc_load_lut(crtc);
2417 break;
2418 case DRM_MODE_DPMS_STANDBY:
2419 case DRM_MODE_DPMS_SUSPEND:
2420 case DRM_MODE_DPMS_OFF:
2421 drm_crtc_vblank_off(crtc);
2422 if (amdgpu_crtc->enabled)
2423 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2424 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2425 amdgpu_crtc->enabled = false;
2426 break;
2427 }
2428 /* adjust pm to dpms */
2429 amdgpu_pm_compute_clocks(adev);
2430 }
2431
dce_v6_0_crtc_prepare(struct drm_crtc * crtc)2432 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2433 {
2434 /* disable crtc pair power gating before programming */
2435 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2436 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2437 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2438 }
2439
dce_v6_0_crtc_commit(struct drm_crtc * crtc)2440 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2441 {
2442 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2443 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2444 }
2445
dce_v6_0_crtc_disable(struct drm_crtc * crtc)2446 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2447 {
2448
2449 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2450 struct drm_device *dev = crtc->dev;
2451 struct amdgpu_device *adev = dev->dev_private;
2452 struct amdgpu_atom_ss ss;
2453 int i;
2454
2455 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2456 if (crtc->primary->fb) {
2457 int r;
2458 struct amdgpu_bo *abo;
2459
2460 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2461 r = amdgpu_bo_reserve(abo, true);
2462 if (unlikely(r))
2463 DRM_ERROR("failed to reserve abo before unpin\n");
2464 else {
2465 amdgpu_bo_unpin(abo);
2466 amdgpu_bo_unreserve(abo);
2467 }
2468 }
2469 /* disable the GRPH */
2470 dce_v6_0_grph_enable(crtc, false);
2471
2472 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2473
2474 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2475 if (adev->mode_info.crtcs[i] &&
2476 adev->mode_info.crtcs[i]->enabled &&
2477 i != amdgpu_crtc->crtc_id &&
2478 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2479 /* one other crtc is using this pll don't turn
2480 * off the pll
2481 */
2482 goto done;
2483 }
2484 }
2485
2486 switch (amdgpu_crtc->pll_id) {
2487 case ATOM_PPLL1:
2488 case ATOM_PPLL2:
2489 /* disable the ppll */
2490 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2491 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2492 break;
2493 default:
2494 break;
2495 }
2496 done:
2497 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2498 amdgpu_crtc->adjusted_clock = 0;
2499 amdgpu_crtc->encoder = NULL;
2500 amdgpu_crtc->connector = NULL;
2501 }
2502
dce_v6_0_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)2503 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2504 struct drm_display_mode *mode,
2505 struct drm_display_mode *adjusted_mode,
2506 int x, int y, struct drm_framebuffer *old_fb)
2507 {
2508 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2509
2510 if (!amdgpu_crtc->adjusted_clock)
2511 return -EINVAL;
2512
2513 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2514 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2515 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2516 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2517 amdgpu_atombios_crtc_scaler_setup(crtc);
2518 dce_v6_0_cursor_reset(crtc);
2519 /* update the hw version fpr dpm */
2520 amdgpu_crtc->hw_mode = *adjusted_mode;
2521
2522 return 0;
2523 }
2524
dce_v6_0_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2525 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2526 const struct drm_display_mode *mode,
2527 struct drm_display_mode *adjusted_mode)
2528 {
2529
2530 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2531 struct drm_device *dev = crtc->dev;
2532 struct drm_encoder *encoder;
2533
2534 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2535 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2536 if (encoder->crtc == crtc) {
2537 amdgpu_crtc->encoder = encoder;
2538 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2539 break;
2540 }
2541 }
2542 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2543 amdgpu_crtc->encoder = NULL;
2544 amdgpu_crtc->connector = NULL;
2545 return false;
2546 }
2547 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2548 return false;
2549 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2550 return false;
2551 /* pick pll */
2552 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2553 /* if we can't get a PPLL for a non-DP encoder, fail */
2554 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2555 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2556 return false;
2557
2558 return true;
2559 }
2560
dce_v6_0_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)2561 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2562 struct drm_framebuffer *old_fb)
2563 {
2564 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2565 }
2566
dce_v6_0_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)2567 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2568 struct drm_framebuffer *fb,
2569 int x, int y, enum mode_set_atomic state)
2570 {
2571 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2572 }
2573
2574 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2575 .dpms = dce_v6_0_crtc_dpms,
2576 .mode_fixup = dce_v6_0_crtc_mode_fixup,
2577 .mode_set = dce_v6_0_crtc_mode_set,
2578 .mode_set_base = dce_v6_0_crtc_set_base,
2579 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2580 .prepare = dce_v6_0_crtc_prepare,
2581 .commit = dce_v6_0_crtc_commit,
2582 .disable = dce_v6_0_crtc_disable,
2583 };
2584
dce_v6_0_crtc_init(struct amdgpu_device * adev,int index)2585 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2586 {
2587 struct amdgpu_crtc *amdgpu_crtc;
2588
2589 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2590 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2591 if (amdgpu_crtc == NULL)
2592 return -ENOMEM;
2593
2594 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2595
2596 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2597 amdgpu_crtc->crtc_id = index;
2598 adev->mode_info.crtcs[index] = amdgpu_crtc;
2599
2600 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2601 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2602 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2603 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2604
2605 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2606
2607 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2608 amdgpu_crtc->adjusted_clock = 0;
2609 amdgpu_crtc->encoder = NULL;
2610 amdgpu_crtc->connector = NULL;
2611 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2612
2613 return 0;
2614 }
2615
dce_v6_0_early_init(void * handle)2616 static int dce_v6_0_early_init(void *handle)
2617 {
2618 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2619
2620 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2621 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2622
2623 dce_v6_0_set_display_funcs(adev);
2624
2625 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2626
2627 switch (adev->asic_type) {
2628 case CHIP_TAHITI:
2629 case CHIP_PITCAIRN:
2630 case CHIP_VERDE:
2631 adev->mode_info.num_hpd = 6;
2632 adev->mode_info.num_dig = 6;
2633 break;
2634 case CHIP_OLAND:
2635 adev->mode_info.num_hpd = 2;
2636 adev->mode_info.num_dig = 2;
2637 break;
2638 default:
2639 return -EINVAL;
2640 }
2641
2642 dce_v6_0_set_irq_funcs(adev);
2643
2644 return 0;
2645 }
2646
dce_v6_0_sw_init(void * handle)2647 static int dce_v6_0_sw_init(void *handle)
2648 {
2649 int r, i;
2650 bool ret;
2651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2652
2653 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2654 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2655 if (r)
2656 return r;
2657 }
2658
2659 for (i = 8; i < 20; i += 2) {
2660 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2661 if (r)
2662 return r;
2663 }
2664
2665 /* HPD hotplug */
2666 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2667 if (r)
2668 return r;
2669
2670 adev->mode_info.mode_config_initialized = true;
2671
2672 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2673 adev->ddev->mode_config.async_page_flip = true;
2674 adev->ddev->mode_config.max_width = 16384;
2675 adev->ddev->mode_config.max_height = 16384;
2676 adev->ddev->mode_config.preferred_depth = 24;
2677 adev->ddev->mode_config.prefer_shadow = 1;
2678 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2679
2680 r = amdgpu_display_modeset_create_props(adev);
2681 if (r)
2682 return r;
2683
2684 adev->ddev->mode_config.max_width = 16384;
2685 adev->ddev->mode_config.max_height = 16384;
2686
2687 /* allocate crtcs */
2688 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2689 r = dce_v6_0_crtc_init(adev, i);
2690 if (r)
2691 return r;
2692 }
2693
2694 ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2695 if (ret)
2696 amdgpu_display_print_display_setup(adev->ddev);
2697 else
2698 return -EINVAL;
2699
2700 /* setup afmt */
2701 r = dce_v6_0_afmt_init(adev);
2702 if (r)
2703 return r;
2704
2705 r = dce_v6_0_audio_init(adev);
2706 if (r)
2707 return r;
2708
2709 drm_kms_helper_poll_init(adev->ddev);
2710
2711 return r;
2712 }
2713
dce_v6_0_sw_fini(void * handle)2714 static int dce_v6_0_sw_fini(void *handle)
2715 {
2716 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2717
2718 kfree(adev->mode_info.bios_hardcoded_edid);
2719
2720 drm_kms_helper_poll_fini(adev->ddev);
2721
2722 dce_v6_0_audio_fini(adev);
2723 dce_v6_0_afmt_fini(adev);
2724
2725 drm_mode_config_cleanup(adev->ddev);
2726 adev->mode_info.mode_config_initialized = false;
2727
2728 return 0;
2729 }
2730
dce_v6_0_hw_init(void * handle)2731 static int dce_v6_0_hw_init(void *handle)
2732 {
2733 int i;
2734 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2735
2736 /* disable vga render */
2737 dce_v6_0_set_vga_render_state(adev, false);
2738 /* init dig PHYs, disp eng pll */
2739 amdgpu_atombios_encoder_init_dig(adev);
2740 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2741
2742 /* initialize hpd */
2743 dce_v6_0_hpd_init(adev);
2744
2745 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2746 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2747 }
2748
2749 dce_v6_0_pageflip_interrupt_init(adev);
2750
2751 return 0;
2752 }
2753
dce_v6_0_hw_fini(void * handle)2754 static int dce_v6_0_hw_fini(void *handle)
2755 {
2756 int i;
2757 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2758
2759 dce_v6_0_hpd_fini(adev);
2760
2761 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2762 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2763 }
2764
2765 dce_v6_0_pageflip_interrupt_fini(adev);
2766
2767 return 0;
2768 }
2769
dce_v6_0_suspend(void * handle)2770 static int dce_v6_0_suspend(void *handle)
2771 {
2772 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2773
2774 adev->mode_info.bl_level =
2775 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2776
2777 return dce_v6_0_hw_fini(handle);
2778 }
2779
dce_v6_0_resume(void * handle)2780 static int dce_v6_0_resume(void *handle)
2781 {
2782 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2783 int ret;
2784
2785 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2786 adev->mode_info.bl_level);
2787
2788 ret = dce_v6_0_hw_init(handle);
2789
2790 /* turn on the BL */
2791 if (adev->mode_info.bl_encoder) {
2792 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2793 adev->mode_info.bl_encoder);
2794 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2795 bl_level);
2796 }
2797
2798 return ret;
2799 }
2800
dce_v6_0_is_idle(void * handle)2801 static bool dce_v6_0_is_idle(void *handle)
2802 {
2803 return true;
2804 }
2805
dce_v6_0_wait_for_idle(void * handle)2806 static int dce_v6_0_wait_for_idle(void *handle)
2807 {
2808 return 0;
2809 }
2810
dce_v6_0_soft_reset(void * handle)2811 static int dce_v6_0_soft_reset(void *handle)
2812 {
2813 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2814 return 0;
2815 }
2816
dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)2817 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2818 int crtc,
2819 enum amdgpu_interrupt_state state)
2820 {
2821 u32 reg_block, interrupt_mask;
2822
2823 if (crtc >= adev->mode_info.num_crtc) {
2824 DRM_DEBUG("invalid crtc %d\n", crtc);
2825 return;
2826 }
2827
2828 switch (crtc) {
2829 case 0:
2830 reg_block = SI_CRTC0_REGISTER_OFFSET;
2831 break;
2832 case 1:
2833 reg_block = SI_CRTC1_REGISTER_OFFSET;
2834 break;
2835 case 2:
2836 reg_block = SI_CRTC2_REGISTER_OFFSET;
2837 break;
2838 case 3:
2839 reg_block = SI_CRTC3_REGISTER_OFFSET;
2840 break;
2841 case 4:
2842 reg_block = SI_CRTC4_REGISTER_OFFSET;
2843 break;
2844 case 5:
2845 reg_block = SI_CRTC5_REGISTER_OFFSET;
2846 break;
2847 default:
2848 DRM_DEBUG("invalid crtc %d\n", crtc);
2849 return;
2850 }
2851
2852 switch (state) {
2853 case AMDGPU_IRQ_STATE_DISABLE:
2854 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2855 interrupt_mask &= ~VBLANK_INT_MASK;
2856 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2857 break;
2858 case AMDGPU_IRQ_STATE_ENABLE:
2859 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2860 interrupt_mask |= VBLANK_INT_MASK;
2861 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2862 break;
2863 default:
2864 break;
2865 }
2866 }
2867
dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device * adev,int crtc,enum amdgpu_interrupt_state state)2868 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2869 int crtc,
2870 enum amdgpu_interrupt_state state)
2871 {
2872
2873 }
2874
dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)2875 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2876 struct amdgpu_irq_src *src,
2877 unsigned type,
2878 enum amdgpu_interrupt_state state)
2879 {
2880 u32 dc_hpd_int_cntl;
2881
2882 if (type >= adev->mode_info.num_hpd) {
2883 DRM_DEBUG("invalid hdp %d\n", type);
2884 return 0;
2885 }
2886
2887 switch (state) {
2888 case AMDGPU_IRQ_STATE_DISABLE:
2889 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2890 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2891 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2892 break;
2893 case AMDGPU_IRQ_STATE_ENABLE:
2894 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2895 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2896 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2897 break;
2898 default:
2899 break;
2900 }
2901
2902 return 0;
2903 }
2904
dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)2905 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2906 struct amdgpu_irq_src *src,
2907 unsigned type,
2908 enum amdgpu_interrupt_state state)
2909 {
2910 switch (type) {
2911 case AMDGPU_CRTC_IRQ_VBLANK1:
2912 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2913 break;
2914 case AMDGPU_CRTC_IRQ_VBLANK2:
2915 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2916 break;
2917 case AMDGPU_CRTC_IRQ_VBLANK3:
2918 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2919 break;
2920 case AMDGPU_CRTC_IRQ_VBLANK4:
2921 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2922 break;
2923 case AMDGPU_CRTC_IRQ_VBLANK5:
2924 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2925 break;
2926 case AMDGPU_CRTC_IRQ_VBLANK6:
2927 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2928 break;
2929 case AMDGPU_CRTC_IRQ_VLINE1:
2930 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2931 break;
2932 case AMDGPU_CRTC_IRQ_VLINE2:
2933 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2934 break;
2935 case AMDGPU_CRTC_IRQ_VLINE3:
2936 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2937 break;
2938 case AMDGPU_CRTC_IRQ_VLINE4:
2939 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2940 break;
2941 case AMDGPU_CRTC_IRQ_VLINE5:
2942 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2943 break;
2944 case AMDGPU_CRTC_IRQ_VLINE6:
2945 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2946 break;
2947 default:
2948 break;
2949 }
2950 return 0;
2951 }
2952
dce_v6_0_crtc_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2953 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2954 struct amdgpu_irq_src *source,
2955 struct amdgpu_iv_entry *entry)
2956 {
2957 unsigned crtc = entry->src_id - 1;
2958 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2959 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
2960 crtc);
2961
2962 switch (entry->src_data[0]) {
2963 case 0: /* vblank */
2964 if (disp_int & interrupt_status_offsets[crtc].vblank)
2965 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2966 else
2967 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2968
2969 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2970 drm_handle_vblank(adev->ddev, crtc);
2971 }
2972 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2973 break;
2974 case 1: /* vline */
2975 if (disp_int & interrupt_status_offsets[crtc].vline)
2976 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2977 else
2978 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2979
2980 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2981 break;
2982 default:
2983 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
2984 break;
2985 }
2986
2987 return 0;
2988 }
2989
dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)2990 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2991 struct amdgpu_irq_src *src,
2992 unsigned type,
2993 enum amdgpu_interrupt_state state)
2994 {
2995 u32 reg;
2996
2997 if (type >= adev->mode_info.num_crtc) {
2998 DRM_ERROR("invalid pageflip crtc %d\n", type);
2999 return -EINVAL;
3000 }
3001
3002 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3003 if (state == AMDGPU_IRQ_STATE_DISABLE)
3004 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3005 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3006 else
3007 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3008 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3009
3010 return 0;
3011 }
3012
dce_v6_0_pageflip_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3013 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
3014 struct amdgpu_irq_src *source,
3015 struct amdgpu_iv_entry *entry)
3016 {
3017 unsigned long flags;
3018 unsigned crtc_id;
3019 struct amdgpu_crtc *amdgpu_crtc;
3020 struct amdgpu_flip_work *works;
3021
3022 crtc_id = (entry->src_id - 8) >> 1;
3023 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3024
3025 if (crtc_id >= adev->mode_info.num_crtc) {
3026 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3027 return -EINVAL;
3028 }
3029
3030 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3031 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3032 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3033 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3034
3035 /* IRQ could occur when in initial stage */
3036 if (amdgpu_crtc == NULL)
3037 return 0;
3038
3039 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3040 works = amdgpu_crtc->pflip_works;
3041 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3042 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3043 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3044 amdgpu_crtc->pflip_status,
3045 AMDGPU_FLIP_SUBMITTED);
3046 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3047 return 0;
3048 }
3049
3050 /* page flip completed. clean up */
3051 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3052 amdgpu_crtc->pflip_works = NULL;
3053
3054 /* wakeup usersapce */
3055 if (works->event)
3056 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3057
3058 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3059
3060 drm_crtc_vblank_put(&amdgpu_crtc->base);
3061 schedule_work(&works->unpin_work);
3062
3063 return 0;
3064 }
3065
dce_v6_0_hpd_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3066 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
3067 struct amdgpu_irq_src *source,
3068 struct amdgpu_iv_entry *entry)
3069 {
3070 uint32_t disp_int, mask, tmp;
3071 unsigned hpd;
3072
3073 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3074 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3075 return 0;
3076 }
3077
3078 hpd = entry->src_data[0];
3079 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3080 mask = interrupt_status_offsets[hpd].hpd;
3081
3082 if (disp_int & mask) {
3083 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3084 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3085 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3086 schedule_work(&adev->hotplug_work);
3087 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3088 }
3089
3090 return 0;
3091
3092 }
3093
dce_v6_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)3094 static int dce_v6_0_set_clockgating_state(void *handle,
3095 enum amd_clockgating_state state)
3096 {
3097 return 0;
3098 }
3099
dce_v6_0_set_powergating_state(void * handle,enum amd_powergating_state state)3100 static int dce_v6_0_set_powergating_state(void *handle,
3101 enum amd_powergating_state state)
3102 {
3103 return 0;
3104 }
3105
3106 static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
3107 .name = "dce_v6_0",
3108 .early_init = dce_v6_0_early_init,
3109 .late_init = NULL,
3110 .sw_init = dce_v6_0_sw_init,
3111 .sw_fini = dce_v6_0_sw_fini,
3112 .hw_init = dce_v6_0_hw_init,
3113 .hw_fini = dce_v6_0_hw_fini,
3114 .suspend = dce_v6_0_suspend,
3115 .resume = dce_v6_0_resume,
3116 .is_idle = dce_v6_0_is_idle,
3117 .wait_for_idle = dce_v6_0_wait_for_idle,
3118 .soft_reset = dce_v6_0_soft_reset,
3119 .set_clockgating_state = dce_v6_0_set_clockgating_state,
3120 .set_powergating_state = dce_v6_0_set_powergating_state,
3121 };
3122
3123 static void
dce_v6_0_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3124 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
3125 struct drm_display_mode *mode,
3126 struct drm_display_mode *adjusted_mode)
3127 {
3128
3129 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3130 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3131
3132 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3133
3134 /* need to call this here rather than in prepare() since we need some crtc info */
3135 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3136
3137 /* set scaler clears this on some chips */
3138 dce_v6_0_set_interleave(encoder->crtc, mode);
3139
3140 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) {
3141 dce_v6_0_afmt_enable(encoder, true);
3142 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
3143 }
3144 }
3145
dce_v6_0_encoder_prepare(struct drm_encoder * encoder)3146 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
3147 {
3148
3149 struct amdgpu_device *adev = encoder->dev->dev_private;
3150 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3151 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3152
3153 if ((amdgpu_encoder->active_device &
3154 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3155 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3156 ENCODER_OBJECT_ID_NONE)) {
3157 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3158 if (dig) {
3159 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
3160 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3161 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3162 }
3163 }
3164
3165 amdgpu_atombios_scratch_regs_lock(adev, true);
3166
3167 if (connector) {
3168 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3169
3170 /* select the clock/data port if it uses a router */
3171 if (amdgpu_connector->router.cd_valid)
3172 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3173
3174 /* turn eDP panel on for mode set */
3175 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3176 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3177 ATOM_TRANSMITTER_ACTION_POWER_ON);
3178 }
3179
3180 /* this is needed for the pll/ss setup to work correctly in some cases */
3181 amdgpu_atombios_encoder_set_crtc_source(encoder);
3182 /* set up the FMT blocks */
3183 dce_v6_0_program_fmt(encoder);
3184 }
3185
dce_v6_0_encoder_commit(struct drm_encoder * encoder)3186 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
3187 {
3188
3189 struct drm_device *dev = encoder->dev;
3190 struct amdgpu_device *adev = dev->dev_private;
3191
3192 /* need to call this here as we need the crtc set up */
3193 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3194 amdgpu_atombios_scratch_regs_lock(adev, false);
3195 }
3196
dce_v6_0_encoder_disable(struct drm_encoder * encoder)3197 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
3198 {
3199
3200 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3201 struct amdgpu_encoder_atom_dig *dig;
3202 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3203
3204 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3205
3206 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3207 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em))
3208 dce_v6_0_afmt_enable(encoder, false);
3209 dig = amdgpu_encoder->enc_priv;
3210 dig->dig_encoder = -1;
3211 }
3212 amdgpu_encoder->active_device = 0;
3213 }
3214
3215 /* these are handled by the primary encoders */
dce_v6_0_ext_prepare(struct drm_encoder * encoder)3216 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
3217 {
3218
3219 }
3220
dce_v6_0_ext_commit(struct drm_encoder * encoder)3221 static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
3222 {
3223
3224 }
3225
3226 static void
dce_v6_0_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3227 dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
3228 struct drm_display_mode *mode,
3229 struct drm_display_mode *adjusted_mode)
3230 {
3231
3232 }
3233
dce_v6_0_ext_disable(struct drm_encoder * encoder)3234 static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
3235 {
3236
3237 }
3238
3239 static void
dce_v6_0_ext_dpms(struct drm_encoder * encoder,int mode)3240 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
3241 {
3242
3243 }
3244
dce_v6_0_ext_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3245 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
3246 const struct drm_display_mode *mode,
3247 struct drm_display_mode *adjusted_mode)
3248 {
3249 return true;
3250 }
3251
3252 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
3253 .dpms = dce_v6_0_ext_dpms,
3254 .mode_fixup = dce_v6_0_ext_mode_fixup,
3255 .prepare = dce_v6_0_ext_prepare,
3256 .mode_set = dce_v6_0_ext_mode_set,
3257 .commit = dce_v6_0_ext_commit,
3258 .disable = dce_v6_0_ext_disable,
3259 /* no detect for TMDS/LVDS yet */
3260 };
3261
3262 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
3263 .dpms = amdgpu_atombios_encoder_dpms,
3264 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3265 .prepare = dce_v6_0_encoder_prepare,
3266 .mode_set = dce_v6_0_encoder_mode_set,
3267 .commit = dce_v6_0_encoder_commit,
3268 .disable = dce_v6_0_encoder_disable,
3269 .detect = amdgpu_atombios_encoder_dig_detect,
3270 };
3271
3272 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
3273 .dpms = amdgpu_atombios_encoder_dpms,
3274 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3275 .prepare = dce_v6_0_encoder_prepare,
3276 .mode_set = dce_v6_0_encoder_mode_set,
3277 .commit = dce_v6_0_encoder_commit,
3278 .detect = amdgpu_atombios_encoder_dac_detect,
3279 };
3280
dce_v6_0_encoder_destroy(struct drm_encoder * encoder)3281 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
3282 {
3283 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3284 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3285 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3286 kfree(amdgpu_encoder->enc_priv);
3287 drm_encoder_cleanup(encoder);
3288 kfree(amdgpu_encoder);
3289 }
3290
3291 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
3292 .destroy = dce_v6_0_encoder_destroy,
3293 };
3294
dce_v6_0_encoder_add(struct amdgpu_device * adev,uint32_t encoder_enum,uint32_t supported_device,u16 caps)3295 static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
3296 uint32_t encoder_enum,
3297 uint32_t supported_device,
3298 u16 caps)
3299 {
3300 struct drm_device *dev = adev->ddev;
3301 struct drm_encoder *encoder;
3302 struct amdgpu_encoder *amdgpu_encoder;
3303
3304 /* see if we already added it */
3305 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3306 amdgpu_encoder = to_amdgpu_encoder(encoder);
3307 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3308 amdgpu_encoder->devices |= supported_device;
3309 return;
3310 }
3311
3312 }
3313
3314 /* add a new one */
3315 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3316 if (!amdgpu_encoder)
3317 return;
3318
3319 encoder = &amdgpu_encoder->base;
3320 switch (adev->mode_info.num_crtc) {
3321 case 1:
3322 encoder->possible_crtcs = 0x1;
3323 break;
3324 case 2:
3325 default:
3326 encoder->possible_crtcs = 0x3;
3327 break;
3328 case 4:
3329 encoder->possible_crtcs = 0xf;
3330 break;
3331 case 6:
3332 encoder->possible_crtcs = 0x3f;
3333 break;
3334 }
3335
3336 amdgpu_encoder->enc_priv = NULL;
3337 amdgpu_encoder->encoder_enum = encoder_enum;
3338 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3339 amdgpu_encoder->devices = supported_device;
3340 amdgpu_encoder->rmx_type = RMX_OFF;
3341 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3342 amdgpu_encoder->is_ext_encoder = false;
3343 amdgpu_encoder->caps = caps;
3344
3345 switch (amdgpu_encoder->encoder_id) {
3346 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3347 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3348 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3349 DRM_MODE_ENCODER_DAC, NULL);
3350 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
3351 break;
3352 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3353 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3355 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3356 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3357 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3358 amdgpu_encoder->rmx_type = RMX_FULL;
3359 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3360 DRM_MODE_ENCODER_LVDS, NULL);
3361 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3362 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3363 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3364 DRM_MODE_ENCODER_DAC, NULL);
3365 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3366 } else {
3367 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3368 DRM_MODE_ENCODER_TMDS, NULL);
3369 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3370 }
3371 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3372 break;
3373 case ENCODER_OBJECT_ID_SI170B:
3374 case ENCODER_OBJECT_ID_CH7303:
3375 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3376 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3377 case ENCODER_OBJECT_ID_TITFP513:
3378 case ENCODER_OBJECT_ID_VT1623:
3379 case ENCODER_OBJECT_ID_HDMI_SI1930:
3380 case ENCODER_OBJECT_ID_TRAVIS:
3381 case ENCODER_OBJECT_ID_NUTMEG:
3382 /* these are handled by the primary encoders */
3383 amdgpu_encoder->is_ext_encoder = true;
3384 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3385 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3386 DRM_MODE_ENCODER_LVDS, NULL);
3387 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3388 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3389 DRM_MODE_ENCODER_DAC, NULL);
3390 else
3391 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3392 DRM_MODE_ENCODER_TMDS, NULL);
3393 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3394 break;
3395 }
3396 }
3397
3398 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3399 .bandwidth_update = &dce_v6_0_bandwidth_update,
3400 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3401 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3402 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3403 .hpd_sense = &dce_v6_0_hpd_sense,
3404 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3405 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3406 .page_flip = &dce_v6_0_page_flip,
3407 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3408 .add_encoder = &dce_v6_0_encoder_add,
3409 .add_connector = &amdgpu_connector_add,
3410 };
3411
dce_v6_0_set_display_funcs(struct amdgpu_device * adev)3412 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3413 {
3414 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3415 }
3416
3417 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3418 .set = dce_v6_0_set_crtc_interrupt_state,
3419 .process = dce_v6_0_crtc_irq,
3420 };
3421
3422 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3423 .set = dce_v6_0_set_pageflip_interrupt_state,
3424 .process = dce_v6_0_pageflip_irq,
3425 };
3426
3427 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3428 .set = dce_v6_0_set_hpd_interrupt_state,
3429 .process = dce_v6_0_hpd_irq,
3430 };
3431
dce_v6_0_set_irq_funcs(struct amdgpu_device * adev)3432 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3433 {
3434 if (adev->mode_info.num_crtc > 0)
3435 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3436 else
3437 adev->crtc_irq.num_types = 0;
3438 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3439
3440 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3441 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3442
3443 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3444 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3445 }
3446
3447 const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3448 {
3449 .type = AMD_IP_BLOCK_TYPE_DCE,
3450 .major = 6,
3451 .minor = 0,
3452 .rev = 0,
3453 .funcs = &dce_v6_0_ip_funcs,
3454 };
3455
3456 const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3457 {
3458 .type = AMD_IP_BLOCK_TYPE_DCE,
3459 .major = 6,
3460 .minor = 4,
3461 .rev = 0,
3462 .funcs = &dce_v6_0_ip_funcs,
3463 };
3464