Home
last modified time | relevance | path

Searched refs:cntl (Results 1 – 25 of 47) sorted by relevance

12

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_link_encoder.c131 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
136 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
835 struct bp_transmitter_control cntl = { 0 }; in dce110_link_encoder_hw_init() local
838 cntl.action = TRANSMITTER_CONTROL_INIT; in dce110_link_encoder_hw_init()
839 cntl.engine_id = ENGINE_ID_UNKNOWN; in dce110_link_encoder_hw_init()
840 cntl.transmitter = enc110->base.transmitter; in dce110_link_encoder_hw_init()
841 cntl.connector_obj_id = enc110->base.connector; in dce110_link_encoder_hw_init()
842 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_link_encoder_hw_init()
843 cntl.coherent = false; in dce110_link_encoder_hw_init()
844 cntl.hpd_sel = enc110->base.hpd_source; in dce110_link_encoder_hw_init()
[all …]
H A Damdgpu_dce_stream_encoder.c564 struct bp_encoder_control cntl = {0}; in dce110_stream_encoder_hdmi_set_stream_attribute() local
566 cntl.action = ENCODER_CONTROL_SETUP; in dce110_stream_encoder_hdmi_set_stream_attribute()
567 cntl.engine_id = enc110->base.id; in dce110_stream_encoder_hdmi_set_stream_attribute()
568 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; in dce110_stream_encoder_hdmi_set_stream_attribute()
569 cntl.enable_dp_audio = enable_audio; in dce110_stream_encoder_hdmi_set_stream_attribute()
570 cntl.pixel_clock = actual_pix_clk_khz; in dce110_stream_encoder_hdmi_set_stream_attribute()
571 cntl.lanes_number = LANE_COUNT_FOUR; in dce110_stream_encoder_hdmi_set_stream_attribute()
574 enc110->base.bp, &cntl) != BP_RESULT_OK) in dce110_stream_encoder_hdmi_set_stream_attribute()
677 struct bp_encoder_control cntl = {0}; in dce110_stream_encoder_dvi_set_stream_attribute() local
679 cntl.action = ENCODER_CONTROL_SETUP; in dce110_stream_encoder_dvi_set_stream_attribute()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
H A Damdgpu_command_table.c111 struct bp_encoder_control *cntl);
115 struct bp_encoder_control *cntl);
119 struct bp_encoder_control *cntl);
148 struct bp_encoder_control *cntl);
151 struct bp_encoder_control *cntl);
154 struct bp_encoder_control *cntl);
175 struct bp_encoder_control *cntl) in encoder_control_dig_v1() argument
180 if (cntl != NULL) in encoder_control_dig_v1()
181 switch (cntl->engine_id) { in encoder_control_dig_v1()
185 cmd_tbl->encoder_control_dig1(bp, cntl); in encoder_control_dig_v1()
[all …]
H A Damdgpu_command_table2.c95 struct bp_encoder_control *cntl);
99 struct bp_encoder_control *cntl);
134 struct bp_encoder_control *cntl) in encoder_control_digx_v1_5() argument
139 params.digid = (uint8_t)(cntl->engine_id); in encoder_control_digx_v1_5()
140 params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action); in encoder_control_digx_v1_5()
142 params.pclk_10khz = cntl->pixel_clock / 10; in encoder_control_digx_v1_5()
145 cntl->signal, in encoder_control_digx_v1_5()
146 cntl->enable_dp_audio)); in encoder_control_digx_v1_5()
147 params.lanenum = (uint8_t)(cntl->lanes_number); in encoder_control_digx_v1_5()
149 switch (cntl->color_depth) { in encoder_control_digx_v1_5()
[all …]
H A Dcommand_table.h89 struct bp_external_encoder_control *cntl);
H A Dcommand_table2.h89 struct bp_external_encoder_control *cntl);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_link_encoder.c103 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
108 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
828 struct bp_transmitter_control cntl = { 0 }; in dcn10_link_encoder_hw_init() local
831 cntl.action = TRANSMITTER_CONTROL_INIT; in dcn10_link_encoder_hw_init()
832 cntl.engine_id = ENGINE_ID_UNKNOWN; in dcn10_link_encoder_hw_init()
833 cntl.transmitter = enc10->base.transmitter; in dcn10_link_encoder_hw_init()
834 cntl.connector_obj_id = enc10->base.connector; in dcn10_link_encoder_hw_init()
835 cntl.lanes_number = LANE_COUNT_FOUR; in dcn10_link_encoder_hw_init()
836 cntl.coherent = false; in dcn10_link_encoder_hw_init()
837 cntl.hpd_sel = enc10->base.hpd_source; in dcn10_link_encoder_hw_init()
[all …]
H A Damdgpu_dcn10_stream_encoder.c502 struct bp_encoder_control cntl = {0}; in enc1_stream_encoder_hdmi_set_stream_attribute() local
504 cntl.action = ENCODER_CONTROL_SETUP; in enc1_stream_encoder_hdmi_set_stream_attribute()
505 cntl.engine_id = enc1->base.id; in enc1_stream_encoder_hdmi_set_stream_attribute()
506 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; in enc1_stream_encoder_hdmi_set_stream_attribute()
507 cntl.enable_dp_audio = enable_audio; in enc1_stream_encoder_hdmi_set_stream_attribute()
508 cntl.pixel_clock = actual_pix_clk_khz; in enc1_stream_encoder_hdmi_set_stream_attribute()
509 cntl.lanes_number = LANE_COUNT_FOUR; in enc1_stream_encoder_hdmi_set_stream_attribute()
512 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc1_stream_encoder_hdmi_set_stream_attribute()
608 struct bp_encoder_control cntl = {0}; in enc1_stream_encoder_dvi_set_stream_attribute() local
610 cntl.action = ENCODER_CONTROL_SETUP; in enc1_stream_encoder_dvi_set_stream_attribute()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
H A Dkfd_dbgdev.c238 union TCP_WATCH_CNTL_BITS *cntl, in dbgdev_address_watch_set_registers() argument
246 cntl->u32All = 0; in dbgdev_address_watch_set_registers()
249 cntl->bitfields.mask = in dbgdev_address_watch_set_registers()
253 cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; in dbgdev_address_watch_set_registers()
262 cntl->bitfields.mode = adw_info->watch_mode[index]; in dbgdev_address_watch_set_registers()
263 cntl->bitfields.vmid = (uint32_t) vmid; in dbgdev_address_watch_set_registers()
265 cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT; in dbgdev_address_watch_set_registers()
267 pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask); in dbgdev_address_watch_set_registers()
279 union TCP_WATCH_CNTL_BITS cntl; in dbgdev_address_watch_nodiq() local
293 cntl.u32All = 0; in dbgdev_address_watch_nodiq()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
H A Damdgpu_dce100_hw_sequencer.c84 enum bp_pipe_control_action cntl; in dce100_enable_display_power_gating() local
88 cntl = ASIC_PIPE_INIT; in dce100_enable_display_power_gating()
90 cntl = ASIC_PIPE_ENABLE; in dce100_enable_display_power_gating()
92 cntl = ASIC_PIPE_DISABLE; in dce100_enable_display_power_gating()
97 dcb, controller_id + 1, cntl); in dce100_enable_display_power_gating()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
H A Damdgpu_dce112_hw_sequencer.c125 enum bp_pipe_control_action cntl; in dce112_enable_display_power_gating() local
132 cntl = ASIC_PIPE_INIT; in dce112_enable_display_power_gating()
134 cntl = ASIC_PIPE_ENABLE; in dce112_enable_display_power_gating()
136 cntl = ASIC_PIPE_DISABLE; in dce112_enable_display_power_gating()
141 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
/netbsd-src/sys/arch/arm/amlogic/
H A Dmeson8b_clkc.c123 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL); in meson8b_clkc_pll_sys_set_rate() local
150 cntl &= ~HHI_SYS_PLL_CNTL_MUL; in meson8b_clkc_pll_sys_set_rate()
151 cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL); in meson8b_clkc_pll_sys_set_rate()
152 cntl &= ~HHI_SYS_PLL_CNTL_DIV; in meson8b_clkc_pll_sys_set_rate()
153 cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV); in meson8b_clkc_pll_sys_set_rate()
154 cntl &= ~HHI_SYS_PLL_CNTL_OD; in meson8b_clkc_pll_sys_set_rate()
155 cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD); in meson8b_clkc_pll_sys_set_rate()
165 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl); in meson8b_clkc_pll_sys_set_rate()
H A Dmeson_sdhc.c597 uint32_t cntl; in meson_sdhc_bus_width() local
599 cntl = SDHC_READ(sc, SD_CNTL_REG); in meson_sdhc_bus_width()
600 cntl &= ~SD_CNTL_DAT_TYPE; in meson_sdhc_bus_width()
603 cntl |= __SHIFTIN(0, SD_CNTL_DAT_TYPE); in meson_sdhc_bus_width()
606 cntl |= __SHIFTIN(1, SD_CNTL_DAT_TYPE); in meson_sdhc_bus_width()
609 cntl |= __SHIFTIN(2, SD_CNTL_DAT_TYPE); in meson_sdhc_bus_width()
615 SDHC_WRITE(sc, SD_CNTL_REG, cntl); in meson_sdhc_bus_width()
630 uint32_t cmdval = 0, cntl, srst, pdma, ictl; in meson_sdhc_exec_command() local
664 cntl = SDHC_READ(sc, SD_CNTL_REG); in meson_sdhc_exec_command()
665 cntl &= ~SD_CNTL_PACK_LEN; in meson_sdhc_exec_command()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_hw_sequencer.c164 enum bp_pipe_control_action cntl; in dce120_enable_display_power_gating()
171 cntl = ASIC_PIPE_INIT; in dce120_enable_display_power_gating()
173 cntl = ASIC_PIPE_ENABLE; in dce120_enable_display_power_gating()
175 cntl = ASIC_PIPE_DISABLE; in dce120_enable_display_power_gating()
180 dcb, controller_id + 1, cntl); in dce120_enable_display_power_gating()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c589 union TCP_WATCH_CNTL_BITS cntl; in kgd_address_watch_disable() local
592 cntl.u32All = 0; in kgd_address_watch_disable()
594 cntl.bitfields.valid = 0; in kgd_address_watch_disable()
595 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; in kgd_address_watch_disable()
596 cntl.bitfields.atc = 1; in kgd_address_watch_disable()
601 ADDRESS_WATCH_REG_CNTL], cntl.u32All); in kgd_address_watch_disable()
613 union TCP_WATCH_CNTL_BITS cntl; in kgd_address_watch_execute() local
615 cntl.u32All = cntl_val; in kgd_address_watch_execute()
618 cntl.bitfields.valid = 0; in kgd_address_watch_execute()
620 ADDRESS_WATCH_REG_CNTL], cntl.u32All); in kgd_address_watch_execute()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_hw_sequencer.c206 enum bp_pipe_control_action cntl; in dce110_enable_display_power_gating() local
214 cntl = ASIC_PIPE_INIT; in dce110_enable_display_power_gating()
216 cntl = ASIC_PIPE_ENABLE; in dce110_enable_display_power_gating()
218 cntl = ASIC_PIPE_DISABLE; in dce110_enable_display_power_gating()
226 dcb, controller_id + 1, cntl); in dce110_enable_display_power_gating()
727 struct bp_transmitter_control *cntl) in link_transmitter_control() argument
731 result = bios->funcs->transmitter_control(bios, cntl); in link_transmitter_control()
814 struct bp_transmitter_control cntl = { 0 }; in dce110_edp_power_control() local
858 cntl.action = power_up ? in dce110_edp_power_control()
861 cntl.transmitter = link->link_enc->transmitter; in dce110_edp_power_control()
[all …]
/netbsd-src/libexec/rlogind/
H A Drlogind.c455 char cntl; in protocol() local
492 cc = read(p, &cntl, 1); in protocol()
493 if (cc == 1 && pkcontrol(cntl)) { in protocol()
494 cntl |= oobdata[0]; in protocol()
495 send(f, &cntl, 1, MSG_OOB); in protocol()
496 if (cntl & TIOCPKT_FLUSHWRITE) in protocol()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_bios_types.h99 struct bp_encoder_control *cntl);
102 struct bp_transmitter_control *cntl);
/netbsd-src/sys/dev/ic/
H A Dadvlib.c402 eep_config->cntl = 0xBFFF; in AscInitFromEEP()
428 sc->dvc_cntl = eep_config->cntl; in AscInitFromEEP()
1425 printf("cntl = 0x%x\n", eep_config->cntl); in AscPrintEEPConfig()
1560 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) { in AscIsrQDone()
1609 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) { in AscIsrQDone()
1821 scsiq->cntl = LO_BYTE(_val); in _AscCopyLramScsiDoneQ()
2284 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT); in AscExeScsiQueue()
2291 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) { in AscExeScsiQueue()
2304 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE); in AscExeScsiQueue()
2312 if (scsiq->q1.cntl & ASC_QC_SG_HEAD) { in AscExeScsiQueue()
[all …]
H A Dadvlib.h441 u_int8_t cntl; /* see below cntl values */ member
551 u_int8_t cntl; member
633 u_int8_t cntl; /* see below cntl values */ member
1005 u_int16_t cntl; member
/netbsd-src/sys/arch/mips/adm5120/dev/
H A Dif_admswvar.h189 __desc->cntl = 0; \
206 __desc->cntl = 0; \
/netbsd-src/sys/dev/ieee1394/
H A Dfwohcireg.h193 fwohcireg_t cntl; member
220 fwohcireg_t cntl; member
/netbsd-src/sys/arch/hppa/gsc/
H A Dharmony.c214 uint32_t cntl; in harmony_attach() local
231 cntl = READ_REG(sc, HARMONY_ID); in harmony_attach()
232 switch ((cntl & ID_REV_MASK)) { in harmony_attach()
239 (cntl & ID_REV_MASK) >> ID_REV_SHIFT); in harmony_attach()
313 cntl = READ_REG(sc, HARMONY_CNTL); in harmony_attach()
314 rev = (cntl & CNTL_CODEC_REV_MASK) >> CNTL_CODEC_REV_SHIFT; in harmony_attach()
/netbsd-src/sys/dev/dec/
H A Dif_le_dec.c108 #define LERDWR(cntl, src, dst) { (dst) = (src); tc_mb(); } argument
/netbsd-src/sys/arch/x86/pci/
H A Dichlpcib.c789 uint8_t cntl; in speedstep_sysctl_helper()
799 cntl = SS_READ(sc, PMC_PM_CTRL); in speedstep_sysctl_helper()
800 SS_WRITE(sc, PMC_PM_CTRL, cntl | PMC_PM_SS_CNTL_ARB_DIS); in speedstep_sysctl_helper()
802 SS_WRITE(sc, PMC_PM_CTRL, cntl); in speedstep_sysctl_helper()
788 uint8_t cntl; speedstep_sysctl_helper() local

12