| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_jpeg_v1_0.c | 185 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_start()
187 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_start()
189 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
190 amdgpu_ring_write(ring, 0x80010000); in jpeg_v1_0_decode_ring_insert_start()
204 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_end()
206 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_end()
208 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
209 amdgpu_ring_write(ring, 0x00010000); in jpeg_v1_0_decode_ring_insert_end()
227 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_emit_fence()
229 amdgpu_ring_write(ring, seq); in jpeg_v1_0_decode_ring_emit_fence()
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| H A D | amdgpu_jpeg_v2_0.c | 467 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
469 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
471 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
473 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
485 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
487 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
489 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
491 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
507 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
509 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
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| H A D | amdgpu_uvd_v6_0.c | 188 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
493 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
494 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
497 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
498 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
502 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
505 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
506 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
508 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
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| H A D | amdgpu_uvd_v5_0.c | 178 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
182 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
186 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
187 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
191 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
194 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
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| H A D | amdgpu_uvd_v4_2.c | 181 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
182 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
185 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
186 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
189 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
190 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
194 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
196 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
197 amdgpu_ring_write(ring, 3); in uvd_v4_2_hw_init()
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| H A D | amdgpu_vcn_v2_0.c | 1302 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1303 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1304 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1305 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1319 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1320 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1338 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1339 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1357 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1358 amdgpu_ring_write(ring, seq); in vcn_v2_0_dec_ring_emit_fence()
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| H A D | amdgpu_sdma_v2_4.c | 242 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
245 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
266 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
271 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
272 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
273 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
293 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
296 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
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| H A D | amdgpu_uvd_v7_0.c | 198 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
559 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
560 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
564 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
565 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
569 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
570 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
575 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
577 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
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| H A D | amdgpu_si_dma.c | 78 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
79 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
80 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
81 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
101 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
102 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
103 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
104 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
108 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
109 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
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| H A D | amdgpu_vcn_v1_0.c | 1429 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1431 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1432 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1434 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1448 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1450 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1468 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1470 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1471 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1473 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
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| H A D | amdgpu_cik_sdma.c | 213 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
216 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
238 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
239 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
241 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
263 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
264 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
265 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
266 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
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| H A D | amdgpu_sdma_v3_0.c | 416 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
419 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
445 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
446 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
447 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
467 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
470 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
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| H A D | amdgpu_sdma_v5_0.c | 243 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
244 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
245 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
246 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
248 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_0_ring_init_cond_exec()
370 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
373 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_0_ring_emit_ib()
405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
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| H A D | amdgpu_gfx_v7_0.c | 2112 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2113 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v7_0_ring_test_ring()
2114 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2159 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2160 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2163 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2164 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2165 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2166 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2167 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
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| H A D | amdgpu_gfx_v8_0.c | 861 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
862 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v8_0_ring_test_ring()
863 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4190 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4191 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4193 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4194 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4195 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4200 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4203 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
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| H A D | amdgpu_gfx_v6_0.c | 1812 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1813 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_test_ring()
1814 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1834 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1835 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1846 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1847 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1848 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1849 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in gfx_v6_0_ring_emit_fence()
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| H A D | amdgpu_gfx_v10_0.c | 270 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
271 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx10_kiq_set_resources()
273 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
274 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
275 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx10_kiq_set_resources()
276 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx10_kiq_set_resources()
277 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx10_kiq_set_resources()
278 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx10_kiq_set_resources()
289 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx10_kiq_map_queues()
291 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx10_kiq_map_queues()
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| H A D | amdgpu_gfx_v9_0.c | 755 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
756 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
760 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
762 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
764 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v9_0_kiq_set_resources()
765 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v9_0_kiq_set_resources()
766 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
767 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_0_kiq_set_resources()
778 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
780 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v9_0_kiq_map_queues()
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| H A D | amdgpu_vce_v3_0.c | 846 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v3_0_ring_emit_ib()
847 amdgpu_ring_write(ring, vmid); in vce_v3_0_ring_emit_ib()
848 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
849 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
850 amdgpu_ring_write(ring, ib->length_dw); in vce_v3_0_ring_emit_ib()
856 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); in vce_v3_0_emit_vm_flush()
857 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
858 amdgpu_ring_write(ring, pd_addr >> 12); in vce_v3_0_emit_vm_flush()
860 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); in vce_v3_0_emit_vm_flush()
861 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
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| H A D | amdgpu_vce_v4_0.c | 963 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v4_0_ring_emit_ib()
964 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
965 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
966 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
967 amdgpu_ring_write(ring, ib->length_dw); in vce_v4_0_ring_emit_ib()
975 amdgpu_ring_write(ring, VCE_CMD_FENCE); in vce_v4_0_ring_emit_fence()
976 amdgpu_ring_write(ring, addr); in vce_v4_0_ring_emit_fence()
977 amdgpu_ring_write(ring, upper_32_bits(addr)); in vce_v4_0_ring_emit_fence()
978 amdgpu_ring_write(ring, seq); in vce_v4_0_ring_emit_fence()
979 amdgpu_ring_write(ring, VCE_CMD_TRAP); in vce_v4_0_ring_emit_fence()
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| H A D | amdgpu_sdma_v4_0.c | 786 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_0_ring_insert_nop()
789 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_0_ring_insert_nop()
810 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_0_ring_emit_ib()
813 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
814 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
815 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
816 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
817 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
827 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_0_wait_reg_mem()
833 amdgpu_ring_write(ring, addr0); in sdma_v4_0_wait_reg_mem()
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| H A D | amdgpu_vce.c | 1055 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1056 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1057 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1058 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1073 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1074 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1075 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1076 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1077 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1078 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
360 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
370 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
372 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
373 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
374 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
375 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 371 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
372 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
382 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
384 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_hiq_mqd_load()
385 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_hiq_mqd_load()
386 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_hiq_mqd_load()
387 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_hiq_mqd_load()
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| H A D | amdgpu_jpeg.c | 125 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0)); in amdgpu_jpeg_dec_ring_test_ring()
126 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_jpeg_dec_ring_test_ring()
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