1 /* $NetBSD: amdgpu_vcn_v2_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vcn_v2_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
28
29 #include <linux/firmware.h>
30
31 #include "amdgpu.h"
32 #include "amdgpu_vcn.h"
33 #include "soc15.h"
34 #include "soc15d.h"
35 #include "amdgpu_pm.h"
36 #include "amdgpu_psp.h"
37
38 #include "vcn/vcn_2_0_0_offset.h"
39 #include "vcn/vcn_2_0_0_sh_mask.h"
40 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
41
42 #include <linux/nbsd-namespace.h>
43
44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
51
52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
56
57 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
58 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
59 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
60 static int vcn_v2_0_set_powergating_state(void *handle,
61 enum amd_powergating_state state);
62 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
63 int inst_idx, struct dpg_pause_state *new_state);
64
65 /**
66 * vcn_v2_0_early_init - set function pointers
67 *
68 * @handle: amdgpu_device pointer
69 *
70 * Set ring and irq function pointers
71 */
vcn_v2_0_early_init(void * handle)72 static int vcn_v2_0_early_init(void *handle)
73 {
74 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
75
76 adev->vcn.num_vcn_inst = 1;
77 adev->vcn.num_enc_rings = 2;
78
79 vcn_v2_0_set_dec_ring_funcs(adev);
80 vcn_v2_0_set_enc_ring_funcs(adev);
81 vcn_v2_0_set_irq_funcs(adev);
82
83 return 0;
84 }
85
86 /**
87 * vcn_v2_0_sw_init - sw init for VCN block
88 *
89 * @handle: amdgpu_device pointer
90 *
91 * Load firmware and sw initialization
92 */
vcn_v2_0_sw_init(void * handle)93 static int vcn_v2_0_sw_init(void *handle)
94 {
95 struct amdgpu_ring *ring;
96 int i, r;
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
98
99 /* VCN DEC TRAP */
100 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
101 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
102 &adev->vcn.inst->irq);
103 if (r)
104 return r;
105
106 /* VCN ENC TRAP */
107 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
108 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
109 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
110 &adev->vcn.inst->irq);
111 if (r)
112 return r;
113 }
114
115 r = amdgpu_vcn_sw_init(adev);
116 if (r)
117 return r;
118
119 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
120 const struct common_firmware_header *hdr;
121 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
122 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
123 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
124 adev->firmware.fw_size +=
125 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
126 DRM_INFO("PSP loading VCN firmware\n");
127 }
128
129 r = amdgpu_vcn_resume(adev);
130 if (r)
131 return r;
132
133 ring = &adev->vcn.inst->ring_dec;
134
135 ring->use_doorbell = true;
136 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
137
138 snprintf(ring->name, sizeof(ring->name), "vcn_dec");
139 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
140 if (r)
141 return r;
142
143 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
144 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
145 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
146 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
147 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
148 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
149
150 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
151 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
152 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
153 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
154 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
155 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
156 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
157 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
158 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
159 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
160
161 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
162 ring = &adev->vcn.inst->ring_enc[i];
163 ring->use_doorbell = true;
164 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
165 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i);
166 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
167 if (r)
168 return r;
169 }
170
171 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
172
173 return 0;
174 }
175
176 /**
177 * vcn_v2_0_sw_fini - sw fini for VCN block
178 *
179 * @handle: amdgpu_device pointer
180 *
181 * VCN suspend and free up sw allocation
182 */
vcn_v2_0_sw_fini(void * handle)183 static int vcn_v2_0_sw_fini(void *handle)
184 {
185 int r;
186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
187
188 r = amdgpu_vcn_suspend(adev);
189 if (r)
190 return r;
191
192 r = amdgpu_vcn_sw_fini(adev);
193
194 return r;
195 }
196
197 /**
198 * vcn_v2_0_hw_init - start and test VCN block
199 *
200 * @handle: amdgpu_device pointer
201 *
202 * Initialize the hardware, boot up the VCPU and do some testing
203 */
vcn_v2_0_hw_init(void * handle)204 static int vcn_v2_0_hw_init(void *handle)
205 {
206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
207 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
208 int i, r;
209
210 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
211 ring->doorbell_index, 0);
212
213 r = amdgpu_ring_test_helper(ring);
214 if (r)
215 goto done;
216
217 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
218 ring = &adev->vcn.inst->ring_enc[i];
219 r = amdgpu_ring_test_helper(ring);
220 if (r)
221 goto done;
222 }
223
224 done:
225 if (!r)
226 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
227 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
228
229 return r;
230 }
231
232 /**
233 * vcn_v2_0_hw_fini - stop the hardware block
234 *
235 * @handle: amdgpu_device pointer
236 *
237 * Stop the VCN block, mark ring as not ready any more
238 */
vcn_v2_0_hw_fini(void * handle)239 static int vcn_v2_0_hw_fini(void *handle)
240 {
241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
242 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
243 int i;
244
245 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
246 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
247 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
248 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
249
250 ring->sched.ready = false;
251
252 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
253 ring = &adev->vcn.inst->ring_enc[i];
254 ring->sched.ready = false;
255 }
256
257 return 0;
258 }
259
260 /**
261 * vcn_v2_0_suspend - suspend VCN block
262 *
263 * @handle: amdgpu_device pointer
264 *
265 * HW fini and suspend VCN block
266 */
vcn_v2_0_suspend(void * handle)267 static int vcn_v2_0_suspend(void *handle)
268 {
269 int r;
270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
271
272 r = vcn_v2_0_hw_fini(adev);
273 if (r)
274 return r;
275
276 r = amdgpu_vcn_suspend(adev);
277
278 return r;
279 }
280
281 /**
282 * vcn_v2_0_resume - resume VCN block
283 *
284 * @handle: amdgpu_device pointer
285 *
286 * Resume firmware and hw init VCN block
287 */
vcn_v2_0_resume(void * handle)288 static int vcn_v2_0_resume(void *handle)
289 {
290 int r;
291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
292
293 r = amdgpu_vcn_resume(adev);
294 if (r)
295 return r;
296
297 r = vcn_v2_0_hw_init(adev);
298
299 return r;
300 }
301
302 /**
303 * vcn_v2_0_mc_resume - memory controller programming
304 *
305 * @adev: amdgpu_device pointer
306 *
307 * Let the VCN memory controller know it's offsets
308 */
vcn_v2_0_mc_resume(struct amdgpu_device * adev)309 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
310 {
311 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
312 uint32_t offset;
313
314 /* cache window 0: fw */
315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
317 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
319 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
321 offset = 0;
322 } else {
323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
324 lower_32_bits(adev->vcn.inst->gpu_addr));
325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
326 upper_32_bits(adev->vcn.inst->gpu_addr));
327 offset = size;
328 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
329 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
330 }
331
332 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
333
334 /* cache window 1: stack */
335 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
336 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
337 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
338 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
339 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
340 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
341
342 /* cache window 2: context */
343 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
344 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
346 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
347 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
348 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
349
350 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
351 }
352
vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device * adev,bool indirect)353 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
354 {
355 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
356 uint32_t offset;
357
358 /* cache window 0: fw */
359 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
360 if (!indirect) {
361 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
362 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
363 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
364 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
365 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
366 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
367 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
368 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
369 } else {
370 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
371 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
372 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
373 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
374 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
375 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
376 }
377 offset = 0;
378 } else {
379 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
380 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
381 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
382 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
383 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
384 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
385 offset = size;
386 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
387 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
388 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
389 }
390
391 if (!indirect)
392 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
393 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
394 else
395 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
396 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
397
398 /* cache window 1: stack */
399 if (!indirect) {
400 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
401 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
402 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
403 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
404 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
405 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
406 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
407 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
408 } else {
409 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
410 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
411 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
412 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
413 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
414 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
415 }
416 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
417 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
418
419 /* cache window 2: context */
420 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
421 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
422 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
423 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
424 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
425 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
426 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
427 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
428 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
429 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
430
431 /* non-cache window */
432 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
433 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
434 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
435 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
436 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
437 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
438 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
439 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
440
441 /* VCN global tiling registers */
442 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
443 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
444 }
445
446 /**
447 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
448 *
449 * @adev: amdgpu_device pointer
450 * @sw: enable SW clock gating
451 *
452 * Disable clock gating for VCN block
453 */
vcn_v2_0_disable_clock_gating(struct amdgpu_device * adev)454 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
455 {
456 uint32_t data;
457
458 /* UVD disable CGC */
459 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
460 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
461 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
462 else
463 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
464 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
465 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
466 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
467
468 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
469 data &= ~(UVD_CGC_GATE__SYS_MASK
470 | UVD_CGC_GATE__UDEC_MASK
471 | UVD_CGC_GATE__MPEG2_MASK
472 | UVD_CGC_GATE__REGS_MASK
473 | UVD_CGC_GATE__RBC_MASK
474 | UVD_CGC_GATE__LMI_MC_MASK
475 | UVD_CGC_GATE__LMI_UMC_MASK
476 | UVD_CGC_GATE__IDCT_MASK
477 | UVD_CGC_GATE__MPRD_MASK
478 | UVD_CGC_GATE__MPC_MASK
479 | UVD_CGC_GATE__LBSI_MASK
480 | UVD_CGC_GATE__LRBBM_MASK
481 | UVD_CGC_GATE__UDEC_RE_MASK
482 | UVD_CGC_GATE__UDEC_CM_MASK
483 | UVD_CGC_GATE__UDEC_IT_MASK
484 | UVD_CGC_GATE__UDEC_DB_MASK
485 | UVD_CGC_GATE__UDEC_MP_MASK
486 | UVD_CGC_GATE__WCB_MASK
487 | UVD_CGC_GATE__VCPU_MASK
488 | UVD_CGC_GATE__SCPU_MASK);
489 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
490
491 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
492 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
493 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
494 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
495 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
496 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
497 | UVD_CGC_CTRL__SYS_MODE_MASK
498 | UVD_CGC_CTRL__UDEC_MODE_MASK
499 | UVD_CGC_CTRL__MPEG2_MODE_MASK
500 | UVD_CGC_CTRL__REGS_MODE_MASK
501 | UVD_CGC_CTRL__RBC_MODE_MASK
502 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
503 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
504 | UVD_CGC_CTRL__IDCT_MODE_MASK
505 | UVD_CGC_CTRL__MPRD_MODE_MASK
506 | UVD_CGC_CTRL__MPC_MODE_MASK
507 | UVD_CGC_CTRL__LBSI_MODE_MASK
508 | UVD_CGC_CTRL__LRBBM_MODE_MASK
509 | UVD_CGC_CTRL__WCB_MODE_MASK
510 | UVD_CGC_CTRL__VCPU_MODE_MASK
511 | UVD_CGC_CTRL__SCPU_MODE_MASK);
512 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
513
514 /* turn on */
515 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
516 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
517 | UVD_SUVD_CGC_GATE__SIT_MASK
518 | UVD_SUVD_CGC_GATE__SMP_MASK
519 | UVD_SUVD_CGC_GATE__SCM_MASK
520 | UVD_SUVD_CGC_GATE__SDB_MASK
521 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
522 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
523 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
524 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
525 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
526 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
527 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
528 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
529 | UVD_SUVD_CGC_GATE__SCLR_MASK
530 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
531 | UVD_SUVD_CGC_GATE__ENT_MASK
532 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
533 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
534 | UVD_SUVD_CGC_GATE__SITE_MASK
535 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
536 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
537 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
538 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
539 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
540 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
541
542 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
543 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
544 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
545 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
546 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
547 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
548 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
549 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
550 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
551 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
552 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
553 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
554 }
555
vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel,uint8_t indirect)556 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
557 uint8_t sram_sel, uint8_t indirect)
558 {
559 uint32_t reg_data = 0;
560
561 /* enable sw clock gating control */
562 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
563 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
564 else
565 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
566 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
567 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
568 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
569 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
570 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
571 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
572 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
573 UVD_CGC_CTRL__SYS_MODE_MASK |
574 UVD_CGC_CTRL__UDEC_MODE_MASK |
575 UVD_CGC_CTRL__MPEG2_MODE_MASK |
576 UVD_CGC_CTRL__REGS_MODE_MASK |
577 UVD_CGC_CTRL__RBC_MODE_MASK |
578 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
579 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
580 UVD_CGC_CTRL__IDCT_MODE_MASK |
581 UVD_CGC_CTRL__MPRD_MODE_MASK |
582 UVD_CGC_CTRL__MPC_MODE_MASK |
583 UVD_CGC_CTRL__LBSI_MODE_MASK |
584 UVD_CGC_CTRL__LRBBM_MODE_MASK |
585 UVD_CGC_CTRL__WCB_MODE_MASK |
586 UVD_CGC_CTRL__VCPU_MODE_MASK |
587 UVD_CGC_CTRL__SCPU_MODE_MASK);
588 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
589 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
590
591 /* turn off clock gating */
592 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
593 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
594
595 /* turn on SUVD clock gating */
596 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
597 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
598
599 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
600 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
601 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
602 }
603
604 /**
605 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
606 *
607 * @adev: amdgpu_device pointer
608 * @sw: enable SW clock gating
609 *
610 * Enable clock gating for VCN block
611 */
vcn_v2_0_enable_clock_gating(struct amdgpu_device * adev)612 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
613 {
614 uint32_t data = 0;
615
616 /* enable UVD CGC */
617 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
618 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
619 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
620 else
621 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
622 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
623 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
624 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
625
626 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
627 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
628 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
629 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
630 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
631 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
632 | UVD_CGC_CTRL__SYS_MODE_MASK
633 | UVD_CGC_CTRL__UDEC_MODE_MASK
634 | UVD_CGC_CTRL__MPEG2_MODE_MASK
635 | UVD_CGC_CTRL__REGS_MODE_MASK
636 | UVD_CGC_CTRL__RBC_MODE_MASK
637 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
638 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
639 | UVD_CGC_CTRL__IDCT_MODE_MASK
640 | UVD_CGC_CTRL__MPRD_MODE_MASK
641 | UVD_CGC_CTRL__MPC_MODE_MASK
642 | UVD_CGC_CTRL__LBSI_MODE_MASK
643 | UVD_CGC_CTRL__LRBBM_MODE_MASK
644 | UVD_CGC_CTRL__WCB_MODE_MASK
645 | UVD_CGC_CTRL__VCPU_MODE_MASK
646 | UVD_CGC_CTRL__SCPU_MODE_MASK);
647 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
648
649 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
650 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
651 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
652 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
653 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
654 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
655 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
656 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
657 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
658 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
659 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
660 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
661 }
662
vcn_v2_0_disable_static_power_gating(struct amdgpu_device * adev)663 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
664 {
665 uint32_t data = 0;
666 int ret __unused;
667
668 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
669 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
670 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
671 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
672 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
673 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
674 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
675 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
676 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
677 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
678 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
679
680 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
681 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
682 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
683 } else {
684 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
685 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
686 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
687 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
688 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
689 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
690 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
691 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
692 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
693 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
694 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
695 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret);
696 }
697
698 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
699 * UVDU_PWR_STATUS are 0 (power on) */
700
701 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
702 data &= ~0x103;
703 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
704 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
705 UVD_POWER_STATUS__UVD_PG_EN_MASK;
706
707 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
708 }
709
vcn_v2_0_enable_static_power_gating(struct amdgpu_device * adev)710 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
711 {
712 uint32_t data = 0;
713 int ret __unused;
714
715 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
716 /* Before power off, this indicator has to be turned on */
717 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
718 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
719 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
720 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
721
722
723 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
724 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
725 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
726 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
727 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
728 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
729 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
730 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
731 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
732 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
733
734 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
735
736 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
737 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
738 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
739 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
740 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
741 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
742 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
743 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
744 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
745 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
746 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
747 }
748 }
749
vcn_v2_0_start_dpg_mode(struct amdgpu_device * adev,bool indirect)750 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
751 {
752 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
753 uint32_t rb_bufsz, tmp;
754
755 vcn_v2_0_enable_static_power_gating(adev);
756
757 /* enable dynamic power gating mode */
758 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
759 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
760 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
761 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
762
763 if (indirect)
764 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
765
766 /* enable clock gating */
767 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
768
769 /* enable VCPU clock */
770 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
771 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
772 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
773 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
774 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
775
776 /* disable master interupt */
777 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
778 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
779
780 /* setup mmUVD_LMI_CTRL */
781 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
782 UVD_LMI_CTRL__REQ_MODE_MASK |
783 UVD_LMI_CTRL__CRC_RESET_MASK |
784 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
785 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
786 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
787 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
788 0x00100000L);
789 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
790 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
791
792 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
793 UVD, 0, mmUVD_MPC_CNTL),
794 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
795
796 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
797 UVD, 0, mmUVD_MPC_SET_MUXA0),
798 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
799 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
800 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
801 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
802
803 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
804 UVD, 0, mmUVD_MPC_SET_MUXB0),
805 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
806 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
807 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
808 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
809
810 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
811 UVD, 0, mmUVD_MPC_SET_MUX),
812 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
813 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
814 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
815
816 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
817
818 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
819 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
820 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
821 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
822
823 /* release VCPU reset to boot */
824 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
825 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
826
827 /* enable LMI MC and UMC channels */
828 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
829 UVD, 0, mmUVD_LMI_CTRL2),
830 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
831
832 /* enable master interrupt */
833 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
834 UVD, 0, mmUVD_MASTINT_EN),
835 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
836
837 if (indirect)
838 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
839 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
840 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
841
842 /* force RBC into idle state */
843 rb_bufsz = order_base_2(ring->ring_size);
844 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
845 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
846 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
847 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
848 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
849 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
850
851 /* set the write pointer delay */
852 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
853
854 /* set the wb address */
855 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
856 (upper_32_bits(ring->gpu_addr) >> 2));
857
858 /* programm the RB_BASE for ring buffer */
859 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
860 lower_32_bits(ring->gpu_addr));
861 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
862 upper_32_bits(ring->gpu_addr));
863
864 /* Initialize the ring buffer's read and write pointers */
865 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
866
867 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
868
869 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
870 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
871 lower_32_bits(ring->wptr));
872
873 return 0;
874 }
875
vcn_v2_0_start(struct amdgpu_device * adev)876 static int vcn_v2_0_start(struct amdgpu_device *adev)
877 {
878 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
879 uint32_t rb_bufsz, tmp;
880 uint32_t lmi_swap_cntl;
881 int i, j, r;
882
883 if (adev->pm.dpm_enabled)
884 amdgpu_dpm_enable_uvd(adev, true);
885
886 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
887 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
888
889 vcn_v2_0_disable_static_power_gating(adev);
890
891 /* set uvd status busy */
892 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
893 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
894
895 /*SW clock gating */
896 vcn_v2_0_disable_clock_gating(adev);
897
898 /* enable VCPU clock */
899 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
900 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
901
902 /* disable master interrupt */
903 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
904 ~UVD_MASTINT_EN__VCPU_EN_MASK);
905
906 /* setup mmUVD_LMI_CTRL */
907 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
908 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
909 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
910 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
911 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
912 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
913
914 /* setup mmUVD_MPC_CNTL */
915 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
916 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
917 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
918 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
919
920 /* setup UVD_MPC_SET_MUXA0 */
921 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
922 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
923 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
924 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
925 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
926
927 /* setup UVD_MPC_SET_MUXB0 */
928 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
929 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
930 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
931 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
932 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
933
934 /* setup mmUVD_MPC_SET_MUX */
935 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
936 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
937 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
938 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
939
940 vcn_v2_0_mc_resume(adev);
941
942 /* release VCPU reset to boot */
943 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
944 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
945
946 /* enable LMI MC and UMC channels */
947 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
948 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
949
950 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
951 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
952 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
953 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
954
955 /* disable byte swapping */
956 lmi_swap_cntl = 0;
957 #ifdef __BIG_ENDIAN
958 /* swap (8 in 32) RB and IB */
959 lmi_swap_cntl = 0xa;
960 #endif
961 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
962
963 for (i = 0; i < 10; ++i) {
964 uint32_t status;
965
966 for (j = 0; j < 100; ++j) {
967 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
968 if (status & 2)
969 break;
970 mdelay(10);
971 }
972 r = 0;
973 if (status & 2)
974 break;
975
976 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
977 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
978 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
979 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
980 mdelay(10);
981 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
982 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
983 mdelay(10);
984 r = -1;
985 }
986
987 if (r) {
988 DRM_ERROR("VCN decode not responding, giving up!!!\n");
989 return r;
990 }
991
992 /* enable master interrupt */
993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
994 UVD_MASTINT_EN__VCPU_EN_MASK,
995 ~UVD_MASTINT_EN__VCPU_EN_MASK);
996
997 /* clear the busy bit of VCN_STATUS */
998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
999 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1000
1001 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1002
1003 /* force RBC into idle state */
1004 rb_bufsz = order_base_2(ring->ring_size);
1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1006 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1007 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1008 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1009 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1010 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1011
1012 /* programm the RB_BASE for ring buffer */
1013 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1014 lower_32_bits(ring->gpu_addr));
1015 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1016 upper_32_bits(ring->gpu_addr));
1017
1018 /* Initialize the ring buffer's read and write pointers */
1019 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1020
1021 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1022 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1023 lower_32_bits(ring->wptr));
1024
1025 ring = &adev->vcn.inst->ring_enc[0];
1026 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1027 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1028 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1029 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1030 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1031
1032 ring = &adev->vcn.inst->ring_enc[1];
1033 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1034 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1035 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1036 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1037 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1038
1039 return 0;
1040 }
1041
vcn_v2_0_stop_dpg_mode(struct amdgpu_device * adev)1042 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1043 {
1044 int ret_code __unused = 0;
1045 uint32_t tmp;
1046
1047 /* Wait for power status to be 1 */
1048 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1049 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1050
1051 /* wait for read ptr to be equal to write ptr */
1052 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1053 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1054
1055 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1056 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1057
1058 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1059 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1060
1061 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1062 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1063
1064 /* disable dynamic power gating mode */
1065 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1066 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1067
1068 return 0;
1069 }
1070
vcn_v2_0_stop(struct amdgpu_device * adev)1071 static int vcn_v2_0_stop(struct amdgpu_device *adev)
1072 {
1073 uint32_t tmp;
1074 int r;
1075
1076 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1077 r = vcn_v2_0_stop_dpg_mode(adev);
1078 if (r)
1079 return r;
1080 goto power_off;
1081 }
1082
1083 /* wait for uvd idle */
1084 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1085 if (r)
1086 return r;
1087
1088 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1089 UVD_LMI_STATUS__READ_CLEAN_MASK |
1090 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1091 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1092 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1093 if (r)
1094 return r;
1095
1096 /* stall UMC channel */
1097 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1098 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1099 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1100
1101 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1102 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1103 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1104 if (r)
1105 return r;
1106
1107 /* disable VCPU clock */
1108 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1109 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1110
1111 /* reset LMI UMC */
1112 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1113 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1114 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1115
1116 /* reset LMI */
1117 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1118 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1119 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1120
1121 /* reset VCPU */
1122 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1123 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1124 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1125
1126 /* clear status */
1127 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1128
1129 vcn_v2_0_enable_clock_gating(adev);
1130 vcn_v2_0_enable_static_power_gating(adev);
1131
1132 power_off:
1133 if (adev->pm.dpm_enabled)
1134 amdgpu_dpm_enable_uvd(adev, false);
1135
1136 return 0;
1137 }
1138
vcn_v2_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1139 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1140 int inst_idx, struct dpg_pause_state *new_state)
1141 {
1142 struct amdgpu_ring *ring;
1143 uint32_t reg_data = 0;
1144 int ret_code;
1145
1146 /* pause/unpause if state is changed */
1147 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1148 DRM_DEBUG("dpg pause state changed %d -> %d",
1149 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1150 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1151 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1152
1153 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1154 ret_code = 0;
1155 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1156 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1157
1158 if (!ret_code) {
1159 /* pause DPG */
1160 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1161 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1162
1163 /* wait for ACK */
1164 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1165 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1166 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1167
1168 /* Restore */
1169 ring = &adev->vcn.inst->ring_enc[0];
1170 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1171 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1172 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1173 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1174 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1175
1176 ring = &adev->vcn.inst->ring_enc[1];
1177 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1178 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1179 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1180 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1181 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1182
1183 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1184 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1185
1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1187 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1188 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1189 }
1190 } else {
1191 /* unpause dpg, no need to wait */
1192 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1193 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1194 }
1195 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1196 }
1197
1198 return 0;
1199 }
1200
vcn_v2_0_is_idle(void * handle)1201 static bool vcn_v2_0_is_idle(void *handle)
1202 {
1203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1204
1205 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1206 }
1207
vcn_v2_0_wait_for_idle(void * handle)1208 static int vcn_v2_0_wait_for_idle(void *handle)
1209 {
1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211 int ret = 0;
1212
1213 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1214 UVD_STATUS__IDLE, ret);
1215
1216 return ret;
1217 }
1218
vcn_v2_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1219 static int vcn_v2_0_set_clockgating_state(void *handle,
1220 enum amd_clockgating_state state)
1221 {
1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223 bool enable = (state == AMD_CG_STATE_GATE);
1224
1225 if (enable) {
1226 /* wait for STATUS to clear */
1227 if (vcn_v2_0_is_idle(handle))
1228 return -EBUSY;
1229 vcn_v2_0_enable_clock_gating(adev);
1230 } else {
1231 /* disable HW gating and enable Sw gating */
1232 vcn_v2_0_disable_clock_gating(adev);
1233 }
1234 return 0;
1235 }
1236
1237 /**
1238 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1239 *
1240 * @ring: amdgpu_ring pointer
1241 *
1242 * Returns the current hardware read pointer
1243 */
vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1244 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1245 {
1246 struct amdgpu_device *adev = ring->adev;
1247
1248 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1249 }
1250
1251 /**
1252 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1253 *
1254 * @ring: amdgpu_ring pointer
1255 *
1256 * Returns the current hardware write pointer
1257 */
vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1258 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1259 {
1260 struct amdgpu_device *adev = ring->adev;
1261
1262 if (ring->use_doorbell)
1263 return adev->wb.wb[ring->wptr_offs];
1264 else
1265 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1266 }
1267
1268 /**
1269 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1270 *
1271 * @ring: amdgpu_ring pointer
1272 *
1273 * Commits the write pointer to the hardware
1274 */
vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1275 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1276 {
1277 struct amdgpu_device *adev = ring->adev;
1278
1279 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1280 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1281 lower_32_bits(ring->wptr) | 0x80000000);
1282
1283 if (ring->use_doorbell) {
1284 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1285 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1286 } else {
1287 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1288 }
1289 }
1290
1291 /**
1292 * vcn_v2_0_dec_ring_insert_start - insert a start command
1293 *
1294 * @ring: amdgpu_ring pointer
1295 *
1296 * Write a start command to the ring.
1297 */
vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)1298 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1299 {
1300 struct amdgpu_device *adev = ring->adev;
1301
1302 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1303 amdgpu_ring_write(ring, 0);
1304 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1305 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1306 }
1307
1308 /**
1309 * vcn_v2_0_dec_ring_insert_end - insert a end command
1310 *
1311 * @ring: amdgpu_ring pointer
1312 *
1313 * Write a end command to the ring.
1314 */
vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)1315 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1316 {
1317 struct amdgpu_device *adev = ring->adev;
1318
1319 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1320 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1321 }
1322
1323 /**
1324 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1325 *
1326 * @ring: amdgpu_ring pointer
1327 *
1328 * Write a nop command to the ring.
1329 */
vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1330 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1331 {
1332 struct amdgpu_device *adev = ring->adev;
1333 int i;
1334
1335 WARN_ON(ring->wptr % 2 || count % 2);
1336
1337 for (i = 0; i < count / 2; i++) {
1338 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1339 amdgpu_ring_write(ring, 0);
1340 }
1341 }
1342
1343 /**
1344 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1345 *
1346 * @ring: amdgpu_ring pointer
1347 * @fence: fence to emit
1348 *
1349 * Write a fence and a trap command to the ring.
1350 */
vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1351 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1352 unsigned flags)
1353 {
1354 struct amdgpu_device *adev = ring->adev;
1355
1356 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1357 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1358 amdgpu_ring_write(ring, seq);
1359
1360 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1361 amdgpu_ring_write(ring, addr & 0xffffffff);
1362
1363 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1364 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1365
1366 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1367 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1368
1369 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1370 amdgpu_ring_write(ring, 0);
1371
1372 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1373 amdgpu_ring_write(ring, 0);
1374
1375 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1376
1377 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1378 }
1379
1380 /**
1381 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1382 *
1383 * @ring: amdgpu_ring pointer
1384 * @ib: indirect buffer to execute
1385 *
1386 * Write ring commands to execute the indirect buffer
1387 */
vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1388 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1389 struct amdgpu_job *job,
1390 struct amdgpu_ib *ib,
1391 uint32_t flags)
1392 {
1393 struct amdgpu_device *adev = ring->adev;
1394 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1395
1396 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1397 amdgpu_ring_write(ring, vmid);
1398
1399 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1400 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1401 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1402 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1403 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1404 amdgpu_ring_write(ring, ib->length_dw);
1405 }
1406
vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1407 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1408 uint32_t val, uint32_t mask)
1409 {
1410 struct amdgpu_device *adev = ring->adev;
1411
1412 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1413 amdgpu_ring_write(ring, reg << 2);
1414
1415 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1416 amdgpu_ring_write(ring, val);
1417
1418 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1419 amdgpu_ring_write(ring, mask);
1420
1421 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1422
1423 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1424 }
1425
vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1426 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1427 unsigned vmid, uint64_t pd_addr)
1428 {
1429 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1430 uint32_t data0, data1, mask;
1431
1432 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1433
1434 /* wait for register write */
1435 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1436 data1 = lower_32_bits(pd_addr);
1437 mask = 0xffffffff;
1438 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1439 }
1440
vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1441 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1442 uint32_t reg, uint32_t val)
1443 {
1444 struct amdgpu_device *adev = ring->adev;
1445
1446 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1447 amdgpu_ring_write(ring, reg << 2);
1448
1449 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1450 amdgpu_ring_write(ring, val);
1451
1452 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1453
1454 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1455 }
1456
1457 /**
1458 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1459 *
1460 * @ring: amdgpu_ring pointer
1461 *
1462 * Returns the current hardware enc read pointer
1463 */
vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1464 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1465 {
1466 struct amdgpu_device *adev = ring->adev;
1467
1468 if (ring == &adev->vcn.inst->ring_enc[0])
1469 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1470 else
1471 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1472 }
1473
1474 /**
1475 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1476 *
1477 * @ring: amdgpu_ring pointer
1478 *
1479 * Returns the current hardware enc write pointer
1480 */
vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1481 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1482 {
1483 struct amdgpu_device *adev = ring->adev;
1484
1485 if (ring == &adev->vcn.inst->ring_enc[0]) {
1486 if (ring->use_doorbell)
1487 return adev->wb.wb[ring->wptr_offs];
1488 else
1489 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1490 } else {
1491 if (ring->use_doorbell)
1492 return adev->wb.wb[ring->wptr_offs];
1493 else
1494 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1495 }
1496 }
1497
1498 /**
1499 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1500 *
1501 * @ring: amdgpu_ring pointer
1502 *
1503 * Commits the enc write pointer to the hardware
1504 */
vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1505 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1506 {
1507 struct amdgpu_device *adev = ring->adev;
1508
1509 if (ring == &adev->vcn.inst->ring_enc[0]) {
1510 if (ring->use_doorbell) {
1511 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1512 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1513 } else {
1514 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1515 }
1516 } else {
1517 if (ring->use_doorbell) {
1518 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1519 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1520 } else {
1521 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1522 }
1523 }
1524 }
1525
1526 /**
1527 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1528 *
1529 * @ring: amdgpu_ring pointer
1530 * @fence: fence to emit
1531 *
1532 * Write enc a fence and a trap command to the ring.
1533 */
vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1534 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1535 u64 seq, unsigned flags)
1536 {
1537 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1538
1539 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1540 amdgpu_ring_write(ring, addr);
1541 amdgpu_ring_write(ring, upper_32_bits(addr));
1542 amdgpu_ring_write(ring, seq);
1543 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1544 }
1545
vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring * ring)1546 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1547 {
1548 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1549 }
1550
1551 /**
1552 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1553 *
1554 * @ring: amdgpu_ring pointer
1555 * @ib: indirect buffer to execute
1556 *
1557 * Write enc ring commands to execute the indirect buffer
1558 */
vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1559 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1560 struct amdgpu_job *job,
1561 struct amdgpu_ib *ib,
1562 uint32_t flags)
1563 {
1564 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1565
1566 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1567 amdgpu_ring_write(ring, vmid);
1568 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1569 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1570 amdgpu_ring_write(ring, ib->length_dw);
1571 }
1572
vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1573 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1574 uint32_t val, uint32_t mask)
1575 {
1576 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1577 amdgpu_ring_write(ring, reg << 2);
1578 amdgpu_ring_write(ring, mask);
1579 amdgpu_ring_write(ring, val);
1580 }
1581
vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1582 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1583 unsigned int vmid, uint64_t pd_addr)
1584 {
1585 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1586
1587 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1588
1589 /* wait for reg writes */
1590 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1591 lower_32_bits(pd_addr), 0xffffffff);
1592 }
1593
vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1594 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1595 {
1596 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1597 amdgpu_ring_write(ring, reg << 2);
1598 amdgpu_ring_write(ring, val);
1599 }
1600
vcn_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1601 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1602 struct amdgpu_irq_src *source,
1603 unsigned type,
1604 enum amdgpu_interrupt_state state)
1605 {
1606 return 0;
1607 }
1608
vcn_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1609 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1610 struct amdgpu_irq_src *source,
1611 struct amdgpu_iv_entry *entry)
1612 {
1613 DRM_DEBUG("IH: VCN TRAP\n");
1614
1615 switch (entry->src_id) {
1616 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1617 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1618 break;
1619 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1620 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1621 break;
1622 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1623 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1624 break;
1625 default:
1626 DRM_ERROR("Unhandled interrupt: %d %d\n",
1627 entry->src_id, entry->src_data[0]);
1628 break;
1629 }
1630
1631 return 0;
1632 }
1633
vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring * ring)1634 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1635 {
1636 struct amdgpu_device *adev = ring->adev;
1637 uint32_t tmp = 0;
1638 unsigned i;
1639 int r;
1640
1641 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1642 r = amdgpu_ring_alloc(ring, 4);
1643 if (r)
1644 return r;
1645 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1646 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1647 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1648 amdgpu_ring_write(ring, 0xDEADBEEF);
1649 amdgpu_ring_commit(ring);
1650 for (i = 0; i < adev->usec_timeout; i++) {
1651 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1652 if (tmp == 0xDEADBEEF)
1653 break;
1654 udelay(1);
1655 }
1656
1657 if (i >= adev->usec_timeout)
1658 r = -ETIMEDOUT;
1659
1660 return r;
1661 }
1662
1663
vcn_v2_0_set_powergating_state(void * handle,enum amd_powergating_state state)1664 static int vcn_v2_0_set_powergating_state(void *handle,
1665 enum amd_powergating_state state)
1666 {
1667 /* This doesn't actually powergate the VCN block.
1668 * That's done in the dpm code via the SMC. This
1669 * just re-inits the block as necessary. The actual
1670 * gating still happens in the dpm code. We should
1671 * revisit this when there is a cleaner line between
1672 * the smc and the hw blocks
1673 */
1674 int ret;
1675 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1676
1677 if (state == adev->vcn.cur_state)
1678 return 0;
1679
1680 if (state == AMD_PG_STATE_GATE)
1681 ret = vcn_v2_0_stop(adev);
1682 else
1683 ret = vcn_v2_0_start(adev);
1684
1685 if (!ret)
1686 adev->vcn.cur_state = state;
1687 return ret;
1688 }
1689
1690 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1691 .name = "vcn_v2_0",
1692 .early_init = vcn_v2_0_early_init,
1693 .late_init = NULL,
1694 .sw_init = vcn_v2_0_sw_init,
1695 .sw_fini = vcn_v2_0_sw_fini,
1696 .hw_init = vcn_v2_0_hw_init,
1697 .hw_fini = vcn_v2_0_hw_fini,
1698 .suspend = vcn_v2_0_suspend,
1699 .resume = vcn_v2_0_resume,
1700 .is_idle = vcn_v2_0_is_idle,
1701 .wait_for_idle = vcn_v2_0_wait_for_idle,
1702 .check_soft_reset = NULL,
1703 .pre_soft_reset = NULL,
1704 .soft_reset = NULL,
1705 .post_soft_reset = NULL,
1706 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
1707 .set_powergating_state = vcn_v2_0_set_powergating_state,
1708 };
1709
1710 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
1711 .type = AMDGPU_RING_TYPE_VCN_DEC,
1712 .align_mask = 0xf,
1713 .vmhub = AMDGPU_MMHUB_0,
1714 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
1715 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
1716 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
1717 .emit_frame_size =
1718 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1719 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1720 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1721 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1722 6,
1723 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1724 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1725 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1726 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1727 .test_ring = vcn_v2_0_dec_ring_test_ring,
1728 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1729 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1730 .insert_start = vcn_v2_0_dec_ring_insert_start,
1731 .insert_end = vcn_v2_0_dec_ring_insert_end,
1732 .pad_ib = amdgpu_ring_generic_pad_ib,
1733 .begin_use = amdgpu_vcn_ring_begin_use,
1734 .end_use = amdgpu_vcn_ring_end_use,
1735 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1736 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1737 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1738 };
1739
1740 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
1741 .type = AMDGPU_RING_TYPE_VCN_ENC,
1742 .align_mask = 0x3f,
1743 .nop = VCN_ENC_CMD_NO_OP,
1744 .vmhub = AMDGPU_MMHUB_0,
1745 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
1746 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
1747 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
1748 .emit_frame_size =
1749 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1750 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1751 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1752 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1753 1, /* vcn_v2_0_enc_ring_insert_end */
1754 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1755 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1756 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1757 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1758 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1759 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1760 .insert_nop = amdgpu_ring_insert_nop,
1761 .insert_end = vcn_v2_0_enc_ring_insert_end,
1762 .pad_ib = amdgpu_ring_generic_pad_ib,
1763 .begin_use = amdgpu_vcn_ring_begin_use,
1764 .end_use = amdgpu_vcn_ring_end_use,
1765 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1766 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1767 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1768 };
1769
vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)1770 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1771 {
1772 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1773 DRM_INFO("VCN decode is enabled in VM mode\n");
1774 }
1775
vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device * adev)1776 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1777 {
1778 int i;
1779
1780 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1781 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
1782
1783 DRM_INFO("VCN encode is enabled in VM mode\n");
1784 }
1785
1786 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
1787 .set = vcn_v2_0_set_interrupt_state,
1788 .process = vcn_v2_0_process_interrupt,
1789 };
1790
vcn_v2_0_set_irq_funcs(struct amdgpu_device * adev)1791 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
1792 {
1793 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
1794 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
1795 }
1796
1797 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
1798 {
1799 .type = AMD_IP_BLOCK_TYPE_VCN,
1800 .major = 2,
1801 .minor = 0,
1802 .rev = 0,
1803 .funcs = &vcn_v2_0_ip_funcs,
1804 };
1805