1 /* $NetBSD: amdgpu_uvd_v7_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v7_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
28
29 #include <linux/firmware.h>
30
31 #include "amdgpu.h"
32 #include "amdgpu_uvd.h"
33 #include "soc15.h"
34 #include "soc15d.h"
35 #include "soc15_common.h"
36 #include "mmsch_v1_0.h"
37
38 #include "uvd/uvd_7_0_offset.h"
39 #include "uvd/uvd_7_0_sh_mask.h"
40 #include "vce/vce_4_0_offset.h"
41 #include "vce/vce_4_0_default.h"
42 #include "vce/vce_4_0_sh_mask.h"
43 #include "nbif/nbif_6_1_offset.h"
44 #include "hdp/hdp_4_0_offset.h"
45 #include "mmhub/mmhub_1_0_offset.h"
46 #include "mmhub/mmhub_1_0_sh_mask.h"
47 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
48
49 #include <linux/nbsd-namespace.h>
50
51 #define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7
52 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1
53 //UVD_PG0_CC_UVD_HARVESTING
54 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
55 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
56
57 #define UVD7_MAX_HW_INSTANCES_VEGA20 2
58
59 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
60 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
61 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
62 static int uvd_v7_0_start(struct amdgpu_device *adev);
63 static void uvd_v7_0_stop(struct amdgpu_device *adev);
64 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
65
66 static int amdgpu_ih_clientid_uvds[] = {
67 SOC15_IH_CLIENTID_UVD,
68 SOC15_IH_CLIENTID_UVD1
69 };
70
71 /**
72 * uvd_v7_0_ring_get_rptr - get read pointer
73 *
74 * @ring: amdgpu_ring pointer
75 *
76 * Returns the current hardware read pointer
77 */
uvd_v7_0_ring_get_rptr(struct amdgpu_ring * ring)78 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
79 {
80 struct amdgpu_device *adev = ring->adev;
81
82 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
83 }
84
85 /**
86 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
87 *
88 * @ring: amdgpu_ring pointer
89 *
90 * Returns the current hardware enc read pointer
91 */
uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring * ring)92 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
93 {
94 struct amdgpu_device *adev = ring->adev;
95
96 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
97 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
98 else
99 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
100 }
101
102 /**
103 * uvd_v7_0_ring_get_wptr - get write pointer
104 *
105 * @ring: amdgpu_ring pointer
106 *
107 * Returns the current hardware write pointer
108 */
uvd_v7_0_ring_get_wptr(struct amdgpu_ring * ring)109 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
110 {
111 struct amdgpu_device *adev = ring->adev;
112
113 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
114 }
115
116 /**
117 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
118 *
119 * @ring: amdgpu_ring pointer
120 *
121 * Returns the current hardware enc write pointer
122 */
uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring * ring)123 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
124 {
125 struct amdgpu_device *adev = ring->adev;
126
127 if (ring->use_doorbell)
128 return adev->wb.wb[ring->wptr_offs];
129
130 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
131 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
132 else
133 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
134 }
135
136 /**
137 * uvd_v7_0_ring_set_wptr - set write pointer
138 *
139 * @ring: amdgpu_ring pointer
140 *
141 * Commits the write pointer to the hardware
142 */
uvd_v7_0_ring_set_wptr(struct amdgpu_ring * ring)143 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
144 {
145 struct amdgpu_device *adev = ring->adev;
146
147 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
148 }
149
150 /**
151 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
152 *
153 * @ring: amdgpu_ring pointer
154 *
155 * Commits the enc write pointer to the hardware
156 */
uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring * ring)157 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
158 {
159 struct amdgpu_device *adev = ring->adev;
160
161 if (ring->use_doorbell) {
162 /* XXX check if swapping is necessary on BE */
163 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
164 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
165 return;
166 }
167
168 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
169 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
170 lower_32_bits(ring->wptr));
171 else
172 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
173 lower_32_bits(ring->wptr));
174 }
175
176 /**
177 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
178 *
179 * @ring: the engine to test on
180 *
181 */
uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring * ring)182 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
183 {
184 struct amdgpu_device *adev = ring->adev;
185 uint32_t rptr;
186 unsigned i;
187 int r;
188
189 if (amdgpu_sriov_vf(adev))
190 return 0;
191
192 r = amdgpu_ring_alloc(ring, 16);
193 if (r)
194 return r;
195
196 rptr = amdgpu_ring_get_rptr(ring);
197
198 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
199 amdgpu_ring_commit(ring);
200
201 for (i = 0; i < adev->usec_timeout; i++) {
202 if (amdgpu_ring_get_rptr(ring) != rptr)
203 break;
204 udelay(1);
205 }
206
207 if (i >= adev->usec_timeout)
208 r = -ETIMEDOUT;
209
210 return r;
211 }
212
213 /**
214 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
215 *
216 * @adev: amdgpu_device pointer
217 * @ring: ring we should submit the msg to
218 * @handle: session handle to use
219 * @fence: optional fence to return
220 *
221 * Open up a stream for HW test
222 */
uvd_v7_0_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_bo * bo,struct dma_fence ** fence)223 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
224 struct amdgpu_bo *bo,
225 struct dma_fence **fence)
226 {
227 const unsigned ib_size_dw = 16;
228 struct amdgpu_job *job;
229 struct amdgpu_ib *ib;
230 struct dma_fence *f = NULL;
231 uint64_t addr;
232 int i, r;
233
234 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
235 if (r)
236 return r;
237
238 ib = &job->ibs[0];
239 addr = amdgpu_bo_gpu_offset(bo);
240
241 ib->length_dw = 0;
242 ib->ptr[ib->length_dw++] = 0x00000018;
243 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
244 ib->ptr[ib->length_dw++] = handle;
245 ib->ptr[ib->length_dw++] = 0x00000000;
246 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
247 ib->ptr[ib->length_dw++] = addr;
248
249 ib->ptr[ib->length_dw++] = 0x00000014;
250 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
251 ib->ptr[ib->length_dw++] = 0x0000001c;
252 ib->ptr[ib->length_dw++] = 0x00000000;
253 ib->ptr[ib->length_dw++] = 0x00000000;
254
255 ib->ptr[ib->length_dw++] = 0x00000008;
256 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
257
258 for (i = ib->length_dw; i < ib_size_dw; ++i)
259 ib->ptr[i] = 0x0;
260
261 r = amdgpu_job_submit_direct(job, ring, &f);
262 if (r)
263 goto err;
264
265 if (fence)
266 *fence = dma_fence_get(f);
267 dma_fence_put(f);
268 return 0;
269
270 err:
271 amdgpu_job_free(job);
272 return r;
273 }
274
275 /**
276 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
277 *
278 * @adev: amdgpu_device pointer
279 * @ring: ring we should submit the msg to
280 * @handle: session handle to use
281 * @fence: optional fence to return
282 *
283 * Close up a stream for HW test or if userspace failed to do so
284 */
uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_bo * bo,struct dma_fence ** fence)285 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
286 struct amdgpu_bo *bo,
287 struct dma_fence **fence)
288 {
289 const unsigned ib_size_dw = 16;
290 struct amdgpu_job *job;
291 struct amdgpu_ib *ib;
292 struct dma_fence *f = NULL;
293 uint64_t addr;
294 int i, r;
295
296 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
297 if (r)
298 return r;
299
300 ib = &job->ibs[0];
301 addr = amdgpu_bo_gpu_offset(bo);
302
303 ib->length_dw = 0;
304 ib->ptr[ib->length_dw++] = 0x00000018;
305 ib->ptr[ib->length_dw++] = 0x00000001;
306 ib->ptr[ib->length_dw++] = handle;
307 ib->ptr[ib->length_dw++] = 0x00000000;
308 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
309 ib->ptr[ib->length_dw++] = addr;
310
311 ib->ptr[ib->length_dw++] = 0x00000014;
312 ib->ptr[ib->length_dw++] = 0x00000002;
313 ib->ptr[ib->length_dw++] = 0x0000001c;
314 ib->ptr[ib->length_dw++] = 0x00000000;
315 ib->ptr[ib->length_dw++] = 0x00000000;
316
317 ib->ptr[ib->length_dw++] = 0x00000008;
318 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
319
320 for (i = ib->length_dw; i < ib_size_dw; ++i)
321 ib->ptr[i] = 0x0;
322
323 r = amdgpu_job_submit_direct(job, ring, &f);
324 if (r)
325 goto err;
326
327 if (fence)
328 *fence = dma_fence_get(f);
329 dma_fence_put(f);
330 return 0;
331
332 err:
333 amdgpu_job_free(job);
334 return r;
335 }
336
337 /**
338 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
339 *
340 * @ring: the engine to test on
341 *
342 */
uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)343 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
344 {
345 struct dma_fence *fence = NULL;
346 struct amdgpu_bo *bo = NULL;
347 long r;
348
349 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
350 AMDGPU_GEM_DOMAIN_VRAM,
351 &bo, NULL, NULL);
352 if (r)
353 return r;
354
355 r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL);
356 if (r)
357 goto error;
358
359 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence);
360 if (r)
361 goto error;
362
363 r = dma_fence_wait_timeout(fence, false, timeout);
364 if (r == 0)
365 r = -ETIMEDOUT;
366 else if (r > 0)
367 r = 0;
368
369 error:
370 dma_fence_put(fence);
371 amdgpu_bo_unreserve(bo);
372 amdgpu_bo_unref(&bo);
373 return r;
374 }
375
uvd_v7_0_early_init(void * handle)376 static int uvd_v7_0_early_init(void *handle)
377 {
378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
379
380 if (adev->asic_type == CHIP_VEGA20) {
381 u32 harvest;
382 int i;
383
384 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
385 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
386 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
387 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
388 adev->uvd.harvest_config |= 1 << i;
389 }
390 }
391 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
392 AMDGPU_UVD_HARVEST_UVD1))
393 /* both instances are harvested, disable the block */
394 return -ENOENT;
395 } else {
396 adev->uvd.num_uvd_inst = 1;
397 }
398
399 if (amdgpu_sriov_vf(adev))
400 adev->uvd.num_enc_rings = 1;
401 else
402 adev->uvd.num_enc_rings = 2;
403 uvd_v7_0_set_ring_funcs(adev);
404 uvd_v7_0_set_enc_ring_funcs(adev);
405 uvd_v7_0_set_irq_funcs(adev);
406
407 return 0;
408 }
409
uvd_v7_0_sw_init(void * handle)410 static int uvd_v7_0_sw_init(void *handle)
411 {
412 struct amdgpu_ring *ring;
413
414 int i, j, r;
415 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
416
417 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
418 if (adev->uvd.harvest_config & (1 << j))
419 continue;
420 /* UVD TRAP */
421 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
422 if (r)
423 return r;
424
425 /* UVD ENC TRAP */
426 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
427 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
428 if (r)
429 return r;
430 }
431 }
432
433 r = amdgpu_uvd_sw_init(adev);
434 if (r)
435 return r;
436
437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
438 const struct common_firmware_header *hdr;
439 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
440 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
441 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
442 adev->firmware.fw_size +=
443 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
444
445 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
446 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
447 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
448 adev->firmware.fw_size +=
449 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
450 }
451 DRM_INFO("PSP loading UVD firmware\n");
452 }
453
454 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
455 if (adev->uvd.harvest_config & (1 << j))
456 continue;
457 if (!amdgpu_sriov_vf(adev)) {
458 ring = &adev->uvd.inst[j].ring;
459 snprintf(ring->name, sizeof(ring->name), "uvd_%d", ring->me);
460 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
461 if (r)
462 return r;
463 }
464
465 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
466 ring = &adev->uvd.inst[j].ring_enc[i];
467 snprintf(ring->name, sizeof(ring->name), "uvd_enc_%d.%d", ring->me, i);
468 if (amdgpu_sriov_vf(adev)) {
469 ring->use_doorbell = true;
470
471 /* currently only use the first enconding ring for
472 * sriov, so set unused location for other unused rings.
473 */
474 if (i == 0)
475 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2;
476 else
477 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1;
478 }
479 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
480 if (r)
481 return r;
482 }
483 }
484
485 r = amdgpu_uvd_resume(adev);
486 if (r)
487 return r;
488
489 r = amdgpu_uvd_entity_init(adev);
490 if (r)
491 return r;
492
493 r = amdgpu_virt_alloc_mm_table(adev);
494 if (r)
495 return r;
496
497 return r;
498 }
499
uvd_v7_0_sw_fini(void * handle)500 static int uvd_v7_0_sw_fini(void *handle)
501 {
502 int i, j, r;
503 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
504
505 amdgpu_virt_free_mm_table(adev);
506
507 r = amdgpu_uvd_suspend(adev);
508 if (r)
509 return r;
510
511 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
512 if (adev->uvd.harvest_config & (1 << j))
513 continue;
514 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
515 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
516 }
517 return amdgpu_uvd_sw_fini(adev);
518 }
519
520 /**
521 * uvd_v7_0_hw_init - start and test UVD block
522 *
523 * @adev: amdgpu_device pointer
524 *
525 * Initialize the hardware, boot up the VCPU and do some testing
526 */
uvd_v7_0_hw_init(void * handle)527 static int uvd_v7_0_hw_init(void *handle)
528 {
529 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
530 struct amdgpu_ring *ring;
531 uint32_t tmp;
532 int i, j, r;
533
534 if (amdgpu_sriov_vf(adev))
535 r = uvd_v7_0_sriov_start(adev);
536 else
537 r = uvd_v7_0_start(adev);
538 if (r)
539 goto done;
540
541 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
542 if (adev->uvd.harvest_config & (1 << j))
543 continue;
544 ring = &adev->uvd.inst[j].ring;
545
546 if (!amdgpu_sriov_vf(adev)) {
547 r = amdgpu_ring_test_helper(ring);
548 if (r)
549 goto done;
550
551 r = amdgpu_ring_alloc(ring, 10);
552 if (r) {
553 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
554 goto done;
555 }
556
557 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
558 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
559 amdgpu_ring_write(ring, tmp);
560 amdgpu_ring_write(ring, 0xFFFFF);
561
562 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
563 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
564 amdgpu_ring_write(ring, tmp);
565 amdgpu_ring_write(ring, 0xFFFFF);
566
567 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
568 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
569 amdgpu_ring_write(ring, tmp);
570 amdgpu_ring_write(ring, 0xFFFFF);
571
572 /* Clear timeout status bits */
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
574 mmUVD_SEMA_TIMEOUT_STATUS), 0));
575 amdgpu_ring_write(ring, 0x8);
576
577 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
578 mmUVD_SEMA_CNTL), 0));
579 amdgpu_ring_write(ring, 3);
580
581 amdgpu_ring_commit(ring);
582 }
583
584 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
585 ring = &adev->uvd.inst[j].ring_enc[i];
586 r = amdgpu_ring_test_helper(ring);
587 if (r)
588 goto done;
589 }
590 }
591 done:
592 if (!r)
593 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
594
595 return r;
596 }
597
598 /**
599 * uvd_v7_0_hw_fini - stop the hardware block
600 *
601 * @adev: amdgpu_device pointer
602 *
603 * Stop the UVD block, mark ring as not ready any more
604 */
uvd_v7_0_hw_fini(void * handle)605 static int uvd_v7_0_hw_fini(void *handle)
606 {
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608 int i;
609
610 if (!amdgpu_sriov_vf(adev))
611 uvd_v7_0_stop(adev);
612 else {
613 /* full access mode, so don't touch any UVD register */
614 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
615 }
616
617 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
618 if (adev->uvd.harvest_config & (1 << i))
619 continue;
620 adev->uvd.inst[i].ring.sched.ready = false;
621 }
622
623 return 0;
624 }
625
uvd_v7_0_suspend(void * handle)626 static int uvd_v7_0_suspend(void *handle)
627 {
628 int r;
629 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
630
631 r = uvd_v7_0_hw_fini(adev);
632 if (r)
633 return r;
634
635 return amdgpu_uvd_suspend(adev);
636 }
637
uvd_v7_0_resume(void * handle)638 static int uvd_v7_0_resume(void *handle)
639 {
640 int r;
641 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
642
643 r = amdgpu_uvd_resume(adev);
644 if (r)
645 return r;
646
647 return uvd_v7_0_hw_init(adev);
648 }
649
650 /**
651 * uvd_v7_0_mc_resume - memory controller programming
652 *
653 * @adev: amdgpu_device pointer
654 *
655 * Let the UVD memory controller know it's offsets
656 */
uvd_v7_0_mc_resume(struct amdgpu_device * adev)657 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
658 {
659 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
660 uint32_t offset;
661 int i;
662
663 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
664 if (adev->uvd.harvest_config & (1 << i))
665 continue;
666 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
667 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
668 i == 0 ?
669 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
670 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
671 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
672 i == 0 ?
673 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
674 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
675 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
676 offset = 0;
677 } else {
678 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
679 lower_32_bits(adev->uvd.inst[i].gpu_addr));
680 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
681 upper_32_bits(adev->uvd.inst[i].gpu_addr));
682 offset = size;
683 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
684 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
685 }
686
687 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
688
689 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
690 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
691 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
692 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
693 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
695
696 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
697 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
698 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
699 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
700 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
701 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
702 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
703
704 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
705 adev->gfx.config.gb_addr_config);
706 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
707 adev->gfx.config.gb_addr_config);
708 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
709 adev->gfx.config.gb_addr_config);
710
711 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
712 }
713 }
714
uvd_v7_0_mmsch_start(struct amdgpu_device * adev,struct amdgpu_mm_table * table)715 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
716 struct amdgpu_mm_table *table)
717 {
718 uint32_t data = 0, loop;
719 uint64_t addr = table->gpu_addr;
720 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
721 uint32_t size;
722 int i;
723
724 size = header->header_size + header->vce_table_size + header->uvd_table_size;
725
726 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
727 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
728 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
729
730 /* 2, update vmid of descriptor */
731 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
732 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
733 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
734 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
735
736 /* 3, notify mmsch about the size of this descriptor */
737 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
738
739 /* 4, set resp to zero */
740 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
741
742 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
743 if (adev->uvd.harvest_config & (1 << i))
744 continue;
745 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
746 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
747 adev->uvd.inst[i].ring_enc[0].wptr = 0;
748 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
749 }
750 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
751 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
752
753 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
754 loop = 1000;
755 while ((data & 0x10000002) != 0x10000002) {
756 udelay(10);
757 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
758 loop--;
759 if (!loop)
760 break;
761 }
762
763 if (!loop) {
764 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
765 return -EBUSY;
766 }
767
768 return 0;
769 }
770
uvd_v7_0_sriov_start(struct amdgpu_device * adev)771 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
772 {
773 struct amdgpu_ring *ring;
774 uint32_t offset, size, tmp;
775 uint32_t table_size = 0;
776 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
777 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
778 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
779 struct mmsch_v1_0_cmd_end end = { {0} };
780 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
781 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
782 uint8_t i = 0;
783
784 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
785 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
786 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
787 end.cmd_header.command_type = MMSCH_COMMAND__END;
788
789 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
790 header->version = MMSCH_VERSION;
791 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
792
793 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
794 header->uvd_table_offset = header->header_size;
795 else
796 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
797
798 init_table += header->uvd_table_offset;
799
800 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
801 if (adev->uvd.harvest_config & (1 << i))
802 continue;
803 ring = &adev->uvd.inst[i].ring;
804 ring->wptr = 0;
805 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
806
807 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
808 0xFFFFFFFF, 0x00000004);
809 /* mc resume*/
810 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
811 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
812 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
813 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo);
814 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
815 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
816 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi);
817 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
818 offset = 0;
819 } else {
820 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
821 lower_32_bits(adev->uvd.inst[i].gpu_addr));
822 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
823 upper_32_bits(adev->uvd.inst[i].gpu_addr));
824 offset = size;
825 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
826 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
827
828 }
829
830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
831
832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
833 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
834 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
835 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
836 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
838
839 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
840 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
842 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
843 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
844 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
845 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
846
847 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
848 /* mc resume end*/
849
850 /* disable clock gating */
851 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
852 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
853
854 /* disable interupt */
855 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
856 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
857
858 /* stall UMC and register bus before resetting VCPU */
859 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
860 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
861 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
862
863 /* put LMI, VCPU, RBC etc... into reset */
864 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
865 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
866 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
867 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
868 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
869 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
870 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
871 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
872 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
873
874 /* initialize UVD memory controller */
875 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
876 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
877 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
878 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
879 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
880 UVD_LMI_CTRL__REQ_MODE_MASK |
881 0x00100000L));
882
883 /* take all subblocks out of reset, except VCPU */
884 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
885 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
886
887 /* enable VCPU clock */
888 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
889 UVD_VCPU_CNTL__CLK_EN_MASK);
890
891 /* enable master interrupt */
892 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
893 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
894 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
895
896 /* clear the bit 4 of UVD_STATUS */
897 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
898 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
899
900 /* force RBC into idle state */
901 size = order_base_2(ring->ring_size);
902 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
903 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
904 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
905
906 ring = &adev->uvd.inst[i].ring_enc[0];
907 ring->wptr = 0;
908 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
909 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
910 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
911
912 /* boot up the VCPU */
913 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
914
915 /* enable UMC */
916 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
917 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
918
919 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
920 }
921 /* add end packet */
922 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
923 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
924 header->uvd_table_size = table_size;
925
926 }
927 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
928 }
929
930 /**
931 * uvd_v7_0_start - start UVD block
932 *
933 * @adev: amdgpu_device pointer
934 *
935 * Setup and start the UVD block
936 */
uvd_v7_0_start(struct amdgpu_device * adev)937 static int uvd_v7_0_start(struct amdgpu_device *adev)
938 {
939 struct amdgpu_ring *ring;
940 uint32_t rb_bufsz, tmp;
941 uint32_t lmi_swap_cntl;
942 uint32_t mp_swap_cntl;
943 int i, j, k, r;
944
945 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
946 if (adev->uvd.harvest_config & (1 << k))
947 continue;
948 /* disable DPG */
949 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
950 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
951 }
952
953 /* disable byte swapping */
954 lmi_swap_cntl = 0;
955 mp_swap_cntl = 0;
956
957 uvd_v7_0_mc_resume(adev);
958
959 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
960 if (adev->uvd.harvest_config & (1 << k))
961 continue;
962 ring = &adev->uvd.inst[k].ring;
963 /* disable clock gating */
964 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
965 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
966
967 /* disable interupt */
968 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
969 ~UVD_MASTINT_EN__VCPU_EN_MASK);
970
971 /* stall UMC and register bus before resetting VCPU */
972 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
973 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
974 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
975 mdelay(1);
976
977 /* put LMI, VCPU, RBC etc... into reset */
978 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
979 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
980 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
981 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
982 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
983 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
984 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
985 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
986 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
987 mdelay(5);
988
989 /* initialize UVD memory controller */
990 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
991 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
993 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
994 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
995 UVD_LMI_CTRL__REQ_MODE_MASK |
996 0x00100000L);
997
998 #ifdef __BIG_ENDIAN
999 /* swap (8 in 32) RB and IB */
1000 lmi_swap_cntl = 0xa;
1001 mp_swap_cntl = 0;
1002 #endif
1003 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1004 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
1005
1006 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
1007 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
1008 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
1009 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
1010 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
1011 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
1012
1013 /* take all subblocks out of reset, except VCPU */
1014 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
1015 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1016 mdelay(5);
1017
1018 /* enable VCPU clock */
1019 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1020 UVD_VCPU_CNTL__CLK_EN_MASK);
1021
1022 /* enable UMC */
1023 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
1024 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1025
1026 /* boot up the VCPU */
1027 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
1028 mdelay(10);
1029
1030 for (i = 0; i < 10; ++i) {
1031 uint32_t status;
1032
1033 for (j = 0; j < 100; ++j) {
1034 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1035 if (status & 2)
1036 break;
1037 mdelay(10);
1038 }
1039 r = 0;
1040 if (status & 2)
1041 break;
1042
1043 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1044 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1045 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1046 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1047 mdelay(10);
1048 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1049 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1050 mdelay(10);
1051 r = -1;
1052 }
1053
1054 if (r) {
1055 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1056 return r;
1057 }
1058 /* enable master interrupt */
1059 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1060 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1061 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1062
1063 /* clear the bit 4 of UVD_STATUS */
1064 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1065 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1066
1067 /* force RBC into idle state */
1068 rb_bufsz = order_base_2(ring->ring_size);
1069 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1070 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1071 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1072 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1073 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1074 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1075 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1076
1077 /* set the write pointer delay */
1078 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1079
1080 /* set the wb address */
1081 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1082 (upper_32_bits(ring->gpu_addr) >> 2));
1083
1084 /* programm the RB_BASE for ring buffer */
1085 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1086 lower_32_bits(ring->gpu_addr));
1087 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1088 upper_32_bits(ring->gpu_addr));
1089
1090 /* Initialize the ring buffer's read and write pointers */
1091 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1092
1093 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1095 lower_32_bits(ring->wptr));
1096
1097 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1098 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1099
1100 ring = &adev->uvd.inst[k].ring_enc[0];
1101 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1102 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1103 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1104 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1105 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1106
1107 ring = &adev->uvd.inst[k].ring_enc[1];
1108 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1109 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1110 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1111 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1112 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1113 }
1114 return 0;
1115 }
1116
1117 /**
1118 * uvd_v7_0_stop - stop UVD block
1119 *
1120 * @adev: amdgpu_device pointer
1121 *
1122 * stop the UVD block
1123 */
uvd_v7_0_stop(struct amdgpu_device * adev)1124 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1125 {
1126 uint8_t i = 0;
1127
1128 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1129 if (adev->uvd.harvest_config & (1 << i))
1130 continue;
1131 /* force RBC into idle state */
1132 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1133
1134 /* Stall UMC and register bus before resetting VCPU */
1135 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1136 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1137 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1138 mdelay(1);
1139
1140 /* put VCPU into reset */
1141 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1142 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1143 mdelay(5);
1144
1145 /* disable VCPU clock */
1146 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1147
1148 /* Unstall UMC and register bus */
1149 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1150 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1151 }
1152 }
1153
1154 /**
1155 * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1156 *
1157 * @ring: amdgpu_ring pointer
1158 * @fence: fence to emit
1159 *
1160 * Write a fence and a trap command to the ring.
1161 */
uvd_v7_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1162 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1163 unsigned flags)
1164 {
1165 struct amdgpu_device *adev = ring->adev;
1166
1167 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1168
1169 amdgpu_ring_write(ring,
1170 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1171 amdgpu_ring_write(ring, seq);
1172 amdgpu_ring_write(ring,
1173 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1174 amdgpu_ring_write(ring, addr & 0xffffffff);
1175 amdgpu_ring_write(ring,
1176 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1177 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1178 amdgpu_ring_write(ring,
1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1180 amdgpu_ring_write(ring, 0);
1181
1182 amdgpu_ring_write(ring,
1183 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1184 amdgpu_ring_write(ring, 0);
1185 amdgpu_ring_write(ring,
1186 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1187 amdgpu_ring_write(ring, 0);
1188 amdgpu_ring_write(ring,
1189 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1190 amdgpu_ring_write(ring, 2);
1191 }
1192
1193 /**
1194 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1195 *
1196 * @ring: amdgpu_ring pointer
1197 * @fence: fence to emit
1198 *
1199 * Write enc a fence and a trap command to the ring.
1200 */
uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1201 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1202 u64 seq, unsigned flags)
1203 {
1204
1205 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1206
1207 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1208 amdgpu_ring_write(ring, addr);
1209 amdgpu_ring_write(ring, upper_32_bits(addr));
1210 amdgpu_ring_write(ring, seq);
1211 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1212 }
1213
1214 /**
1215 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1216 *
1217 * @ring: amdgpu_ring pointer
1218 */
uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)1219 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1220 {
1221 /* The firmware doesn't seem to like touching registers at this point. */
1222 }
1223
1224 /**
1225 * uvd_v7_0_ring_test_ring - register write test
1226 *
1227 * @ring: amdgpu_ring pointer
1228 *
1229 * Test if we can successfully write to the context register
1230 */
uvd_v7_0_ring_test_ring(struct amdgpu_ring * ring)1231 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1232 {
1233 struct amdgpu_device *adev = ring->adev;
1234 uint32_t tmp = 0;
1235 unsigned i;
1236 int r;
1237
1238 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1239 r = amdgpu_ring_alloc(ring, 3);
1240 if (r)
1241 return r;
1242
1243 amdgpu_ring_write(ring,
1244 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1245 amdgpu_ring_write(ring, 0xDEADBEEF);
1246 amdgpu_ring_commit(ring);
1247 for (i = 0; i < adev->usec_timeout; i++) {
1248 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1249 if (tmp == 0xDEADBEEF)
1250 break;
1251 udelay(1);
1252 }
1253
1254 if (i >= adev->usec_timeout)
1255 r = -ETIMEDOUT;
1256
1257 return r;
1258 }
1259
1260 /**
1261 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
1262 *
1263 * @p: the CS parser with the IBs
1264 * @ib_idx: which IB to patch
1265 *
1266 */
uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser * p,uint32_t ib_idx)1267 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1268 uint32_t ib_idx)
1269 {
1270 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1271 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1272 unsigned i;
1273
1274 /* No patching necessary for the first instance */
1275 if (!ring->me)
1276 return 0;
1277
1278 for (i = 0; i < ib->length_dw; i += 2) {
1279 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1280
1281 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1282 reg += p->adev->reg_offset[UVD_HWIP][1][1];
1283
1284 amdgpu_set_ib_value(p, ib_idx, i, reg);
1285 }
1286 return 0;
1287 }
1288
1289 /**
1290 * uvd_v7_0_ring_emit_ib - execute indirect buffer
1291 *
1292 * @ring: amdgpu_ring pointer
1293 * @ib: indirect buffer to execute
1294 *
1295 * Write ring commands to execute the indirect buffer
1296 */
uvd_v7_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1297 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1298 struct amdgpu_job *job,
1299 struct amdgpu_ib *ib,
1300 uint32_t flags)
1301 {
1302 struct amdgpu_device *adev = ring->adev;
1303 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1304
1305 amdgpu_ring_write(ring,
1306 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1307 amdgpu_ring_write(ring, vmid);
1308
1309 amdgpu_ring_write(ring,
1310 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1311 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1312 amdgpu_ring_write(ring,
1313 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1314 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1315 amdgpu_ring_write(ring,
1316 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1317 amdgpu_ring_write(ring, ib->length_dw);
1318 }
1319
1320 /**
1321 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1322 *
1323 * @ring: amdgpu_ring pointer
1324 * @ib: indirect buffer to execute
1325 *
1326 * Write enc ring commands to execute the indirect buffer
1327 */
uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1328 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1329 struct amdgpu_job *job,
1330 struct amdgpu_ib *ib,
1331 uint32_t flags)
1332 {
1333 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1334
1335 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1336 amdgpu_ring_write(ring, vmid);
1337 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1338 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1339 amdgpu_ring_write(ring, ib->length_dw);
1340 }
1341
uvd_v7_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1342 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1343 uint32_t reg, uint32_t val)
1344 {
1345 struct amdgpu_device *adev = ring->adev;
1346
1347 amdgpu_ring_write(ring,
1348 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1349 amdgpu_ring_write(ring, reg << 2);
1350 amdgpu_ring_write(ring,
1351 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1352 amdgpu_ring_write(ring, val);
1353 amdgpu_ring_write(ring,
1354 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1355 amdgpu_ring_write(ring, 8);
1356 }
1357
uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1358 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1359 uint32_t val, uint32_t mask)
1360 {
1361 struct amdgpu_device *adev = ring->adev;
1362
1363 amdgpu_ring_write(ring,
1364 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1365 amdgpu_ring_write(ring, reg << 2);
1366 amdgpu_ring_write(ring,
1367 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1368 amdgpu_ring_write(ring, val);
1369 amdgpu_ring_write(ring,
1370 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1371 amdgpu_ring_write(ring, mask);
1372 amdgpu_ring_write(ring,
1373 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1374 amdgpu_ring_write(ring, 12);
1375 }
1376
uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1377 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1378 unsigned vmid, uint64_t pd_addr)
1379 {
1380 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1381 uint32_t data0, data1, mask;
1382
1383 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1384
1385 /* wait for reg writes */
1386 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1387 data1 = lower_32_bits(pd_addr);
1388 mask = 0xffffffff;
1389 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1390 }
1391
uvd_v7_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1392 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1393 {
1394 struct amdgpu_device *adev = ring->adev;
1395 int i;
1396
1397 WARN_ON(ring->wptr % 2 || count % 2);
1398
1399 for (i = 0; i < count / 2; i++) {
1400 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1401 amdgpu_ring_write(ring, 0);
1402 }
1403 }
1404
uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring * ring)1405 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1406 {
1407 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1408 }
1409
uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1410 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1411 uint32_t reg, uint32_t val,
1412 uint32_t mask)
1413 {
1414 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1415 amdgpu_ring_write(ring, reg << 2);
1416 amdgpu_ring_write(ring, mask);
1417 amdgpu_ring_write(ring, val);
1418 }
1419
uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1420 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1421 unsigned int vmid, uint64_t pd_addr)
1422 {
1423 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1424
1425 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1426
1427 /* wait for reg writes */
1428 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1429 lower_32_bits(pd_addr), 0xffffffff);
1430 }
1431
uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1432 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1433 uint32_t reg, uint32_t val)
1434 {
1435 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1436 amdgpu_ring_write(ring, reg << 2);
1437 amdgpu_ring_write(ring, val);
1438 }
1439
1440 #if 0
1441 static bool uvd_v7_0_is_idle(void *handle)
1442 {
1443 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444
1445 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1446 }
1447
1448 static int uvd_v7_0_wait_for_idle(void *handle)
1449 {
1450 unsigned i;
1451 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1452
1453 for (i = 0; i < adev->usec_timeout; i++) {
1454 if (uvd_v7_0_is_idle(handle))
1455 return 0;
1456 }
1457 return -ETIMEDOUT;
1458 }
1459
1460 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
1461 static bool uvd_v7_0_check_soft_reset(void *handle)
1462 {
1463 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1464 u32 srbm_soft_reset = 0;
1465 u32 tmp = RREG32(mmSRBM_STATUS);
1466
1467 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1468 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1469 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1470 AMDGPU_UVD_STATUS_BUSY_MASK))
1471 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1472 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1473
1474 if (srbm_soft_reset) {
1475 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1476 return true;
1477 } else {
1478 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1479 return false;
1480 }
1481 }
1482
1483 static int uvd_v7_0_pre_soft_reset(void *handle)
1484 {
1485 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1486
1487 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1488 return 0;
1489
1490 uvd_v7_0_stop(adev);
1491 return 0;
1492 }
1493
1494 static int uvd_v7_0_soft_reset(void *handle)
1495 {
1496 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1497 u32 srbm_soft_reset;
1498
1499 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1500 return 0;
1501 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1502
1503 if (srbm_soft_reset) {
1504 u32 tmp;
1505
1506 tmp = RREG32(mmSRBM_SOFT_RESET);
1507 tmp |= srbm_soft_reset;
1508 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1509 WREG32(mmSRBM_SOFT_RESET, tmp);
1510 tmp = RREG32(mmSRBM_SOFT_RESET);
1511
1512 udelay(50);
1513
1514 tmp &= ~srbm_soft_reset;
1515 WREG32(mmSRBM_SOFT_RESET, tmp);
1516 tmp = RREG32(mmSRBM_SOFT_RESET);
1517
1518 /* Wait a little for things to settle down */
1519 udelay(50);
1520 }
1521
1522 return 0;
1523 }
1524
1525 static int uvd_v7_0_post_soft_reset(void *handle)
1526 {
1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1528
1529 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1530 return 0;
1531
1532 mdelay(5);
1533
1534 return uvd_v7_0_start(adev);
1535 }
1536 #endif
1537
uvd_v7_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1538 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1539 struct amdgpu_irq_src *source,
1540 unsigned type,
1541 enum amdgpu_interrupt_state state)
1542 {
1543 // TODO
1544 return 0;
1545 }
1546
uvd_v7_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1547 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1548 struct amdgpu_irq_src *source,
1549 struct amdgpu_iv_entry *entry)
1550 {
1551 uint32_t ip_instance;
1552
1553 switch (entry->client_id) {
1554 case SOC15_IH_CLIENTID_UVD:
1555 ip_instance = 0;
1556 break;
1557 case SOC15_IH_CLIENTID_UVD1:
1558 ip_instance = 1;
1559 break;
1560 default:
1561 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1562 return 0;
1563 }
1564
1565 DRM_DEBUG("IH: UVD TRAP\n");
1566
1567 switch (entry->src_id) {
1568 case 124:
1569 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1570 break;
1571 case 119:
1572 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1573 break;
1574 case 120:
1575 if (!amdgpu_sriov_vf(adev))
1576 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1577 break;
1578 default:
1579 DRM_ERROR("Unhandled interrupt: %d %d\n",
1580 entry->src_id, entry->src_data[0]);
1581 break;
1582 }
1583
1584 return 0;
1585 }
1586
1587 #if 0
1588 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1589 {
1590 uint32_t data, data1, data2, suvd_flags;
1591
1592 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1593 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1594 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1595
1596 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1597 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1598
1599 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1600 UVD_SUVD_CGC_GATE__SIT_MASK |
1601 UVD_SUVD_CGC_GATE__SMP_MASK |
1602 UVD_SUVD_CGC_GATE__SCM_MASK |
1603 UVD_SUVD_CGC_GATE__SDB_MASK;
1604
1605 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1606 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1607 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1608
1609 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1610 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1611 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1612 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1613 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1614 UVD_CGC_CTRL__SYS_MODE_MASK |
1615 UVD_CGC_CTRL__UDEC_MODE_MASK |
1616 UVD_CGC_CTRL__MPEG2_MODE_MASK |
1617 UVD_CGC_CTRL__REGS_MODE_MASK |
1618 UVD_CGC_CTRL__RBC_MODE_MASK |
1619 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1620 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1621 UVD_CGC_CTRL__IDCT_MODE_MASK |
1622 UVD_CGC_CTRL__MPRD_MODE_MASK |
1623 UVD_CGC_CTRL__MPC_MODE_MASK |
1624 UVD_CGC_CTRL__LBSI_MODE_MASK |
1625 UVD_CGC_CTRL__LRBBM_MODE_MASK |
1626 UVD_CGC_CTRL__WCB_MODE_MASK |
1627 UVD_CGC_CTRL__VCPU_MODE_MASK |
1628 UVD_CGC_CTRL__JPEG_MODE_MASK |
1629 UVD_CGC_CTRL__JPEG2_MODE_MASK |
1630 UVD_CGC_CTRL__SCPU_MODE_MASK);
1631 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1632 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1633 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1634 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1635 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1636 data1 |= suvd_flags;
1637
1638 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1639 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1640 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1641 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1642 }
1643
1644 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1645 {
1646 uint32_t data, data1, cgc_flags, suvd_flags;
1647
1648 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1649 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1650
1651 cgc_flags = UVD_CGC_GATE__SYS_MASK |
1652 UVD_CGC_GATE__UDEC_MASK |
1653 UVD_CGC_GATE__MPEG2_MASK |
1654 UVD_CGC_GATE__RBC_MASK |
1655 UVD_CGC_GATE__LMI_MC_MASK |
1656 UVD_CGC_GATE__IDCT_MASK |
1657 UVD_CGC_GATE__MPRD_MASK |
1658 UVD_CGC_GATE__MPC_MASK |
1659 UVD_CGC_GATE__LBSI_MASK |
1660 UVD_CGC_GATE__LRBBM_MASK |
1661 UVD_CGC_GATE__UDEC_RE_MASK |
1662 UVD_CGC_GATE__UDEC_CM_MASK |
1663 UVD_CGC_GATE__UDEC_IT_MASK |
1664 UVD_CGC_GATE__UDEC_DB_MASK |
1665 UVD_CGC_GATE__UDEC_MP_MASK |
1666 UVD_CGC_GATE__WCB_MASK |
1667 UVD_CGC_GATE__VCPU_MASK |
1668 UVD_CGC_GATE__SCPU_MASK |
1669 UVD_CGC_GATE__JPEG_MASK |
1670 UVD_CGC_GATE__JPEG2_MASK;
1671
1672 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1673 UVD_SUVD_CGC_GATE__SIT_MASK |
1674 UVD_SUVD_CGC_GATE__SMP_MASK |
1675 UVD_SUVD_CGC_GATE__SCM_MASK |
1676 UVD_SUVD_CGC_GATE__SDB_MASK;
1677
1678 data |= cgc_flags;
1679 data1 |= suvd_flags;
1680
1681 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1682 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1683 }
1684
1685 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1686 {
1687 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1688
1689 if (enable)
1690 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1691 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1692 else
1693 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1694 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1695
1696 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1697 }
1698
1699
1700 static int uvd_v7_0_set_clockgating_state(void *handle,
1701 enum amd_clockgating_state state)
1702 {
1703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1704 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1705
1706 uvd_v7_0_set_bypass_mode(adev, enable);
1707
1708 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1709 return 0;
1710
1711 if (enable) {
1712 /* disable HW gating and enable Sw gating */
1713 uvd_v7_0_set_sw_clock_gating(adev);
1714 } else {
1715 /* wait for STATUS to clear */
1716 if (uvd_v7_0_wait_for_idle(handle))
1717 return -EBUSY;
1718
1719 /* enable HW gates because UVD is idle */
1720 /* uvd_v7_0_set_hw_clock_gating(adev); */
1721 }
1722
1723 return 0;
1724 }
1725
1726 static int uvd_v7_0_set_powergating_state(void *handle,
1727 enum amd_powergating_state state)
1728 {
1729 /* This doesn't actually powergate the UVD block.
1730 * That's done in the dpm code via the SMC. This
1731 * just re-inits the block as necessary. The actual
1732 * gating still happens in the dpm code. We should
1733 * revisit this when there is a cleaner line between
1734 * the smc and the hw blocks
1735 */
1736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1737
1738 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1739 return 0;
1740
1741 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1742
1743 if (state == AMD_PG_STATE_GATE) {
1744 uvd_v7_0_stop(adev);
1745 return 0;
1746 } else {
1747 return uvd_v7_0_start(adev);
1748 }
1749 }
1750 #endif
1751
uvd_v7_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1752 static int uvd_v7_0_set_clockgating_state(void *handle,
1753 enum amd_clockgating_state state)
1754 {
1755 /* needed for driver unload*/
1756 return 0;
1757 }
1758
1759 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1760 .name = "uvd_v7_0",
1761 .early_init = uvd_v7_0_early_init,
1762 .late_init = NULL,
1763 .sw_init = uvd_v7_0_sw_init,
1764 .sw_fini = uvd_v7_0_sw_fini,
1765 .hw_init = uvd_v7_0_hw_init,
1766 .hw_fini = uvd_v7_0_hw_fini,
1767 .suspend = uvd_v7_0_suspend,
1768 .resume = uvd_v7_0_resume,
1769 .is_idle = NULL /* uvd_v7_0_is_idle */,
1770 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1771 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1772 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1773 .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1774 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1775 .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1776 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1777 };
1778
1779 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1780 .type = AMDGPU_RING_TYPE_UVD,
1781 .align_mask = 0xf,
1782 .support_64bit_ptrs = false,
1783 .no_user_fence = true,
1784 .vmhub = AMDGPU_MMHUB_0,
1785 .get_rptr = uvd_v7_0_ring_get_rptr,
1786 .get_wptr = uvd_v7_0_ring_get_wptr,
1787 .set_wptr = uvd_v7_0_ring_set_wptr,
1788 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
1789 .emit_frame_size =
1790 6 + /* hdp invalidate */
1791 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1792 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1793 8 + /* uvd_v7_0_ring_emit_vm_flush */
1794 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1795 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1796 .emit_ib = uvd_v7_0_ring_emit_ib,
1797 .emit_fence = uvd_v7_0_ring_emit_fence,
1798 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1799 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1800 .test_ring = uvd_v7_0_ring_test_ring,
1801 .test_ib = amdgpu_uvd_ring_test_ib,
1802 .insert_nop = uvd_v7_0_ring_insert_nop,
1803 .pad_ib = amdgpu_ring_generic_pad_ib,
1804 .begin_use = amdgpu_uvd_ring_begin_use,
1805 .end_use = amdgpu_uvd_ring_end_use,
1806 .emit_wreg = uvd_v7_0_ring_emit_wreg,
1807 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1808 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1809 };
1810
1811 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1812 .type = AMDGPU_RING_TYPE_UVD_ENC,
1813 .align_mask = 0x3f,
1814 .nop = HEVC_ENC_CMD_NO_OP,
1815 .support_64bit_ptrs = false,
1816 .no_user_fence = true,
1817 .vmhub = AMDGPU_MMHUB_0,
1818 .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1819 .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1820 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1821 .emit_frame_size =
1822 3 + 3 + /* hdp flush / invalidate */
1823 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1824 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1825 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1826 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1827 1, /* uvd_v7_0_enc_ring_insert_end */
1828 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1829 .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1830 .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1831 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1832 .test_ring = uvd_v7_0_enc_ring_test_ring,
1833 .test_ib = uvd_v7_0_enc_ring_test_ib,
1834 .insert_nop = amdgpu_ring_insert_nop,
1835 .insert_end = uvd_v7_0_enc_ring_insert_end,
1836 .pad_ib = amdgpu_ring_generic_pad_ib,
1837 .begin_use = amdgpu_uvd_ring_begin_use,
1838 .end_use = amdgpu_uvd_ring_end_use,
1839 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1840 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1841 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1842 };
1843
uvd_v7_0_set_ring_funcs(struct amdgpu_device * adev)1844 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1845 {
1846 int i;
1847
1848 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1849 if (adev->uvd.harvest_config & (1 << i))
1850 continue;
1851 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1852 adev->uvd.inst[i].ring.me = i;
1853 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1854 }
1855 }
1856
uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device * adev)1857 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1858 {
1859 int i, j;
1860
1861 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1862 if (adev->uvd.harvest_config & (1 << j))
1863 continue;
1864 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1865 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1866 adev->uvd.inst[j].ring_enc[i].me = j;
1867 }
1868
1869 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1870 }
1871 }
1872
1873 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1874 .set = uvd_v7_0_set_interrupt_state,
1875 .process = uvd_v7_0_process_interrupt,
1876 };
1877
uvd_v7_0_set_irq_funcs(struct amdgpu_device * adev)1878 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1879 {
1880 int i;
1881
1882 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1883 if (adev->uvd.harvest_config & (1 << i))
1884 continue;
1885 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1886 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1887 }
1888 }
1889
1890 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1891 {
1892 .type = AMD_IP_BLOCK_TYPE_UVD,
1893 .major = 7,
1894 .minor = 0,
1895 .rev = 0,
1896 .funcs = &uvd_v7_0_ip_funcs,
1897 };
1898