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Searched refs:vsrd (Results 1 – 16 of 16) sorted by relevance

/llvm-project/llvm/test/MC/VE/
H A DVSRD.s6 # CHECK-INST: vsrd %v11, (%v22, %v23), %s20
8 vsrd %v11, (%v22, %v23), %s20 label
10 # CHECK-INST: vsrd %vix, (%vix, %vix), %s23
12 vsrd %vix, (%vix, %vix), %s23 label
14 # CHECK-INST: vsrd %vix, (%v22, %v30), 22
16 vsrd %vix, (%v22, %v30), 22 label
18 # CHECK-INST: vsrd %v11, (%v22, %vix), 127, %vm11
20 vsrd %v11, (%v22, %vix), 127, %vm11 label
22 # CHECK-INST: vsrd %v11, (%vix, %v22), 21, %vm11
24 vsrd %v11, (%vix, %v22), 21, %vm11 label
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dvec-intrinsics-03.ll7 declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32)
41 ; CHECK-NEXT: vsrd %v24, %v24, %v26, 1
43 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 1)
51 ; CHECK-NEXT: vsrd %v24, %v24, %v26, 7
53 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 7)
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dvec_rotate_shift.ll7 declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone
27 ; CHECK: vsrd 2, 2, 3
H A Dpr47891.ll28 ; CHECK-NEXT: vsrd v3, v3, v4
H A Dshift_mask.ll168 ; CHECK-NEXT: vsrd 2, 2, 3
H A Dvsx.ll1904 ; CHECK-LE-NEXT: vsrd v2, v2, v3
/llvm-project/llvm/test/MC/SystemZ/
H A Dinsn-good-z15.s956 #CHECK: vsrd %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x87]
957 #CHECK: vsrd %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x00,0x87]
958 #CHECK: vsrd %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x87]
959 #CHECK: vsrd %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x87]
960 #CHECK: vsrd %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x87]
961 #CHECK: vsrd %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x87]
963 vsrd %v0, %v0, %v0, 0
964 vsrd %v0, %v0, %v0, 255
965 vsrd %v0, %v0, %v31, 0
966 vsrd
[all...]
H A Dinsn-bad-z15.s650 #CHECK: vsrd %v0, %v0, %v0, -1
652 #CHECK: vsrd %v0, %v0, %v0, 256
654 vsrd %v0, %v0, %v0, -1
655 vsrd %v0, %v0, %v0, 256
H A Dinsn-bad-z14.s783 #CHECK: vsrd %v0, %v0, %v0, 0
785 vsrd %v0, %v0, %v0, 0
/llvm-project/llvm/test/MC/Disassembler/SystemZ/
H A Dinsns-z15.txt974 # CHECK: vsrd %v0, %v0, %v0, 0
977 # CHECK: vsrd %v0, %v0, %v0, 255
980 # CHECK: vsrd %v0, %v0, %v31, 0
983 # CHECK: vsrd %v0, %v31, %v0, 0
986 # CHECK: vsrd %v31, %v0, %v0, 0
989 # CHECK: vsrd %v13, %v17, %v21, 121
/llvm-project/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s604 # CHECK-BE: vsrd 2, 3, 4 # encoding: [0x10,0x43,0x26,0xc4]
605 # CHECK-LE: vsrd 2, 3, 4 # encoding: [0xc4,0x26,0x43,0x10]
606 vsrd 2, 3, 4
/llvm-project/llvm/test/Verifier/SystemZ/
H A Dintrinsic-immarg.ll393 declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32)
397 ; CHECK-NEXT: %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 %c)
398 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 %c)
/llvm-project/llvm/test/MC/Disassembler/PowerPC/
H A Dppc64-encoding-vmx.txt549 # CHECK: vsrd 2, 3, 4
/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td1065 defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM>;
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td1245 "vsrd $VD, $VA, $VB", IIC_VecGeneral, []>;
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td998 def VSRD : TernaryVRId<"vsrd", 0xE787, int_s390_vsrd, v128b, v128b, 0>;