xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr47891.ll (revision 032014ef103157bfd8403418538e25f3f58efa9d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
4%struct.poly2 = type { [11 x i64] }
5
6; Function Attrs: nofree norecurse nounwind
7define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
8; CHECK-LABEL: poly2_lshift1:
9; CHECK:       # %bb.0: # %entry
10; CHECK-NEXT:    li r4, 72
11; CHECK-NEXT:    addis r6, r2, .LCPI0_1@toc@ha
12; CHECK-NEXT:    ld r5, 64(r3)
13; CHECK-NEXT:    lxvd2x vs0, r3, r4
14; CHECK-NEXT:    addi r6, r6, .LCPI0_1@toc@l
15; CHECK-NEXT:    lxvd2x v4, 0, r6
16; CHECK-NEXT:    addis r6, r2, .LCPI0_0@toc@ha
17; CHECK-NEXT:    addi r6, r6, .LCPI0_0@toc@l
18; CHECK-NEXT:    xxswapd v2, vs0
19; CHECK-NEXT:    mtfprd f0, r5
20; CHECK-NEXT:    xxpermdi v3, v2, vs0, 2
21; CHECK-NEXT:    vsld v2, v2, v4
22; CHECK-NEXT:    lxvd2x v4, 0, r6
23; CHECK-NEXT:    ld r6, 0(r3)
24; CHECK-NEXT:    sldi r7, r6, 1
25; CHECK-NEXT:    rotldi r6, r6, 1
26; CHECK-NEXT:    std r7, 0(r3)
27; CHECK-NEXT:    ld r7, 8(r3)
28; CHECK-NEXT:    vsrd v3, v3, v4
29; CHECK-NEXT:    xxlor vs0, v2, v3
30; CHECK-NEXT:    rldimi r6, r7, 1, 0
31; CHECK-NEXT:    rotldi r7, r7, 1
32; CHECK-NEXT:    std r6, 8(r3)
33; CHECK-NEXT:    ld r6, 16(r3)
34; CHECK-NEXT:    rldimi r7, r6, 1, 0
35; CHECK-NEXT:    rotldi r6, r6, 1
36; CHECK-NEXT:    std r7, 16(r3)
37; CHECK-NEXT:    ld r7, 24(r3)
38; CHECK-NEXT:    rldimi r6, r7, 1, 0
39; CHECK-NEXT:    rotldi r7, r7, 1
40; CHECK-NEXT:    std r6, 24(r3)
41; CHECK-NEXT:    ld r6, 32(r3)
42; CHECK-NEXT:    rldimi r7, r6, 1, 0
43; CHECK-NEXT:    rotldi r6, r6, 1
44; CHECK-NEXT:    std r7, 32(r3)
45; CHECK-NEXT:    ld r7, 40(r3)
46; CHECK-NEXT:    rldimi r6, r7, 1, 0
47; CHECK-NEXT:    rotldi r7, r7, 1
48; CHECK-NEXT:    std r6, 40(r3)
49; CHECK-NEXT:    ld r6, 48(r3)
50; CHECK-NEXT:    rldimi r7, r6, 1, 0
51; CHECK-NEXT:    rotldi r6, r6, 1
52; CHECK-NEXT:    std r7, 48(r3)
53; CHECK-NEXT:    ld r7, 56(r3)
54; CHECK-NEXT:    rldimi r6, r7, 1, 0
55; CHECK-NEXT:    std r6, 56(r3)
56; CHECK-NEXT:    rotldi r6, r7, 1
57; CHECK-NEXT:    xxswapd vs0, vs0
58; CHECK-NEXT:    stxvd2x vs0, r3, r4
59; CHECK-NEXT:    rldimi r6, r5, 1, 0
60; CHECK-NEXT:    std r6, 64(r3)
61; CHECK-NEXT:    blr
62entry:
63  %0 = load i64, ptr %p, align 8
64  %shl = shl i64 %0, 1
65  store i64 %shl, ptr %p, align 8
66  %arrayidx.1 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 1
67  %1 = load i64, ptr %arrayidx.1, align 8
68  %or.1 = call i64 @llvm.fshl.i64(i64 %1, i64 %0, i64 1)
69  store i64 %or.1, ptr %arrayidx.1, align 8
70  %arrayidx.2 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 2
71  %2 = load i64, ptr %arrayidx.2, align 8
72  %or.2 = call i64 @llvm.fshl.i64(i64 %2, i64 %1, i64 1)
73  store i64 %or.2, ptr %arrayidx.2, align 8
74  %arrayidx.3 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 3
75  %3 = load i64, ptr %arrayidx.3, align 8
76  %or.3 = call i64 @llvm.fshl.i64(i64 %3, i64 %2, i64 1)
77  store i64 %or.3, ptr %arrayidx.3, align 8
78  %arrayidx.4 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 4
79  %4 = load i64, ptr %arrayidx.4, align 8
80  %or.4 = call i64 @llvm.fshl.i64(i64 %4, i64 %3, i64 1)
81  store i64 %or.4, ptr %arrayidx.4, align 8
82  %arrayidx.5 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 5
83  %5 = load i64, ptr %arrayidx.5, align 8
84  %or.5 = call i64 @llvm.fshl.i64(i64 %5, i64 %4, i64 1)
85  store i64 %or.5, ptr %arrayidx.5, align 8
86  %arrayidx.6 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 6
87  %6 = load i64, ptr %arrayidx.6, align 8
88  %or.6 = call i64 @llvm.fshl.i64(i64 %6, i64 %5, i64 1)
89  store i64 %or.6, ptr %arrayidx.6, align 8
90  %arrayidx.7 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 7
91  %7 = load i64, ptr %arrayidx.7, align 8
92  %or.7 = call i64 @llvm.fshl.i64(i64 %7, i64 %6, i64 1)
93  store i64 %or.7, ptr %arrayidx.7, align 8
94  %arrayidx.8 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 8
95  %8 = load i64, ptr %arrayidx.8, align 8
96  %or.8 = call i64 @llvm.fshl.i64(i64 %8, i64 %7, i64 1)
97  store i64 %or.8, ptr %arrayidx.8, align 8
98  %arrayidx.9 = getelementptr inbounds %struct.poly2, ptr %p, i64 0, i32 0, i64 9
99  %9 = load <2 x i64>, ptr %arrayidx.9, align 8
100  %10 = insertelement <2 x i64> undef, i64 %8, i32 0
101  %11 = shufflevector <2 x i64> %10, <2 x i64> %9, <2 x i32> <i32 0, i32 2>
102  %12 = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %9, <2 x i64> %11, <2 x i64> <i64 1, i64 1>)
103  store <2 x i64> %12, ptr %arrayidx.9, align 8
104  ret void
105}
106
107; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
108declare i64 @llvm.fshl.i64(i64, i64, i64) #1
109
110; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
111declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) #1
112