1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Move instructions 11//===----------------------------------------------------------------------===// 12 13let Predicates = [FeatureVector] in { 14 // Register move. 15 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 16 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; 17 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 18 19 // Load GR from VR element. 20 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 21 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 22 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 23 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 24 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 25 26 // Load VR element from GR. 27 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 28 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 29 v128b, v128b, GR32, 0>; 30 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 31 v128h, v128h, GR32, 1>; 32 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 33 v128f, v128f, GR32, 2>; 34 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 35 v128g, v128g, GR64, 3>; 36 37 // Load VR from GRs disjoint. 38 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 39 def VLVGP32 : BinaryAliasVRRf<GR32>; 40} 41 42// Extractions always assign to the full GR64, even if the element would 43// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 44// subreg of the result. 45class VectorExtractSubreg<ValueType type, Instruction insn> 46 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 47 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 48 49def : VectorExtractSubreg<v16i8, VLGVB>; 50def : VectorExtractSubreg<v8i16, VLGVH>; 51def : VectorExtractSubreg<v4i32, VLGVF>; 52 53//===----------------------------------------------------------------------===// 54// Immediate instructions 55//===----------------------------------------------------------------------===// 56 57let Predicates = [FeatureVector] in { 58 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 59 60 // Generate byte mask. 61 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 62 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 63 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16_timm>; 64 65 // Generate mask. 66 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 67 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 68 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 69 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 70 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 71 72 // Replicate immediate. 73 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 74 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16_timm, 0>; 75 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16_timm, 1>; 76 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16_timm, 2>; 77 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16_timm, 3>; 78 } 79 80 // Load element immediate. 81 // 82 // We want these instructions to be used ahead of VLVG* where possible. 83 // However, VLVG* takes a variable BD-format index whereas VLEI takes 84 // a plain immediate index. This means that VLVG* has an extra "base" 85 // register operand and is 3 units more complex. Bumping the complexity 86 // of the VLEI* instructions by 4 means that they are strictly better 87 // than VLVG* in cases where both forms match. 88 let AddedComplexity = 4 in { 89 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 90 v128b, v128b, imm32sx16trunc, imm32zx4>; 91 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 92 v128h, v128h, imm32sx16trunc, imm32zx3>; 93 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 94 v128f, v128f, imm32sx16, imm32zx2>; 95 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 96 v128g, v128g, imm64sx16, imm32zx1>; 97 } 98} 99 100//===----------------------------------------------------------------------===// 101// Loads 102//===----------------------------------------------------------------------===// 103 104let Predicates = [FeatureVector] in { 105 // Load. 106 defm VL : UnaryVRXAlign<"vl", 0xE706>; 107 108 // Load to block boundary. The number of loaded bytes is only known 109 // at run time. The instruction is really polymorphic, but v128b matches 110 // the return type of the associated intrinsic. 111 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 112 113 // Load count to block boundary. 114 let Defs = [CC] in 115 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 116 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 117 "lcbb\t$R1, $XBD2, $M3", 118 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 119 imm32zx4_timm:$M3))]>; 120 121 // Load with length. The number of loaded bytes is only known at run time. 122 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 123 124 // Load multiple. 125 defm VLM : LoadMultipleVRSaAlign<"vlm", 0xE736>; 126 127 // Load and replicate 128 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 129 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 130 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 131 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 132 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 133 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 134 (VLREPF bdxaddr12only:$addr)>; 135 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 136 (VLREPG bdxaddr12only:$addr)>; 137 138 // Use VLREP to load subvectors. These patterns use "12pair" because 139 // LEY and LDY offer full 20-bit displacement fields. It's often better 140 // to use those instructions rather than force a 20-bit displacement 141 // into a GPR temporary. 142 let mayLoad = 1, canFoldAsLoad = 1 in { 143 def VL32 : UnaryAliasVRX<z_load, v32sb, bdxaddr12pair>; 144 def VL64 : UnaryAliasVRX<z_load, v64db, bdxaddr12pair>; 145 } 146 147 // Load logical element and zero. 148 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 149 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 150 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 151 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 152 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 153 def : Pat<(z_vllezf32 bdxaddr12only:$addr), 154 (VLLEZF bdxaddr12only:$addr)>; 155 def : Pat<(z_vllezf64 bdxaddr12only:$addr), 156 (VLLEZG bdxaddr12only:$addr)>; 157 let Predicates = [FeatureVectorEnhancements1] in { 158 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; 159 def : Pat<(z_vllezlf32 bdxaddr12only:$addr), 160 (VLLEZLF bdxaddr12only:$addr)>; 161 } 162 163 // Load element. 164 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 165 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 166 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 167 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 169 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 170 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 171 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 172 173 // Gather element. 174 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 175 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 176} 177 178let Predicates = [FeatureVectorPackedDecimal] in { 179 // Load rightmost with length. The number of loaded bytes is only known 180 // at run time. Note that while the instruction will accept immediate 181 // lengths larger that 15 at runtime, those will always result in a trap, 182 // so we never emit them here. 183 def VLRL : BinaryVSI<"vlrl", 0xE635, null_frag, 0>; 184 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; 185 def : Pat<(int_s390_vlrl imm32zx4:$len, bdaddr12only:$addr), 186 (VLRL bdaddr12only:$addr, imm32zx4:$len)>; 187} 188 189// Use replicating loads if we're inserting a single element into an 190// undefined vector. This avoids a false dependency on the previous 191// register contents. 192multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 193 SDPatternOperator load, ValueType scalartype> { 194 def : Pat<(vectype (z_vector_insert 195 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 196 (vlrep bdxaddr12only:$addr)>; 197 def : Pat<(vectype (scalar_to_vector 198 (scalartype (load bdxaddr12only:$addr)))), 199 (vlrep bdxaddr12only:$addr)>; 200} 201defm : ReplicatePeephole<VLREPB, v16i8, z_anyextloadi8, i32>; 202defm : ReplicatePeephole<VLREPH, v8i16, z_anyextloadi16, i32>; 203defm : ReplicatePeephole<VLREPF, v4i32, z_load, i32>; 204defm : ReplicatePeephole<VLREPG, v2i64, z_load, i64>; 205defm : ReplicatePeephole<VLREPF, v4f32, z_load, f32>; 206defm : ReplicatePeephole<VLREPG, v2f64, z_load, f64>; 207 208//===----------------------------------------------------------------------===// 209// Stores 210//===----------------------------------------------------------------------===// 211 212let Predicates = [FeatureVector] in { 213 // Store. 214 defm VST : StoreVRXAlign<"vst", 0xE70E>; 215 216 // Store with length. The number of stored bytes is only known at run time. 217 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 218 219 // Store multiple. 220 defm VSTM : StoreMultipleVRSaAlign<"vstm", 0xE73E>; 221 222 // Store element. 223 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 224 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 225 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 226 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 227 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 228 imm32zx2:$index), 229 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 230 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 231 imm32zx1:$index), 232 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 233 234 // Use VSTE to store subvectors. These patterns use "12pair" because 235 // STEY and STDY offer full 20-bit displacement fields. It's often better 236 // to use those instructions rather than force a 20-bit displacement 237 // into a GPR temporary. 238 let mayStore = 1 in { 239 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>; 240 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 241 } 242 243 // Scatter element. 244 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 245 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 246} 247 248let Predicates = [FeatureVectorPackedDecimal] in { 249 // Store rightmost with length. The number of stored bytes is only known 250 // at run time. Note that while the instruction will accept immediate 251 // lengths larger that 15 at runtime, those will always result in a trap, 252 // so we never emit them here. 253 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, null_frag, 0>; 254 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; 255 def : Pat<(int_s390_vstrl VR128:$val, imm32zx4:$len, bdaddr12only:$addr), 256 (VSTRL VR128:$val, bdaddr12only:$addr, imm32zx4:$len)>; 257} 258 259//===----------------------------------------------------------------------===// 260// Byte swaps 261//===----------------------------------------------------------------------===// 262 263let Predicates = [FeatureVectorEnhancements2] in { 264 // Load byte-reversed elements. 265 def VLBR : UnaryVRXGeneric<"vlbr", 0xE606>; 266 def VLBRH : UnaryVRX<"vlbrh", 0xE606, z_loadbswap, v128h, 16, 1>; 267 def VLBRF : UnaryVRX<"vlbrf", 0xE606, z_loadbswap, v128f, 16, 2>; 268 def VLBRG : UnaryVRX<"vlbrg", 0xE606, z_loadbswap, v128g, 16, 3>; 269 def VLBRQ : UnaryVRX<"vlbrq", 0xE606, z_loadbswap, v128q, 16, 4>; 270 271 // Load elements reversed. 272 def VLER : UnaryVRXGeneric<"vler", 0xE607>; 273 def VLERH : UnaryVRX<"vlerh", 0xE607, z_loadeswap, v128h, 16, 1>; 274 def VLERF : UnaryVRX<"vlerf", 0xE607, z_loadeswap, v128f, 16, 2>; 275 def VLERG : UnaryVRX<"vlerg", 0xE607, z_loadeswap, v128g, 16, 3>; 276 def : Pat<(v4f32 (z_loadeswap bdxaddr12only:$addr)), 277 (VLERF bdxaddr12only:$addr)>; 278 def : Pat<(v2f64 (z_loadeswap bdxaddr12only:$addr)), 279 (VLERG bdxaddr12only:$addr)>; 280 def : Pat<(v16i8 (z_loadeswap bdxaddr12only:$addr)), 281 (VLBRQ bdxaddr12only:$addr)>; 282 283 // Load byte-reversed element. 284 def VLEBRH : TernaryVRX<"vlebrh", 0xE601, z_vlebri16, v128h, v128h, 2, imm32zx3>; 285 def VLEBRF : TernaryVRX<"vlebrf", 0xE603, z_vlebri32, v128f, v128f, 4, imm32zx2>; 286 def VLEBRG : TernaryVRX<"vlebrg", 0xE602, z_vlebri64, v128g, v128g, 8, imm32zx1>; 287 288 // Load byte-reversed element and zero. 289 def VLLEBRZ : UnaryVRXGeneric<"vllebrz", 0xE604>; 290 def VLLEBRZH : UnaryVRX<"vllebrzh", 0xE604, z_vllebrzi16, v128h, 2, 1>; 291 def VLLEBRZF : UnaryVRX<"vllebrzf", 0xE604, z_vllebrzi32, v128f, 4, 2>; 292 def VLLEBRZG : UnaryVRX<"vllebrzg", 0xE604, z_vllebrzi64, v128g, 8, 3>; 293 def VLLEBRZE : UnaryVRX<"vllebrze", 0xE604, z_vllebrzli32, v128f, 4, 6>; 294 def : InstAlias<"lerv\t$V1, $XBD2", 295 (VLLEBRZE VR128:$V1, bdxaddr12only:$XBD2), 0>; 296 def : InstAlias<"ldrv\t$V1, $XBD2", 297 (VLLEBRZG VR128:$V1, bdxaddr12only:$XBD2), 0>; 298 299 // Load byte-reversed element and replicate. 300 def VLBRREP : UnaryVRXGeneric<"vlbrrep", 0xE605>; 301 def VLBRREPH : UnaryVRX<"vlbrreph", 0xE605, z_replicate_loadbswapi16, v128h, 2, 1>; 302 def VLBRREPF : UnaryVRX<"vlbrrepf", 0xE605, z_replicate_loadbswapi32, v128f, 4, 2>; 303 def VLBRREPG : UnaryVRX<"vlbrrepg", 0xE605, z_replicate_loadbswapi64, v128g, 8, 3>; 304 305 // Store byte-reversed elements. 306 def VSTBR : StoreVRXGeneric<"vstbr", 0xE60E>; 307 def VSTBRH : StoreVRX<"vstbrh", 0xE60E, z_storebswap, v128h, 16, 1>; 308 def VSTBRF : StoreVRX<"vstbrf", 0xE60E, z_storebswap, v128f, 16, 2>; 309 def VSTBRG : StoreVRX<"vstbrg", 0xE60E, z_storebswap, v128g, 16, 3>; 310 def VSTBRQ : StoreVRX<"vstbrq", 0xE60E, z_storebswap, v128q, 16, 4>; 311 312 // Store elements reversed. 313 def VSTER : StoreVRXGeneric<"vster", 0xE60F>; 314 def VSTERH : StoreVRX<"vsterh", 0xE60F, z_storeeswap, v128h, 16, 1>; 315 def VSTERF : StoreVRX<"vsterf", 0xE60F, z_storeeswap, v128f, 16, 2>; 316 def VSTERG : StoreVRX<"vsterg", 0xE60F, z_storeeswap, v128g, 16, 3>; 317 def : Pat<(z_storeeswap (v4f32 VR128:$val), bdxaddr12only:$addr), 318 (VSTERF VR128:$val, bdxaddr12only:$addr)>; 319 def : Pat<(z_storeeswap (v2f64 VR128:$val), bdxaddr12only:$addr), 320 (VSTERG VR128:$val, bdxaddr12only:$addr)>; 321 def : Pat<(z_storeeswap (v16i8 VR128:$val), bdxaddr12only:$addr), 322 (VSTBRQ VR128:$val, bdxaddr12only:$addr)>; 323 324 // Store byte-reversed element. 325 def VSTEBRH : StoreBinaryVRX<"vstebrh", 0xE609, z_vstebri16, v128h, 2, imm32zx3>; 326 def VSTEBRF : StoreBinaryVRX<"vstebrf", 0xE60B, z_vstebri32, v128f, 4, imm32zx2>; 327 def VSTEBRG : StoreBinaryVRX<"vstebrg", 0xE60A, z_vstebri64, v128g, 8, imm32zx1>; 328 def : InstAlias<"sterv\t$V1, $XBD2", 329 (VSTEBRF VR128:$V1, bdxaddr12only:$XBD2, 0), 0>; 330 def : InstAlias<"stdrv\t$V1, $XBD2", 331 (VSTEBRG VR128:$V1, bdxaddr12only:$XBD2, 0), 0>; 332} 333 334//===----------------------------------------------------------------------===// 335// Selects and permutes 336//===----------------------------------------------------------------------===// 337 338let Predicates = [FeatureVector] in { 339 // Merge high. 340 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 341 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 342 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 343 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 344 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 345 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 346 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 347 348 // Merge low. 349 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 350 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 351 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 352 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 353 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 354 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 355 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 356 357 // Permute. 358 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 359 360 // Permute doubleword immediate. 361 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 362 363 // Bit Permute. 364 let Predicates = [FeatureVectorEnhancements1] in 365 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; 366 367 // Replicate. 368 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 369 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 370 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 371 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 372 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 373 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16_timm:$index)), 374 (VREPF VR128:$vec, imm32zx16:$index)>; 375 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16_timm:$index)), 376 (VREPG VR128:$vec, imm32zx16:$index)>; 377 378 // Select. 379 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 380 381 // Blend. 382 let Predicates = [FeatureVectorEnhancements3] in { 383 def VBLEND : TernaryVRRdGeneric<"vblend", 0xE789>; 384 def VBLENDB : TernaryVRRd<"vblendb", 0xE789, null_frag, v128b, v128b, 0>; 385 def VBLENDH : TernaryVRRd<"vblendh", 0xE789, null_frag, v128h, v128h, 1>; 386 def VBLENDF : TernaryVRRd<"vblendf", 0xE789, null_frag, v128f, v128f, 2>; 387 def VBLENDG : TernaryVRRd<"vblendg", 0xE789, null_frag, v128g, v128g, 3>; 388 def VBLENDQ : TernaryVRRd<"vblendq", 0xE789, null_frag, v128q, v128q, 4>; 389 } 390} 391 392//===----------------------------------------------------------------------===// 393// Widening and narrowing 394//===----------------------------------------------------------------------===// 395 396let Predicates = [FeatureVector] in { 397 // Pack 398 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 399 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 400 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 401 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 402 403 // Pack saturate. 404 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 405 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 406 v128b, v128h, 1>; 407 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 408 v128h, v128f, 2>; 409 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 410 v128f, v128g, 3>; 411 412 // Pack saturate logical. 413 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 414 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 415 v128b, v128h, 1>; 416 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 417 v128h, v128f, 2>; 418 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 419 v128f, v128g, 3>; 420 421 // Sign-extend to doubleword. 422 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 423 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 424 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 425 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 426 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 427 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 428 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 429 430 // Generate element masks. 431 let Predicates = [FeatureVectorEnhancements3] in { 432 def VGEM : UnaryVRRaGeneric<"vgem", 0xE754>; 433 def VGEMB : UnaryVRRa<"vgemb", 0xE754, int_s390_vgemb, v128b, v128h, 0>; 434 def VGEMH : UnaryVRRa<"vgemh", 0xE754, int_s390_vgemh, v128h, v128b, 1>; 435 def VGEMF : UnaryVRRa<"vgemf", 0xE754, int_s390_vgemf, v128f, v128b, 2>; 436 def VGEMG : UnaryVRRa<"vgemg", 0xE754, int_s390_vgemg, v128g, v128b, 3>; 437 def VGEMQ : UnaryVRRa<"vgemq", 0xE754, int_s390_vgemq, v128q, v128b, 4>; 438 } 439 440 // Unpack high. 441 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 442 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 443 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 444 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 445 let Predicates = [FeatureVectorEnhancements3] in 446 def VUPHG : UnaryVRRa<"vuphg", 0xE7D7, z_unpack_high, v128q, v128g, 3>; 447 448 // Unpack logical high. 449 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 450 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 451 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 452 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 453 let Predicates = [FeatureVectorEnhancements3] in 454 def VUPLHG : UnaryVRRa<"vuplhg", 0xE7D5, z_unpackl_high, v128q, v128g, 3>; 455 456 // Unpack low. 457 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 458 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 459 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 460 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 461 let Predicates = [FeatureVectorEnhancements3] in 462 def VUPLG : UnaryVRRa<"vuplg", 0xE7D6, z_unpack_low, v128q, v128g, 3>; 463 464 // Unpack logical low. 465 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 466 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 467 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 468 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 469 let Predicates = [FeatureVectorEnhancements3] in 470 def VUPLLG : UnaryVRRa<"vupllg", 0xE7D4, z_unpackl_low, v128q, v128g, 3>; 471} 472 473//===----------------------------------------------------------------------===// 474// Instantiating generic operations for specific types. 475//===----------------------------------------------------------------------===// 476 477multiclass GenericVectorOps<ValueType type, ValueType inttype> { 478 let Predicates = [FeatureVector] in { 479 def : Pat<(type (load bdxaddr12only:$addr)), 480 (VL bdxaddr12only:$addr)>; 481 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 482 (VST VR128:$src, bdxaddr12only:$addr)>; 483 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 484 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 485 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 486 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 487 } 488} 489 490defm : GenericVectorOps<v16i8, v16i8>; 491defm : GenericVectorOps<v8i16, v8i16>; 492defm : GenericVectorOps<v4i32, v4i32>; 493defm : GenericVectorOps<v2i64, v2i64>; 494defm : GenericVectorOps<v4f32, v4i32>; 495defm : GenericVectorOps<v2f64, v2i64>; 496 497multiclass BlendVectorOps<ValueType type, ValueType inttype, 498 Instruction blend> { 499 let Predicates = [FeatureVectorEnhancements3] in { 500 def : Pat<(type (vselect (inttype (z_vicmpl_zero VR128:$x)), 501 VR128:$y, VR128:$z)), 502 (blend VR128:$y, VR128:$z, VR128:$x)>; 503 def : Pat<(type (vselect (inttype (z_vnot (z_vicmpl_zero VR128:$x))), 504 VR128:$y, VR128:$z)), 505 (blend VR128:$z, VR128:$y, VR128:$x)>; 506 } 507} 508 509defm : BlendVectorOps<v16i8, v16i8, VBLENDB>; 510defm : BlendVectorOps<v8i16, v8i16, VBLENDH>; 511defm : BlendVectorOps<v4i32, v4i32, VBLENDF>; 512defm : BlendVectorOps<v2i64, v2i64, VBLENDG>; 513defm : BlendVectorOps<v4f32, v4i32, VBLENDF>; 514defm : BlendVectorOps<v2f64, v2i64, VBLENDG>; 515 516let Predicates = [FeatureVectorEnhancements3] in { 517 def : Pat<(i128 (or (and VR128:$y, (z_vicmph 0, VR128:$x)), 518 (and VR128:$z, (not (z_vicmph 0, VR128:$x))))), 519 (VBLENDQ VR128:$y, VR128:$z, VR128:$x)>; 520} 521 522//===----------------------------------------------------------------------===// 523// Integer arithmetic 524//===----------------------------------------------------------------------===// 525 526let Predicates = [FeatureVector] in { 527 let isCommutable = 1 in { 528 // Add. 529 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 530 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 531 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 532 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 533 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 534 def VAQ : BinaryVRRc<"vaq", 0xE7F3, add, v128q, v128q, 4>; 535 } 536 537 let isCommutable = 1 in { 538 // Add compute carry. 539 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 540 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, z_vacc, v128b, v128b, 0>; 541 def VACCH : BinaryVRRc<"vacch", 0xE7F1, z_vacc, v128h, v128h, 1>; 542 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, z_vacc, v128f, v128f, 2>; 543 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, z_vacc, v128g, v128g, 3>; 544 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, z_vacc, v128q, v128q, 4>; 545 546 // Add with carry. 547 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 548 def VACQ : TernaryVRRd<"vacq", 0xE7BB, z_vac, v128q, v128q, 4>; 549 550 // Add with carry compute carry. 551 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 552 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, z_vaccc, v128q, v128q, 4>; 553 } 554 555 // And. 556 let isCommutable = 1 in 557 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 558 559 // And with complement. 560 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 561 562 let isCommutable = 1 in { 563 // Average. 564 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 565 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 566 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 567 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 568 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 569 let Predicates = [FeatureVectorEnhancements3] in 570 def VAVGQ : BinaryVRRc<"vavgq", 0xE7F2, int_s390_vavgq, v128q, v128q, 4>; 571 572 // Average logical. 573 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 574 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 575 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 576 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 577 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 578 let Predicates = [FeatureVectorEnhancements3] in 579 def VAVGLQ : BinaryVRRc<"vavglq", 0xE7F0, int_s390_vavglq, v128q, v128q, 4>; 580 } 581 582 // Checksum. 583 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 584 585 // Count leading zeros. 586 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 587 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 588 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 589 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 590 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 591 let Predicates = [FeatureVectorEnhancements3] in 592 def VCLZQ : UnaryVRRa<"vclzq", 0xE753, ctlz, v128q, v128q, 4>; 593 594 // Count trailing zeros. 595 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 596 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 597 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 598 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 599 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 600 let Predicates = [FeatureVectorEnhancements3] in 601 def VCTZQ : UnaryVRRa<"vctzq", 0xE752, cttz, v128q, v128q, 4>; 602 603 // Divide. 604 let Predicates = [FeatureVectorEnhancements3] in { 605 let hasSideEffects = 1 in { 606 def VD : TernaryVRRcIntGeneric<"vd", 0xE7B2>; 607 def VDF : TernaryVRRcInt<"vdf", 0xE7B2, null_frag, v128f, v128f, 2>; 608 def VDG : TernaryVRRcInt<"vdg", 0xE7B2, null_frag, v128g, v128g, 3>; 609 def VDQ : TernaryVRRcInt<"vdq", 0xE7B2, null_frag, v128q, v128q, 4>; 610 } 611 def : Pat<(v4i32 (sdiv VR128:$x, VR128:$y)), (VDF VR128:$x, VR128:$y, 0)>; 612 def : Pat<(v2i64 (sdiv VR128:$x, VR128:$y)), (VDG VR128:$x, VR128:$y, 0)>; 613 def : Pat<(i128 (sdiv VR128:$x, VR128:$y)), (VDQ VR128:$x, VR128:$y, 0)>; 614 } 615 616 // Divide logical. 617 let Predicates = [FeatureVectorEnhancements3] in { 618 let hasSideEffects = 1 in { 619 def VDL : TernaryVRRcIntGeneric<"vdl", 0xE7B0>; 620 def VDLF : TernaryVRRcInt<"vdlf", 0xE7B0, null_frag, v128f, v128f, 2>; 621 def VDLG : TernaryVRRcInt<"vdlg", 0xE7B0, null_frag, v128g, v128g, 3>; 622 def VDLQ : TernaryVRRcInt<"vdlq", 0xE7B0, null_frag, v128q, v128q, 4>; 623 } 624 def : Pat<(v4i32 (udiv VR128:$x, VR128:$y)), (VDLF VR128:$x, VR128:$y, 0)>; 625 def : Pat<(v2i64 (udiv VR128:$x, VR128:$y)), (VDLG VR128:$x, VR128:$y, 0)>; 626 def : Pat<(i128 (udiv VR128:$x, VR128:$y)), (VDLQ VR128:$x, VR128:$y, 0)>; 627 } 628 629 // Evaluate. 630 let Predicates = [FeatureVectorEnhancements3] in 631 def VEVAL : QuaternaryVRIk<"veval", 0xE788, int_s390_veval, v128b>; 632 633 let isCommutable = 1 in { 634 // Not exclusive or. 635 let Predicates = [FeatureVectorEnhancements1] in 636 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; 637 638 // Exclusive or. 639 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 640 } 641 642 // Galois field multiply sum. 643 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 644 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 645 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 646 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 647 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 648 649 // Galois field multiply sum and accumulate. 650 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 651 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 652 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 653 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 654 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 655 656 // Load complement. 657 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 658 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 659 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 660 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 661 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 662 let Predicates = [FeatureVectorEnhancements3] in 663 def VLCQ : UnaryVRRa<"vlcq", 0xE7DE, ineg, v128q, v128q, 4>; 664 665 // Load positive. 666 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 667 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, abs, v128b, v128b, 0>; 668 def VLPH : UnaryVRRa<"vlph", 0xE7DF, abs, v128h, v128h, 1>; 669 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, abs, v128f, v128f, 2>; 670 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, abs, v128g, v128g, 3>; 671 let Predicates = [FeatureVectorEnhancements3] in 672 def VLPQ : UnaryVRRa<"vlpq", 0xE7DF, abs, v128q, v128q, 4>; 673 674 let isCommutable = 1 in { 675 // Maximum. 676 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 677 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 678 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 679 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 680 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 681 let Predicates = [FeatureVectorEnhancements3] in 682 def VMXQ : BinaryVRRc<"vmxq", 0xE7FF, null_frag, v128q, v128q, 4>; 683 684 // Maximum logical. 685 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 686 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 687 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 688 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 689 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 690 let Predicates = [FeatureVectorEnhancements3] in 691 def VMXLQ : BinaryVRRc<"vmxlq", 0xE7FD, null_frag, v128q, v128q, 4>; 692 } 693 694 let isCommutable = 1 in { 695 // Minimum. 696 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 697 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 698 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 699 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 700 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 701 let Predicates = [FeatureVectorEnhancements3] in 702 def VMNQ : BinaryVRRc<"vmnq", 0xE7FE, null_frag, v128q, v128q, 4>; 703 704 // Minimum logical. 705 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 706 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 707 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 708 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 709 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 710 let Predicates = [FeatureVectorEnhancements3] in 711 def VMNLQ : BinaryVRRc<"vmnlq", 0xE7FC, null_frag, v128q, v128q, 4>; 712 } 713 714 let isCommutable = 1 in { 715 // Multiply and add low. 716 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 717 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 718 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 719 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 720 let Predicates = [FeatureVectorEnhancements3] in { 721 def VMALG : TernaryVRRd<"vmalg", 0xE7AA, z_muladd, v128g, v128g, 3>; 722 def VMALQ : TernaryVRRd<"vmalq", 0xE7AA, z_muladd, v128q, v128q, 4>; 723 } 724 725 // Multiply and add high. 726 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 727 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 728 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 729 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 730 let Predicates = [FeatureVectorEnhancements3] in { 731 def VMAHG : TernaryVRRd<"vmahg", 0xE7AB, int_s390_vmahg, v128g, v128g, 3>; 732 def VMAHQ : TernaryVRRd<"vmahq", 0xE7AB, int_s390_vmahq, v128q, v128q, 4>; 733 } 734 735 // Multiply and add logical high. 736 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 737 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 738 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 739 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 740 let Predicates = [FeatureVectorEnhancements3] in { 741 def VMALHG : TernaryVRRd<"vmalhg", 0xE7A9, int_s390_vmalhg, v128g, v128g, 3>; 742 def VMALHQ : TernaryVRRd<"vmalhq", 0xE7A9, int_s390_vmalhq, v128q, v128q, 4>; 743 } 744 745 // Multiply and add even. 746 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 747 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 748 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 749 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 750 let Predicates = [FeatureVectorEnhancements3] in 751 def VMAEG : TernaryVRRd<"vmaeg", 0xE7AE, int_s390_vmaeg, v128q, v128g, 3>; 752 753 // Multiply and add logical even. 754 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 755 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 756 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 757 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 758 let Predicates = [FeatureVectorEnhancements3] in 759 def VMALEG : TernaryVRRd<"vmaleg", 0xE7AC, int_s390_vmaleg, v128q, v128g, 3>; 760 761 // Multiply and add odd. 762 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 763 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 764 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 765 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 766 let Predicates = [FeatureVectorEnhancements3] in 767 def VMAOG : TernaryVRRd<"vmaog", 0xE7AF, int_s390_vmaog, v128q, v128g, 3>; 768 769 // Multiply and add logical odd. 770 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 771 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 772 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 773 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 774 let Predicates = [FeatureVectorEnhancements3] in 775 def VMALOG : TernaryVRRd<"vmalog", 0xE7AD, int_s390_vmalog, v128q, v128g, 3>; 776 } 777 778 let isCommutable = 1 in { 779 // Multiply high. 780 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 781 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 782 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 783 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 784 let Predicates = [FeatureVectorEnhancements3] in { 785 def VMHG : BinaryVRRc<"vmhg", 0xE7A3, int_s390_vmhg, v128g, v128g, 3>; 786 def VMHQ : BinaryVRRc<"vmhq", 0xE7A3, int_s390_vmhq, v128q, v128q, 4>; 787 } 788 789 // Multiply logical high. 790 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 791 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 792 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 793 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 794 let Predicates = [FeatureVectorEnhancements3] in { 795 def VMLHG : BinaryVRRc<"vmlhg", 0xE7A1, int_s390_vmlhg, v128g, v128g, 3>; 796 def VMLHQ : BinaryVRRc<"vmlhq", 0xE7A1, int_s390_vmlhq, v128q, v128q, 4>; 797 } 798 799 // Multiply low. 800 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 801 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 802 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 803 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 804 let Predicates = [FeatureVectorEnhancements3] in { 805 def VMLG : BinaryVRRc<"vmlg", 0xE7A2, mul, v128g, v128g, 3>; 806 def VMLQ : BinaryVRRc<"vmlq", 0xE7A2, mul, v128q, v128q, 4>; 807 } 808 809 // Multiply even. 810 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 811 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 812 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 813 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 814 let Predicates = [FeatureVectorEnhancements3] in 815 def VMEG : BinaryVRRc<"vmeg", 0xE7A6, int_s390_vmeg, v128q, v128g, 3>; 816 817 // Multiply logical even. 818 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 819 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 820 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 821 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 822 let Predicates = [FeatureVectorEnhancements3] in 823 def VMLEG : BinaryVRRc<"vmleg", 0xE7A4, int_s390_vmleg, v128q, v128g, 3>; 824 825 // Multiply odd. 826 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 827 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 828 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 829 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 830 let Predicates = [FeatureVectorEnhancements3] in 831 def VMOG : BinaryVRRc<"vmog", 0xE7A7, int_s390_vmog, v128q, v128g, 3>; 832 833 // Multiply logical odd. 834 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 835 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 836 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 837 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 838 let Predicates = [FeatureVectorEnhancements3] in 839 def VMLOG : BinaryVRRc<"vmlog", 0xE7A5, int_s390_vmlog, v128q, v128g, 3>; 840 } 841 let Predicates = [FeatureVectorEnhancements3] in { 842 def : Pat<(i128 (mulhs VR128:$x, VR128:$y)), (VMHQ VR128:$x, VR128:$y)>; 843 def : Pat<(i128 (mulhu VR128:$x, VR128:$y)), (VMLHQ VR128:$x, VR128:$y)>; 844 } 845 846 // Multiply sum logical. 847 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in { 848 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; 849 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, 850 v128q, v128g, v128g, v128q, 3>; 851 } 852 853 // Nand. 854 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in 855 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; 856 857 // Nor. 858 let isCommutable = 1 in 859 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 860 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 861 862 // Or. 863 let isCommutable = 1 in 864 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 865 866 // Or with complement. 867 let Predicates = [FeatureVectorEnhancements1] in 868 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; 869 870 // Population count. 871 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 872 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 873 let Predicates = [FeatureVectorEnhancements1] in { 874 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; 875 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; 876 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; 877 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; 878 } 879 880 // Remainder. 881 let Predicates = [FeatureVectorEnhancements3] in { 882 let hasSideEffects = 1 in { 883 def VR : TernaryVRRcIntGeneric<"vr", 0xE7B3>; 884 def VRF : TernaryVRRcInt<"vrf", 0xE7B3, null_frag, v128f, v128f, 2>; 885 def VRG : TernaryVRRcInt<"vrg", 0xE7B3, null_frag, v128g, v128g, 3>; 886 def VRQ : TernaryVRRcInt<"vrq", 0xE7B3, null_frag, v128q, v128q, 4>; 887 } 888 def : Pat<(v4i32 (srem VR128:$x, VR128:$y)), (VRF VR128:$x, VR128:$y, 0)>; 889 def : Pat<(v2i64 (srem VR128:$x, VR128:$y)), (VRG VR128:$x, VR128:$y, 0)>; 890 def : Pat<(i128 (srem VR128:$x, VR128:$y)), (VRQ VR128:$x, VR128:$y, 0)>; 891 } 892 893 // Remainder logical. 894 let Predicates = [FeatureVectorEnhancements3] in { 895 let hasSideEffects = 1 in { 896 def VRL : TernaryVRRcIntGeneric<"vrl", 0xE7B1>; 897 def VRLF : TernaryVRRcInt<"vrlf", 0xE7B1, null_frag, v128f, v128f, 2>; 898 def VRLG : TernaryVRRcInt<"vrlg", 0xE7B1, null_frag, v128g, v128g, 3>; 899 def VRLQ : TernaryVRRcInt<"vrlq", 0xE7B1, null_frag, v128q, v128q, 4>; 900 } 901 def : Pat<(v4i32 (urem VR128:$x, VR128:$y)), (VRLF VR128:$x, VR128:$y, 0)>; 902 def : Pat<(v2i64 (urem VR128:$x, VR128:$y)), (VRLG VR128:$x, VR128:$y, 0)>; 903 def : Pat<(i128 (urem VR128:$x, VR128:$y)), (VRLQ VR128:$x, VR128:$y, 0)>; 904 } 905 906 // Element rotate left logical (with vector shift amount). 907 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 908 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, rotl, v128b, v128b, 0>; 909 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, rotl, v128h, v128h, 1>; 910 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, rotl, v128f, v128f, 2>; 911 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, rotl, v128g, v128g, 3>; 912 913 // Element rotate left logical (with scalar shift amount). 914 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 915 def VERLLB : BinaryVRSa<"verllb", 0xE733, z_vrotl_by_scalar, v128b, v128b, 0>; 916 def VERLLH : BinaryVRSa<"verllh", 0xE733, z_vrotl_by_scalar, v128h, v128h, 1>; 917 def VERLLF : BinaryVRSa<"verllf", 0xE733, z_vrotl_by_scalar, v128f, v128f, 2>; 918 def VERLLG : BinaryVRSa<"verllg", 0xE733, z_vrotl_by_scalar, v128g, v128g, 3>; 919 920 // Element rotate and insert under mask. 921 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 922 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 923 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 924 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 925 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 926 927 // Element shift left (with vector shift amount). 928 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 929 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 930 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 931 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 932 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 933 934 // Element shift left (with scalar shift amount). 935 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 936 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 937 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 938 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 939 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 940 941 // Element shift right arithmetic (with vector shift amount). 942 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 943 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 944 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 945 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 946 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 947 948 // Element shift right arithmetic (with scalar shift amount). 949 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 950 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 951 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 952 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 953 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 954 955 // Element shift right logical (with vector shift amount). 956 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 957 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 958 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 959 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 960 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 961 962 // Element shift right logical (with scalar shift amount). 963 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 964 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 965 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 966 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 967 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 968 969 // Shift left. 970 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 971 972 // Shift left by byte. 973 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 974 975 // Shift left double by byte. 976 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 977 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8_timm:$z), 978 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 979 980 // Shift left double by bit. 981 let Predicates = [FeatureVectorEnhancements2] in 982 def VSLD : TernaryVRId<"vsld", 0xE786, int_s390_vsld, v128b, v128b, 0>; 983 984 // Shift right arithmetic. 985 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 986 987 // Shift right arithmetic by byte. 988 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 989 990 // Shift right logical. 991 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 992 993 // Shift right logical by byte. 994 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 995 996 // Shift right double by bit. 997 let Predicates = [FeatureVectorEnhancements2] in 998 def VSRD : TernaryVRId<"vsrd", 0xE787, int_s390_vsrd, v128b, v128b, 0>; 999 1000 // Subtract. 1001 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 1002 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 1003 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 1004 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 1005 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 1006 def VSQ : BinaryVRRc<"vsq", 0xE7F7, sub, v128q, v128q, 4>; 1007 1008 // Subtract compute borrow indication. 1009 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 1010 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, z_vscbi, v128b, v128b, 0>; 1011 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, z_vscbi, v128h, v128h, 1>; 1012 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, z_vscbi, v128f, v128f, 2>; 1013 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, z_vscbi, v128g, v128g, 3>; 1014 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, z_vscbi, v128q, v128q, 4>; 1015 1016 // Subtract with borrow indication. 1017 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 1018 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, z_vsbi, v128q, v128q, 4>; 1019 1020 // Subtract with borrow compute borrow indication. 1021 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 1022 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, z_vsbcbi, v128q, v128q, 4>; 1023 1024 // Sum across doubleword. 1025 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 1026 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 1027 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 1028 1029 // Sum across quadword. 1030 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 1031 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 1032 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 1033 1034 // Sum across word. 1035 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 1036 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 1037 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 1038} 1039 1040// Instantiate the bitwise ops for type TYPE. 1041multiclass BitwiseVectorOps<ValueType type, SDPatternOperator not_op> { 1042 let Predicates = [FeatureVector] in { 1043 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 1044 def : Pat<(type (and VR128:$x, (not_op VR128:$y))), 1045 (VNC VR128:$x, VR128:$y)>; 1046 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 1047 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 1048 def : Pat<(type (or (and VR128:$x, VR128:$z), 1049 (and VR128:$y, (not_op VR128:$z)))), 1050 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 1051 def : Pat<(type (not_op (or VR128:$x, VR128:$y))), 1052 (VNO VR128:$x, VR128:$y)>; 1053 def : Pat<(type (not_op VR128:$x)), (VNO VR128:$x, VR128:$x)>; 1054 } 1055 let Predicates = [FeatureVectorEnhancements1] in { 1056 def : Pat<(type (not_op (xor VR128:$x, VR128:$y))), 1057 (VNX VR128:$x, VR128:$y)>; 1058 def : Pat<(type (not_op (and VR128:$x, VR128:$y))), 1059 (VNN VR128:$x, VR128:$y)>; 1060 def : Pat<(type (or VR128:$x, (not_op VR128:$y))), 1061 (VOC VR128:$x, VR128:$y)>; 1062 } 1063 let Predicates = [FeatureVectorEnhancements3] in { 1064 def : Pat<(type (and VR128:$x, (and VR128:$y, VR128:$z))), 1065 (VEVAL VR128:$x, VR128:$y, VR128:$z, 1)>; 1066 def : Pat<(type (and (not_op VR128:$z), (and VR128:$x, VR128:$y))), 1067 (VEVAL VR128:$x, VR128:$y, VR128:$z, 2)>; 1068 def : Pat<(type (and VR128:$x, (xor VR128:$y, VR128:$z))), 1069 (VEVAL VR128:$x, VR128:$y, VR128:$z, 6)>; 1070 def : Pat<(type (and VR128:$x, (or VR128:$y, VR128:$z))), 1071 (VEVAL VR128:$x, VR128:$y, VR128:$z, 7)>; 1072 def : Pat<(type (and VR128:$x, (not_op (or VR128:$y, VR128:$z)))), 1073 (VEVAL VR128:$x, VR128:$y, VR128:$z, 8)>; 1074 def : Pat<(type (and VR128:$x, (not_op (xor VR128:$y, VR128:$z)))), 1075 (VEVAL VR128:$x, VR128:$y, VR128:$z, 9)>; 1076 def : Pat<(type (and VR128:$x, (or VR128:$y, (not_op VR128:$z)))), 1077 (VEVAL VR128:$x, VR128:$y, VR128:$z, 11)>; 1078 def : Pat<(type (and VR128:$x, (not_op (and VR128:$y, VR128:$z)))), 1079 (VEVAL VR128:$x, VR128:$y, VR128:$z, 14)>; 1080 def : Pat<(type (and (or VR128:$x, VR128:$y), (xor VR128:$z, (and VR128:$x, VR128:$y)))), 1081 (VEVAL VR128:$x, VR128:$y, VR128:$z, 22)>; 1082 def : Pat<(type (or (and VR128:$x, VR128:$y), (and VR128:$z, (or VR128:$x, VR128:$y)))), 1083 (VEVAL VR128:$x, VR128:$y, VR128:$z, 23)>; 1084 def : Pat<(type (and (xor VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z))), 1085 (VEVAL VR128:$x, VR128:$y, VR128:$z, 24)>; 1086 def : Pat<(type (and (or VR128:$x, VR128:$y), (not_op (xor VR128:$y, VR128:$z)))), 1087 (VEVAL VR128:$x, VR128:$y, VR128:$z, 25)>; 1088 def : Pat<(type (and (or VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z))), 1089 (VEVAL VR128:$x, VR128:$y, VR128:$z, 26)>; 1090 def : Pat<(type (and (or VR128:$x, VR128:$z), (or VR128:$y, (not_op VR128:$z)))), 1091 (VEVAL VR128:$x, VR128:$y, VR128:$z, 27)>; 1092 def : Pat<(type (xor VR128:$x, (and VR128:$y, VR128:$z))), 1093 (VEVAL VR128:$x, VR128:$y, VR128:$z, 30)>; 1094 def : Pat<(type (or VR128:$x, (and VR128:$y, VR128:$z))), 1095 (VEVAL VR128:$x, VR128:$y, VR128:$z, 31)>; 1096 def : Pat<(type (and (not_op VR128:$z), (xor VR128:$x, VR128:$y))), 1097 (VEVAL VR128:$x, VR128:$y, VR128:$z, 40)>; 1098 def : Pat<(type (and (or VR128:$x, VR128:$y), (not_op (xor VR128:$z, (and VR128:$x, VR128:$y))))), 1099 (VEVAL VR128:$x, VR128:$y, VR128:$z, 41)>; 1100 def : Pat<(type (and (not_op VR128:$z), (or VR128:$x, VR128:$y))), 1101 (VEVAL VR128:$x, VR128:$y, VR128:$z, 42)>; 1102 def : Pat<(type (or (and VR128:$x, VR128:$y), (and (not_op VR128:$z), (or VR128:$x, VR128:$y)))), 1103 (VEVAL VR128:$x, VR128:$y, VR128:$z, 43)>; 1104 def : Pat<(type (xor VR128:$y, (or VR128:$x, (and VR128:$y, VR128:$z)))), 1105 (VEVAL VR128:$x, VR128:$y, VR128:$z, 44)>; 1106 def : Pat<(type (xor VR128:$x, (and VR128:$y, (not_op VR128:$z)))), 1107 (VEVAL VR128:$x, VR128:$y, VR128:$z, 45)>; 1108 def : Pat<(type (and (or VR128:$x, VR128:$y), (not_op (and VR128:$y, VR128:$z)))), 1109 (VEVAL VR128:$x, VR128:$y, VR128:$z, 46)>; 1110 def : Pat<(type (or VR128:$x, (and VR128:$y, (not_op VR128:$z)))), 1111 (VEVAL VR128:$x, VR128:$y, VR128:$z, 47)>; 1112 def : Pat<(type (or (xor VR128:$x, VR128:$y), (and VR128:$x, VR128:$z))), 1113 (VEVAL VR128:$x, VR128:$y, VR128:$z, 61)>; 1114 def : Pat<(type (or (xor VR128:$x, VR128:$y), (and VR128:$x, (not_op VR128:$z)))), 1115 (VEVAL VR128:$x, VR128:$y, VR128:$z, 62)>; 1116 def : Pat<(type (xor (or VR128:$x, VR128:$y), (or VR128:$z, (and VR128:$x, VR128:$y)))), 1117 (VEVAL VR128:$x, VR128:$y, VR128:$z, 104)>; 1118 def : Pat<(type (xor VR128:$x, (xor VR128:$y, VR128:$z))), 1119 (VEVAL VR128:$x, VR128:$y, VR128:$z, 105)>; 1120 def : Pat<(type (xor VR128:$z, (or VR128:$x, VR128:$y))), 1121 (VEVAL VR128:$x, VR128:$y, VR128:$z, 106)>; 1122 def : Pat<(type (or (and VR128:$x, VR128:$y), (xor VR128:$z, (or VR128:$x, VR128:$y)))), 1123 (VEVAL VR128:$x, VR128:$y, VR128:$z, 107)>; 1124 def : Pat<(type (or (xor VR128:$y, VR128:$z), (and VR128:$x, (not_op VR128:$y)))), 1125 (VEVAL VR128:$x, VR128:$y, VR128:$z, 110)>; 1126 def : Pat<(type (or VR128:$x, (xor VR128:$y, VR128:$z))), 1127 (VEVAL VR128:$x, VR128:$y, VR128:$z, 111)>; 1128 def : Pat<(type (or (xor VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z))), 1129 (VEVAL VR128:$x, VR128:$y, VR128:$z, 126)>; 1130 def : Pat<(type (or VR128:$x, (or VR128:$y, VR128:$z))), 1131 (VEVAL VR128:$x, VR128:$y, VR128:$z, 127)>; 1132 def : Pat<(type (not_op (or VR128:$x, (or VR128:$y, VR128:$z)))), 1133 (VEVAL VR128:$x, VR128:$y, VR128:$z, 128)>; 1134 def : Pat<(type (not_op (or (xor VR128:$x, VR128:$y), (xor VR128:$x, VR128:$z)))), 1135 (VEVAL VR128:$x, VR128:$y, VR128:$z, 129)>; 1136 def : Pat<(type (not_op (or VR128:$z, (xor VR128:$x, VR128:$y)))), 1137 (VEVAL VR128:$x, VR128:$y, VR128:$z, 130)>; 1138 def : Pat<(type (and (not_op (xor VR128:$x, VR128:$y)), (or VR128:$x, (not_op VR128:$z)))), 1139 (VEVAL VR128:$x, VR128:$y, VR128:$z, 131)>; 1140 def : Pat<(type (xor (or VR128:$y, VR128:$z), (or (not_op VR128:$x), (and VR128:$y, VR128:$z)))), 1141 (VEVAL VR128:$x, VR128:$y, VR128:$z, 134)>; 1142 def : Pat<(type (not_op (xor VR128:$x, (or VR128:$y, VR128:$z)))), 1143 (VEVAL VR128:$x, VR128:$y, VR128:$z, 135)>; 1144 def : Pat<(type (or (not_op (or VR128:$y, VR128:$z)), (and VR128:$x, (and VR128:$y, VR128:$z)))), 1145 (VEVAL VR128:$x, VR128:$y, VR128:$z, 137)>; 1146 def : Pat<(type (and (not_op VR128:$z), (or VR128:$x, (not_op VR128:$y)))), 1147 (VEVAL VR128:$x, VR128:$y, VR128:$z, 138)>; 1148 def : Pat<(type (or (and VR128:$x, VR128:$y), (not_op (or VR128:$y, VR128:$z)))), 1149 (VEVAL VR128:$x, VR128:$y, VR128:$z, 139)>; 1150 def : Pat<(type (or (not_op (or VR128:$y, VR128:$z)), (and VR128:$x, (xor VR128:$y, VR128:$z)))), 1151 (VEVAL VR128:$x, VR128:$y, VR128:$z, 142)>; 1152 def : Pat<(type (or VR128:$x, (not_op (or VR128:$y, VR128:$z)))), 1153 (VEVAL VR128:$x, VR128:$y, VR128:$z, 143)>; 1154 def : Pat<(type (not_op (xor VR128:$x, (xor VR128:$y, VR128:$z)))), 1155 (VEVAL VR128:$x, VR128:$y, VR128:$z, 150)>; 1156 def : Pat<(type (or (and VR128:$x, VR128:$y), (not_op (xor VR128:$z, (or VR128:$x, VR128:$y))))), 1157 (VEVAL VR128:$x, VR128:$y, VR128:$z, 151)>; 1158 def : Pat<(type (not_op (or (and VR128:$x, VR128:$y), (xor VR128:$y, VR128:$z)))), 1159 (VEVAL VR128:$x, VR128:$y, VR128:$z, 152)>; 1160 def : Pat<(type (xor VR128:$z, (or VR128:$x, (not_op VR128:$y)))), 1161 (VEVAL VR128:$x, VR128:$y, VR128:$z, 154)>; 1162 def : Pat<(type (or (and VR128:$x, VR128:$y), (not_op (xor VR128:$y, VR128:$z)))), 1163 (VEVAL VR128:$x, VR128:$y, VR128:$z, 155)>; 1164 def : Pat<(type (or (not_op (or VR128:$y, VR128:$z)), (xor VR128:$x, (and VR128:$y, VR128:$z)))), 1165 (VEVAL VR128:$x, VR128:$y, VR128:$z, 158)>; 1166 def : Pat<(type (or VR128:$x, (not_op (xor VR128:$y, VR128:$z)))), 1167 (VEVAL VR128:$x, VR128:$y, VR128:$z, 159)>; 1168 def : Pat<(type (not_op (or VR128:$z, (and VR128:$x, VR128:$y)))), 1169 (VEVAL VR128:$x, VR128:$y, VR128:$z, 168)>; 1170 def : Pat<(type (not_op (xor VR128:$z, (and VR128:$x, VR128:$y)))), 1171 (VEVAL VR128:$x, VR128:$y, VR128:$z, 169)>; 1172 def : Pat<(type (or (not_op VR128:$z), (and VR128:$x, VR128:$y))), 1173 (VEVAL VR128:$x, VR128:$y, VR128:$z, 171)>; 1174 def : Pat<(type (and (not_op (and VR128:$x, VR128:$y)), (or VR128:$x, (not_op VR128:$z)))), 1175 (VEVAL VR128:$x, VR128:$y, VR128:$z, 172)>; 1176 def : Pat<(type (not_op (and (xor VR128:$x, VR128:$z), (or VR128:$y, VR128:$z)))), 1177 (VEVAL VR128:$x, VR128:$y, VR128:$z, 173)>; 1178 def : Pat<(type (or (not_op VR128:$z), (and VR128:$x, (not_op VR128:$y)))), 1179 (VEVAL VR128:$x, VR128:$y, VR128:$z, 174)>; 1180 def : Pat<(type (or (xor VR128:$x, VR128:$y), (not_op (or VR128:$x, VR128:$z)))), 1181 (VEVAL VR128:$x, VR128:$y, VR128:$z, 188)>; 1182 def : Pat<(type (not_op (and (xor VR128:$x, VR128:$z), (xor VR128:$y, VR128:$z)))), 1183 (VEVAL VR128:$x, VR128:$y, VR128:$z, 189)>; 1184 def : Pat<(type (or (not_op VR128:$z), (xor VR128:$x, VR128:$y))), 1185 (VEVAL VR128:$x, VR128:$y, VR128:$z, 190)>; 1186 def : Pat<(type (or (not_op VR128:$z), (or VR128:$x, VR128:$y))), 1187 (VEVAL VR128:$x, VR128:$y, VR128:$z, 191)>; 1188 def : Pat<(type (or (not_op (or VR128:$x, VR128:$y)), (and (not_op VR128:$z), (xor VR128:$x, VR128:$y)))), 1189 (VEVAL VR128:$x, VR128:$y, VR128:$z, 232)>; 1190 def : Pat<(type (xor (not_op (and VR128:$x, VR128:$y)), (and VR128:$z, (or VR128:$x, VR128:$y)))), 1191 (VEVAL VR128:$x, VR128:$y, VR128:$z, 233)>; 1192 def : Pat<(type (not_op (and VR128:$z, (or VR128:$x, VR128:$y)))), 1193 (VEVAL VR128:$x, VR128:$y, VR128:$z, 234)>; 1194 def : Pat<(type (not_op (and VR128:$z, (xor VR128:$x, VR128:$y)))), 1195 (VEVAL VR128:$x, VR128:$y, VR128:$z, 235)>; 1196 def : Pat<(type (or VR128:$x, (not_op (and VR128:$y, VR128:$z)))), 1197 (VEVAL VR128:$x, VR128:$y, VR128:$z, 239)>; 1198 def : Pat<(type (not_op (and VR128:$x, (and VR128:$y, VR128:$z)))), 1199 (VEVAL VR128:$x, VR128:$y, VR128:$z, 254)>; 1200 } 1201} 1202 1203defm : BitwiseVectorOps<v16i8, z_vnot>; 1204defm : BitwiseVectorOps<v8i16, z_vnot>; 1205defm : BitwiseVectorOps<v4i32, z_vnot>; 1206defm : BitwiseVectorOps<v2i64, z_vnot>; 1207defm : BitwiseVectorOps<i128, not>; 1208 1209// Instantiate additional patterns for absolute-related expressions on 1210// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 1211// instruction. 1212multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 1213 Instruction lp, int shift> { 1214 let Predicates = [FeatureVector] in { 1215 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 1216 (z_vneg VR128:$x), VR128:$x)), 1217 (lc (lp VR128:$x))>; 1218 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 1219 VR128:$x, (z_vneg VR128:$x))), 1220 (lc (lp VR128:$x))>; 1221 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 1222 VR128:$x, (z_vneg VR128:$x))), 1223 (lc (lp VR128:$x))>; 1224 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 1225 (z_vneg VR128:$x), VR128:$x)), 1226 (lc (lp VR128:$x))>; 1227 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 1228 (z_vneg VR128:$x)), 1229 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 1230 VR128:$x))), 1231 (lp VR128:$x)>; 1232 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 1233 VR128:$x), 1234 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 1235 (z_vneg VR128:$x)))), 1236 (lc (lp VR128:$x))>; 1237 } 1238} 1239 1240defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 1241defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 1242defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 1243defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 1244 1245// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 1246// signed or unsigned "set if greater than" comparison instruction and 1247// MIN and MAX are the associated minimum and maximum instructions. 1248multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 1249 Instruction min, Instruction max> { 1250 let Predicates = [FeatureVector] in { 1251 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 1252 (max VR128:$x, VR128:$y)>; 1253 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 1254 (min VR128:$x, VR128:$y)>; 1255 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 1256 VR128:$x, VR128:$y)), 1257 (min VR128:$x, VR128:$y)>; 1258 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 1259 VR128:$y, VR128:$x)), 1260 (max VR128:$x, VR128:$y)>; 1261 } 1262} 1263 1264// Signed min/max. 1265defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 1266defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 1267defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 1268defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 1269 1270let Predicates = [FeatureVectorEnhancements3] in { 1271 def : Pat<(i128 (or (and VR128:$x, (z_vicmph VR128:$x, VR128:$y)), 1272 (and VR128:$y, (not (z_vicmph VR128:$x, VR128:$y))))), 1273 (VMXQ VR128:$x, VR128:$y)>; 1274 def : Pat<(i128 (or (and VR128:$y, (z_vicmph VR128:$x, VR128:$y)), 1275 (and VR128:$x, (not (z_vicmph VR128:$x, VR128:$y))))), 1276 (VMNQ VR128:$x, VR128:$y)>; 1277} 1278 1279// Unsigned min/max. 1280defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 1281defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 1282defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 1283defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 1284 1285let Predicates = [FeatureVectorEnhancements3] in { 1286 def : Pat<(i128 (or (and VR128:$x, (z_vicmphl VR128:$x, VR128:$y)), 1287 (and VR128:$y, (not (z_vicmphl VR128:$x, VR128:$y))))), 1288 (VMXLQ VR128:$x, VR128:$y)>; 1289 def : Pat<(i128 (or (and VR128:$y, (z_vicmphl VR128:$x, VR128:$y)), 1290 (and VR128:$x, (not (z_vicmphl VR128:$x, VR128:$y))))), 1291 (VMNLQ VR128:$x, VR128:$y)>; 1292} 1293 1294// Instantiate full-vector shifts. 1295multiclass FullVectorShiftOps<SDPatternOperator shift, 1296 Instruction sbit, Instruction sbyte> { 1297 let Predicates = [FeatureVector] in { 1298 def : Pat<(shift (i128 VR128:$x), imm32nobytes:$amt), 1299 (sbit VR128:$x, (VREPIB (UIMM8 imm:$amt)))>; 1300 def : Pat<(shift (i128 VR128:$x), imm32nobits:$amt), 1301 (sbyte VR128:$x, (VREPIB (UIMM8 imm:$amt)))>; 1302 def : Pat<(shift (i128 VR128:$x), imm32:$amt), 1303 (sbit (sbyte VR128:$x, (VREPIB (UIMM8 imm:$amt))), 1304 (VREPIB (UIMM8 imm:$amt)))>; 1305 def : Pat<(shift (i128 VR128:$x), GR32:$amt), 1306 (sbit (sbyte VR128:$x, (VREPB (VLVGP32 GR32:$amt, GR32:$amt), 15)), 1307 (VREPB (VLVGP32 GR32:$amt, GR32:$amt), 15))>; 1308 } 1309} 1310defm : FullVectorShiftOps<vshiftop<shl>, VSL, VSLB>; 1311defm : FullVectorShiftOps<vshiftop<srl>, VSRL, VSRLB>; 1312defm : FullVectorShiftOps<vshiftop<sra>, VSRA, VSRAB>; 1313 1314//===----------------------------------------------------------------------===// 1315// Integer comparison 1316//===----------------------------------------------------------------------===// 1317 1318let Predicates = [FeatureVector] in { 1319 // Element compare. 1320 let Defs = [CC] in { 1321 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 1322 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 1323 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 1324 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 1325 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 1326 let Predicates = [FeatureVectorEnhancements3] in 1327 def VECQ : CompareVRRa<"vecq", 0xE7DB, z_scmp, v128q, 4>; 1328 } 1329 1330 // Element compare logical. 1331 let Defs = [CC] in { 1332 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 1333 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 1334 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 1335 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 1336 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 1337 let Predicates = [FeatureVectorEnhancements3] in 1338 def VECLQ : CompareVRRa<"veclq", 0xE7D9, z_ucmp, v128q, 4>; 1339 } 1340 1341 // Compare equal. 1342 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 1343 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 1344 v128b, v128b, 0>; 1345 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 1346 v128h, v128h, 1>; 1347 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 1348 v128f, v128f, 2>; 1349 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 1350 v128g, v128g, 3>; 1351 let Predicates = [FeatureVectorEnhancements3] in 1352 defm VCEQQ : BinaryVRRbSPair<"vceqq", 0xE7F8, z_vicmpe, z_vicmpes, 1353 v128q, v128q, 4>; 1354 1355 // Compare high. 1356 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 1357 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 1358 v128b, v128b, 0>; 1359 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 1360 v128h, v128h, 1>; 1361 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 1362 v128f, v128f, 2>; 1363 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 1364 v128g, v128g, 3>; 1365 let Predicates = [FeatureVectorEnhancements3] in 1366 defm VCHQ : BinaryVRRbSPair<"vchq", 0xE7FB, z_vicmph, z_vicmphs, 1367 v128q, v128q, 4>; 1368 1369 // Compare high logical. 1370 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 1371 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 1372 v128b, v128b, 0>; 1373 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 1374 v128h, v128h, 1>; 1375 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 1376 v128f, v128f, 2>; 1377 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 1378 v128g, v128g, 3>; 1379 let Predicates = [FeatureVectorEnhancements3] in 1380 defm VCHLQ : BinaryVRRbSPair<"vchlq", 0xE7F9, z_vicmphl, z_vicmphls, 1381 v128q, v128q, 4>; 1382 1383 // Test under mask. 1384 let Defs = [CC] in 1385 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 1386} 1387 1388//===----------------------------------------------------------------------===// 1389// Floating-point arithmetic 1390//===----------------------------------------------------------------------===// 1391 1392// See comments in SystemZInstrFP.td for the suppression flags and 1393// rounding modes. 1394multiclass VectorRounding<Instruction insn, TypedReg tr> { 1395 def : FPConversion<insn, any_frint, tr, tr, 0, 0>; 1396 def : FPConversion<insn, any_fnearbyint, tr, tr, 4, 0>; 1397 def : FPConversion<insn, any_ffloor, tr, tr, 4, 7>; 1398 def : FPConversion<insn, any_fceil, tr, tr, 4, 6>; 1399 def : FPConversion<insn, any_ftrunc, tr, tr, 4, 5>; 1400 def : FPConversion<insn, any_fround, tr, tr, 4, 1>; 1401} 1402 1403let Predicates = [FeatureVector] in { 1404 // Add. 1405 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1406 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 1407 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, any_fadd, v128db, v128db, 3, 0>; 1408 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, any_fadd, v64db, v64db, 3, 8, 0, 1409 "adbr">; 1410 let Predicates = [FeatureVectorEnhancements1] in { 1411 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, any_fadd, v128sb, v128sb, 2, 0>; 1412 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, any_fadd, v32sb, v32sb, 2, 8, 0, 1413 "aebr">; 1414 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, any_fadd, v128xb, v128xb, 4, 8>; 1415 } 1416 } 1417 1418 // Convert from fixed. 1419 let Uses = [FPC], mayRaiseFPException = 1 in { 1420 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 1421 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 1422 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 1423 } 1424 def : FPConversion<VCDGB, any_sint_to_fp, v128db, v128g, 0, 0>; 1425 let Predicates = [FeatureVectorEnhancements2] in { 1426 let Uses = [FPC], mayRaiseFPException = 1 in { 1427 let isAsmParserOnly = 1 in 1428 def VCFPS : TernaryVRRaFloatGeneric<"vcfps", 0xE7C3>; 1429 def VCEFB : TernaryVRRa<"vcefb", 0xE7C3, null_frag, v128sb, v128g, 2, 0>; 1430 def WCEFB : TernaryVRRa<"wcefb", 0xE7C3, null_frag, v32sb, v32f, 2, 8>; 1431 } 1432 def : FPConversion<VCEFB, any_sint_to_fp, v128sb, v128f, 0, 0>; 1433 } 1434 1435 // Convert from logical. 1436 let Uses = [FPC], mayRaiseFPException = 1 in { 1437 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 1438 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 1439 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 1440 } 1441 def : FPConversion<VCDLGB, any_uint_to_fp, v128db, v128g, 0, 0>; 1442 let Predicates = [FeatureVectorEnhancements2] in { 1443 let Uses = [FPC], mayRaiseFPException = 1 in { 1444 let isAsmParserOnly = 1 in 1445 def VCFPL : TernaryVRRaFloatGeneric<"vcfpl", 0xE7C1>; 1446 def VCELFB : TernaryVRRa<"vcelfb", 0xE7C1, null_frag, v128sb, v128g, 2, 0>; 1447 def WCELFB : TernaryVRRa<"wcelfb", 0xE7C1, null_frag, v32sb, v32f, 2, 8>; 1448 } 1449 def : FPConversion<VCELFB, any_uint_to_fp, v128sb, v128f, 0, 0>; 1450 } 1451 1452 // Convert to fixed. 1453 let Uses = [FPC], mayRaiseFPException = 1 in { 1454 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 1455 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 1456 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 1457 } 1458 // Rounding mode should agree with SystemZInstrFP.td. 1459 def : FPConversion<VCGDB, any_fp_to_sint, v128g, v128db, 0, 5>; 1460 let Predicates = [FeatureVectorEnhancements2] in { 1461 let Uses = [FPC], mayRaiseFPException = 1 in { 1462 let isAsmParserOnly = 1 in 1463 def VCSFP : TernaryVRRaFloatGeneric<"vcsfp", 0xE7C2>; 1464 def VCFEB : TernaryVRRa<"vcfeb", 0xE7C2, null_frag, v128sb, v128g, 2, 0>; 1465 def WCFEB : TernaryVRRa<"wcfeb", 0xE7C2, null_frag, v32sb, v32f, 2, 8>; 1466 } 1467 // Rounding mode should agree with SystemZInstrFP.td. 1468 def : FPConversion<VCFEB, any_fp_to_sint, v128f, v128sb, 0, 5>; 1469 } 1470 1471 // Convert to logical. 1472 let Uses = [FPC], mayRaiseFPException = 1 in { 1473 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 1474 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 1475 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 1476 } 1477 // Rounding mode should agree with SystemZInstrFP.td. 1478 def : FPConversion<VCLGDB, any_fp_to_uint, v128g, v128db, 0, 5>; 1479 let Predicates = [FeatureVectorEnhancements2] in { 1480 let Uses = [FPC], mayRaiseFPException = 1 in { 1481 let isAsmParserOnly = 1 in 1482 def VCLFP : TernaryVRRaFloatGeneric<"vclfp", 0xE7C0>; 1483 def VCLFEB : TernaryVRRa<"vclfeb", 0xE7C0, null_frag, v128sb, v128g, 2, 0>; 1484 def WCLFEB : TernaryVRRa<"wclfeb", 0xE7C0, null_frag, v32sb, v32f, 2, 8>; 1485 } 1486 // Rounding mode should agree with SystemZInstrFP.td. 1487 def : FPConversion<VCLFEB, any_fp_to_uint, v128f, v128sb, 0, 5>; 1488 } 1489 1490 // Divide. 1491 let Uses = [FPC], mayRaiseFPException = 1 in { 1492 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 1493 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, any_fdiv, v128db, v128db, 3, 0>; 1494 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, any_fdiv, v64db, v64db, 3, 8, 0, 1495 "ddbr">; 1496 let Predicates = [FeatureVectorEnhancements1] in { 1497 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, any_fdiv, v128sb, v128sb, 2, 0>; 1498 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, any_fdiv, v32sb, v32sb, 2, 8, 0, 1499 "debr">; 1500 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, any_fdiv, v128xb, v128xb, 4, 8>; 1501 } 1502 } 1503 1504 // Load FP integer. 1505 let Uses = [FPC], mayRaiseFPException = 1 in { 1506 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 1507 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 1508 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 1509 } 1510 defm : VectorRounding<VFIDB, v128db>; 1511 defm : VectorRounding<WFIDB, v64db>; 1512 let Predicates = [FeatureVectorEnhancements1] in { 1513 let Uses = [FPC], mayRaiseFPException = 1 in { 1514 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>; 1515 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>; 1516 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>; 1517 } 1518 defm : VectorRounding<VFISB, v128sb>; 1519 defm : VectorRounding<WFISB, v32sb>; 1520 defm : VectorRounding<WFIXB, v128xb>; 1521 } 1522 1523 // Load lengthened. 1524 let Uses = [FPC], mayRaiseFPException = 1 in { 1525 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 1526 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_any_vextend, v128db, v128sb, 2, 0>; 1527 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, any_fpextend, v64db, v32sb, 2, 8, 0, 1528 "ldebr">; 1529 } 1530 let Predicates = [FeatureVectorEnhancements1] in { 1531 let Uses = [FPC], mayRaiseFPException = 1 in { 1532 let isAsmParserOnly = 1 in { 1533 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>; 1534 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>; 1535 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>; 1536 } 1537 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, any_fpextend, v128xb, v64db, 3, 8>; 1538 } 1539 def : Pat<(f128 (any_fpextend (f32 VR32:$src))), 1540 (WFLLD (WLDEB VR32:$src))>; 1541 } 1542 1543 // Load rounded. 1544 let Uses = [FPC], mayRaiseFPException = 1 in { 1545 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 1546 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1547 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1548 } 1549 def : Pat<(v4f32 (z_any_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 1550 def : FPConversion<WLEDB, any_fpround, v32sb, v64db, 0, 0>; 1551 let Predicates = [FeatureVectorEnhancements1] in { 1552 let Uses = [FPC], mayRaiseFPException = 1 in { 1553 let isAsmParserOnly = 1 in { 1554 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>; 1555 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1556 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1557 } 1558 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>; 1559 } 1560 def : FPConversion<WFLRX, any_fpround, v64db, v128xb, 0, 0>; 1561 def : Pat<(f32 (any_fpround (f128 VR128:$src))), 1562 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>; 1563 } 1564 1565 // Maximum. 1566 multiclass VectorMax<Instruction insn, TypedReg tr> { 1567 def : FPMinMax<insn, any_fmaxnum, tr, 4>; 1568 def : FPMinMax<insn, any_fmaximum, tr, 1>; 1569 } 1570 let Predicates = [FeatureVectorEnhancements1] in { 1571 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1572 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; 1573 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, 1574 v128db, v128db, 3, 0>; 1575 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, 1576 v64db, v64db, 3, 8>; 1577 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb, 1578 v128sb, v128sb, 2, 0>; 1579 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag, 1580 v32sb, v32sb, 2, 8>; 1581 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag, 1582 v128xb, v128xb, 4, 8>; 1583 } 1584 defm : VectorMax<VFMAXDB, v128db>; 1585 defm : VectorMax<WFMAXDB, v64db>; 1586 defm : VectorMax<VFMAXSB, v128sb>; 1587 defm : VectorMax<WFMAXSB, v32sb>; 1588 defm : VectorMax<WFMAXXB, v128xb>; 1589 } 1590 1591 // Minimum. 1592 multiclass VectorMin<Instruction insn, TypedReg tr> { 1593 def : FPMinMax<insn, any_fminnum, tr, 4>; 1594 def : FPMinMax<insn, any_fminimum, tr, 1>; 1595 } 1596 let Predicates = [FeatureVectorEnhancements1] in { 1597 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1598 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; 1599 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, 1600 v128db, v128db, 3, 0>; 1601 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, 1602 v64db, v64db, 3, 8>; 1603 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb, 1604 v128sb, v128sb, 2, 0>; 1605 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag, 1606 v32sb, v32sb, 2, 8>; 1607 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag, 1608 v128xb, v128xb, 4, 8>; 1609 } 1610 defm : VectorMin<VFMINDB, v128db>; 1611 defm : VectorMin<WFMINDB, v64db>; 1612 defm : VectorMin<VFMINSB, v128sb>; 1613 defm : VectorMin<WFMINSB, v32sb>; 1614 defm : VectorMin<WFMINXB, v128xb>; 1615 } 1616 1617 // Multiply. 1618 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1619 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 1620 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, any_fmul, v128db, v128db, 3, 0>; 1621 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, any_fmul, v64db, v64db, 3, 8, 0, 1622 "mdbr">; 1623 let Predicates = [FeatureVectorEnhancements1] in { 1624 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, any_fmul, v128sb, v128sb, 2, 0>; 1625 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, any_fmul, v32sb, v32sb, 2, 8, 0, 1626 "meebr">; 1627 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, any_fmul, v128xb, v128xb, 4, 8>; 1628 } 1629 } 1630 1631 // Multiply and add. 1632 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1633 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 1634 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, any_fma, v128db, v128db, 0, 3>; 1635 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, any_fma, v64db, v64db, 8, 3, 1636 "madbr">; 1637 let Predicates = [FeatureVectorEnhancements1] in { 1638 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, any_fma, v128sb, v128sb, 0, 2>; 1639 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, any_fma, v32sb, v32sb, 8, 2, 1640 "maebr">; 1641 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, any_fma, v128xb, v128xb, 8, 4>; 1642 } 1643 } 1644 1645 // Multiply and subtract. 1646 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1647 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 1648 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, any_fms, v128db, v128db, 0, 3>; 1649 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, any_fms, v64db, v64db, 8, 3, 1650 "msdbr">; 1651 let Predicates = [FeatureVectorEnhancements1] in { 1652 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, any_fms, v128sb, v128sb, 0, 2>; 1653 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, any_fms, v32sb, v32sb, 8, 2, 1654 "msebr">; 1655 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, any_fms, v128xb, v128xb, 8, 4>; 1656 } 1657 } 1658 1659 // Negative multiply and add. 1660 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1, 1661 Predicates = [FeatureVectorEnhancements1] in { 1662 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; 1663 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, any_fnma, v128db, v128db, 0, 3>; 1664 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, any_fnma, v64db, v64db, 8, 3>; 1665 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, any_fnma, v128sb, v128sb, 0, 2>; 1666 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, any_fnma, v32sb, v32sb, 8, 2>; 1667 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, any_fnma, v128xb, v128xb, 8, 4>; 1668 } 1669 1670 // Negative multiply and subtract. 1671 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1, 1672 Predicates = [FeatureVectorEnhancements1] in { 1673 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; 1674 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, any_fnms, v128db, v128db, 0, 3>; 1675 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, any_fnms, v64db, v64db, 8, 3>; 1676 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, any_fnms, v128sb, v128sb, 0, 2>; 1677 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, any_fnms, v32sb, v32sb, 8, 2>; 1678 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, any_fnms, v128xb, v128xb, 8, 4>; 1679 } 1680 1681 // Perform sign operation. 1682 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 1683 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 1684 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 1685 let Predicates = [FeatureVectorEnhancements1] in { 1686 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>; 1687 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>; 1688 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>; 1689 } 1690 1691 // Load complement. 1692 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 1693 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 1694 let Predicates = [FeatureVectorEnhancements1] in { 1695 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>; 1696 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>; 1697 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>; 1698 } 1699 1700 // Load negative. 1701 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 1702 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 1703 let Predicates = [FeatureVectorEnhancements1] in { 1704 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>; 1705 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>; 1706 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>; 1707 } 1708 1709 // Load positive. 1710 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 1711 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 1712 let Predicates = [FeatureVectorEnhancements1] in { 1713 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>; 1714 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>; 1715 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>; 1716 } 1717 1718 // Square root. 1719 let Uses = [FPC], mayRaiseFPException = 1 in { 1720 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 1721 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, any_fsqrt, v128db, v128db, 3, 0>; 1722 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, any_fsqrt, v64db, v64db, 3, 8, 0, 1723 "sqdbr">; 1724 let Predicates = [FeatureVectorEnhancements1] in { 1725 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, any_fsqrt, v128sb, v128sb, 2, 0>; 1726 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, any_fsqrt, v32sb, v32sb, 2, 8, 0, 1727 "sqebr">; 1728 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, any_fsqrt, v128xb, v128xb, 4, 8>; 1729 } 1730 } 1731 1732 // Subtract. 1733 let Uses = [FPC], mayRaiseFPException = 1 in { 1734 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 1735 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, any_fsub, v128db, v128db, 3, 0>; 1736 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, any_fsub, v64db, v64db, 3, 8, 0, 1737 "sdbr">; 1738 let Predicates = [FeatureVectorEnhancements1] in { 1739 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, any_fsub, v128sb, v128sb, 2, 0>; 1740 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, any_fsub, v32sb, v32sb, 2, 8, 0, 1741 "sebr">; 1742 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, any_fsub, v128xb, v128xb, 4, 8>; 1743 } 1744 } 1745 1746 // Test data class immediate. 1747 let Defs = [CC] in { 1748 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 1749 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 1750 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 1751 let Predicates = [FeatureVectorEnhancements1] in { 1752 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>; 1753 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>; 1754 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>; 1755 } 1756 } 1757} 1758 1759//===----------------------------------------------------------------------===// 1760// Floating-point comparison 1761//===----------------------------------------------------------------------===// 1762 1763let Predicates = [FeatureVector] in { 1764 // Compare scalar. 1765 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 1766 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 1767 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_any_fcmp, v64db, 3, "cdbr">; 1768 let Predicates = [FeatureVectorEnhancements1] in { 1769 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_any_fcmp, v32sb, 2, "cebr">; 1770 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_any_fcmp, v128xb, 4>; 1771 } 1772 } 1773 1774 // Compare and signal scalar. 1775 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 1776 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 1777 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, z_strict_fcmps, v64db, 3, "kdbr">; 1778 let Predicates = [FeatureVectorEnhancements1] in { 1779 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, z_strict_fcmps, v32sb, 2, "kebr">; 1780 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, z_strict_fcmps, v128xb, 4>; 1781 } 1782 } 1783 1784 // Compare equal. 1785 let Uses = [FPC], mayRaiseFPException = 1 in { 1786 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1787 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_any_vfcmpe, z_vfcmpes, 1788 v128g, v128db, 3, 0>; 1789 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1790 v64g, v64db, 3, 8>; 1791 let Predicates = [FeatureVectorEnhancements1] in { 1792 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_any_vfcmpe, z_vfcmpes, 1793 v128f, v128sb, 2, 0>; 1794 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag, 1795 v32f, v32sb, 2, 8>; 1796 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag, 1797 v128q, v128xb, 4, 8>; 1798 } 1799 } 1800 1801 // Compare and signal equal. 1802 let Uses = [FPC], mayRaiseFPException = 1, 1803 Predicates = [FeatureVectorEnhancements1] in { 1804 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, z_strict_vfcmpes, null_frag, 1805 v128g, v128db, 3, 4>; 1806 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, 1807 v64g, v64db, 3, 12>; 1808 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, z_strict_vfcmpes, null_frag, 1809 v128f, v128sb, 2, 4>; 1810 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag, 1811 v32f, v32sb, 2, 12>; 1812 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag, 1813 v128q, v128xb, 4, 12>; 1814 } 1815 1816 // Compare high. 1817 let Uses = [FPC], mayRaiseFPException = 1 in { 1818 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1819 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_any_vfcmph, z_vfcmphs, 1820 v128g, v128db, 3, 0>; 1821 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1822 v64g, v64db, 3, 8>; 1823 let Predicates = [FeatureVectorEnhancements1] in { 1824 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_any_vfcmph, z_vfcmphs, 1825 v128f, v128sb, 2, 0>; 1826 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag, 1827 v32f, v32sb, 2, 8>; 1828 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag, 1829 v128q, v128xb, 4, 8>; 1830 } 1831 } 1832 1833 // Compare and signal high. 1834 let Uses = [FPC], mayRaiseFPException = 1, 1835 Predicates = [FeatureVectorEnhancements1] in { 1836 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, z_strict_vfcmphs, null_frag, 1837 v128g, v128db, 3, 4>; 1838 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, 1839 v64g, v64db, 3, 12>; 1840 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, z_strict_vfcmphs, null_frag, 1841 v128f, v128sb, 2, 4>; 1842 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag, 1843 v32f, v32sb, 2, 12>; 1844 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag, 1845 v128q, v128xb, 4, 12>; 1846 } 1847 1848 // Compare high or equal. 1849 let Uses = [FPC], mayRaiseFPException = 1 in { 1850 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1851 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_any_vfcmphe, z_vfcmphes, 1852 v128g, v128db, 3, 0>; 1853 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1854 v64g, v64db, 3, 8>; 1855 let Predicates = [FeatureVectorEnhancements1] in { 1856 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_any_vfcmphe, z_vfcmphes, 1857 v128f, v128sb, 2, 0>; 1858 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag, 1859 v32f, v32sb, 2, 8>; 1860 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag, 1861 v128q, v128xb, 4, 8>; 1862 } 1863 } 1864 1865 // Compare and signal high or equal. 1866 let Uses = [FPC], mayRaiseFPException = 1, 1867 Predicates = [FeatureVectorEnhancements1] in { 1868 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, z_strict_vfcmphes, null_frag, 1869 v128g, v128db, 3, 4>; 1870 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, 1871 v64g, v64db, 3, 12>; 1872 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, z_strict_vfcmphes, null_frag, 1873 v128f, v128sb, 2, 4>; 1874 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag, 1875 v32f, v32sb, 2, 12>; 1876 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag, 1877 v128q, v128xb, 4, 12>; 1878 } 1879} 1880 1881//===----------------------------------------------------------------------===// 1882// Support for 128-bit integer values in vector registers 1883//===----------------------------------------------------------------------===// 1884 1885// Loads and stores. 1886let Predicates = [FeatureVector] in { 1887 def : Pat<(i128 (load bdxaddr12only:$addr)), 1888 (VL bdxaddr12only:$addr)>; 1889 def : Pat<(store (i128 VR128:$src), bdxaddr12only:$addr), 1890 (VST VR128:$src, bdxaddr12only:$addr)>; 1891} 1892 1893// Full i128 move from GPR pair. 1894let Predicates = [FeatureVector] in 1895 def : Pat<(i128 (or (zext GR64:$x), (shl (anyext GR64:$y), (i32 64)))), 1896 (VLVGP GR64:$y, GR64:$x)>; 1897 1898// Any-extensions from GPR to i128. 1899let Predicates = [FeatureVector] in { 1900 def : Pat<(i128 (anyext GR32:$x)), (VLVGP32 GR32:$x, GR32:$x)>; 1901 def : Pat<(i128 (anyext GR64:$x)), (VLVGP GR64:$x, GR64:$x)>; 1902} 1903 1904// Any-extending loads into i128. 1905let Predicates = [FeatureVector] in { 1906 def : Pat<(i128 (z_extloadi8 bdxaddr12only:$addr)), 1907 (VLREPB bdxaddr12only:$addr)>; 1908 def : Pat<(i128 (z_extloadi16 bdxaddr12only:$addr)), 1909 (VLREPH bdxaddr12only:$addr)>; 1910 def : Pat<(i128 (z_extloadi32 bdxaddr12only:$addr)), 1911 (VLREPF bdxaddr12only:$addr)>; 1912 def : Pat<(i128 (z_extloadi64 bdxaddr12only:$addr)), 1913 (VLREPG bdxaddr12only:$addr)>; 1914} 1915 1916// Truncations from i128 to GPR. 1917let Predicates = [FeatureVector] in { 1918 def : Pat<(i32 (trunc (i128 VR128:$vec))), 1919 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 3), subreg_l32)>; 1920 def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 32)))), 1921 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 2), subreg_l32)>; 1922 def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 64)))), 1923 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 1), subreg_l32)>; 1924 def : Pat<(i32 (trunc (srl (i128 VR128:$vec), (i32 96)))), 1925 (EXTRACT_SUBREG (VLGVF VR128:$vec, zero_reg, 0), subreg_l32)>; 1926 def : Pat<(i64 (trunc (i128 VR128:$vec))), 1927 (VLGVG VR128:$vec, zero_reg, 1)>; 1928 def : Pat<(i64 (trunc (srl (i128 VR128:$vec), (i32 64)))), 1929 (VLGVG VR128:$vec, zero_reg, 0)>; 1930} 1931 1932// Truncating stores from i128. 1933let Predicates = [FeatureVector] in { 1934 def : Pat<(truncstorei8 (i128 VR128:$x), bdxaddr12only:$addr), 1935 (VSTEB VR128:$x, bdxaddr12only:$addr, 15)>; 1936 def : Pat<(truncstorei16 (i128 VR128:$x), bdxaddr12only:$addr), 1937 (VSTEH VR128:$x, bdxaddr12only:$addr, 7)>; 1938 def : Pat<(truncstorei32 (i128 VR128:$x), bdxaddr12only:$addr), 1939 (VSTEF VR128:$x, bdxaddr12only:$addr, 3)>; 1940 def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 32)), bdxaddr12only:$addr), 1941 (VSTEF VR128:$x, bdxaddr12only:$addr, 2)>; 1942 def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 64)), bdxaddr12only:$addr), 1943 (VSTEF VR128:$x, bdxaddr12only:$addr, 1)>; 1944 def : Pat<(truncstorei32 (srl (i128 VR128:$x), (i32 96)), bdxaddr12only:$addr), 1945 (VSTEF VR128:$x, bdxaddr12only:$addr, 0)>; 1946 def : Pat<(truncstorei64 (i128 VR128:$x), bdxaddr12only:$addr), 1947 (VSTEG VR128:$x, bdxaddr12only:$addr, 1)>; 1948 def : Pat<(truncstorei64 (srl (i128 VR128:$x), (i32 64)), bdxaddr12only:$addr), 1949 (VSTEG VR128:$x, bdxaddr12only:$addr, 0)>; 1950} 1951 1952// Zero-extensions from GPR to i128. 1953let Predicates = [FeatureVector] in { 1954 def : Pat<(i128 (zext8 (anyext GR32:$x))), 1955 (VLVGB (VGBM 0), GR32:$x, zero_reg, 15)>; 1956 def : Pat<(i128 (zext16 (anyext GR32:$x))), 1957 (VLVGH (VGBM 0), GR32:$x, zero_reg, 7)>; 1958 def : Pat<(i128 (zext GR32:$x)), 1959 (VLVGF (VGBM 0), GR32:$x, zero_reg, 3)>; 1960 def : Pat<(i128 (zext GR64:$x)), 1961 (VLVGG (VGBM 0), GR64:$x, zero_reg, 1)>; 1962} 1963 1964// Zero-extending loads into i128. 1965let Predicates = [FeatureVector] in { 1966 def : Pat<(i128 (z_zextloadi8 bdxaddr12only:$addr)), 1967 (VLEB (VGBM 0), bdxaddr12only:$addr, 15)>; 1968 def : Pat<(i128 (z_zextloadi16 bdxaddr12only:$addr)), 1969 (VLEH (VGBM 0), bdxaddr12only:$addr, 7)>; 1970 def : Pat<(i128 (z_zextloadi32 bdxaddr12only:$addr)), 1971 (VLEF (VGBM 0), bdxaddr12only:$addr, 3)>; 1972 def : Pat<(i128 (z_zextloadi64 bdxaddr12only:$addr)), 1973 (VLEG (VGBM 0), bdxaddr12only:$addr, 1)>; 1974} 1975 1976// In-register i128 sign-extensions on arch15. 1977let Predicates = [FeatureVectorEnhancements3] in { 1978 def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>; 1979 def : Pat<(i128 (sext_inreg VR128:$x, i16)), (VUPLG (VSEGH VR128:$x))>; 1980 def : Pat<(i128 (sext_inreg VR128:$x, i32)), (VUPLG (VSEGF VR128:$x))>; 1981 def : Pat<(i128 (sext_inreg VR128:$x, i64)), (VUPLG VR128:$x)>; 1982} 1983 1984// In-register i128 sign-extensions. 1985let Predicates = [FeatureVector] in { 1986 def : Pat<(i128 (sext_inreg VR128:$x, i8)), 1987 (VSRAB (VREPB VR128:$x, 15), (VREPIB 120))>; 1988 def : Pat<(i128 (sext_inreg VR128:$x, i16)), 1989 (VSRAB (VREPH VR128:$x, 7), (VREPIB 112))>; 1990 def : Pat<(i128 (sext_inreg VR128:$x, i32)), 1991 (VSRAB (VREPF VR128:$x, 3), (VREPIB 96))>; 1992 def : Pat<(i128 (sext_inreg VR128:$x, i64)), 1993 (VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>; 1994} 1995 1996// Sign-extensions from GPR to i128 on arch15. 1997let Predicates = [FeatureVectorEnhancements3] in { 1998 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)), 1999 (VUPLG (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)), 2000 (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32))))>; 2001 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i16)), 2002 (VUPLG (VLVGP (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)), 2003 (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32))))>; 2004 def : Pat<(i128 (sext GR32:$x)), 2005 (VUPLG (VLVGP (LGFR GR32:$x), (LGFR GR32:$x)))>; 2006 def : Pat<(i128 (sext GR64:$x)), 2007 (VUPLG (VLVGP GR64:$x, GR64:$x))>; 2008} 2009 2010// Sign-extensions from GPR to i128. 2011let Predicates = [FeatureVector] in { 2012 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)), 2013 (VLVGP (SRAG (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2014 GR32:$x, subreg_l32)), zero_reg, 63), 2015 (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2016 GR32:$x, subreg_l32)))>; 2017 def : Pat<(i128 (sext_inreg (anyext GR32:$x), i16)), 2018 (VLVGP (SRAG (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2019 GR32:$x, subreg_l32)), zero_reg, 63), 2020 (LGHR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2021 GR32:$x, subreg_l32)))>; 2022 def : Pat<(i128 (sext GR32:$x)), 2023 (VLVGP (SRAG (LGFR GR32:$x), zero_reg, 63), (LGFR GR32:$x))>; 2024 def : Pat<(i128 (sext GR64:$x)), 2025 (VLVGP (SRAG GR64:$x, zero_reg, 63), GR64:$x)>; 2026} 2027 2028// Sign-extending loads into i128. 2029let Predicates = [FeatureVector] in { 2030 def : Pat<(i128 (z_sextloadi8 bdxaddr12only:$addr)), 2031 (VSRAB (VLREPB bdxaddr12only:$addr), (VREPIB 120))>; 2032 def : Pat<(i128 (z_sextloadi16 bdxaddr12only:$addr)), 2033 (VSRAB (VLREPH bdxaddr12only:$addr), (VREPIB 112))>; 2034 def : Pat<(i128 (z_sextloadi32 bdxaddr12only:$addr)), 2035 (VSRAB (VLREPF bdxaddr12only:$addr), (VREPIB 96))>; 2036 def : Pat<(i128 (z_sextloadi64 bdxaddr12only:$addr)), 2037 (VSRAB (VLREPG bdxaddr12only:$addr), (VREPIB 64))>; 2038} 2039 2040// i128 comparison pseudo-instructions. 2041let Predicates = [FeatureVector], Defs = [CC], 2042 usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 2043 def SCmp128Hi : Pseudo<(outs), (ins VR128:$src1, VR128:$src2), 2044 [(set CC, (z_scmp128hi (i128 VR128:$src1), 2045 (i128 VR128:$src2)))]>; 2046 def UCmp128Hi : Pseudo<(outs), (ins VR128:$src1, VR128:$src2), 2047 [(set CC, (z_ucmp128hi (i128 VR128:$src1), 2048 (i128 VR128:$src2)))]>; 2049} 2050 2051// i128 select pseudo-instructions. 2052let Predicates = [FeatureVector] in 2053 def Select128 : SelectWrapper<i128, VR128>; 2054 2055//===----------------------------------------------------------------------===// 2056// Conversions 2057//===----------------------------------------------------------------------===// 2058 2059let Predicates = [FeatureVector] in { 2060def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 2061def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 2062def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 2063def : Pat<(v16i8 (bitconvert (i128 VR128:$src))), (v16i8 VR128:$src)>; 2064def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 2065def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 2066def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>; 2067 2068def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 2069def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 2070def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 2071def : Pat<(v8i16 (bitconvert (i128 VR128:$src))), (v8i16 VR128:$src)>; 2072def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 2073def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 2074def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>; 2075 2076def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 2077def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 2078def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 2079def : Pat<(v4i32 (bitconvert (i128 VR128:$src))), (v4i32 VR128:$src)>; 2080def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 2081def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 2082def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>; 2083 2084def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 2085def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 2086def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 2087def : Pat<(v2i64 (bitconvert (i128 VR128:$src))), (v2i64 VR128:$src)>; 2088def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 2089def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 2090def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>; 2091 2092def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 2093def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 2094def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 2095def : Pat<(v4f32 (bitconvert (i128 VR128:$src))), (v4f32 VR128:$src)>; 2096def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 2097def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 2098def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>; 2099 2100def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 2101def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 2102def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 2103def : Pat<(v2f64 (bitconvert (i128 VR128:$src))), (v2f64 VR128:$src)>; 2104def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 2105def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 2106def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>; 2107 2108def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>; 2109def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>; 2110def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>; 2111def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>; 2112def : Pat<(f128 (bitconvert (i128 VR128:$src))), (f128 VR128:$src)>; 2113def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>; 2114def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>; 2115 2116def : Pat<(i128 (bitconvert (v16i8 VR128:$src))), (i128 VR128:$src)>; 2117def : Pat<(i128 (bitconvert (v8i16 VR128:$src))), (i128 VR128:$src)>; 2118def : Pat<(i128 (bitconvert (v4i32 VR128:$src))), (i128 VR128:$src)>; 2119def : Pat<(i128 (bitconvert (v2i64 VR128:$src))), (i128 VR128:$src)>; 2120def : Pat<(i128 (bitconvert (v4f32 VR128:$src))), (i128 VR128:$src)>; 2121def : Pat<(i128 (bitconvert (v2f64 VR128:$src))), (i128 VR128:$src)>; 2122def : Pat<(i128 (bitconvert (f128 VR128:$src))), (i128 VR128:$src)>; 2123} // End Predicates = [FeatureVector] 2124 2125//===----------------------------------------------------------------------===// 2126// Replicating scalars 2127//===----------------------------------------------------------------------===// 2128 2129// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 2130// INDEX is 8 minus the element size in bytes. 2131class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 2132 : Pat<(type (z_replicate GR32:$scalar)), 2133 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 2134 2135def : VectorReplicateScalar<v16i8, VREPB, 7>; 2136def : VectorReplicateScalar<v8i16, VREPH, 3>; 2137def : VectorReplicateScalar<v4i32, VREPF, 1>; 2138 2139// i64 replications are just a single instruction. 2140def : Pat<(v2i64 (z_replicate GR64:$scalar)), 2141 (VLVGP GR64:$scalar, GR64:$scalar)>; 2142 2143//===----------------------------------------------------------------------===// 2144// Floating-point insertion and extraction 2145//===----------------------------------------------------------------------===// 2146 2147// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 2148// and VLGVF. 2149let Predicates = [FeatureVector] in { 2150 def LEFR : UnaryAliasVRS<VR32, GR32>; 2151 def LFER : UnaryAliasVRS<GR64, VR32>; 2152 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 2153 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 2154 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 2155} 2156 2157// Floating-point values are stored in element 0 of the corresponding 2158// vector register. Scalar to vector conversion is just a subreg and 2159// scalar replication can just replicate element 0 of the vector register. 2160multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 2161 SubRegIndex subreg> { 2162 def : Pat<(vt (scalar_to_vector cls:$scalar)), 2163 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 2164 def : Pat<(vt (z_replicate cls:$scalar)), 2165 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 2166 subreg), 0)>; 2167} 2168defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>; 2169defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>; 2170 2171// Match v2f64 insertions. The AddedComplexity counters the 3 added by 2172// TableGen for the base register operand in VLVG-based integer insertions 2173// and ensures that this version is strictly better. 2174let AddedComplexity = 4 in { 2175 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 2176 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 2177 subreg_h64), VR128:$vec, 1)>; 2178 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 2179 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 2180 subreg_h64), 0)>; 2181} 2182 2183// We extract floating-point element X by replicating (for elements other 2184// than 0) and then taking a high subreg. The AddedComplexity counters the 2185// 3 added by TableGen for the base register operand in VLGV-based integer 2186// extractions and ensures that this version is strictly better. 2187let AddedComplexity = 4 in { 2188 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 2189 (EXTRACT_SUBREG VR128:$vec, subreg_h32)>; 2190 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 2191 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_h32)>; 2192 2193 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 2194 (EXTRACT_SUBREG VR128:$vec, subreg_h64)>; 2195 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 2196 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_h64)>; 2197} 2198 2199//===----------------------------------------------------------------------===// 2200// Support for 128-bit floating-point values in vector registers 2201//===----------------------------------------------------------------------===// 2202 2203let Predicates = [FeatureVectorEnhancements1] in { 2204 def : Pat<(f128 (load bdxaddr12only:$addr)), 2205 (VL bdxaddr12only:$addr)>; 2206 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr), 2207 (VST VR128:$src, bdxaddr12only:$addr)>; 2208 2209 def : Pat<(f128 fpimm0), (VZERO)>; 2210 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>; 2211} 2212 2213//===----------------------------------------------------------------------===// 2214// String instructions 2215//===----------------------------------------------------------------------===// 2216 2217let Predicates = [FeatureVector] in { 2218 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 2219 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 2220 z_vfae_cc, v128b, v128b, 0>; 2221 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 2222 z_vfae_cc, v128h, v128h, 1>; 2223 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 2224 z_vfae_cc, v128f, v128f, 2>; 2225 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 2226 z_vfaez_cc, v128b, v128b, 0, 2>; 2227 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 2228 z_vfaez_cc, v128h, v128h, 1, 2>; 2229 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 2230 z_vfaez_cc, v128f, v128f, 2, 2>; 2231 2232 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 2233 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 2234 z_vfee_cc, v128b, v128b, 0>; 2235 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 2236 z_vfee_cc, v128h, v128h, 1>; 2237 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 2238 z_vfee_cc, v128f, v128f, 2>; 2239 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 2240 z_vfeez_cc, v128b, v128b, 0, 2>; 2241 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 2242 z_vfeez_cc, v128h, v128h, 1, 2>; 2243 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 2244 z_vfeez_cc, v128f, v128f, 2, 2>; 2245 2246 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 2247 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 2248 z_vfene_cc, v128b, v128b, 0>; 2249 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 2250 z_vfene_cc, v128h, v128h, 1>; 2251 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 2252 z_vfene_cc, v128f, v128f, 2>; 2253 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 2254 z_vfenez_cc, v128b, v128b, 0, 2>; 2255 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 2256 z_vfenez_cc, v128h, v128h, 1, 2>; 2257 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 2258 z_vfenez_cc, v128f, v128f, 2, 2>; 2259 2260 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 2261 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 2262 z_vistr_cc, v128b, v128b, 0>; 2263 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 2264 z_vistr_cc, v128h, v128h, 1>; 2265 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 2266 z_vistr_cc, v128f, v128f, 2>; 2267 2268 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 2269 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 2270 z_vstrc_cc, v128b, v128b, 0>; 2271 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 2272 z_vstrc_cc, v128h, v128h, 1>; 2273 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 2274 z_vstrc_cc, v128f, v128f, 2>; 2275 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 2276 z_vstrcz_cc, v128b, v128b, 0, 2>; 2277 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 2278 z_vstrcz_cc, v128h, v128h, 1, 2>; 2279 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 2280 z_vstrcz_cc, v128f, v128f, 2, 2>; 2281} 2282 2283let Predicates = [FeatureVectorEnhancements2] in { 2284 defm VSTRS : TernaryExtraVRRdGeneric<"vstrs", 0xE78B>; 2285 defm VSTRSB : TernaryExtraVRRd<"vstrsb", 0xE78B, 2286 z_vstrs_cc, v128b, v128b, 0>; 2287 defm VSTRSH : TernaryExtraVRRd<"vstrsh", 0xE78B, 2288 z_vstrs_cc, v128b, v128h, 1>; 2289 defm VSTRSF : TernaryExtraVRRd<"vstrsf", 0xE78B, 2290 z_vstrs_cc, v128b, v128f, 2>; 2291 let Defs = [CC] in { 2292 def VSTRSZB : TernaryVRRd<"vstrszb", 0xE78B, 2293 z_vstrsz_cc, v128b, v128b, 0, 2>; 2294 def VSTRSZH : TernaryVRRd<"vstrszh", 0xE78B, 2295 z_vstrsz_cc, v128b, v128h, 1, 2>; 2296 def VSTRSZF : TernaryVRRd<"vstrszf", 0xE78B, 2297 z_vstrsz_cc, v128b, v128f, 2, 2>; 2298 } 2299} 2300 2301//===----------------------------------------------------------------------===// 2302// NNP assist instructions 2303//===----------------------------------------------------------------------===// 2304 2305let Predicates = [FeatureVector, FeatureNNPAssist] in { 2306 let Uses = [FPC], mayRaiseFPException = 1 in 2307 def VCFN : UnaryVRRaFloatGeneric<"vcfn", 0xE65D>; 2308 def : Pat<(int_s390_vcfn VR128:$x, imm32zx4_timm:$m), 2309 (VCFN VR128:$x, 1, imm32zx4:$m)>; 2310 2311 let Uses = [FPC], mayRaiseFPException = 1 in 2312 def VCLFNL : UnaryVRRaFloatGeneric<"vclfnl", 0xE65E>; 2313 def : Pat<(int_s390_vclfnls VR128:$x, imm32zx4_timm:$m), 2314 (VCLFNL VR128:$x, 2, imm32zx4:$m)>; 2315 2316 let Uses = [FPC], mayRaiseFPException = 1 in 2317 def VCLFNH : UnaryVRRaFloatGeneric<"vclfnh", 0xE656>; 2318 def : Pat<(int_s390_vclfnhs VR128:$x, imm32zx4_timm:$m), 2319 (VCLFNH VR128:$x, 2, imm32zx4:$m)>; 2320 2321 let Uses = [FPC], mayRaiseFPException = 1 in 2322 def VCNF : UnaryVRRaFloatGeneric<"vcnf", 0xE655>; 2323 def : Pat<(int_s390_vcnf VR128:$x, imm32zx4_timm:$m), 2324 (VCNF VR128:$x, imm32zx4:$m, 1)>; 2325 2326 let Uses = [FPC], mayRaiseFPException = 1 in 2327 def VCRNF : BinaryVRRcFloatGeneric<"vcrnf", 0xE675>; 2328 def : Pat<(int_s390_vcrnfs VR128:$x, VR128:$y, imm32zx4_timm:$m), 2329 (VCRNF VR128:$x, VR128:$y, imm32zx4:$m, 2)>; 2330} 2331 2332//===----------------------------------------------------------------------===// 2333// Packed-decimal instructions 2334//===----------------------------------------------------------------------===// 2335 2336let Predicates = [FeatureVectorPackedDecimal] in { 2337 def VLIP : BinaryVRIh<"vlip", 0xE649>; 2338 2339 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; 2340 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; 2341 2342 let Defs = [CC] in { 2343 let Predicates = [FeatureVectorPackedDecimalEnhancement] in { 2344 def VCVBOpt : TernaryVRRi<"vcvb", 0xE650, GR32>; 2345 def VCVBGOpt : TernaryVRRi<"vcvbg", 0xE652, GR64>; 2346 } 2347 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; 2348 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; 2349 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; 2350 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; 2351 2352 def VAP : QuaternaryVRIf<"vap", 0xE671>; 2353 def VSP : QuaternaryVRIf<"vsp", 0xE673>; 2354 2355 def VMP : QuaternaryVRIf<"vmp", 0xE678>; 2356 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; 2357 2358 def VDP : QuaternaryVRIf<"vdp", 0xE67A>; 2359 def VRP : QuaternaryVRIf<"vrp", 0xE67B>; 2360 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; 2361 2362 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; 2363 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; 2364 2365 def VTP : TestVRRg<"vtp", 0xE65F>; 2366 def VCP : CompareVRRh<"vcp", 0xE677>; 2367 } 2368} 2369 2370let Predicates = [FeatureVectorPackedDecimalEnhancement2] in { 2371 def VSCHP : BinaryExtraVRRbGeneric<"vschp", 0xE674>; 2372 def VSCHSP : BinaryExtraVRRb<"vschsp", 0xE674, 2>; 2373 def VSCHDP : BinaryExtraVRRb<"vschdp", 0xE674, 3>; 2374 def VSCHXP : BinaryExtraVRRb<"vschxp", 0xE674, 4>; 2375 2376 def VSCSHP : BinaryVRRb<"vscshp", 0xE67C, null_frag, v128b, v128b>; 2377 2378 def VCSPH : TernaryVRRj<"vcsph", 0xE67D>; 2379 2380 let Defs = [CC] in 2381 def VCLZDP : BinaryVRRk<"vclzdp", 0xE651>; 2382 2383 let Defs = [CC] in 2384 def VSRPR : QuaternaryVRIf<"vsrpr", 0xE672>; 2385 2386 let Defs = [CC] in { 2387 def VPKZR : QuaternaryVRIf<"vpkzr", 0xE670>; 2388 def VUPKZH : BinaryVRRk<"vupkzh", 0xE654>; 2389 def VUPKZL : BinaryVRRk<"vupkzl", 0xE65C>; 2390 } 2391} 2392 2393let Predicates = [FeatureVectorPackedDecimalEnhancement3] in { 2394 def VCVBQ : BinaryVRRk<"vcvbq", 0xE64E>; 2395 let Defs = [CC] in 2396 def VCVDQ : TernaryVRIj<"vcvdq", 0xE64A>; 2397 2398 let Defs = [CC] in { 2399 def VTPOpt : TestExtraVRRg<"vtp", 0xE65F>; 2400 def VTZ : TestExtraVRIl<"vtz", 0xE67F>; 2401 } 2402} 2403