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Searched refs:vsld (Results 1 – 22 of 22) sorted by relevance

/llvm-project/llvm/test/MC/VE/
H A DVSLD.s6 # CHECK-INST: vsld %v11, (%v22, %v23), %s20
8 vsld %v11, (%v22, %v23), %s20 label
10 # CHECK-INST: vsld %vix, (%vix, %vix), %s23
12 vsld %vix, (%vix, %vix), %s23 label
14 # CHECK-INST: vsld %vix, (%v22, %v30), 22
16 vsld %vix, (%v22, %v30), 22 label
18 # CHECK-INST: vsld %v11, (%v22, %vix), 127, %vm11
20 vsld %v11, (%v22, %vix), 127, %vm11 label
22 # CHECK-INST: vsld %v11, (%vix, %v22), 21, %vm11
24 vsld %v11, (%vix, %v22), 21, %vm11 label
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dvector-extend-sign.ll83 ; CHECK-P8-NEXT: vsld 2, 2, 3
109 ; CHECK-P8-NEXT: vsld 2, 2, 3
135 ; CHECK-P8-NEXT: vsld 2, 2, 3
150 ; CHECK-P9-NEXT: vsld 2, 2, 3
167 ; CHECK-P8-NEXT: vsld 2, 2, 3
H A Dvec_rotate_shift.ll6 declare <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64>, <2 x i64>) nounwind readnone
20 ; CHECK: vsld 2, 2, 3
H A Dmul-const-vector.ll281 ; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]]
292 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
304 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
318 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
332 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
347 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
362 ; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]
373 ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
H A Dvec_conv_i16_to_fp64_elts.ll391 ; CHECK-P8-NEXT: vsld v2, v2, v3
441 ; CHECK-P8-NEXT: vsld v2, v2, v4
444 ; CHECK-P8-NEXT: vsld v2, v3, v4
524 ; CHECK-P8-NEXT: vsld v3, v3, v0
525 ; CHECK-P8-NEXT: vsld v2, v2, v0
526 ; CHECK-P8-NEXT: vsld v4, v4, v0
527 ; CHECK-P8-NEXT: vsld v5, v5, v0
653 ; CHECK-P8-NEXT: vsld v0, v0, v1
654 ; CHECK-P8-NEXT: vsld v7, v7, v1
655 ; CHECK-P8-NEXT: vsld v
[all...]
H A Dvec_conv_i8_to_fp64_elts.ll426 ; CHECK-P8-NEXT: vsld v2, v2, v3
476 ; CHECK-P8-NEXT: vsld v2, v2, v4
479 ; CHECK-P8-NEXT: vsld v2, v3, v4
560 ; CHECK-P8-NEXT: vsld v2, v2, v0
561 ; CHECK-P8-NEXT: vsld v5, v5, v0
562 ; CHECK-P8-NEXT: vsld v3, v3, v0
563 ; CHECK-P8-NEXT: vsld v4, v4, v0
703 ; CHECK-P8-NEXT: vsld v4, v4, v8
704 ; CHECK-P8-NEXT: vsld v3, v3, v8
705 ; CHECK-P8-NEXT: vsld v
[all...]
H A Dvec-itofp.ll263 ; CHECK-P8-NEXT: vsld v3, v3, v0
264 ; CHECK-P8-NEXT: vsld v2, v2, v0
265 ; CHECK-P8-NEXT: vsld v4, v4, v0
266 ; CHECK-P8-NEXT: vsld v5, v5, v0
378 ; CHECK-P8-NEXT: vsld v3, v3, v4
379 ; CHECK-P8-NEXT: vsld v2, v2, v4
447 ; CHECK-P8-NEXT: vsld v2, v2, v3
H A Doptimize-vector.ll42 ; CHECK-NEXT: vsld v2, v2, v3
H A Dpr47891.ll21 ; CHECK-NEXT: vsld v2, v2, v4
H A Dshift_mask.ll82 ; CHECK-NEXT: vsld 2, 2, 3
H A Dvsx.ll1839 ; CHECK-LE-NEXT: vsld v2, v2, v3
2292 ; CHECK-LE-NEXT: vsld v2, v2, v3
2372 ; CHECK-LE-NEXT: vsld v2, v2, v3
H A Dvector-constrained-fp-intrinsics.ll6957 ; PC64LE-NEXT: vsld 2, 2, 3
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dvec-intrinsics-03.ll6 declare <16 x i8> @llvm.s390.vsld(<16 x i8>, <16 x i8>, i32)
21 ; CHECK-NEXT: vsld %v24, %v24, %v26, 1
23 %res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 1)
31 ; CHECK-NEXT: vsld %v24, %v24, %v26, 7
33 %res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 7)
/llvm-project/llvm/test/MC/SystemZ/
H A Dinsn-good-z15.s942 #CHECK: vsld %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x86]
943 #CHECK: vsld %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x00,0x86]
944 #CHECK: vsld %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x86]
945 #CHECK: vsld %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x86]
946 #CHECK: vsld %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x86]
947 #CHECK: vsld %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x86]
949 vsld %v0, %v0, %v0, 0
950 vsld %v0, %v0, %v0, 255
951 vsld %v0, %v0, %v31, 0
952 vsld
[all...]
H A Dinsn-bad-z15.s642 #CHECK: vsld %v0, %v0, %v0, -1
644 #CHECK: vsld %v0, %v0, %v0, 256
646 vsld %v0, %v0, %v0, -1
647 vsld %v0, %v0, %v0, 256
H A Dinsn-bad-z14.s764 #CHECK: vsld %v0, %v0, %v0, 0
766 vsld %v0, %v0, %v0, 0
/llvm-project/llvm/test/MC/Disassembler/SystemZ/
H A Dinsns-z15.txt956 # CHECK: vsld %v0, %v0, %v0, 0
959 # CHECK: vsld %v0, %v0, %v0, 255
962 # CHECK: vsld %v0, %v0, %v31, 0
965 # CHECK: vsld %v0, %v31, %v0, 0
968 # CHECK: vsld %v31, %v0, %v0, 0
971 # CHECK: vsld %v13, %v17, %v21, 121
/llvm-project/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s592 # CHECK-BE: vsld 2, 3, 4 # encoding: [0x10,0x43,0x25,0xc4]
593 # CHECK-LE: vsld 2, 3, 4 # encoding: [0xc4,0x25,0x43,0x10]
594 vsld 2, 3, 4
/llvm-project/llvm/test/Verifier/SystemZ/
H A Dintrinsic-immarg.ll384 declare <16 x i8> @llvm.s390.vsld(<16 x i8>, <16 x i8>, i32)
388 ; CHECK-NEXT: %res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 %c)
389 %res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 %c)
/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td1056 defm VSLD : RVSDm<"vsld", 0xe4, V64, VM>;
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td1243 "vsld $VD, $VA, $VB", IIC_VecGeneral, []>;
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td982 def VSLD : TernaryVRId<"vsld", 0xE786, int_s390_vsld, v128b, v128b, 0>;