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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1567 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
1570 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
1575 def VOP3ModsNonCanonicalizing : ComplexPattern<untyped, 2,
1578 def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
1580 def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
1582 def VOP3PMods : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
1584 def VOP3PModsDOT : ComplexPattern<untyped, 2, "SelectVOP3PModsDOT">;
1585 def VOP3PModsNeg : ComplexPattern<untyped, 1, "SelectVOP3PModsNeg">;
1586 def WMMAOpSelVOP3PMods : ComplexPattern<untyped, 1, "SelectWMMAOpSelVOP3PMods">;
1588 def WMMAModsF32NegAbs : ComplexPattern<untyped,
[all...]
H A DVOP1Instructions.td181 VOPProfile<[dstVt, srcVt, untyped, untyped]> {
203 def VOP_NOP_PROFILE : VOPProfile <[untyped, untyped, untyped, untyped]>{
210 VOPProfile<[dstVt, srcVt, untyped, untyped]> {
231 def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped]> {
[all...]
H A DVOP3Instructions.td66 def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
75 def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
385 def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>,
590 VOP3_Profile<VOPProfile<[i32, SrcVT, i32, untyped]>> {
843 def VOP3_PERMLANE_VAR_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, untyped]>, VOP3_OPSEL> {
951 class VOP3_CVT_SCALE_F1632_FP8BF8_Profile<ValueType DstTy> : VOP3_Profile<VOPProfile<[DstTy, i32, f32, untyped]>,
1042 class VOP3_CVT_SCALE_PK_F16BF16F32_FP4FP8BF8_Profile<ValueType DstTy> : VOP3_Profile<VOPProfile<[DstTy, i32, f32, untyped]>,
1463 : VOPProfile<[dstVt, srcVt, untyped, untyped]> {
H A DVOP2Instructions.td592 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/1> {
750 def VOP_READLANE : VOPProfile<[i32, i32, i32, untyped]> {
985 def LDEXP_F16_VOPProfile : VOPProfile <[f16, f16, f16, untyped]> {
/llvm-project/lld/test/ELF/
H A Dmips-jalr-non-functions.s31 .reloc .Ltmp3, R_MIPS_JALR, untyped
36 ## However, we do perform the optimization for untyped symbols:
37 untyped: label
57 # CHECK-NEXT: b {{.*}} <untyped>
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td561 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
565 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
569 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
582 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
586 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
590 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
807 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
811 def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
1113 def PPR2 : RegisterClass<"AArch64", [untyped], 16, (add PSeqPairs)> {
1144 def PPR2Mul2 : RegisterClass<"AArch64", [untyped], 1
[all...]
H A DSMEInstrFormats.td908 def : Pat<(Store PPR3bAny:$pg, GPR64sp:$base, (imm2tile untyped:$tile),
915 (imm2tile untyped:$tile),
1290 (imm2tile untyped:$tile), MatrixIndexGPR32Op12_15:$idx)),
1294 (imm2tile untyped:$tile),
3509 def : Pat<(int_aarch64_sme_zero_zt (imm_to_zt untyped:$zt)),
3540 def : Pat<(op (imm_to_zt untyped:$tile), GPR64sp:$base),
3593 def : Pat<(intrinsic_lane (imm_to_zt untyped:$zt), vt:$zn, sme_elm_idx0_3:$imm),
3595 def : Pat<(intrinsic (imm_to_zt untyped:$zt), vt:$zn),
3630 def : Pat<(nxv16i8 (intrinsic (imm_to_zt untyped:$zt), nxv16i8:$zn, (i32 VectorIndexB32b_timm:$imm))),
3632 def : Pat<(nxv8i16 (intrinsic (imm_to_zt untyped
[all...]
/llvm-project/llvm/test/TableGen/
H A DConcatenatedSubregs.td65 def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>;
70 def Stup2 : MyClass<32, [untyped], (interleave DRegs, Stup2_odds_regs)>;
H A DDefaultOpsGlobalISel.td
H A DHwModeSubRegs.td55 def XPairsClass : MyClass<64, [untyped], (add XPairs)>;
H A DHwModeBitSet.td67 def XPairsClass : MyClass<64, [untyped], (add XPairs)>;
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td128 // register pairs as untyped instead.
130 defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
145 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q),
313 def v128any : TypedReg<untyped, VR128>;
H A DSystemZOperators.td48 [SDTCisVT<0, untyped>,
94 [SDTCisVT<0, untyped>,
97 [SDTCisVT<0, untyped>,
100 [SDTCisVT<0, untyped>,
103 SDTCisVT<3, untyped>,
104 SDTCisVT<4, untyped>]>;
/llvm-project/llvm/docs/GlobalISel/
H A DMIRPatterns.rst46 * untyped, unnamed: ``0``
47 * untyped, named: ``0:$y``
53 * untyped: ``$x``
294 need to leave it untyped and check the type in C++, or duplicate the
420 * If the immediate is untyped, a simple immediate is added
/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td464 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
468 def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
472 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
H A DMipsDSPInstrInfo.td32 SDTCisVT<2, untyped>]>;
33 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
35 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
H A DMipsInstrInfo.td26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td551 def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp, Tuples2Rsp)> {
556 def GPRPairnosp : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp)> {
567 def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {
628 def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {
/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td826 def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
827 def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
828 def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
829 def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
830 def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;}
846 def TILEPAIR : RegisterClass<"X86", [untyped], 512, (add TPAIRS)> {let Size = 16384;}
/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td323 def untyped : ValueType<8, 226> { // Produces an untyped value
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td180 def GPRPair : RegisterClass<"CSKY", [untyped], 32, (add GPRTuple)> {
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td211 defvar XLenPairVT = untyped;
/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td861 SDTypeProfile<1, 0, [SDTCisVT<0,untyped>]>>;
863 SDTypeProfile<1, 0, [SDTCisVT<0,untyped>]>>;
866 [SDTCisVT<0,untyped>, SDTCisVT<1,untyped>]>>;
868 SDTypeProfile<0, 1, [SDTCisVT<0, untyped>]>>;
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td525 def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048,
/llvm-project/llvm/docs/
H A DMIRLangRef.rst469 The immediate machine operands are untyped, 64-bit signed integers. The

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