xref: /llvm-project/llvm/test/TableGen/HwModeSubRegs.td (revision baf66ec061aa4da85d6bdfd1f9cd1030b9607fbb)
1// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
2include "llvm/Target/Target.td"
3
4def HasFeat : Predicate<"Subtarget->hasFeat()">;
5
6def TestMode : HwMode<"+feat1", [HasFeat]>;
7
8class MyReg<string n>
9  : Register<n> {
10  let Namespace = "Test";
11}
12class MyClass<int size, list<ValueType> types, dag registers>
13  : RegisterClass<"Test", types, size, registers> {
14  let Size = size;
15}
16
17def X0 : MyReg<"x0">;
18def X1 : MyReg<"x1">;
19def X2 : MyReg<"x2">;
20def X3 : MyReg<"x3">;
21def X4 : MyReg<"x4">;
22def X5 : MyReg<"x5">;
23def X6 : MyReg<"x6">;
24def X7 : MyReg<"x7">;
25def X8 : MyReg<"x8">;
26def X9 : MyReg<"x9">;
27def X10 : MyReg<"x10">;
28def X11 : MyReg<"x11">;
29def X12 : MyReg<"x12">;
30def X13 : MyReg<"x13">;
31def X14 : MyReg<"x14">;
32def X15 : MyReg<"x15">;
33
34def ModeVT : ValueTypeByHwMode<[DefaultMode, TestMode],
35                               [i32,  i64]>;
36let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],
37                               [RegInfo<32,32,32>, RegInfo<64,64,64>]> in
38def XRegs : MyClass<32, [ModeVT], (sequence "X%u", 0, 15)>;
39
40def sub_even : SubRegIndex<32> {
41  let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],
42                                         [SubRegRange<32>, SubRegRange<64>]>;
43}
44def sub_odd  : SubRegIndex<32, 32> {
45  let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],
46                                         [SubRegRange<32, 32>, SubRegRange<64, 64>]>;
47}
48
49def XPairs : RegisterTuples<[sub_even, sub_odd],
50                            [(decimate (rotl XRegs, 0), 2),
51                             (decimate (rotl XRegs, 1), 2)]>;
52
53let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],
54                               [RegInfo<64,64,32>, RegInfo<128,128,64>]> in
55def XPairsClass : MyClass<64, [untyped], (add XPairs)>;
56
57def TestTarget : Target;
58
59// CHECK-LABEL: RegisterClass XRegs:
60// CHECK: SpillSize: { Default:32 TestMode:64 }
61// CHECK: SpillAlignment: { Default:32 TestMode:64 }
62// CHECK: Regs: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
63
64// CHECK-LABEL: RegisterClass XPairsClass:
65// CHECK: SpillSize: { Default:64 TestMode:128 }
66// CHECK: SpillAlignment: { Default:32 TestMode:64 }
67// CHECK: CoveredBySubRegs: 1
68// CHECK: Regs: X0_X1 X2_X3 X4_X5 X6_X7 X8_X9 X10_X11 X12_X13 X14_X15
69
70// CHECK-LABEL: SubRegIndex sub_even:
71// CHECK: Offset: { Default:0 TestMode:0 }
72// CHECK: Size: { Default:32 TestMode:64 }
73// CHECK-LABEL: SubRegIndex sub_odd:
74// CHECK: Offset: { Default:32 TestMode:64 }
75// CHECK: Size: { Default:32 TestMode:64 }
76