1// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s 2// Checks that tablegen correctly and completely infers subregister relations. 3include "llvm/Target/Target.td" 4 5class MyReg<string n, list<Register> subregs = []> 6 : Register<n> { 7 let Namespace = "Test"; 8 let SubRegs = subregs; 9 let CoveredBySubRegs = 1; 10} 11class MyClass<int size, list<ValueType> types, dag registers> 12 : RegisterClass<"Test", types, size, registers> { 13 let Size = size; 14} 15 16// Register Example: 17// D0_D1 -- D0 (sub0) -- S0 (ssub0) 18// \ \- S1 (ssub1) 19// \ D1 (sub1) -- S2 (ssub2) 20// \- S3 (ssub3) 21 22def sub0 : SubRegIndex<32>; 23def sub1 : SubRegIndex<32, 32>; 24def sub2 : SubRegIndex<32, 64>; 25 26def ssub0 : SubRegIndex<-1>; 27def ssub1 : SubRegIndex<16, 16>; 28def ssub2 : ComposedSubRegIndex<sub1, ssub0>; 29def ssub3 : ComposedSubRegIndex<sub1, ssub1>; 30def ssub4 : ComposedSubRegIndex<sub2, ssub0>; 31 32def S0 : MyReg<"s0">; 33def S1 : MyReg<"s1">; 34def S2 : MyReg<"s2">; 35def S3 : MyReg<"s3">; 36def S4 : MyReg<"s4">; 37def S5 : MyReg<"s5">; 38def S6 : MyReg<"s6">; 39def S7 : MyReg<"s7">; 40def S8 : MyReg<"s8">; 41def S9 : MyReg<"s9">; 42def S10 : MyReg<"s10">; 43def S11 : MyReg<"s11">; 44def S12 : MyReg<"s12">; 45def S13 : MyReg<"s13">; 46def S14 : MyReg<"s14">; 47def S15 : MyReg<"s15">; 48def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>; 49 50let SubRegIndices = [ssub0, ssub1] in { 51def D0 : MyReg<"d0", [S0, S1]>; 52def D1 : MyReg<"d1", [S2, S3]>; 53def D2 : MyReg<"d2", [S4, S5]>; 54def D3 : MyReg<"d3", [S6, S7]>; 55def D4 : MyReg<"d4", [S8, S9]>; 56def D5 : MyReg<"d5", [S10, S11]>; 57def D6 : MyReg<"d6", [S12, S13]>; 58def D7 : MyReg<"d7", [S14, S15]>; 59} 60 61def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 7)>; 62 63def Dtup2regs : RegisterTuples<[sub0, sub1], 64 [(shl DRegs, 0), (shl DRegs, 1)]>; 65def Dtup2 : MyClass<64, [untyped], (add Dtup2regs)>; 66 67def Stup2_odds_regs : RegisterTuples<[ssub0, ssub1], 68 [(decimate (shl SRegs, 1), 2), 69 (decimate (shl SRegs, 2), 2)]>; 70def Stup2 : MyClass<32, [untyped], (interleave DRegs, Stup2_odds_regs)>; 71 72def Stup5 : RegisterTuples<[ssub0, ssub1, ssub2, ssub3, ssub4], [ 73 (shl SRegs, 0), 74 (shl SRegs, 1), 75 (shl SRegs, 2), 76 (shl SRegs, 3), 77 (shl SRegs, 4) 78 ]>; 79 80 81def TestTarget : Target; 82 83// CHECK-LABEL: RegisterClass SRegs: 84// CHECK: CoveredBySubRegs: 1 85// CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 86 87// CHECK-LABEL: RegisterClass Stup2: 88// CHECK: CoveredBySubRegs: 1 89// CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14 90// CHECK-LABEL: RegisterClass DRegs: 91 92// CHECK-LABEL: SubRegIndex ssub1: 93// CHECK: Offset: { Default:16 } 94// CHECK: Size: { Default:16 } 95// CHECK-LABEL: SubRegIndex sub0: 96// CHECK-LABEL: SubRegIndex sub1: 97// CHECK-LABEL: SubRegIndex sub2: 98// Check inferred indexes: 99// CHECK-LABEL: SubRegIndex ssub1_ssub2: 100// CHECK: Offset: { Default:16 } 101// CHECK: Size: { Default:65535 } 102// CHECK-LABEL: SubRegIndex ssub3_ssub4: 103// CHECK-LABEL: SubRegIndex ssub0_ssub1_ssub2_ssub3: 104// CHECK: Offset: { Default:65535 } 105// CHECK: Size: { Default:65535 } 106// CHECK-LABEL: SubRegIndex ssub1_ssub2_ssub3_ssub4: 107 108// Check that all subregs are generated on some examples 109// CHECK-LABEL: Register D0: 110// CHECK: HasDisjunctSubRegs: 1 111// CHECK-NEXT: SubReg ssub0 = S0 112// CHECK-NEXT: SubReg ssub1 = S1 113 114// CHECK-LABEL: Register S9_S10_S11_S12_S13: 115// CHECK: HasDisjunctSubRegs: 1 116// CHECK-NEXT: SubReg ssub0 = S9 117// CHECK-NEXT: SubReg ssub1 = S10 118// CHECK-NEXT: SubReg ssub2 = S11 119// CHECK-NEXT: SubReg ssub3 = S12 120// CHECK-NEXT: SubReg ssub4 = S13 121// CHECK-NEXT: SubReg sub0 = S9_S10 122// CHECK-NEXT: SubReg sub1 = S11_S12 123// CHECK-NEXT: SubReg ssub1_ssub2 = D5 124// CHECK-NEXT: SubReg ssub3_ssub4 = D6 125// CHECK-NEXT: SubReg ssub1_ssub2_ssub3_ssub4 = D5_D6 126 127// CHECK-LABEL: Register S10_S11_S12_S13_S14: 128// CHECK: HasDisjunctSubRegs: 1 129// CHECK-NEXT: SubReg ssub0 = S10 130// CHECK-NEXT: SubReg ssub1 = S11 131// CHECK-NEXT: SubReg ssub2 = S12 132// CHECK-NEXT: SubReg ssub3 = S13 133// CHECK-NEXT: SubReg ssub4 = S14 134// CHECK-NEXT: SubReg sub0 = D5 135// CHECK-NEXT: SubReg sub1 = D6 136// CHECK-NEXT: SubReg ssub1_ssub2 = S11_S12 137// CHECK-NEXT: SubReg ssub3_ssub4 = S13_S14 138// CHECK-NEXT: SubReg ssub0_ssub1_ssub2_ssub3 = D5_D6 139