| /llvm-project/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 29 class Opcode {
41 Opcode() = default;
43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
70 m_type = Opcode::eTypeInvalid; in Clear()
73 Opcode::Type GetType() const { return m_type; } in GetType()
77 case Opcode::eTypeInvalid:
[all …]
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 106 static BranchPredicate getBranchPredicate(unsigned Opcode);
135 unsigned Opcode) const;
138 unsigned Opcode) const;
141 unsigned Opcode, bool Swap = false) const;
144 unsigned Opcode,
160 unsigned Opcode,
421 bool isSALU(uint16_t Opcode) const { in isVALU()
422 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isVALU()
429 bool isVALU(uint16_t Opcode) const { in isImage()
430 return get(Opcode) in isImage()
412 isSALU(uint16_t Opcode) isSALU() argument
420 isVALU(uint16_t Opcode) isVALU() argument
428 isImage(uint16_t Opcode) isImage() argument
436 isVMEM(uint16_t Opcode) isVMEM() argument
444 isSOP1(uint16_t Opcode) isSOP1() argument
452 isSOP2(uint16_t Opcode) isSOP2() argument
460 isSOPC(uint16_t Opcode) isSOPC() argument
468 isSOPK(uint16_t Opcode) isSOPK() argument
476 isSOPP(uint16_t Opcode) isSOPP() argument
484 isPacked(uint16_t Opcode) isPacked() argument
492 isVOP1(uint16_t Opcode) isVOP1() argument
500 isVOP2(uint16_t Opcode) isVOP2() argument
508 isVOP3(uint16_t Opcode) isVOP3() argument
516 isSDWA(uint16_t Opcode) isSDWA() argument
524 isVOPC(uint16_t Opcode) isVOPC() argument
532 isMUBUF(uint16_t Opcode) isMUBUF() argument
540 isMTBUF(uint16_t Opcode) isMTBUF() argument
548 isSMRD(uint16_t Opcode) isSMRD() argument
558 isDS(uint16_t Opcode) isDS() argument
566 isLDSDMA(uint16_t Opcode) isLDSDMA() argument
574 isGWS(uint16_t Opcode) isGWS() argument
584 isMIMG(uint16_t Opcode) isMIMG() argument
592 isVIMAGE(uint16_t Opcode) isVIMAGE() argument
600 isVSAMPLE(uint16_t Opcode) isVSAMPLE() argument
608 isGather4(uint16_t Opcode) isGather4() argument
623 isSegmentSpecificFLAT(uint16_t Opcode) isSegmentSpecificFLAT() argument
632 isFLATGlobal(uint16_t Opcode) isFLATGlobal() argument
640 isFLATScratch(uint16_t Opcode) isFLATScratch() argument
645 isFLAT(uint16_t Opcode) isFLAT() argument
661 isEXP(uint16_t Opcode) isEXP() argument
669 isAtomicNoRet(uint16_t Opcode) isAtomicNoRet() argument
677 isAtomicRet(uint16_t Opcode) isAtomicRet() argument
686 isAtomic(uint16_t Opcode) isAtomic() argument
699 isWQM(uint16_t Opcode) isWQM() argument
707 isDisableWQM(uint16_t Opcode) isDisableWQM() argument
722 isVGPRSpill(uint16_t Opcode) isVGPRSpill() argument
734 isSGPRSpill(uint16_t Opcode) isSGPRSpill() argument
740 isSpill(uint16_t Opcode) isSpill() argument
748 isWWMRegSpillOpcode(uint16_t Opcode) isWWMRegSpillOpcode() argument
755 isChainCallOpcode(uint64_t Opcode) isChainCallOpcode() argument
764 isDPP(uint16_t Opcode) isDPP() argument
772 isTRANS(uint16_t Opcode) isTRANS() argument
780 isVOP3P(uint16_t Opcode) isVOP3P() argument
788 isVINTRP(uint16_t Opcode) isVINTRP() argument
796 isMAI(uint16_t Opcode) isMAI() argument
813 isWMMA(uint16_t Opcode) isWMMA() argument
825 isSWMMAC(uint16_t Opcode) isSWMMAC() argument
829 isDOT(uint16_t Opcode) isDOT() argument
837 isLDSDIR(uint16_t Opcode) isLDSDIR() argument
845 isVINTERP(uint16_t Opcode) isVINTERP() argument
863 sopkIsZext(unsigned Opcode) sopkIsZext() argument
876 isScalarStore(uint16_t Opcode) isScalarStore() argument
884 isFixedSize(uint16_t Opcode) isFixedSize() argument
892 hasFPClamp(uint16_t Opcode) hasFPClamp() argument
912 usesFPDPRounding(uint16_t Opcode) usesFPDPRounding() argument
920 isFPAtomic(uint16_t Opcode) isFPAtomic() argument
931 isBarrierStart(unsigned Opcode) isBarrierStart() argument
943 doesNotReadTiedSource(uint16_t Opcode) doesNotReadTiedSource() argument
947 getNonSoftWaitcntOpcode(unsigned Opcode) getNonSoftWaitcntOpcode() argument
1105 getOpSize(uint16_t Opcode,unsigned OpNo) getOpSize() argument
1246 getMCOpcodeFromPseudo(unsigned Opcode) getMCOpcodeFromPseudo() argument
[all...] |
| /llvm-project/llvm/test/tools/llvm-readtapi/ |
| H A D | stubify-ehtypes.test | 419 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
421 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
424 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
427 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
430 - Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
433 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
436 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
438 - Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
440 - Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
443 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
[all …]
|
| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 63 bool isLoadInst(unsigned Opcode);
77 unsigned Opcode);
97 static bool isST(unsigned Opcode) { in isST() argument
98 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isST()
99 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32() argument
103 return Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32; in isSTX32()
106 static bool isSTX64(unsigned Opcode) { in isSTX64() argument
107 return Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in isSTX64()
108 Opcode == BPF::STD; in isSTX64()
[all …]
|
| /llvm-project/lldb/source/Core/ |
| H A D | Opcode.cpp | 24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
62 lldb::ByteOrder Opcode::GetDataByteOrder() const { in GetDataByteOrder()
67 case Opcode::eTypeInvalid: in GetDataByteOrder()
[all …]
|
| /llvm-project/clang/lib/AST/Interp/ |
| H A D | Opcodes.td | |
| /llvm-project/mlir/lib/Target/SPIRV/Deserialization/ |
| H A D | DeserializeOps.cpp | 34 static inline spirv::Opcode extractOpcode(uint32_t word) { in extractOpcode()
35 return static_cast<spirv::Opcode>(word & 0xffff); in extractOpcode()
78 spirv::Opcode &opcode, ArrayRef<uint32_t> &operands, in sliceInstruction()
79 std::optional<spirv::Opcode> expectedOpcode) { in sliceInstruction()
107 spirv::Opcode opcode, ArrayRef<uint32_t> operands, bool deferInstructions) { in processInstruction()
114 case spirv::Opcode::OpCapability: in processInstruction()
116 case spirv::Opcode::OpExtension: in processInstruction()
118 case spirv::Opcode::OpExtInst: in processInstruction()
120 case spirv::Opcode::OpExtInstImport: in processInstruction()
122 case spirv::Opcode in processInstruction()
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
171 switch (Opcode) { in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in opcodeHasEEWAndEMULInfo() argument
209 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in opcodeHasEEWAndEMULInfo()
210 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in opcodeHasEEWAndEMULInfo()
211 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V || in opcodeHasEEWAndEMULInfo()
212 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V || in opcodeHasEEWAndEMULInfo()
213 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V || in opcodeHasEEWAndEMULInfo()
214 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V || in opcodeHasEEWAndEMULInfo()
215 Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V || in opcodeHasEEWAndEMULInfo()
[all …]
|
| /llvm-project/llvm/unittests/tools/llvm-exegesis/X86/ |
| H A D | SnippetGeneratorTest.cpp | 45 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { in checkAndGetCodeTemplates() argument
47 const Instruction &Instr = State.getIC().getInstr(Opcode); in checkAndGetCodeTemplates()
73 const unsigned Opcode = X86::ADC16i16; in TEST_F() local
74 EXPECT_THAT(InstrInfo.get(Opcode).implicit_defs()[0], X86::AX); in TEST_F()
75 EXPECT_THAT(InstrInfo.get(Opcode).implicit_defs()[1], X86::EFLAGS); in TEST_F()
76 EXPECT_THAT(InstrInfo.get(Opcode).implicit_uses()[0], X86::AX); in TEST_F()
77 EXPECT_THAT(InstrInfo.get(Opcode).implicit_uses()[1], X86::EFLAGS); in TEST_F()
78 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); in TEST_F()
84 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
99 const unsigned Opcode in TEST_F() local
122 const unsigned Opcode = X86::VXORPSrr; TEST_F() local
147 const unsigned Opcode = X86::VXORPSrr; TEST_F() local
168 const unsigned Opcode = X86::VXORPSrr; TEST_F() local
199 const unsigned Opcode = X86::CMP64rr; TEST_F() local
220 const unsigned Opcode = X86::LAHF; TEST_F() local
239 const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int; TEST_F() local
258 const unsigned Opcode = X86::CDQ; TEST_F() local
284 const unsigned Opcode = X86::CMOV32rr; TEST_F() local
324 const unsigned Opcode = X86::VFMADD132PDr; TEST_F() local
366 const unsigned Opcode = X86::CMOV_GR32; TEST_F() local
403 const unsigned Opcode = X86::MOV32rm; TEST_F() local
422 const unsigned Opcode = X86::MOV16ms; TEST_F() local
436 const unsigned Opcode = X86::MULX32rr; TEST_F() local
460 getInstr(unsigned Opcode) getInstr() argument
464 getInstructionTemplate(unsigned Opcode) getInstructionTemplate() argument
500 const unsigned Opcode = X86::MOVSB; TEST_F() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetTransformInfo.cpp | 173 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst()
188 switch (Opcode) { in getIntImmCostInst()
528 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost()
535 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
555 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
557 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
580 if (Opcode == Instruction::FAdd || Opcode in getArithmeticInstrCost()
107 getIntImmCostInst(unsigned Opcode,unsigned Idx,const APInt & Imm,Type * Ty,TTI::TargetCostKind CostKind,Instruction * Inst) getIntImmCostInst() argument
426 getArithmeticInstrCost(unsigned Opcode,Type * Ty,TTI::TargetCostKind CostKind,TTI::OperandValueInfo Op1Info,TTI::OperandValueInfo Op2Info,ArrayRef<const Value * > Args,const Instruction * CxtI) getArithmeticInstrCost() argument
752 getBoolVecToIntConversionCost(unsigned Opcode,Type * Dst,const Instruction * I) getBoolVecToIntConversionCost() argument
768 getCastInstrCost(unsigned Opcode,Type * Dst,Type * Src,TTI::CastContextHint CCH,TTI::TargetCostKind CostKind,const Instruction * I) getCastInstrCost() argument
962 getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy,CmpInst::Predicate VecPred,TTI::TargetCostKind CostKind,const Instruction * I) getCmpSelInstrCost() argument
1047 getVectorInstrCost(unsigned Opcode,Type * Val,TTI::TargetCostKind CostKind,unsigned Index,Value * Op0,Value * Op1) getVectorInstrCost() argument
1158 getMemoryOpCost(unsigned Opcode,Type * Src,MaybeAlign Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,TTI::OperandValueInfo OpInfo,const Instruction * I) getMemoryOpCost() argument
1236 getInterleavedMemoryOpCost(unsigned Opcode,Type * VecTy,unsigned Factor,ArrayRef<unsigned> Indices,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,bool UseMaskForCond,bool UseMaskForGaps) getInterleavedMemoryOpCost() argument
[all...] |
| /llvm-project/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 327 static const char *getOpcodeName(unsigned Opcode);
329 static inline bool isTerminator(unsigned Opcode) {
330 return Opcode >= TermOpsBegin && Opcode < TermOpsEnd;
333 static inline bool isUnaryOp(unsigned Opcode) {
334 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
336 static inline bool isBinaryOp(unsigned Opcode) {
337 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEn
[all...] |
| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPostLegalizer.cpp | 46 extern bool isTypeFoldingSupported(unsigned Opcode);
58 static bool mayBeInserted(unsigned Opcode) { in isMetaInstrGET()
59 switch (Opcode) { in isMetaInstrGET()
70 return isTypeFoldingSupported(Opcode); in mayBeInserted()
80 const unsigned Opcode = I.getOpcode(); in processNewInstrs()
81 if (Opcode == TargetOpcode::G_UNMERGE_VALUES) { in processNewInstrs()
102 } else if (mayBeInserted(Opcode) && I.getNumDefs() == 1 && in processNewInstrs()
121 if (isTypeFoldingSupported(Opcode)) { in processNewInstrs()
56 isMetaInstrGET(unsigned Opcode) isMetaInstrGET() argument
64 mayBeInserted(unsigned Opcode) mayBeInserted() argument
86 const unsigned Opcode = I.getOpcode(); processNewInstrs() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86AvoidStoreForwardingBlocks.cpp | 132 static bool isXMMLoadOpcode(unsigned Opcode) {
133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode() argument
134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
137 Opcode in isXMMLoadOpcode()
143 isYMMLoadOpcode(unsigned Opcode) isYMMLoadOpcode() argument
153 isPotentialBlockedMemCpyLd(unsigned Opcode) isPotentialBlockedMemCpyLd() argument
209 isPotentialBlockingStoreInst(unsigned Opcode,unsigned LoadOpcode) isPotentialBlockingStoreInst() argument
[all...] |
| /llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanPatternMatch.h | 132 template <unsigned Opcode, typename...> struct MatchRecipeAndOpcode {};
134 template <unsigned Opcode, typename RecipeTy>
135 struct MatchRecipeAndOpcode<Opcode, RecipeTy> {
146 return DefR && DefR->getOpcode() == Opcode;
150 template <unsigned Opcode, typename RecipeTy, typename... RecipeTys>
151 struct MatchRecipeAndOpcode<Opcode, RecipeTy, RecipeTys...> {
153 return MatchRecipeAndOpcode<Opcode, RecipeTy>::match(R) ||
154 MatchRecipeAndOpcode<Opcode, RecipeTys...>::match(R);
170 template <typename Ops_t, unsigned Opcode, bool Commutative,
196 if (!detail::MatchRecipeAndOpcode<Opcode, RecipeTy
[all...] |
| /llvm-project/lld/test/MachO/ |
| H A D | bind-opcodes.s | 16 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
19 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_TYPE_IMM
22 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
25 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
29 # CHECK-NEXT: Opcode: BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB
33 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_ADDEND_SLEB
37 # CHECK-NEXT: Opcode: BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB
41 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_ADDEND_SLEB
45 # CHECK-NEXT: Opcode: BIND_OPCODE_DO_BIND
48 # CHECK-NEXT: Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
[all …]
|
| H A D | rebase-opcodes.s | 13 # CHECK-NEXT: Opcode: REBASE_OPCODE_SET_TYPE_IMM
15 # CHECK-NEXT: Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
22 # CHECK-NEXT: Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
30 # CHECK-NEXT: Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
35 # CHECK-NEXT: Opcode: REBASE_OPCODE_ADD_ADDR_IMM_SCALED
43 # CHECK-NEXT: Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
50 # CHECK-NEXT: Opcode: REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
56 # CHECK-NEXT: Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
61 # CHECK-NEXT: Opcode: REBASE_OPCODE_ADD_ADDR_ULEB
70 # CHECK-NEXT: Opcode: REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
[all …]
|
| /llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFExpression.cpp | 114 static Desc getDescImpl(ArrayRef<Desc> Descriptions, unsigned Opcode) { in getDescImpl()
116 if (Opcode >= Descriptions.size()) in getDescImpl()
118 return Descriptions[Opcode];
121 static Desc getOpDesc(unsigned Opcode) { in getOpDesc()
123 return getDescImpl(Descriptions, Opcode);
137 static Desc getSubOpDesc(unsigned Opcode, unsigned SubOpcode) { in getSubOpDesc()
138 assert(Opcode == DW_OP_LLVM_user); in getSubOpDesc()
147 Opcode = Data.getU8(&Offset); in extract()
149 Desc = getOpDesc(Opcode); in extract()
163 Desc = getSubOpDesc(Opcode, Operand in extract()
112 getDescImpl(ArrayRef<Desc> Descriptions,unsigned Opcode) getDescImpl() argument
119 getOpDesc(unsigned Opcode) getOpDesc() argument
135 getSubOpDesc(unsigned Opcode,unsigned SubOpcode) getSubOpDesc() argument
262 prettyPrintRegisterOp(DWARFUnit * U,raw_ostream & OS,DIDumpOptions DumpOpts,uint8_t Opcode,ArrayRef<uint64_t> Operands) prettyPrintRegisterOp() argument
448 uint8_t Opcode = Op.getCode(); printCompactDWARFExpr() local
[all...] |
| /llvm-project/llvm/test/tools/llvm-objcopy/MachO/ |
| H A D | linkedit-order-1.test | 316 - Opcode: REBASE_OPCODE_SET_TYPE_IMM
318 - Opcode: REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
321 - Opcode: REBASE_OPCODE_DO_REBASE_IMM_TIMES
323 - Opcode: REBASE_OPCODE_DONE
326 - Opcode: BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
329 - Opcode: BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
332 - Opcode: BIND_OPCODE_SET_TYPE_IMM
335 - Opcode: BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
339 - Opcode: BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB
343 - Opcode: BIND_OPCODE_DO_BIND
[all …]
|
| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 85 unsigned Opcode; member
89 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
90 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
91 : Opcode(Opcode), Idx(Idx), Type(Type) {} in InstrAspect()
94 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type;
158 const unsigned OpcodeIdx = Aspect.Opcode in setAction()
180 setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode,const unsigned TypeIdx,SizeChangeStrategy S) setLegalizeScalarToDifferentSizeStrategy() argument
191 setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode,const unsigned TypeIdx,SizeChangeStrategy S) setLegalizeVectorElementToDifferentSizeStrategy() argument
311 setScalarAction(const unsigned Opcode,const unsigned TypeIndex,const SizeAndActionsVec & SizeAndActions) setScalarAction() argument
317 setPointerAction(const unsigned Opcode,const unsigned TypeIndex,const unsigned AddressSpace,const SizeAndActionsVec & SizeAndActions) setPointerAction() argument
334 setScalarInVectorAction(const unsigned Opcode,const unsigned TypeIndex,const SizeAndActionsVec & SizeAndActions) setScalarInVectorAction() argument
345 setVectorNumElementAction(const unsigned Opcode,const unsigned TypeIndex,const unsigned ElementSize,const SizeAndActionsVec & SizeAndActions) setVectorNumElementAction() argument
[all...] |
| /llvm-project/llvm/test/TableGen/ |
| H A D | HwModeEncodeDecode3.td | 120 // DECODER-DAG: Opcode: bar
122 // DECODER-DAG: Opcode: fooTypeEncDefault:foo
124 // DECODER-DAG: Opcode: unrelated
126 // DECODER-DAG: Opcode: unrelated
128 // DECODER-DAG: Opcode: unrelated
130 // DECODER-DAG: Opcode: unrelated
132 // DECODER-DAG: Opcode: fooTypeEncA:foo
133 // DECODER-DAG: Opcode: bar
135 // DECODER-DAG: Opcode: fooTypeEncB:foo
136 // DECODER-DAG: Opcode: fooTypeEncA:baz
[all …]
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.cpp | 80 OS << "Opcode=" << Opcode << ", Tys={"; in print()
269 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode()
270 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
271 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
274 unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const { in getActionDefinitionsIdx()
275 unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); in getActionDefinitionsIdx()
277 LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias in getActionDefinitionsIdx()
287 LegalizerInfo::getActionDefinitions(unsigned Opcode) const { in getActionDefinitions()
288 unsigned OpcodeIdx = getActionDefinitionsIdx(Opcode); in getActionDefinitions()
292 LegalizeRuleSet &LegalizerInfo::getActionDefinitionsBuilder(unsigned Opcode) { in getActionDefinitionsBuilder() argument
[all …]
|
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | MatchContext.h | 31 bool match(SDValue OpN, unsigned Opcode) const { in getRootBaseOpcode()
32 return Opcode == OpN->getOpcode(); in match() argument
75 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( in getRootBaseOpcode()
77 assert(Opcode.has_value()); in getRootBaseOpcode()
78 return *Opcode; in getRootBaseOpcode()
110 // SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT) { return
111 // DAG.getNode(Opcode, DL, VT); } in getNode() argument
112 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode()
113 unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode); in getNode()
120 SDValue getNode(unsigned Opcode, cons in getNode()
74 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( getRootBaseOpcode() local
119 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2) getNode() argument
127 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3) getNode() argument
136 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue Operand,SDNodeFlags Flags) getNode() argument
145 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDNodeFlags Flags) getNode() argument
154 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDNodeFlags Flags) getNode() argument
[all...] |
| /llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
100 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx()
101 ((Opcode & 0x3f) << 2) + 4); in Decode_00xxxxxx()
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
106 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx()
107 ((Opcode & 0x3f) << 2) + 4); in Decode_01xxxxxx()
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101()
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
130 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111()
[all …]
|
| /llvm-project/llvm/test/tools/llvm-dwarfdump/X86/Inputs/ |
| H A D | debug_line_malformed.s | 13 .byte 13 # Opcode Base
14 .byte 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1 # Standard Opcode Lengths
54 .byte 13 # Opcode Base
55 .byte 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1 # Standard Opcode Lengths
74 .byte 13 # Opcode Base
75 .byte 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1 # Standard Opcode Lengths
100 .byte 13 # Opcode Base
101 .byte 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1 # Standard Opcode Lengths
129 .byte 13 # Opcode Base
130 .byte 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1 # Standard Opcode Lengths
[all …]
|